source: GPL/trunk/alsa-kernel/pci/hda/hda_controller.c

Last change on this file was 777, checked in by David Azarewicz, 7 months ago

Merge from uniaud32-exp branch
File size: 36.9 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Implementation of primary alsa driver code base for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 */
11
12#include <linux/clocksource.h>
13#include <linux/delay.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pm_runtime.h>
18#include <linux/slab.h>
19
20#ifdef CONFIG_X86
21/* for art-tsc conversion */
22#include <asm/tsc.h>
23#endif
24
25#include <sound/core.h>
26#include <sound/initval.h>
27#include <sound/pcm_params.h>
28#include "hda_controller.h"
29#include "hda_local.h"
30
31#ifndef TARGET_OS2
32#define CREATE_TRACE_POINTS
33#include "hda_controller_trace.h"
34#else
35#pragma disable_message (201)
36#define trace_azx_pcm_close(...)
37#define trace_azx_pcm_open(...)
38#define trace_azx_pcm_prepare(...)
39#define trace_azx_pcm_hw_params(...)
40#define trace_azx_resume(...)
41#endif
42/* DSP lock helpers */
43#define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev))
44#define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev))
45#define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
46
47/* assign a stream for the PCM */
48static inline struct azx_dev *
49azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
50{
51 struct hdac_stream *s;
52
53 s = snd_hdac_stream_assign(azx_bus(chip), substream);
54 if (!s)
55 return NULL;
56 return stream_to_azx_dev(s);
57}
58
59/* release the assigned stream */
60static inline void azx_release_device(struct azx_dev *azx_dev)
61{
62 snd_hdac_stream_release(azx_stream(azx_dev));
63}
64
65static inline struct hda_pcm_stream *
66to_hda_pcm_stream(struct snd_pcm_substream *substream)
67{
68 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
69 return &apcm->info->stream[substream->stream];
70}
71
72static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
73 u64 nsec)
74{
75 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
76 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
77 u64 codec_frames, codec_nsecs;
78
79 if (!hinfo->ops.get_delay)
80 return nsec;
81
82 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
83 codec_nsecs = div_u64(codec_frames * 1000000000LL,
84 substream->runtime->rate);
85
86 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
87 return nsec + codec_nsecs;
88
89 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
90}
91
92/*
93 * PCM ops
94 */
95
96static int azx_pcm_close(struct snd_pcm_substream *substream)
97{
98 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
99 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
100 struct azx *chip = apcm->chip;
101 struct azx_dev *azx_dev = get_azx_dev(substream);
102
103 trace_azx_pcm_close(chip, azx_dev);
104 mutex_lock(&chip->open_mutex);
105 azx_release_device(azx_dev);
106 if (hinfo->ops.close)
107 hinfo->ops.close(hinfo, apcm->codec, substream);
108 snd_hda_power_down(apcm->codec);
109 mutex_unlock(&chip->open_mutex);
110 snd_hda_codec_pcm_put(apcm->info);
111 return 0;
112}
113
114static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
115 struct snd_pcm_hw_params *hw_params)
116{
117 //NOT_USED struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
118 //NOT_USED struct azx *chip = apcm->chip;
119 struct azx_dev *azx_dev = get_azx_dev(substream);
120 struct hdac_stream *hdas = azx_stream(azx_dev);
121 int ret = 0;
122
123 trace_azx_pcm_hw_params(chip, azx_dev);
124 dsp_lock(azx_dev);
125 if (dsp_is_locked(azx_dev)) {
126 ret = -EBUSY;
127 goto unlock;
128 }
129
130 /* Set up BDLEs here, return -ENOMEM if too many BDLEs are required */
131 hdas->bufsize = params_buffer_bytes(hw_params);
132 hdas->period_bytes = params_period_bytes(hw_params);
133 hdas->format_val = 0;
134 hdas->no_period_wakeup =
135 (hw_params->info & SNDRV_PCM_INFO_NO_PERIOD_WAKEUP) &&
136 (hw_params->flags & SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP);
137 if (snd_hdac_stream_setup_periods(hdas) < 0)
138 ret = -ENOMEM;
139
140unlock:
141 dsp_unlock(azx_dev);
142 return ret;
143}
144
145static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
146{
147 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
148 struct azx_dev *azx_dev = get_azx_dev(substream);
149 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
150
151 /* reset BDL address */
152 dsp_lock(azx_dev);
153 if (!dsp_is_locked(azx_dev))
154 snd_hdac_stream_cleanup(azx_stream(azx_dev));
155
156 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
157
158 azx_stream(azx_dev)->prepared = 0;
159 dsp_unlock(azx_dev);
160 return 0;
161}
162
163static int azx_pcm_prepare(struct snd_pcm_substream *substream)
164{
165 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
166 struct azx *chip = apcm->chip;
167 struct azx_dev *azx_dev = get_azx_dev(substream);
168 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
169 struct snd_pcm_runtime *runtime = substream->runtime;
170 unsigned int format_val, stream_tag, bits;
171 int err;
172 struct hda_spdif_out *spdif =
173 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
174 unsigned short ctls = spdif ? spdif->ctls : 0;
175
176 trace_azx_pcm_prepare(chip, azx_dev);
177 dsp_lock(azx_dev);
178 if (dsp_is_locked(azx_dev)) {
179 err = -EBUSY;
180 goto unlock;
181 }
182
183 snd_hdac_stream_reset(azx_stream(azx_dev));
184 bits = snd_hdac_stream_format_bits(runtime->format, SNDRV_PCM_SUBFORMAT_STD, hinfo->maxbps);
185
186 format_val = snd_hdac_spdif_stream_format(runtime->channels, bits, runtime->rate, ctls);
187 if (!format_val) {
188 dev_err(chip->card->dev,
189 "invalid format_val, rate=%d, ch=%d, format=%d\n",
190 runtime->rate, runtime->channels, runtime->format);
191 err = -EINVAL;
192 goto unlock;
193 }
194
195 err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
196 if (err < 0)
197 goto unlock;
198
199 snd_hdac_stream_setup(azx_stream(azx_dev), false);
200
201 stream_tag = azx_dev->core.stream_tag;
202 /* CA-IBG chips need the playback stream starting from 1 */
203 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
204 stream_tag > chip->capture_streams)
205 stream_tag -= chip->capture_streams;
206 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
207 azx_dev->core.format_val, substream);
208
209 unlock:
210 if (!err)
211 azx_stream(azx_dev)->prepared = 1;
212 dsp_unlock(azx_dev);
213 return err;
214}
215
216static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
217{
218 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
219 struct azx *chip = apcm->chip;
220 struct hdac_bus *bus = azx_bus(chip);
221 struct azx_dev *azx_dev;
222 struct snd_pcm_substream *s;
223 struct hdac_stream *hstr;
224 bool start;
225 int sbits = 0;
226 int sync_reg;
227
228 azx_dev = get_azx_dev(substream);
229#ifndef TARGET_OS2
230 trace_azx_pcm_trigger(chip, azx_dev, cmd);
231#endif
232
233 hstr = azx_stream(azx_dev);
234 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
235 sync_reg = AZX_REG_OLD_SSYNC;
236 else
237 sync_reg = AZX_REG_SSYNC;
238
239 if (dsp_is_locked(azx_dev) || !hstr->prepared)
240 return -EPIPE;
241
242 switch (cmd) {
243 case SNDRV_PCM_TRIGGER_START:
244 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
245 case SNDRV_PCM_TRIGGER_RESUME:
246 start = true;
247 break;
248 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
249 case SNDRV_PCM_TRIGGER_SUSPEND:
250 case SNDRV_PCM_TRIGGER_STOP:
251 start = false;
252 break;
253 default:
254 return -EINVAL;
255 }
256
257 snd_pcm_group_for_each_entry(s, substream) {
258 if (s->pcm->card != substream->pcm->card)
259 continue;
260 azx_dev = get_azx_dev(s);
261 sbits |= 1 << azx_dev->core.index;
262 snd_pcm_trigger_done(s, substream);
263 }
264
265 spin_lock(&bus->reg_lock);
266
267 /* first, set SYNC bits of corresponding streams */
268 snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
269
270 snd_pcm_group_for_each_entry(s, substream) {
271 if (s->pcm->card != substream->pcm->card)
272 continue;
273 azx_dev = get_azx_dev(s);
274 if (start) {
275 azx_dev->insufficient = 1;
276 snd_hdac_stream_start(azx_stream(azx_dev));
277 } else {
278 snd_hdac_stream_stop(azx_stream(azx_dev));
279 }
280 }
281 spin_unlock(&bus->reg_lock);
282
283 snd_hdac_stream_sync(hstr, start, sbits);
284
285 spin_lock(&bus->reg_lock);
286 /* reset SYNC bits */
287 snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
288 snd_hdac_stream_timecounter_init(hstr, sbits, start);
289 spin_unlock(&bus->reg_lock);
290 return 0;
291}
292
293unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
294{
295 return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
296}
297EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
298
299unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
300{
301 return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
302}
303EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
304
305unsigned int azx_get_position(struct azx *chip,
306 struct azx_dev *azx_dev)
307{
308 struct snd_pcm_substream *substream = azx_dev->core.substream;
309 unsigned int pos;
310 int stream = substream->stream;
311 int delay = 0;
312
313 if (chip->get_position[stream])
314 pos = chip->get_position[stream](chip, azx_dev);
315 else /* use the position buffer as default */
316 pos = azx_get_pos_posbuf(chip, azx_dev);
317
318 if (pos >= azx_dev->core.bufsize)
319 pos = 0;
320
321 if (substream->runtime) {
322 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
323 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
324
325 if (chip->get_delay[stream])
326 delay += chip->get_delay[stream](chip, azx_dev, pos);
327 if (hinfo->ops.get_delay)
328 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
329 substream);
330 substream->runtime->delay = delay;
331 }
332
333#ifndef TARGET_OS2
334 trace_azx_get_position(chip, azx_dev, pos, delay);
335#endif
336 return pos;
337}
338EXPORT_SYMBOL_GPL(azx_get_position);
339
340static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
341{
342 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
343 struct azx *chip = apcm->chip;
344 struct azx_dev *azx_dev = get_azx_dev(substream);
345 return bytes_to_frames(substream->runtime,
346 azx_get_position(chip, azx_dev));
347}
348
349/*
350 * azx_scale64: Scale base by mult/div while not overflowing sanely
351 *
352 * Derived from scale64_check_overflow in kernel/time/timekeeping.c
353 *
354 * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
355 * is about 384307 ie ~4.5 days.
356 *
357 * This scales the calculation so that overflow will happen but after 2^64 /
358 * 48000 secs, which is pretty large!
359 *
360 * In caln below:
361 * base may overflow, but since there isn’t any additional division
362 * performed on base it’s OK
363 * rem can’t overflow because both are 32-bit values
364 */
365
366#ifdef CONFIG_X86
367static u64 azx_scale64(u64 base, u32 num, u32 den)
368{
369 u64 rem;
370
371 rem = do_div(base, den);
372
373 base *= num;
374 rem *= num;
375
376 do_div(rem, den);
377
378 return base + rem;
379}
380
381static int azx_get_sync_time(ktime_t *device,
382 struct system_counterval_t *system, void *ctx)
383{
384 struct snd_pcm_substream *substream = ctx;
385 struct azx_dev *azx_dev = get_azx_dev(substream);
386 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
387 struct azx *chip = apcm->chip;
388 struct snd_pcm_runtime *runtime;
389 u64 ll_counter, ll_counter_l, ll_counter_h;
390 u64 tsc_counter, tsc_counter_l, tsc_counter_h;
391 u32 wallclk_ctr, wallclk_cycles;
392 bool direction;
393 u32 dma_select;
394 u32 timeout;
395 u32 retry_count = 0;
396
397 runtime = substream->runtime;
398
399 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
400 direction = 1;
401 else
402 direction = 0;
403
404 /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
405 do {
406 timeout = 100;
407 dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
408 (azx_dev->core.stream_tag - 1);
409 snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
410
411 /* Enable the capture */
412 snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
413
414 while (timeout) {
415 if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
416 GTSCC_TSCCD_MASK)
417 break;
418
419 timeout--;
420 }
421
422 if (!timeout) {
423 dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
424 return -EIO;
425 }
426
427 /* Read wall clock counter */
428 wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
429
430 /* Read TSC counter */
431 tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
432 tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
433
434 /* Read Link counter */
435 ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
436 ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
437
438 /* Ack: registers read done */
439 snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
440
441 tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
442 tsc_counter_l;
443
444 ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
445 wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
446
447 /*
448 * An error occurs near frame "rollover". The clocks in
449 * frame value indicates whether this error may have
450 * occurred. Here we use the value of 10 i.e.,
451 * HDA_MAX_CYCLE_OFFSET
452 */
453 if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
454 && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
455 break;
456
457 /*
458 * Sleep before we read again, else we may again get
459 * value near to MAX_CYCLE. Try to sleep for different
460 * amount of time so we dont hit the same number again
461 */
462 udelay(retry_count++);
463
464 } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
465
466 if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
467 dev_err_ratelimited(chip->card->dev,
468 "Error in WALFCC cycle count\n");
469 return -EIO;
470 }
471
472 *device = ns_to_ktime(azx_scale64(ll_counter,
473 NSEC_PER_SEC, runtime->rate));
474 *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
475 ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
476
477 system->cycles = tsc_counter;
478 system->cs_id = CSID_X86_ART;
479
480 return 0;
481}
482
483#else
484#ifdef NOT_USED
485static int azx_get_sync_time(ktime_t *device,
486 struct system_counterval_t *system, void *ctx)
487{
488 return -ENXIO;
489}
490#endif /* NOT_USED */
491#endif
492
493#ifndef TARGET_OS2
494static int azx_get_crosststamp(struct snd_pcm_substream *substream,
495 struct system_device_crosststamp *xtstamp)
496{
497 return get_device_system_crosststamp(azx_get_sync_time,
498 substream, NULL, xtstamp);
499}
500#endif
501
502
503static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
504 struct snd_pcm_audio_tstamp_config *ts)
505{
506 if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
507 if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
508 return true;
509
510 return false;
511}
512
513static int azx_get_time_info(struct snd_pcm_substream *substream,
514 struct timespec64 *system_ts, struct timespec64 *audio_ts,
515 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
516 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
517{
518 struct azx_dev *azx_dev = get_azx_dev(substream);
519 struct snd_pcm_runtime *runtime = substream->runtime;
520 struct system_device_crosststamp xtstamp;
521#ifndef TARGET_OS2
522 int ret;
523#endif
524 u64 nsec;
525
526 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
527 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
528
529 snd_pcm_gettime(substream->runtime, system_ts);
530
531 nsec = timecounter_read(&azx_dev->core.tc);
532 if (audio_tstamp_config->report_delay)
533 nsec = azx_adjust_codec_delay(substream, nsec);
534
535 *audio_ts = ns_to_timespec64(nsec);
536
537 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
538 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
539 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
540
541 } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
542
543#ifndef TARGET_OS2
544 ret = azx_get_crosststamp(substream, &xtstamp);
545 if (ret)
546 return ret;
547#endif
548 switch (runtime->tstamp_type) {
549 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
550 return -EINVAL;
551
552 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
553 *system_ts = ktime_to_timespec64(xtstamp.sys_monoraw);
554 break;
555
556 default:
557 *system_ts = ktime_to_timespec64(xtstamp.sys_realtime);
558 break;
559
560 }
561
562 *audio_ts = ktime_to_timespec64(xtstamp.device);
563
564 audio_tstamp_report->actual_type =
565 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
566 audio_tstamp_report->accuracy_report = 1;
567 /* 24 MHz WallClock == 42ns resolution */
568 audio_tstamp_report->accuracy = 42;
569
570 } else {
571 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
572 }
573
574 return 0;
575}
576
577static const struct snd_pcm_hardware azx_pcm_hw = {
578 .info = (SNDRV_PCM_INFO_MMAP |
579 SNDRV_PCM_INFO_INTERLEAVED |
580 SNDRV_PCM_INFO_BLOCK_TRANSFER |
581 SNDRV_PCM_INFO_MMAP_VALID |
582 /* No full-resume yet implemented */
583 /* SNDRV_PCM_INFO_RESUME |*/
584 SNDRV_PCM_INFO_PAUSE |
585 SNDRV_PCM_INFO_SYNC_START |
586 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
587 SNDRV_PCM_INFO_HAS_LINK_ATIME |
588 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
589 .formats = SNDRV_PCM_FMTBIT_S16_LE,
590 .rates = SNDRV_PCM_RATE_48000,
591 .rate_min = 48000,
592 .rate_max = 48000,
593 .channels_min = 2,
594 .channels_max = 2,
595 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
596 .period_bytes_min = 128,
597 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
598 .periods_min = 2,
599 .periods_max = AZX_MAX_FRAG,
600 .fifo_size = 0,
601};
602
603static int azx_pcm_open(struct snd_pcm_substream *substream)
604{
605 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
606 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
607 struct azx *chip = apcm->chip;
608 struct azx_dev *azx_dev;
609 struct snd_pcm_runtime *runtime = substream->runtime;
610 int err;
611 int buff_step;
612
613 snd_hda_codec_pcm_get(apcm->info);
614 mutex_lock(&chip->open_mutex);
615 azx_dev = azx_assign_device(chip, substream);
616 trace_azx_pcm_open(chip, azx_dev);
617 if (azx_dev == NULL) {
618 err = -EBUSY;
619 goto unlock;
620 }
621 runtime->private_data = azx_dev;
622
623 runtime->hw = azx_pcm_hw;
624 if (chip->gts_present)
625 runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
626 runtime->hw.channels_min = hinfo->channels_min;
627 runtime->hw.channels_max = hinfo->channels_max;
628 runtime->hw.formats = hinfo->formats;
629 runtime->hw.rates = hinfo->rates;
630 snd_pcm_limit_hw_rates(runtime);
631 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
632
633 /* avoid wrap-around with wall-clock */
634 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
635 20,
636 178000000);
637
638 if (chip->align_buffer_size)
639 /* constrain buffer sizes to be multiple of 128
640 bytes. This is more efficient in terms of memory
641 access but isn't required by the HDA spec and
642 prevents users from specifying exact period/buffer
643 sizes. For example for 44.1kHz, a period size set
644 to 20ms will be rounded to 19.59ms. */
645 buff_step = 128;
646 else
647 /* Don't enforce steps on buffer sizes, still need to
648 be multiple of 4 bytes (HDA spec). Tested on Intel
649 HDA controllers, may not work on all devices where
650 option needs to be disabled */
651 buff_step = 4;
652
653 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
654 buff_step);
655 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
656 buff_step);
657 snd_hda_power_up(apcm->codec);
658 if (hinfo->ops.open)
659 err = hinfo->ops.open(hinfo, apcm->codec, substream);
660 else
661 err = -ENODEV;
662 if (err < 0) {
663 azx_release_device(azx_dev);
664 goto powerdown;
665 }
666 snd_pcm_limit_hw_rates(runtime);
667 /* sanity check */
668 if (snd_BUG_ON(!runtime->hw.channels_min) ||
669 snd_BUG_ON(!runtime->hw.channels_max) ||
670 snd_BUG_ON(!runtime->hw.formats) ||
671 snd_BUG_ON(!runtime->hw.rates)) {
672 azx_release_device(azx_dev);
673 if (hinfo->ops.close)
674 hinfo->ops.close(hinfo, apcm->codec, substream);
675 err = -EINVAL;
676 goto powerdown;
677 }
678
679 /* disable LINK_ATIME timestamps for capture streams
680 until we figure out how to handle digital inputs */
681 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
682 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
683 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
684 }
685
686 snd_pcm_set_sync(substream);
687 mutex_unlock(&chip->open_mutex);
688 return 0;
689
690 powerdown:
691 snd_hda_power_down(apcm->codec);
692 unlock:
693 mutex_unlock(&chip->open_mutex);
694 snd_hda_codec_pcm_put(apcm->info);
695 return err;
696}
697
698static const struct snd_pcm_ops azx_pcm_ops = {
699 .open = azx_pcm_open,
700 .close = azx_pcm_close,
701 .hw_params = azx_pcm_hw_params,
702 .hw_free = azx_pcm_hw_free,
703 .prepare = azx_pcm_prepare,
704 .trigger = azx_pcm_trigger,
705 .pointer = azx_pcm_pointer,
706 .get_time_info = azx_get_time_info,
707};
708
709static void azx_pcm_free(struct snd_pcm *pcm)
710{
711 struct azx_pcm *apcm = pcm->private_data;
712 if (apcm) {
713 list_del(&apcm->list);
714 apcm->info->pcm = NULL;
715 kfree(apcm);
716 }
717}
718
719#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
720
721int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
722 struct hda_pcm *cpcm)
723{
724 struct hdac_bus *bus = &_bus->core;
725 struct azx *chip = bus_to_azx(bus);
726 struct snd_pcm *pcm;
727 struct azx_pcm *apcm;
728 int pcm_dev = cpcm->device;
729 unsigned int size;
730 int s, err;
731 int type = SNDRV_DMA_TYPE_DEV_SG;
732
733 list_for_each_entry(apcm, &chip->pcm_list, list, struct azx_pcm) {
734 if (apcm->pcm->device == pcm_dev) {
735 dev_err(chip->card->dev, "PCM %d already exists\n",
736 pcm_dev);
737 return -EBUSY;
738 }
739 }
740 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
741 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
742 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
743 &pcm);
744 if (err < 0)
745 return err;
746 strscpy(pcm->name, cpcm->name, sizeof(pcm->name));
747 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
748 if (apcm == NULL) {
749 snd_device_free(chip->card, pcm);
750 return -ENOMEM;
751 }
752 apcm->chip = chip;
753 apcm->pcm = pcm;
754 apcm->codec = codec;
755 apcm->info = cpcm;
756 pcm->private_data = apcm;
757 pcm->private_free = azx_pcm_free;
758 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
759 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
760 list_add_tail(&apcm->list, &chip->pcm_list);
761 cpcm->pcm = pcm;
762 for (s = 0; s < 2; s++) {
763 if (cpcm->stream[s].substreams)
764 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
765 }
766 /* buffer pre-allocation */
767 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
768 if (size > MAX_PREALLOC_SIZE)
769 size = MAX_PREALLOC_SIZE;
770 if (chip->uc_buffer)
771 type = SNDRV_DMA_TYPE_DEV_WC_SG;
772 snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev,
773 size, MAX_PREALLOC_SIZE);
774 return 0;
775}
776
777static unsigned int azx_command_addr(u32 cmd)
778{
779 unsigned int addr = cmd >> 28;
780
781 if (addr >= AZX_MAX_CODECS) {
782 snd_BUG();
783 addr = 0;
784 }
785
786 return addr;
787}
788
789/* receive a response */
790static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
791 unsigned int *res)
792{
793 struct azx *chip = bus_to_azx(bus);
794 struct hda_bus *hbus = &chip->bus;
795 int err;
796
797 again:
798 err = snd_hdac_bus_get_response(bus, addr, res);
799 if (!err)
800 return 0;
801
802#ifndef TARGET_OS2 /* fixes 2nd HDA adapter on OS/2 */
803 if (hbus->no_response_fallback)
804#else
805 if (!hbus->no_response_fallback)
806#endif
807 return -EIO;
808
809 if (!bus->polling_mode) {
810 dev_warn(chip->card->dev,
811 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
812 bus->last_cmd[addr]);
813 bus->polling_mode = 1;
814 goto again;
815 }
816
817 if (chip->msi) {
818 dev_warn(chip->card->dev,
819 "No response from codec, disabling MSI: last cmd=0x%08x\n",
820 bus->last_cmd[addr]);
821 if (chip->ops->disable_msi_reset_irq &&
822 chip->ops->disable_msi_reset_irq(chip) < 0)
823 return -EIO;
824 goto again;
825 }
826
827 if (chip->probing) {
828 /* If this critical timeout happens during the codec probing
829 * phase, this is likely an access to a non-existing codec
830 * slot. Better to return an error and reset the system.
831 */
832 return -EIO;
833 }
834
835 /* no fallback mechanism? */
836 if (!chip->fallback_to_single_cmd)
837 return -EIO;
838
839 /* a fatal communication error; need either to reset or to fallback
840 * to the single_cmd mode
841 */
842 if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
843 hbus->response_reset = 1;
844 dev_err(chip->card->dev,
845 "No response from codec, resetting bus: last cmd=0x%08x\n",
846 bus->last_cmd[addr]);
847 return -EAGAIN; /* give a chance to retry */
848 }
849
850 dev_err(chip->card->dev,
851 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
852 bus->last_cmd[addr]);
853 chip->single_cmd = 1;
854 hbus->response_reset = 0;
855 snd_hdac_bus_stop_cmd_io(bus);
856 return -EIO;
857}
858
859/*
860 * Use the single immediate command instead of CORB/RIRB for simplicity
861 *
862 * Note: according to Intel, this is not preferred use. The command was
863 * intended for the BIOS only, and may get confused with unsolicited
864 * responses. So, we shouldn't use it for normal operation from the
865 * driver.
866 * I left the codes, however, for debugging/testing purposes.
867 */
868
869/* receive a response */
870static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
871{
872 int timeout = 50;
873
874 while (timeout--) {
875 /* check IRV busy bit */
876 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
877 /* reuse rirb.res as the response return value */
878 azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
879 return 0;
880 }
881 udelay(1);
882 }
883 if (printk_ratelimit())
884 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
885 azx_readw(chip, IRS));
886 azx_bus(chip)->rirb.res[addr] = -1;
887 return -EIO;
888}
889
890/* send a command */
891static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
892{
893 struct azx *chip = bus_to_azx(bus);
894 unsigned int addr = azx_command_addr(val);
895 int timeout = 50;
896
897 bus->last_cmd[azx_command_addr(val)] = val;
898 while (timeout--) {
899 /* check ICB busy bit */
900 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
901 /* Clear IRV valid bit */
902 azx_writew(chip, IRS, azx_readw(chip, IRS) |
903 AZX_IRS_VALID);
904 azx_writel(chip, IC, val);
905 azx_writew(chip, IRS, azx_readw(chip, IRS) |
906 AZX_IRS_BUSY);
907 return azx_single_wait_for_response(chip, addr);
908 }
909 udelay(1);
910 }
911 if (printk_ratelimit())
912 dev_dbg(chip->card->dev,
913 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
914 azx_readw(chip, IRS), val);
915 return -EIO;
916}
917
918/* receive a response */
919static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
920 unsigned int *res)
921{
922 if (res)
923 *res = bus->rirb.res[addr];
924 return 0;
925}
926
927/*
928 * The below are the main callbacks from hda_codec.
929 *
930 * They are just the skeleton to call sub-callbacks according to the
931 * current setting of chip->single_cmd.
932 */
933
934/* send a command */
935static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
936{
937 struct azx *chip = bus_to_azx(bus);
938
939 if (chip->disabled)
940 return 0;
941 if (chip->single_cmd || bus->use_pio_for_commands)
942 return azx_single_send_cmd(bus, val);
943 else
944 return snd_hdac_bus_send_cmd(bus, val);
945}
946
947/* get a response */
948static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
949 unsigned int *res)
950{
951 struct azx *chip = bus_to_azx(bus);
952
953 if (chip->disabled)
954 return 0;
955 if (chip->single_cmd || bus->use_pio_for_commands)
956 return azx_single_get_response(bus, addr, res);
957 else
958 return azx_rirb_get_response(bus, addr, res);
959}
960
961static const struct hdac_bus_ops bus_core_ops = {
962 .command = azx_send_cmd,
963 .get_response = azx_get_response,
964};
965
966#ifdef CONFIG_SND_HDA_DSP_LOADER
967/*
968 * DSP loading code (e.g. for CA0132)
969 */
970
971/* use the first stream for loading DSP */
972static struct azx_dev *
973azx_get_dsp_loader_dev(struct azx *chip)
974{
975 struct hdac_bus *bus = azx_bus(chip);
976 struct hdac_stream *s;
977
978 list_for_each_entry(s, &bus->stream_list, list, struct hdac_stream)
979 if (s->index == chip->playback_index_offset)
980 return stream_to_azx_dev(s);
981
982 return NULL;
983}
984
985int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
986 unsigned int byte_size,
987 struct snd_dma_buffer *bufp)
988{
989 struct hdac_bus *bus = &codec->bus->core;
990 struct azx *chip = bus_to_azx(bus);
991 struct azx_dev *azx_dev;
992 struct hdac_stream *hstr;
993 bool saved = false;
994 int err;
995
996 azx_dev = azx_get_dsp_loader_dev(chip);
997 hstr = azx_stream(azx_dev);
998 spin_lock_irq(&bus->reg_lock);
999 if (hstr->opened) {
1000 chip->saved_azx_dev = *azx_dev;
1001 saved = true;
1002 }
1003 spin_unlock_irq(&bus->reg_lock);
1004
1005 err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
1006 if (err < 0) {
1007 spin_lock_irq(&bus->reg_lock);
1008 if (saved)
1009 *azx_dev = chip->saved_azx_dev;
1010 spin_unlock_irq(&bus->reg_lock);
1011 return err;
1012 }
1013
1014 hstr->prepared = 0;
1015 return err;
1016}
1017EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
1018
1019void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
1020{
1021 struct hdac_bus *bus = &codec->bus->core;
1022 struct azx *chip = bus_to_azx(bus);
1023 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1024
1025 snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
1026}
1027EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
1028
1029void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
1030 struct snd_dma_buffer *dmab)
1031{
1032 struct hdac_bus *bus = &codec->bus->core;
1033 struct azx *chip = bus_to_azx(bus);
1034 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1035 struct hdac_stream *hstr = azx_stream(azx_dev);
1036
1037 if (!dmab->area || !hstr->locked)
1038 return;
1039
1040 snd_hdac_dsp_cleanup(hstr, dmab);
1041 spin_lock_irq(&bus->reg_lock);
1042 if (hstr->opened)
1043 *azx_dev = chip->saved_azx_dev;
1044 hstr->locked = false;
1045 spin_unlock_irq(&bus->reg_lock);
1046}
1047EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1048#endif /* CONFIG_SND_HDA_DSP_LOADER */
1049
1050/*
1051 * reset and start the controller registers
1052 */
1053void azx_init_chip(struct azx *chip, bool full_reset)
1054{
1055 if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1056 /* correct RINTCNT for CXT */
1057 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1058 azx_writew(chip, RINTCNT, 0xc0);
1059 }
1060}
1061EXPORT_SYMBOL_GPL(azx_init_chip);
1062
1063void azx_stop_all_streams(struct azx *chip)
1064{
1065 struct hdac_bus *bus = azx_bus(chip);
1066
1067 snd_hdac_stop_streams(bus);
1068}
1069EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1070
1071void azx_stop_chip(struct azx *chip)
1072{
1073 snd_hdac_bus_stop_chip(azx_bus(chip));
1074}
1075EXPORT_SYMBOL_GPL(azx_stop_chip);
1076
1077/*
1078 * interrupt handler
1079 */
1080static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1081{
1082 struct azx *chip = bus_to_azx(bus);
1083 struct azx_dev *azx_dev = stream_to_azx_dev(s);
1084
1085 /* check whether this IRQ is really acceptable */
1086 if (!chip->ops->position_check ||
1087 chip->ops->position_check(chip, azx_dev)) {
1088 spin_unlock(&bus->reg_lock);
1089 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1090 spin_lock(&bus->reg_lock);
1091 }
1092}
1093
1094irqreturn_t azx_interrupt(int irq, void *dev_id)
1095{
1096 struct azx *chip = dev_id;
1097 struct hdac_bus *bus = azx_bus(chip);
1098 u32 status;
1099 bool active, handled = false;
1100 int repeat = 0; /* count for avoiding endless loop */
1101
1102 if (azx_has_pm_runtime(chip))
1103 if (!pm_runtime_active(chip->card->dev))
1104 return IRQ_NONE;
1105
1106 spin_lock(&bus->reg_lock);
1107
1108 if (chip->disabled)
1109 goto unlock;
1110
1111 do {
1112 status = azx_readl(chip, INTSTS);
1113 if (status == 0 || status == 0xffffffff)
1114 break;
1115
1116 handled = true;
1117 active = false;
1118 if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1119 active = true;
1120
1121 status = azx_readb(chip, RIRBSTS);
1122 if (status & RIRB_INT_MASK) {
1123 /*
1124 * Clearing the interrupt status here ensures that no
1125 * interrupt gets masked after the RIRB wp is read in
1126 * snd_hdac_bus_update_rirb. This avoids a possible
1127 * race condition where codec response in RIRB may
1128 * remain unserviced by IRQ, eventually falling back
1129 * to polling mode in azx_rirb_get_response.
1130 */
1131 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1132 active = true;
1133 if (status & RIRB_INT_RESPONSE) {
1134 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1135 udelay(80);
1136 snd_hdac_bus_update_rirb(bus);
1137 }
1138 }
1139 } while (active && ++repeat < 10);
1140
1141 unlock:
1142 spin_unlock(&bus->reg_lock);
1143
1144#ifdef TARGET_OS2
1145 if (status & RIRB_INT_MASK) {
1146 return 2;
1147 }
1148#endif
1149 return IRQ_RETVAL(handled);
1150}
1151EXPORT_SYMBOL_GPL(azx_interrupt);
1152
1153/*
1154 * Codec initerface
1155 */
1156
1157/*
1158 * Probe the given codec address
1159 */
1160static int probe_codec(struct azx *chip, int addr)
1161{
1162 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1163 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1164 struct hdac_bus *bus = azx_bus(chip);
1165 int err;
1166 unsigned int res = -1;
1167
1168 mutex_lock(&bus->cmd_mutex);
1169 chip->probing = 1;
1170 azx_send_cmd(bus, cmd);
1171 err = azx_get_response(bus, addr, &res);
1172 chip->probing = 0;
1173 mutex_unlock(&bus->cmd_mutex);
1174 if (err < 0 || res == -1)
1175 return -EIO;
1176 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1177 return 0;
1178}
1179
1180void snd_hda_bus_reset(struct hda_bus *bus)
1181{
1182 struct azx *chip = bus_to_azx(&bus->core);
1183
1184 bus->in_reset = 1;
1185 azx_stop_chip(chip);
1186 azx_init_chip(chip, true);
1187 if (bus->core.chip_init)
1188 snd_hda_bus_reset_codecs(bus);
1189 bus->in_reset = 0;
1190}
1191
1192/* HD-audio bus initialization */
1193int azx_bus_init(struct azx *chip, const char *model)
1194{
1195 struct hda_bus *bus = &chip->bus;
1196 int err;
1197
1198 err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops);
1199 if (err < 0)
1200 return err;
1201
1202 bus->card = chip->card;
1203 mutex_init(&bus->prepare_mutex);
1204 bus->pci = chip->pci;
1205 bus->modelname = model;
1206 bus->mixer_assigned = -1;
1207 bus->core.snoop = azx_snoop(chip);
1208 if (chip->get_position[0] != azx_get_pos_lpib ||
1209 chip->get_position[1] != azx_get_pos_lpib)
1210 bus->core.use_posbuf = true;
1211 bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1212 if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1213 bus->core.corbrp_self_clear = true;
1214
1215 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1216 bus->core.align_bdle_4k = true;
1217
1218 if (chip->driver_caps & AZX_DCAPS_PIO_COMMANDS)
1219 bus->core.use_pio_for_commands = true;
1220
1221 /* enable sync_write flag for stable communication as default */
1222 bus->core.sync_write = 1;
1223
1224 return 0;
1225}
1226EXPORT_SYMBOL_GPL(azx_bus_init);
1227
1228/* Probe codecs */
1229int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1230{
1231 struct hdac_bus *bus = azx_bus(chip);
1232 int c, codecs, err;
1233
1234 codecs = 0;
1235 if (!max_slots)
1236 max_slots = AZX_DEFAULT_CODECS;
1237
1238 /* First try to probe all given codec slots */
1239 for (c = 0; c < max_slots; c++) {
1240 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1241 if (probe_codec(chip, c) < 0) {
1242 /* Some BIOSen give you wrong codec addresses
1243 * that don't exist
1244 */
1245 dev_warn(chip->card->dev,
1246 "Codec #%d probe error; disabling it...\n", c);
1247 bus->codec_mask &= ~(1 << c);
1248 /* no codecs */
1249 if (bus->codec_mask == 0)
1250 break;
1251 /* More badly, accessing to a non-existing
1252 * codec often screws up the controller chip,
1253 * and disturbs the further communications.
1254 * Thus if an error occurs during probing,
1255 * better to reset the controller chip to
1256 * get back to the sanity state.
1257 */
1258 azx_stop_chip(chip);
1259 azx_init_chip(chip, true);
1260 }
1261 }
1262 }
1263
1264 /* Then create codec instances */
1265 for (c = 0; c < max_slots; c++) {
1266 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1267 struct hda_codec *codec;
1268 err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1269 if (err < 0)
1270 continue;
1271 codec->jackpoll_interval = chip->jackpoll_interval;
1272 codec->beep_mode = chip->beep_mode;
1273 codec->ctl_dev_id = chip->ctl_dev_id;
1274 codecs++;
1275 }
1276 }
1277 if (!codecs) {
1278 dev_err(chip->card->dev, "no codecs initialized\n");
1279 return -ENXIO;
1280 }
1281 return 0;
1282}
1283EXPORT_SYMBOL_GPL(azx_probe_codecs);
1284
1285/* configure each codec instance */
1286int azx_codec_configure(struct azx *chip)
1287{
1288 struct hda_codec *codec, *next;
1289 int success = 0;
1290
1291 list_for_each_codec(codec, &chip->bus) {
1292 if (!snd_hda_codec_configure(codec))
1293 success++;
1294 }
1295
1296 if (success) {
1297 /* unregister failed codecs if any codec has been probed */
1298 list_for_each_codec_safe(codec, next, &chip->bus) {
1299 if (!codec->configured) {
1300 codec_err(codec, "Unable to configure, disabling\n");
1301 snd_hdac_device_unregister(&codec->core);
1302 }
1303 }
1304 }
1305
1306 return success ? 0 : -ENODEV;
1307}
1308EXPORT_SYMBOL_GPL(azx_codec_configure);
1309
1310static int stream_direction(struct azx *chip, unsigned char index)
1311{
1312 if (index >= chip->capture_index_offset &&
1313 index < chip->capture_index_offset + chip->capture_streams)
1314 return SNDRV_PCM_STREAM_CAPTURE;
1315 return SNDRV_PCM_STREAM_PLAYBACK;
1316}
1317
1318/* initialize SD streams */
1319int azx_init_streams(struct azx *chip)
1320{
1321 int i;
1322 int stream_tags[2] = { 0, 0 };
1323
1324 /* initialize each stream (aka device)
1325 * assign the starting bdl address to each stream (device)
1326 * and initialize
1327 */
1328 for (i = 0; i < chip->num_streams; i++) {
1329 struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
1330 int dir, tag;
1331
1332 if (!azx_dev)
1333 return -ENOMEM;
1334
1335 dir = stream_direction(chip, i);
1336 /* stream tag must be unique throughout
1337 * the stream direction group,
1338 * valid values 1...15
1339 * use separate stream tag if the flag
1340 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
1341 */
1342 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1343 tag = ++stream_tags[dir];
1344 else
1345 tag = i + 1;
1346 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
1347 i, dir, tag);
1348 }
1349
1350 return 0;
1351}
1352EXPORT_SYMBOL_GPL(azx_init_streams);
1353
1354void azx_free_streams(struct azx *chip)
1355{
1356 struct hdac_bus *bus = azx_bus(chip);
1357 struct hdac_stream *s;
1358
1359 while (!list_empty(&bus->stream_list)) {
1360 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1361 list_del(&s->list);
1362 kfree(stream_to_azx_dev(s));
1363 }
1364}
1365EXPORT_SYMBOL_GPL(azx_free_streams);
Note: See TracBrowser for help on using the repository browser.