source: GPL/trunk/alsa-kernel/pci/ens1370.c@ 60

Last change on this file since 60 was 34, checked in by vladest, 20 years ago

Latest update from ALSA. some intial > 15 interrupts support
File size: 91.5 KB
Line 
1/*
2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 * Thomas Sailer <sailer@ife.ee.ethz.ch>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#define SNDRV_MAIN_OBJECT_FILE
23#include <sound/driver.h>
24#include <sound/control.h>
25#include <sound/pcm.h>
26#include <sound/rawmidi.h>
27#ifdef CHIP1371
28#include <sound/ac97_codec.h>
29#else
30#include <sound/ak4531_codec.h>
31#endif
32#define SNDRV_GET_ID
33#include <sound/initval.h>
34
35#ifndef CHIP1371
36#undef CHIP1370
37#define CHIP1370
38#endif
39
40#ifdef CHIP1370
41#define DRIVER_NAME "ENS1370"
42#else
43#define DRIVER_NAME "ENS1371"
44#endif
45
46
47MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
48MODULE_LICENSE("GPL");
49MODULE_CLASSES("{sound}");
50#ifdef CHIP1370
51MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
52MODULE_DEVICES("{{Ensoniq,AudioPCI-97 ES1370},"
53 "{Creative Labs,SB PCI64/128 (ES1370)}}");
54#endif
55#ifdef CHIP1371
56MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
57MODULE_DEVICES("{{Ensoniq,AudioPCI ES1371/73},"
58 "{Ensoniq,AudioPCI ES1373},"
59 "{Creative Labs,Ectiva EV1938},"
60 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
61 "{Creative Labs,Vibra PCI128},"
62 "{Ectiva,EV1938}}");
63#endif
64
65static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
66static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
67static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
68
69MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
70MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
71MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
72MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
73MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
74MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
75MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
76MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
77MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
78
79#include <dbgos2.h>
80
81#ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
82#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
83#endif
84#ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
85#define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
86#endif
87
88/* ES1371 chip ID */
89/* This is a little confusing because all ES1371 compatible chips have the
90 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
91 This is only significant if you want to enable features on the later parts.
92 Yes, I know it's stupid and why didn't we use the sub IDs?
93 */
94#define ES1371REV_ES1373_A 0x04
95#define ES1371REV_ES1373_B 0x06
96#define ES1371REV_CT5880_A 0x07
97#define CT5880REV_CT5880_C 0x02
98#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
99#define CT5880REV_CT5880_E 0x04 /* mw */
100#define ES1371REV_ES1371_B 0x09
101#define EV1938REV_EV1938_A 0x00
102#define ES1371REV_ES1373_8 0x08
103
104/*
105 * Direct registers
106 */
107
108#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
109
110#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
111#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
112#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
113#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
114#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
115#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
116#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
117#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
118#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
119#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24) /* joystick port mapping */
120#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
121#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
122#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f) /* GPIO in [3:0] pins - R/O */
123#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16) /* clock divide ratio for DAC2 */
124#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
125#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff) /* clock divide ratio for DAC2 */
126#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16) /* GPIO out [3:0] pins - W/R */
127#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
128#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
129#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
130#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
131#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12) /* fixed frequency clock for DAC1 */
132#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
133#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
134#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
135#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
136#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
137#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
138#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
139#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
140#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
141#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
142#define ES_BREQ (1<<7) /* memory bus request enable */
143#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
144#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
145#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
146#define ES_UART_EN (1<<3) /* UART enable */
147#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
148#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
149#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
150#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
151#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
152#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
153#define ES_INTR (1<<31) /* Interrupt is pending */
154#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
155#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
156#define ES_1373_REAR_BIT26 (1<<26)
157#define ES_1373_REAR_BIT24 (1<<24)
158#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
159#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
160#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
161#define ES_1371_TEST (1<<16) /* test ASIC */
162#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
163#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
164#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
165#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
166#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
167#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
168#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
169#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
170#define ES_MCCB (1<<4) /* CCB interrupt pending */
171#define ES_UART (1<<3) /* UART interrupt pending */
172#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
173#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
174#define ES_ADC (1<<0) /* ADC channel interrupt pending */
175#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
176#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
177#define ES_RXINT (1<<7) /* RX interrupt occurred */
178#define ES_TXINT (1<<2) /* TX interrupt occurred */
179#define ES_TXRDY (1<<1) /* transmitter ready */
180#define ES_RXRDY (1<<0) /* receiver ready */
181#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
182#define ES_RXINTEN (1<<7) /* RX interrupt enable */
183#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
184#define ES_TXINTENM (0x03<<5) /* mask for above */
185#define ES_TXINTENI(i) (((i)>>5)&0x03)
186#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
187#define ES_CNTRLM (0x03<<0) /* mask for above */
188#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
189#define ES_TEST_MODE (1<<0) /* test mode enabled */
190#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
191#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
192#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
193#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
194#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
195#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
196#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
197#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
198#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
199#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
200#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
201#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
202#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
203
204#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
205#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25) /* address of the sample rate converter */
206#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
207#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f) /* address of the sample rate converter */
208#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
209#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
210#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
211#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
212#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
213#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
214#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0) /* current value of the sample rate converter */
215#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
216#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff) /* current value of the sample rate converter */
217
218#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
219#define ES_1371_JFAST (1<<31) /* fast joystick timing */
220#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
221#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
222#define ES_1371_VMPUO(o) (((o)&0x03)<<27) /* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
223#define ES_1371_VMPUM (0x03<<27) /* mask for above */
224#define ES_1371_VMPUI(i) (((i)>>27)&0x03) /* base register address */
225#define ES_1371_VCDCO(o) (((o)&0x03)<<25) /* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
226#define ES_1371_VCDCM (0x03<<25) /* mask for above */
227#define ES_1371_VCDCI(i) (((i)>>25)&0x03) /* CODEC address */
228#define ES_1371_FIRQ (1<<24) /* force an interrupt */
229#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
230#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
231#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
232#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
233#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
234#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
235#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
236#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
237#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
238#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
239#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
240#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
241
242#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
243
244#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
245#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
246#define ES_P2_END_INCO(o) (((o)&0x07)<<19) /* binary offset value to increment / loop end */
247#define ES_P2_END_INCM (0x07<<19) /* mask for above */
248#define ES_P2_END_INCI(i) (((i)>>16)&0x07) /* binary offset value to increment / loop end */
249#define ES_P2_ST_INCO(o) (((o)&0x07)<<16) /* binary offset value to increment / start */
250#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
251#define ES_P2_ST_INCI(i) (((i)<<16)&0x07) /* binary offset value to increment / start */
252#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
253#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
254#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
255#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
256#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
257#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
258#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
259#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
260#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
261#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
262#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
263#define ES_R1_MODEM (0x03<<4) /* mask for above */
264#define ES_R1_MODEI(i) (((i)>>4)&0x03)
265#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
266#define ES_P2_MODEM (0x03<<2) /* mask for above */
267#define ES_P2_MODEI(i) (((i)>>2)&0x03)
268#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
269#define ES_P1_MODEM (0x03<<0) /* mask for above */
270#define ES_P1_MODEI(i) (((i)>>0)&0x03)
271
272#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
273#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
274#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
275#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
276#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
277#define ES_REG_COUNTM (0xffff<<0)
278#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
279
280#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
281#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
282#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
283#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
284#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
285#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
286#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
287#define ES_REG_FCURR_COUNTM (0xffff<<16)
288#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
289#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
290#define ES_REG_FSIZEM (0xffff<<0)
291#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
292#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
293#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
294
295#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
296#define ES_REG_UF_VALID (1<<8)
297#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
298#define ES_REG_UF_BYTEM (0xff<<0)
299#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
300
301
302/*
303 * Pages
304 */
305
306#define ES_PAGE_DAC 0x0c
307#define ES_PAGE_ADC 0x0d
308#define ES_PAGE_UART 0x0e
309#define ES_PAGE_UART1 0x0f
310
311/*
312 * Sample rate converter addresses
313 */
314
315#define ES_SMPREG_DAC1 0x70
316#define ES_SMPREG_DAC2 0x74
317#define ES_SMPREG_ADC 0x78
318#define ES_SMPREG_VOL_ADC 0x6c
319#define ES_SMPREG_VOL_DAC1 0x7c
320#define ES_SMPREG_VOL_DAC2 0x7e
321#define ES_SMPREG_TRUNC_N 0x00
322#define ES_SMPREG_INT_REGS 0x01
323#define ES_SMPREG_ACCUM_FRAC 0x02
324#define ES_SMPREG_VFREQ_FRAC 0x03
325
326/*
327 * Some contants
328 */
329
330#define ES_1370_SRCLOCK 1411200
331#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
332
333/*
334 * Open modes
335 */
336
337#define ES_MODE_PLAY1 0x0001
338#define ES_MODE_PLAY2 0x0002
339#define ES_MODE_CAPTURE 0x0004
340
341#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
342#define ES_MODE_INPUT 0x0002 /* for MIDI */
343
344/*
345
346*/
347
348typedef struct _snd_ensoniq ensoniq_t;
349
350struct _snd_ensoniq {
351 spinlock_t reg_lock;
352 struct semaphore src_mutex;
353
354 int irq;
355
356 unsigned long playback1size;
357 unsigned long playback2size;
358 unsigned long capture3size;
359
360 unsigned long port;
361 unsigned int mode;
362 unsigned int uartm; /* UART mode */
363
364 unsigned int ctrl; /* control register */
365 unsigned int sctrl; /* serial control register */
366 unsigned int cssr; /* control status register */
367 unsigned int uartc; /* uart control register */
368 unsigned int rev; /* chip revision */
369
370 union {
371#ifdef CHIP1371
372 struct {
373 ac97_t *ac97;
374 } es1371;
375#else
376 struct {
377 int pclkdiv_lock;
378 ak4531_t *ak4531;
379 } es1370;
380#endif
381 } u;
382
383 struct pci_dev *pci;
384 unsigned short subsystem_vendor_id;
385 unsigned short subsystem_device_id;
386 snd_card_t *card;
387 snd_pcm_t *pcm1; /* DAC1/ADC PCM */
388 snd_pcm_t *pcm2; /* DAC2 PCM */
389 snd_pcm_substream_t *playback1_substream;
390 snd_pcm_substream_t *playback2_substream;
391 snd_pcm_substream_t *capture_substream;
392 unsigned int p1_dma_size;
393 unsigned int p2_dma_size;
394 unsigned int c_dma_size;
395 unsigned int p1_period_size;
396 unsigned int p2_period_size;
397 unsigned int c_period_size;
398 snd_rawmidi_t *rmidi;
399 snd_rawmidi_substream_t *midi_input;
400 snd_rawmidi_substream_t *midi_output;
401
402 unsigned int spdif;
403 unsigned int spdif_default;
404 unsigned int spdif_stream;
405
406#ifdef CHIP1370
407 struct snd_dma_buffer dma_bug;
408#endif
409
410#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
411 struct gameport gameport;
412 struct semaphore joy_sem; // gameport configuration semaphore
413#endif
414};
415
416static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
417
418static struct pci_device_id snd_audiopci_ids[] = {
419#ifdef CHIP1370
420 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */
421#endif
422#ifdef CHIP1371
423 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */
424 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */
425 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */
426#endif
427 { 0, }
428};
429
430MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
431
432/*
433 * constants
434 */
435
436#define POLL_COUNT 0xa000
437
438#ifdef CHIP1370
439static unsigned int snd_es1370_fixed_rates[] =
440{5512, 11025, 22050, 44100};
441
442static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
443 4,
444 snd_es1370_fixed_rates,
445 0
446};
447static ratnum_t es1370_clock = {
448 ES_1370_SRCLOCK,
449 29,
450 353,
451 1
452};
453static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
454 1,
455 &es1370_clock
456};
457#else
458static ratden_t es1371_dac_clock = {
459 3000 * 32768, /* num_min */
460 48000 * 32768, /* num_max */
461 3000, /* num_step */
462 32768 /* den */
463};
464static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
465 1,
466 &es1371_dac_clock
467};
468static ratnum_t es1371_adc_clock = {
469 48000 << 15,
470 32768,
471 393216,
472 1
473};
474static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
475 1,
476 &es1371_adc_clock
477};
478#endif
479static const unsigned int snd_ensoniq_sample_shift[] =
480{0, 1, 1, 2};
481
482/*
483 * common I/O routines
484 */
485
486#ifdef CHIP1371
487
488static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
489{
490 unsigned int t, r = 0;
491
492 for (t = 0; t < POLL_COUNT; t++) {
493 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
494 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
495 return r;
496 cond_resched();
497 }
498 snd_printk("wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
499 return 0;
500}
501
502static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
503{
504 unsigned int temp, i, orig, r;
505
506 /* wait for ready */
507 temp = orig = snd_es1371_wait_src_ready(ensoniq);
508
509 /* expose the SRC state bits */
510 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
511 ES_1371_DIS_P2 | ES_1371_DIS_R1);
512 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
513 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
514
515 /* now, wait for busy and the correct time to read */
516 temp = snd_es1371_wait_src_ready(ensoniq);
517
518 if ((temp & 0x00870000) != 0x00010000) {
519 /* wait for the right state */
520 for (i = 0; i < POLL_COUNT; i++) {
521 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
522 if ((temp & 0x00870000) == 0x00010000)
523 break;
524 }
525 }
526
527 /* hide the state bits */
528 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
529 ES_1371_DIS_P2 | ES_1371_DIS_R1);
530 r |= ES_1371_SRC_RAM_ADDRO(reg);
531 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
532
533 return temp;
534}
535
536static void snd_es1371_src_write(ensoniq_t * ensoniq,
537 unsigned short reg, unsigned short data)
538{
539 unsigned int r;
540
541 r = snd_es1371_wait_src_ready(ensoniq) &
542 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
543 ES_1371_DIS_P2 | ES_1371_DIS_R1);
544 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
545 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
546}
547
548#endif /* CHIP1371 */
549
550#ifdef CHIP1370
551
552static void snd_es1370_codec_write(ak4531_t *ak4531,
553 unsigned short reg, unsigned short val)
554{
555 ensoniq_t *ensoniq = ak4531->private_data;
556 unsigned long end_time = jiffies + HZ / 10;
557
558#if 0
559 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
560#endif
561 do {
562 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
563 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
564 return;
565 }
566 set_current_state(TASK_UNINTERRUPTIBLE);
567 schedule_timeout(1);
568 } while (time_after(end_time, jiffies));
569 snd_printk("codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
570}
571
572#endif /* CHIP1370 */
573
574#ifdef CHIP1371
575
576static void snd_es1371_codec_write(ac97_t *ac97,
577 unsigned short reg, unsigned short val)
578{
579 ensoniq_t *ensoniq = ac97->private_data;
580 unsigned int t, x;
581
582 down(&ensoniq->src_mutex);
583 for (t = 0; t < POLL_COUNT; t++) {
584 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
585 /* save the current state for latter */
586 x = snd_es1371_wait_src_ready(ensoniq);
587 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
588 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
589 ES_REG(ensoniq, 1371_SMPRATE));
590 /* wait for not busy (state 0) first to avoid
591 transition states */
592 for (t = 0; t < POLL_COUNT; t++) {
593 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
594 break;
595 }
596 /* wait for a SAFE time to write addr/data and then do it, dammit */
597 for (t = 0; t < POLL_COUNT; t++) {
598 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
599 break;
600 }
601 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
602 /* restore SRC reg */
603 snd_es1371_wait_src_ready(ensoniq);
604 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
605 up(&ensoniq->src_mutex);
606 return;
607 }
608 }
609 up(&ensoniq->src_mutex);
610 snd_printk("codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
611}
612
613static unsigned short snd_es1371_codec_read(ac97_t *ac97,
614 unsigned short reg)
615{
616 ensoniq_t *ensoniq = ac97->private_data;
617 unsigned int t, x, fail = 0;
618
619__again:
620 down(&ensoniq->src_mutex);
621 for (t = 0; t < POLL_COUNT; t++) {
622 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
623 /* save the current state for latter */
624 x = snd_es1371_wait_src_ready(ensoniq);
625 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
626 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
627 ES_REG(ensoniq, 1371_SMPRATE));
628 /* wait for not busy (state 0) first to avoid
629 transition states */
630 for (t = 0; t < POLL_COUNT; t++) {
631 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
632 break;
633 }
634 /* wait for a SAFE time to write addr/data and then do it, dammit */
635 for (t = 0; t < POLL_COUNT; t++) {
636 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
637 break;
638 }
639 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
640 /* restore SRC reg */
641 snd_es1371_wait_src_ready(ensoniq);
642 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
643 /* wait for WIP again */
644 for (t = 0; t < POLL_COUNT; t++) {
645 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
646 break;
647 }
648 /* now wait for the stinkin' data (RDY) */
649 for (t = 0; t < POLL_COUNT; t++) {
650 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
651 up(&ensoniq->src_mutex);
652 return ES_1371_CODEC_READ(x);
653 }
654 }
655 up(&ensoniq->src_mutex);
656 if (++fail > 10) {
657 snd_printk("codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
658 return 0;
659 }
660 goto __again;
661 }
662 }
663 up(&ensoniq->src_mutex);
664 snd_printk("es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
665 return 0;
666}
667
668static void snd_es1371_codec_wait(ac97_t *ac97)
669{
670 msleep(750);
671 snd_es1371_codec_read(ac97, AC97_RESET);
672 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
673 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
674 msleep(50);
675}
676
677static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
678{
679 unsigned int n, truncm, freq, result;
680
681 down(&ensoniq->src_mutex);
682 n = rate / 3000;
683 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
684 n--;
685 truncm = (21 * n - 1) | 1;
686 freq = ((48000UL << 15) / rate) * n;
687 result = (48000UL << 15) / (freq / n);
688 if (rate >= 24000) {
689 if (truncm > 239)
690 truncm = 239;
691 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
692 (((239 - truncm) >> 1) << 9) | (n << 4));
693 } else {
694 if (truncm > 119)
695 truncm = 119;
696 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
697 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
698 }
699 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
700 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
701 ((freq >> 5) & 0xfc00));
702 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
703 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
704 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
705 up(&ensoniq->src_mutex);
706}
707
708static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
709{
710 unsigned int freq, r;
711
712 down(&ensoniq->src_mutex);
713 freq = ((rate << 15) + 1500) / 3000;
714 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
715 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
716 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
717 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
718 ((freq >> 5) & 0xfc00));
719 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
720 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
721 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
722 up(&ensoniq->src_mutex);
723}
724
725static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
726{
727 unsigned int freq, r;
728
729 down(&ensoniq->src_mutex);
730 freq = ((rate << 15) + 1500) / 3000;
731 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
732 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
733 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
734 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
735 ((freq >> 5) & 0xfc00));
736 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
737 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
738 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
739 up(&ensoniq->src_mutex);
740}
741
742#endif /* CHIP1371 */
743
744static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
745{
746 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
747 switch (cmd) {
748 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
749 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
750 {
751 unsigned int what = 0;
752 struct list_head *pos;
753 snd_pcm_substream_t *s;
754 snd_pcm_group_for_each(pos, substream) {
755 s = snd_pcm_group_substream_entry(pos);
756 if (s == ensoniq->playback1_substream) {
757 what |= ES_P1_PAUSE;
758 snd_pcm_trigger_done(s, substream);
759 } else if (s == ensoniq->playback2_substream) {
760 what |= ES_P2_PAUSE;
761 snd_pcm_trigger_done(s, substream);
762 } else if (s == ensoniq->capture_substream)
763 return -EINVAL;
764 }
765 spin_lock(&ensoniq->reg_lock);
766 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
767 ensoniq->sctrl |= what;
768 else
769 ensoniq->sctrl &= ~what;
770 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
771 spin_unlock(&ensoniq->reg_lock);
772 break;
773 }
774 case SNDRV_PCM_TRIGGER_START:
775 case SNDRV_PCM_TRIGGER_STOP:
776 {
777 unsigned int what = 0;
778 struct list_head *pos;
779 snd_pcm_substream_t *s;
780 snd_pcm_group_for_each(pos, substream) {
781 s = snd_pcm_group_substream_entry(pos);
782 if (s == ensoniq->playback1_substream) {
783 what |= ES_DAC1_EN;
784 snd_pcm_trigger_done(s, substream);
785 } else if (s == ensoniq->playback2_substream) {
786 what |= ES_DAC2_EN;
787 snd_pcm_trigger_done(s, substream);
788 } else if (s == ensoniq->capture_substream) {
789 what |= ES_ADC_EN;
790 snd_pcm_trigger_done(s, substream);
791 }
792 }
793 spin_lock(&ensoniq->reg_lock);
794 if (cmd == SNDRV_PCM_TRIGGER_START)
795 ensoniq->ctrl |= what;
796 else
797 ensoniq->ctrl &= ~what;
798 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
799 spin_unlock(&ensoniq->reg_lock);
800 break;
801 }
802 default:
803 return -EINVAL;
804 }
805 return 0;
806}
807
808/*
809 * PCM part
810 */
811
812static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
813 snd_pcm_hw_params_t * hw_params)
814{
815 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
816}
817
818static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
819{
820 return snd_pcm_lib_free_pages(substream);
821}
822
823static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
824{
825 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
826 snd_pcm_runtime_t *runtime = substream->runtime;
827 unsigned int mode = 0;
828
829#ifdef DEBUG
830 dprintf(("snd_ensoniq_playback1_prepare"));
831#endif
832
833 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
834 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
835 if (snd_pcm_format_width(runtime->format) == 16)
836 mode |= 0x02;
837 if (runtime->channels > 1)
838 mode |= 0x01;
839 spin_lock_irq(&ensoniq->reg_lock);
840 ensoniq->ctrl &= ~ES_DAC1_EN;
841#ifdef CHIP1371
842 /* 48k doesn't need SRC (it breaks AC3-passthru) */
843 if (runtime->rate == 48000)
844 ensoniq->ctrl |= ES_1373_BYPASS_P1;
845 else
846 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
847#endif
848 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
849 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
850 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
851 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
852 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
853 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
854 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
855 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
856#ifdef CHIP1370
857 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
858 switch (runtime->rate) {
859 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
860 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
861 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
862 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
863 default: snd_BUG();
864 }
865#endif
866 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
867 spin_unlock_irq(&ensoniq->reg_lock);
868#ifndef CHIP1370
869 snd_es1371_dac1_rate(ensoniq, runtime->rate);
870#endif
871 return 0;
872}
873
874static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
875{
876 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
877 snd_pcm_runtime_t *runtime = substream->runtime;
878 unsigned int mode = 0;
879
880#ifdef DEBUG
881 dprintf(("snd_ensoniq_playback2_prepare"));
882#endif
883 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
884 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
885 if (snd_pcm_format_width(runtime->format) == 16)
886 mode |= 0x02;
887 if (runtime->channels > 1)
888 mode |= 0x01;
889 spin_lock_irq(&ensoniq->reg_lock);
890 ensoniq->ctrl &= ~ES_DAC2_EN;
891 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
892 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
893 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
894 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
895 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
896 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
897 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
898 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
899 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
900 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
901#ifdef CHIP1370
902 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
903 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
904 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
905 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
906 }
907#endif
908 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
909 spin_unlock_irq(&ensoniq->reg_lock);
910#ifndef CHIP1370
911 snd_es1371_dac2_rate(ensoniq, runtime->rate);
912#endif
913 return 0;
914}
915
916static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
917{
918 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
919 snd_pcm_runtime_t *runtime = substream->runtime;
920 unsigned int mode = 0;
921
922 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
923 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
924 if (snd_pcm_format_width(runtime->format) == 16)
925 mode |= 0x02;
926 if (runtime->channels > 1)
927 mode |= 0x01;
928 spin_lock_irq(&ensoniq->reg_lock);
929 ensoniq->ctrl &= ~ES_ADC_EN;
930 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
931 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
932 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
933 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
934 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
935 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
936 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
937 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
938#ifdef CHIP1370
939 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
940 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
941 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
942 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
943 }
944#endif
945 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
946 spin_unlock_irq(&ensoniq->reg_lock);
947#ifndef CHIP1370
948 snd_es1371_adc_rate(ensoniq, runtime->rate);
949#endif
950 return 0;
951}
952
953static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
954{
955 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
956 size_t ptr;
957
958 spin_lock(&ensoniq->reg_lock);
959 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
960 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
961 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
962 ptr = bytes_to_frames(substream->runtime, ptr);
963 } else {
964 ptr = 0;
965 }
966 spin_unlock(&ensoniq->reg_lock);
967 return ptr;
968}
969
970static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
971{
972 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
973 size_t ptr;
974
975 spin_lock(&ensoniq->reg_lock);
976 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
977 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
978 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
979 ptr = bytes_to_frames(substream->runtime, ptr);
980 } else {
981 ptr = 0;
982 }
983 spin_unlock(&ensoniq->reg_lock);
984 return ptr;
985}
986
987static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
988{
989 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
990 size_t ptr;
991
992 spin_lock(&ensoniq->reg_lock);
993 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
994 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
995 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
996 ptr = bytes_to_frames(substream->runtime, ptr);
997 } else {
998 ptr = 0;
999 }
1000 spin_unlock(&ensoniq->reg_lock);
1001 return ptr;
1002}
1003
1004static snd_pcm_hardware_t snd_ensoniq_playback1 =
1005{
1006 /* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1007 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1008 SNDRV_PCM_INFO_MMAP_VALID |
1009 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1010 /* formats: */ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1011 /* rates: */
1012#ifndef CHIP1370
1013 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1014#else
1015 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1016 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1017 SNDRV_PCM_RATE_44100),
1018#endif
1019 /* rate_min: */ 4000,
1020 /* rate_max: */ 48000,
1021 /* channels_min: */ 1,
1022 /* channels_max: */ 2,
1023 /* buffer_bytes_max: */ (128*1024),
1024 /* period_bytes_min: */ 64,
1025 /* period_bytes_max: */ (128*1024),
1026 /* periods_min: */ 1,
1027 /* periods_max: */ 1024,
1028 /* fifo_size: */ 0
1029};
1030
1031static snd_pcm_hardware_t snd_ensoniq_playback2 =
1032{
1033 /* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1034 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1035 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1036 SNDRV_PCM_INFO_SYNC_START),
1037 /* formats: */ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1038 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1039 /* rate_min: */ 4000,
1040 /* rate_max: */ 48000,
1041 /* channels_min: */ 1,
1042 /* channels_max: */ 2,
1043 /* buffer_bytes_max: */ (128*1024),
1044 /* period_bytes_min: */ 64,
1045 /* period_bytes_max: */ (128*1024),
1046 /* periods_min: */ 1,
1047 /* periods_max: */ 1024,
1048 /* fifo_size: */ 0
1049};
1050
1051static snd_pcm_hardware_t snd_ensoniq_capture =
1052{
1053 /* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1054 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1055 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1056 /* formats: */ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1057 /* rates: */ SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1058 /* rate_min: */ 4000,
1059 /* rate_max: */ 48000,
1060 /* channels_min: */ 1,
1061 /* channels_max: */ 2,
1062 /* buffer_bytes_max: */ (128*1024),
1063 /* period_bytes_min: */ 64,
1064 /* period_bytes_max: */ (128*1024),
1065 /* periods_min: */ 1,
1066 /* periods_max: */ 1024,
1067 /* fifo_size: */ 0,
1068};
1069
1070static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1071{
1072 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1073 snd_pcm_runtime_t *runtime = substream->runtime;
1074
1075#ifdef DEBUG
1076 dprintf(("snd_ensoniq_playback1_open"));
1077#endif
1078
1079 ensoniq->mode |= ES_MODE_PLAY1;
1080 ensoniq->playback1_substream = substream;
1081 runtime->hw = snd_ensoniq_playback1;
1082 snd_pcm_set_sync(substream);
1083 spin_lock_irq(&ensoniq->reg_lock);
1084 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1085 ensoniq->spdif_stream = ensoniq->spdif_default;
1086 spin_unlock_irq(&ensoniq->reg_lock);
1087#ifdef CHIP1370
1088 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1089 &snd_es1370_hw_constraints_rates);
1090#else
1091 // snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1092 // &snd_es1371_hw_constraints_dac_clock);
1093#endif
1094 return 0;
1095}
1096
1097static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1098{
1099 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1100 snd_pcm_runtime_t *runtime = substream->runtime;
1101
1102#ifdef DEBUG
1103 dprintf(("snd_ensoniq_playback2_open"));
1104#endif
1105 ensoniq->mode |= ES_MODE_PLAY2;
1106 ensoniq->playback2_substream = substream;
1107 runtime->hw = snd_ensoniq_playback2;
1108 snd_pcm_set_sync(substream);
1109 spin_lock_irq(&ensoniq->reg_lock);
1110 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1111 ensoniq->spdif_stream = ensoniq->spdif_default;
1112 spin_unlock_irq(&ensoniq->reg_lock);
1113#ifdef CHIP1370
1114 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1115 &snd_es1370_hw_constraints_clock);
1116#else
1117 // snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1118 // &snd_es1371_hw_constraints_dac_clock);
1119#endif
1120 return 0;
1121}
1122
1123static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1124{
1125 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1126 snd_pcm_runtime_t *runtime = substream->runtime;
1127
1128 ensoniq->mode |= ES_MODE_CAPTURE;
1129 ensoniq->capture_substream = substream;
1130 runtime->hw = snd_ensoniq_capture;
1131 snd_pcm_set_sync(substream);
1132#ifdef CHIP1370
1133 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1134 &snd_es1370_hw_constraints_clock);
1135#else
1136 // snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1137 // &snd_es1371_hw_constraints_adc_clock);
1138#endif
1139 return 0;
1140}
1141
1142static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1143{
1144 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1145
1146 ensoniq->playback1_substream = NULL;
1147 ensoniq->mode &= ~ES_MODE_PLAY1;
1148 return 0;
1149}
1150
1151static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1152{
1153 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1154
1155 ensoniq->playback2_substream = NULL;
1156 spin_lock_irq(&ensoniq->reg_lock);
1157#ifdef CHIP1370
1158 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1159#endif
1160 ensoniq->mode &= ~ES_MODE_PLAY2;
1161 spin_unlock_irq(&ensoniq->reg_lock);
1162 return 0;
1163}
1164
1165static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1166{
1167 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1168
1169 ensoniq->capture_substream = NULL;
1170 spin_lock_irq(&ensoniq->reg_lock);
1171#ifdef CHIP1370
1172 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1173#endif
1174 ensoniq->mode &= ~ES_MODE_CAPTURE;
1175 spin_unlock_irq(&ensoniq->reg_lock);
1176 return 0;
1177}
1178
1179static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1180 /* open: */ snd_ensoniq_playback1_open,
1181 /* close: */ snd_ensoniq_playback1_close,
1182 /* ioctl: */ snd_pcm_lib_ioctl,
1183 /* hw_params:*/ snd_ensoniq_hw_params,
1184 /* hw_free: */ snd_ensoniq_hw_free,
1185 /* prepare: */ snd_ensoniq_playback1_prepare,
1186 /* trigger: */ snd_ensoniq_trigger,
1187 /* pointer: */ snd_ensoniq_playback1_pointer,
1188 0, 0
1189};
1190
1191static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1192 /* open: */ snd_ensoniq_playback2_open,
1193 /* close: */ snd_ensoniq_playback2_close,
1194 /* ioctl: */ snd_pcm_lib_ioctl,
1195 /* hw_params:*/ snd_ensoniq_hw_params,
1196 /* hw_free: */ snd_ensoniq_hw_free,
1197 /* prepare: */ snd_ensoniq_playback2_prepare,
1198 /* trigger: */ snd_ensoniq_trigger,
1199 /* pointer: */ snd_ensoniq_playback2_pointer,
1200 0, 0
1201};
1202
1203static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1204 /* open: */ snd_ensoniq_capture_open,
1205 /* close: */ snd_ensoniq_capture_close,
1206 /* ioctl: */ snd_pcm_lib_ioctl,
1207 /* hw_params:*/ snd_ensoniq_hw_params,
1208 /* hw_free: */ snd_ensoniq_hw_free,
1209 /* prepare: */ snd_ensoniq_capture_prepare,
1210 /* trigger: */ snd_ensoniq_trigger,
1211 /* pointer: */ snd_ensoniq_capture_pointer,
1212 0, 0
1213};
1214
1215static void snd_ensoniq_pcm_free(snd_pcm_t *pcm)
1216{
1217 ensoniq_t *ensoniq = pcm->private_data;
1218 ensoniq->pcm1 = NULL;
1219 snd_pcm_lib_preallocate_free_for_all(pcm);
1220}
1221
1222static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1223{
1224 snd_pcm_t *pcm;
1225 int err;
1226
1227 if (rpcm)
1228 *rpcm = NULL;
1229#ifdef DEBUG
1230 dprintf(("snd_ensoniq_pcm"));
1231#endif
1232
1233#ifdef CHIP1370
1234 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1235#else
1236 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1237#endif
1238 if (err < 0)
1239 {
1240#ifdef DEBUG
1241 dprintf(("snd_ensoniq_pcm error"));
1242#endif
1243 return err;
1244 }
1245
1246#ifdef CHIP1370
1247 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1248#else
1249 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1250#endif
1251 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1252
1253 pcm->private_data = ensoniq;
1254 pcm->private_free = snd_ensoniq_pcm_free;
1255 pcm->info_flags = 0;
1256#ifdef CHIP1370
1257 strcpy(pcm->name, "ES1370 DAC2/ADC");
1258#else
1259 strcpy(pcm->name, "ES1371 DAC2/ADC");
1260#endif
1261 ensoniq->pcm1 = pcm;
1262
1263 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1264 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1265
1266 if (rpcm)
1267 *rpcm = pcm;
1268 return 0;
1269}
1270
1271static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm)
1272{
1273 ensoniq_t *ensoniq = pcm->private_data;
1274 ensoniq->pcm2 = NULL;
1275 snd_pcm_lib_preallocate_free_for_all(pcm);
1276}
1277
1278static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1279{
1280 snd_pcm_t *pcm;
1281 int err;
1282
1283#ifdef DEBUG
1284 dprintf(("snd_ensoniq_pcm2"));
1285#endif
1286
1287 if (rpcm)
1288 *rpcm = NULL;
1289#ifdef CHIP1370
1290 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1291#else
1292 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1293#endif
1294 if (err < 0)
1295 return err;
1296
1297#ifdef CHIP1370
1298 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1299#else
1300 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1301#endif
1302 pcm->private_data = ensoniq;
1303 pcm->private_free = snd_ensoniq_pcm_free2;
1304 pcm->info_flags = 0;
1305#ifdef CHIP1370
1306 strcpy(pcm->name, "ES1370 DAC1");
1307#else
1308 strcpy(pcm->name, "ES1371 DAC1");
1309#endif
1310 ensoniq->pcm2 = pcm;
1311
1312 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1313 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1314
1315 if (rpcm)
1316 *rpcm = pcm;
1317 return 0;
1318}
1319
1320/*
1321 * Mixer section
1322 */
1323
1324/*
1325 * ENS1371 mixer (including SPDIF interface)
1326 */
1327#ifdef CHIP1371
1328static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1329{
1330 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1331 uinfo->count = 1;
1332 return 0;
1333}
1334
1335static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1336 snd_ctl_elem_value_t * ucontrol)
1337{
1338 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1339 spin_lock_irq(&ensoniq->reg_lock);
1340 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1341 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1342 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1343 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1344 spin_unlock_irq(&ensoniq->reg_lock);
1345 return 0;
1346}
1347
1348static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1349 snd_ctl_elem_value_t * ucontrol)
1350{
1351 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1352 unsigned int val;
1353 int change;
1354
1355 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1356 ((u32)ucontrol->value.iec958.status[1] << 8) |
1357 ((u32)ucontrol->value.iec958.status[2] << 16) |
1358 ((u32)ucontrol->value.iec958.status[3] << 24);
1359 spin_lock_irq(&ensoniq->reg_lock);
1360 change = ensoniq->spdif_default != val;
1361 ensoniq->spdif_default = val;
1362 if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1363 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1364 spin_unlock_irq(&ensoniq->reg_lock);
1365 return change;
1366}
1367
1368static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1369 snd_ctl_elem_value_t * ucontrol)
1370{
1371 ucontrol->value.iec958.status[0] = 0xff;
1372 ucontrol->value.iec958.status[1] = 0xff;
1373 ucontrol->value.iec958.status[2] = 0xff;
1374 ucontrol->value.iec958.status[3] = 0xff;
1375 return 0;
1376}
1377
1378static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1379 snd_ctl_elem_value_t * ucontrol)
1380{
1381 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1382 spin_lock_irq(&ensoniq->reg_lock);
1383 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1384 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1385 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1386 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1387 spin_unlock_irq(&ensoniq->reg_lock);
1388 return 0;
1389}
1390
1391static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1392 snd_ctl_elem_value_t * ucontrol)
1393{
1394 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1395 unsigned int val;
1396 int change;
1397
1398 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1399 ((u32)ucontrol->value.iec958.status[1] << 8) |
1400 ((u32)ucontrol->value.iec958.status[2] << 16) |
1401 ((u32)ucontrol->value.iec958.status[3] << 24);
1402 spin_lock_irq(&ensoniq->reg_lock);
1403 change = ensoniq->spdif_stream != val;
1404 ensoniq->spdif_stream = val;
1405 if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1406 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1407 spin_unlock_irq(&ensoniq->reg_lock);
1408 return change;
1409}
1410
1411static snd_kcontrol_new_t snd_ens1373_spdif_default __devinitdata =
1412{
1413 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
1414 SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1415 0,0,0,
1416 snd_ens1373_spdif_info,
1417 snd_ens1373_spdif_default_get,
1418 snd_ens1373_spdif_default_put,0
1419};
1420
1421static snd_kcontrol_new_t snd_ens1373_spdif_mask __devinitdata =
1422{
1423 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
1424 SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1425 0,
1426 SNDRV_CTL_ELEM_ACCESS_READ,0,
1427 snd_ens1373_spdif_info,
1428 snd_ens1373_spdif_mask_get,0,0
1429};
1430
1431static snd_kcontrol_new_t snd_ens1373_spdif_stream __devinitdata =
1432{
1433 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
1434 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1435 0,0,0,
1436 snd_ens1373_spdif_info,
1437 snd_ens1373_spdif_stream_get,
1438 snd_ens1373_spdif_stream_put,0
1439};
1440
1441#define ES1371_SPDIF(xname) \
1442 { SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, 0, 0, 0, snd_es1371_spdif_info, \
1443 snd_es1371_spdif_get, snd_es1371_spdif_put, 0 }
1444
1445static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1446{
1447 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1448 uinfo->count = 1;
1449 uinfo->value.integer.min = 0;
1450 uinfo->value.integer.max = 1;
1451 return 0;
1452}
1453
1454static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1455{
1456 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1457
1458 spin_lock_irq(&ensoniq->reg_lock);
1459 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1460 spin_unlock_irq(&ensoniq->reg_lock);
1461 return 0;
1462}
1463
1464static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1465{
1466 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1467 unsigned int nval1, nval2;
1468 int change;
1469
1470 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1471 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1472 spin_lock_irq(&ensoniq->reg_lock);
1473 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1474 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1475 ensoniq->ctrl |= nval1;
1476 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1477 ensoniq->cssr |= nval2;
1478 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1479 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1480 spin_unlock_irq(&ensoniq->reg_lock);
1481 return change;
1482}
1483
1484/* spdif controls */
1485static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = {
1486 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1487 {
1488 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1489 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1490 .info = snd_ens1373_spdif_info,
1491 .get = snd_ens1373_spdif_default_get,
1492 .put = snd_ens1373_spdif_default_put,
1493 },
1494 {
1495 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1496 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1497 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1498 .info = snd_ens1373_spdif_info,
1499 .get = snd_ens1373_spdif_mask_get
1500 },
1501 {
1502 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1503 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1504 .info = snd_ens1373_spdif_info,
1505 .get = snd_ens1373_spdif_stream_get,
1506 .put = snd_ens1373_spdif_stream_put
1507 },
1508};
1509
1510static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1511{
1512 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1513 uinfo->count = 1;
1514 uinfo->value.integer.min = 0;
1515 uinfo->value.integer.max = 1;
1516 return 0;
1517}
1518
1519static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1520{
1521 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1522 int val = 0;
1523
1524 spin_lock_irq(&ensoniq->reg_lock);
1525 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1526 val = 1;
1527 ucontrol->value.integer.value[0] = val;
1528 spin_unlock_irq(&ensoniq->reg_lock);
1529 return 0;
1530}
1531
1532static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1533{
1534 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1535 unsigned int nval1;
1536 int change;
1537
1538 nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1539 spin_lock_irq(&ensoniq->reg_lock);
1540 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1541 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1542 ensoniq->cssr |= nval1;
1543 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1544 spin_unlock_irq(&ensoniq->reg_lock);
1545 return change;
1546}
1547
1548static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1549{
1550 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
1551 "AC97 2ch->4ch Copy Switch",0,0,0,
1552 snd_es1373_rear_info,
1553 snd_es1373_rear_get,
1554 snd_es1373_rear_put,0
1555};
1556
1557static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1558{
1559 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1560 uinfo->count = 1;
1561 uinfo->value.integer.min = 0;
1562 uinfo->value.integer.max = 1;
1563 return 0;
1564}
1565
1566static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1567{
1568 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1569 int val = 0;
1570
1571 spin_lock_irq(&ensoniq->reg_lock);
1572 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1573 val = 1;
1574 ucontrol->value.integer.value[0] = val;
1575 spin_unlock_irq(&ensoniq->reg_lock);
1576 return 0;
1577}
1578
1579static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1580{
1581 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1582 int changed;
1583 unsigned int ctrl;
1584
1585 spin_lock_irq(&ensoniq->reg_lock);
1586 ctrl = ensoniq->ctrl;
1587 if (ucontrol->value.integer.value[0])
1588 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1589 else
1590 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1591 changed = (ctrl != ensoniq->ctrl);
1592 if (changed)
1593 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1594 spin_unlock_irq(&ensoniq->reg_lock);
1595 return changed;
1596}
1597
1598static snd_kcontrol_new_t snd_ens1373_line __devinitdata =
1599{
1600 SNDRV_CTL_ELEM_IFACE_MIXER, 0,0,
1601 "Line In->Rear Out Switch",0,0,0,
1602 snd_es1373_line_info,
1603 snd_es1373_line_get,
1604 snd_es1373_line_put,0
1605};
1606
1607static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1608{
1609 ensoniq_t *ensoniq = ac97->private_data;
1610 ensoniq->u.es1371.ac97 = NULL;
1611}
1612
1613static struct {
1614 unsigned short vid; /* vendor ID */
1615 unsigned short did; /* device ID */
1616 unsigned char rev; /* revision */
1617} es1371_spdif_present[] __devinitdata = {
1618 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, CT5880REV_CT5880_C },
1619 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, CT5880REV_CT5880_D },
1620 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, CT5880REV_CT5880_E },
1621 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, ES1371REV_CT5880_A },
1622 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, ES1371REV_ES1373_8 },
1623 { PCI_ANY_ID, PCI_ANY_ID }
1624};
1625
1626static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1627{
1628 snd_card_t *card = ensoniq->card;
1629 ac97_bus_t *pbus;
1630 ac97_template_t ac97;
1631 int err, idx;
1632
1633 static struct snd_ac97_bus_ops ops = {
1634 .write = snd_es1371_codec_write,
1635 .read = snd_es1371_codec_read,
1636 .wait = snd_es1371_codec_wait,
1637 };
1638#ifdef DEBUG
1639 dprintf(("snd_ensoniq_1371_mixer"));
1640#endif
1641 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1642 return err;
1643
1644 memset(&ac97, 0, sizeof(ac97));
1645 ac97.private_data = ensoniq;
1646 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1647 ac97.scaps = AC97_SCAP_AUDIO;
1648 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1649 return err;
1650 for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1651 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1652 ensoniq->pci->device == es1371_spdif_present[idx].did &&
1653 ensoniq->rev == es1371_spdif_present[idx].rev) {
1654 snd_kcontrol_t *kctl;
1655 int index = 0;
1656
1657 ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1658 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1659
1660 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1661 index++;
1662
1663 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif, ensoniq);
1664 kctl->id.index = index;
1665 snd_ctl_add(card, kctl);
1666
1667 kctl = snd_ctl_new1(&snd_ens1373_spdif_default, ensoniq);
1668 kctl->id.index = index;
1669 snd_ctl_add(card, kctl);
1670
1671 kctl = snd_ctl_new1(&snd_ens1373_spdif_mask, ensoniq);
1672 kctl->id.index = index;
1673 snd_ctl_add(card, kctl);
1674
1675 kctl = snd_ctl_new1(&snd_ens1373_spdif_stream, ensoniq);
1676 kctl->id.index = index;
1677 snd_ctl_add(card, kctl);
1678 break;
1679 }
1680 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1681 /* mirror rear to front speakers */
1682 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1683 ensoniq->cssr |= ES_1373_REAR_BIT26;
1684 snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1685 }
1686 if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1687 (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1688 ((ensoniq->subsystem_vendor_id == 0x1458) &&
1689 (ensoniq->subsystem_device_id == 0xa000))) { /* GA-8IEXP */
1690 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1691 if (err < 0)
1692 return err;
1693 }
1694
1695 return 0;
1696}
1697
1698#endif /* CHIP1371 */
1699
1700/* generic control callbacks for ens1370 and for joystick */
1701#if defined(CHIP1370) || defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1702
1703#define ENSONIQ_CONTROL(xname, mask) \
1704 { SNDRV_CTL_ELEM_IFACE_CARD, 0, 0, xname, 0, 0, 0, snd_ensoniq_control_info,\
1705 snd_ensoniq_control_get, snd_ensoniq_control_put, \
1706 mask }
1707
1708static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1709{
1710 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1711 uinfo->count = 1;
1712 uinfo->value.integer.min = 0;
1713 uinfo->value.integer.max = 1;
1714 return 0;
1715}
1716
1717static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1718{
1719 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1720 int mask = kcontrol->private_value;
1721
1722 spin_lock_irq(&ensoniq->reg_lock);
1723 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1724 spin_unlock_irq(&ensoniq->reg_lock);
1725 return 0;
1726}
1727
1728#ifdef CHIP1370
1729static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1730{
1731 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1732 int mask = kcontrol->private_value;
1733 unsigned int nval;
1734 int change;
1735
1736 nval = ucontrol->value.integer.value[0] ? mask : 0;
1737 spin_lock_irq(&ensoniq->reg_lock);
1738 change = (ensoniq->ctrl & mask) != nval;
1739 ensoniq->ctrl &= ~mask;
1740 ensoniq->ctrl |= nval;
1741 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1742 spin_unlock_irq(&ensoniq->reg_lock);
1743 return change;
1744}
1745#endif /* CHIP1370 */
1746#endif /* CHIP1370 || GAMEPORT */
1747
1748/*
1749 * ENS1370 mixer
1750 */
1751#ifdef CHIP1370
1752static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1753 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1754 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1755};
1756
1757#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1758
1759static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1760{
1761 ensoniq_t *ensoniq = ak4531->private_data;
1762 ensoniq->u.es1370.ak4531 = NULL;
1763}
1764
1765static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1766{
1767 snd_card_t *card = ensoniq->card;
1768 ak4531_t ak4531;
1769 unsigned int idx;
1770 int err;
1771
1772 /* try reset AK4531 */
1773 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1774 inw(ES_REG(ensoniq, 1370_CODEC));
1775 udelay(100);
1776 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1777 inw(ES_REG(ensoniq, 1370_CODEC));
1778 udelay(100);
1779
1780 memset(&ak4531, 0, sizeof(ak4531));
1781 ak4531.write = snd_es1370_codec_write;
1782 ak4531.private_data = ensoniq;
1783 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1784 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1785 return err;
1786 for (idx = 0; idx < ES1370_CONTROLS; idx++)
1787 snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1788 return 0;
1789}
1790
1791#endif /* CHIP1370 */
1792
1793/*
1794 * General Switches...
1795 */
1796
1797#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1798/* MQ: gameport driver connectivity */
1799#define ENSONIQ_JOY_CONTROL(xname, mask) \
1800 { SNDRV_CTL_ELEM_IFACE_CARD, xname, snd_ensoniq_control_info, \
1801 snd_ensoniq_control_get, snd_ensoniq_joy_control_put, \
1802 mask }
1803
1804static int snd_ensoniq_joy_enable(ensoniq_t *ensoniq)
1805{
1806 static unsigned long last_jiffies = 0;
1807 unsigned long flags;
1808
1809 if (!request_region(ensoniq->gameport.io, 8, "ens137x: gameport")) {
1810#define ES___GAMEPORT_LOG_DELAY (30*HZ)
1811 // avoid log pollution: limit to 2 infos per minute
1812 if (time_after(jiffies, last_jiffies + ES___GAMEPORT_LOG_DELAY)) {
1813 last_jiffies = jiffies;
1814 snd_printk("gameport io port 0x%03x in use", ensoniq->gameport.io);
1815 }
1816 return 0;
1817 }
1818 spin_lock_irqsave(&ensoniq->reg_lock, flags);
1819 ensoniq->ctrl |= ES_JYSTK_EN;
1820 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1821 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1822 gameport_register_port(&ensoniq->gameport);
1823 return 1;
1824}
1825
1826static int snd_ensoniq_joy_disable(ensoniq_t *ensoniq)
1827{
1828 unsigned long flags;
1829
1830 gameport_unregister_port(&ensoniq->gameport);
1831 spin_lock_irqsave(&ensoniq->reg_lock, flags);
1832 ensoniq->ctrl &= ~ES_JYSTK_EN;
1833 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1834 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1835 release_region(ensoniq->gameport.io, 8);
1836 return 1;
1837}
1838
1839static int snd_ensoniq_joy_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1840{
1841 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1842 unsigned int nval;
1843 int change;
1844
1845 down(&ensoniq->joy_sem);
1846 nval = ucontrol->value.integer.value[0] ? ES_JYSTK_EN : 0;
1847 change = (ensoniq->ctrl & ES_JYSTK_EN) != nval; // spinlock shouldn't be needed because of joy_sem
1848 if (change) {
1849 if (nval) // enable
1850 change = snd_ensoniq_joy_enable(ensoniq);
1851 else change = snd_ensoniq_joy_disable(ensoniq);
1852 }
1853 up(&ensoniq->joy_sem);
1854 return change;
1855}
1856
1857static snd_kcontrol_new_t snd_ensoniq_control_joystick __devinitdata =
1858ENSONIQ_JOY_CONTROL("Joystick Enable", ES_JYSTK_EN);
1859
1860#ifdef CHIP1371
1861
1862#define ES1371_JOYSTICK_ADDR(xname) \
1863 { SNDRV_CTL_ELEM_IFACE_CARD, 0, 0, xname, 0, 0, 0,snd_es1371_joystick_addr_info, \
1864 snd_es1371_joystick_addr_get, snd_es1371_joystick_addr_put, 0 }
1865
1866static int snd_es1371_joystick_addr_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1867{
1868 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1869 uinfo->count = 1;
1870 uinfo->value.enumerated.items = 4;
1871 if (uinfo->value.enumerated.item >= 4)
1872 uinfo->value.enumerated.item = 3;
1873 sprintf(uinfo->value.enumerated.name, "port 0x%x", (uinfo->value.enumerated.item * 8) + 0x200);
1874 return 0;
1875}
1876
1877static int snd_es1371_joystick_addr_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1878{
1879 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1880 unsigned long flags;
1881
1882 spin_lock_irqsave(&ensoniq->reg_lock, flags);
1883 ucontrol->value.enumerated.item[0] = ES_1371_JOY_ASELI(ensoniq->ctrl);
1884 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1885 return 0;
1886}
1887
1888static int snd_es1371_joystick_addr_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1889{
1890 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1891 unsigned long flags;
1892 unsigned int nval;
1893 int change;
1894
1895 down(&ensoniq->joy_sem);
1896 nval = ES_1371_JOY_ASEL(ucontrol->value.integer.value[0]);
1897 spin_lock_irqsave(&ensoniq->reg_lock, flags);
1898 if (!(change = !(ensoniq->ctrl & ES_JYSTK_EN)))
1899 goto no_change; // FIXME: now we allow change only when joystick is disabled
1900 change = (ensoniq->ctrl & ES_1371_JOY_ASELM) != nval;
1901 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1902 ensoniq->ctrl |= nval;
1903 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1904 ensoniq->gameport.io = 0x200 + ES_1371_JOY_ASELI(nval) * 8;
1905no_change:
1906 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
1907 up(&ensoniq->joy_sem);
1908 return change;
1909}
1910
1911static snd_kcontrol_new_t snd_es1371_joystick_addr __devinitdata =
1912ES1371_JOYSTICK_ADDR("Joystick Address");
1913
1914#endif /* CHIP1371 */
1915#endif /* CONFIG_GAMEPORT */
1916
1917/*
1918
1919*/
1920
1921static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1922 snd_info_buffer_t * buffer)
1923{
1924 ensoniq_t *ensoniq = entry->private_data;
1925
1926#ifdef CHIP1370
1927 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1928#else
1929 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1930#endif
1931 snd_iprintf(buffer, "Joystick enable : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1932#ifdef CHIP1370
1933 snd_iprintf(buffer, "MIC +5V bias : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1934 snd_iprintf(buffer, "Line In to AOUT : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1935#else
1936 snd_iprintf(buffer, "Joystick port : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1937#endif
1938}
1939
1940static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1941{
1942 snd_info_entry_t *entry;
1943
1944 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1945 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1946}
1947
1948/*
1949
1950*/
1951
1952static int snd_ensoniq_free(ensoniq_t *ensoniq)
1953{
1954#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1955 if (ensoniq->ctrl & ES_JYSTK_EN)
1956 snd_ensoniq_joy_disable(ensoniq);
1957#endif
1958 if (ensoniq->irq < 0)
1959 goto __hw_end;
1960#ifdef CHIP1370
1961 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1962 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1963#else
1964 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1965 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1966#endif
1967 synchronize_irq(ensoniq->irq);
1968 pci_set_power_state(ensoniq->pci, 3);
1969__hw_end:
1970#ifdef CHIP1370
1971 if (ensoniq->dma_bug.area)
1972 snd_dma_free_pages(&ensoniq->dma_bug);
1973#endif
1974 if (ensoniq->irq >= 0)
1975 free_irq(ensoniq->irq, (void *)ensoniq);
1976 pci_release_regions(ensoniq->pci);
1977 kfree(ensoniq);
1978 return 0;
1979}
1980
1981static int snd_ensoniq_dev_free(snd_device_t *device)
1982{
1983 ensoniq_t *ensoniq = device->device_data;
1984 return snd_ensoniq_free(ensoniq);
1985}
1986
1987#ifdef CHIP1371
1988static struct {
1989 unsigned short svid; /* subsystem vendor ID */
1990 unsigned short sdid; /* subsystem device ID */
1991} es1371_amplifier_hack[] = {
1992 { 0x107b, 0x2150 }, /* Gateway Solo 2150 */
1993 { 0x13bd, 0x100c }, /* EV1938 on Mebius PC-MJ100V */
1994 { 0x1102, 0x5938 }, /* Targa Xtender300 */
1995 { 0x1102, 0x8938 }, /* IPC Topnote G notebook */
1996 { PCI_ANY_ID, PCI_ANY_ID }
1997};
1998static struct {
1999 unsigned short vid; /* vendor ID */
2000 unsigned short did; /* device ID */
2001 unsigned char rev; /* revision */
2002} es1371_ac97_reset_hack[] = {
2003 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, CT5880REV_CT5880_C },
2004 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, CT5880REV_CT5880_D },
2005 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, CT5880REV_CT5880_E },
2006 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, ES1371REV_CT5880_A },
2007 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, ES1371REV_ES1373_8 },
2008 { PCI_ANY_ID, PCI_ANY_ID, 0 }
2009};
2010#endif
2011
2012static int __devinit snd_ensoniq_create(snd_card_t * card,
2013 struct pci_dev *pci,
2014 ensoniq_t ** rensoniq)
2015{
2016 ensoniq_t *ensoniq;
2017 unsigned short cmdw;
2018 unsigned char cmdb;
2019#ifdef CHIP1371
2020 int idx;
2021#endif
2022 int err;
2023 static snd_device_ops_t ops = {
2024 snd_ensoniq_dev_free,0,0,0
2025 };
2026
2027 *rensoniq = NULL;
2028 if ((err = pci_enable_device(pci)) < 0)
2029 return err;
2030 ensoniq = kcalloc(1, sizeof(*ensoniq), GFP_KERNEL);
2031 if (ensoniq == NULL)
2032 return -ENOMEM;
2033 spin_lock_init(&ensoniq->reg_lock);
2034 init_MUTEX(&ensoniq->src_mutex);
2035 ensoniq->card = card;
2036 ensoniq->pci = pci;
2037 ensoniq->irq = -1;
2038 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2039 kfree(ensoniq);
2040 return err;
2041 }
2042 ensoniq->port = pci_resource_start(pci, 0);
2043 if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
2044 snd_printk("unable to grab IRQ %d\n", pci->irq);
2045 snd_ensoniq_free(ensoniq);
2046 return -EBUSY;
2047 }
2048 ensoniq->irq = pci->irq;
2049#ifdef CHIP1370
2050 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2051 16, &ensoniq->dma_bug) < 0) {
2052 snd_printk("unable to allocate space for phantom area - dma_bug\n");
2053 snd_ensoniq_free(ensoniq);
2054 return -EBUSY;
2055 }
2056#endif
2057 pci_set_master(pci);
2058 pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
2059 ensoniq->rev = cmdb;
2060 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
2061 ensoniq->subsystem_vendor_id = cmdw;
2062 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
2063 ensoniq->subsystem_device_id = cmdw;
2064 snd_ensoniq_proc_init(ensoniq);
2065#ifdef CHIP1370
2066#if 0
2067 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2068#else /* get microphone working */
2069 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2070#endif
2071 ensoniq->sctrl = 0;
2072 /* initialize the chips */
2073 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2074 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2075 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
2076 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
2077 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
2078#else
2079 ensoniq->ctrl = 0;
2080 ensoniq->sctrl = 0;
2081 ensoniq->cssr = 0;
2082 for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2083 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2084 ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2085 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2086 break;
2087 }
2088 /* initialize the chips */
2089 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2090 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2091 outl(0, ES_REG(ensoniq, 1371_LEGACY));
2092 for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2093 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2094 pci->device == es1371_ac97_reset_hack[idx].did &&
2095 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2096
2097 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2098 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2099 /* need to delay around 20ms(bleech) to give
2100 some CODECs enough time to wakeup */
2101 msleep(20);
2102 break;
2103 }
2104 /* AC'97 warm reset to start the bitclk */
2105 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2106 inl(ES_REG(ensoniq, CONTROL));
2107 udelay(20);
2108 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2109 /* Init the sample rate converter */
2110 snd_es1371_wait_src_ready(ensoniq);
2111 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2112 for (idx = 0; idx < 0x80; idx++)
2113 snd_es1371_src_write(ensoniq, idx, 0);
2114 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2115 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2116 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2117 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2118 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2119 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2120 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2121 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2122 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2123 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2124 snd_es1371_adc_rate(ensoniq, 22050);
2125 snd_es1371_dac1_rate(ensoniq, 22050);
2126 snd_es1371_dac2_rate(ensoniq, 22050);
2127 /* WARNING:
2128 * enabling the sample rate converter without properly programming
2129 * its parameters causes the chip to lock up (the SRC busy bit will
2130 * be stuck high, and I've found no way to rectify this other than
2131 * power cycle) - Thomas Sailer
2132 */
2133 snd_es1371_wait_src_ready(ensoniq);
2134 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2135 /* try reset codec directly */
2136 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2137#endif
2138 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2139 outb(0x00, ES_REG(ensoniq, UART_RES));
2140 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2141#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2142 init_MUTEX(&ensoniq->joy_sem);
2143#ifdef CHIP1371
2144 snd_ctl_add(card, snd_ctl_new1(&snd_es1371_joystick_addr, ensoniq));
2145#endif
2146 snd_ctl_add(card, snd_ctl_new1(&snd_ensoniq_control_joystick, ensoniq));
2147 ensoniq->gameport.io = 0x200; // FIXME: is ES1371 configured like this above ?
2148#endif
2149 synchronize_irq(ensoniq->irq);
2150
2151 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2152 snd_ensoniq_free(ensoniq);
2153 return err;
2154 }
2155
2156 *rensoniq = ensoniq;
2157 snd_card_set_dev(card, &pci->dev);
2158 return 0;
2159}
2160
2161/*
2162 * MIDI section
2163 */
2164
2165static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2166{
2167 snd_rawmidi_t * rmidi = ensoniq->rmidi;
2168 unsigned char status, mask, byte;
2169
2170 if (rmidi == NULL)
2171 return;
2172 /* do Rx at first */
2173 spin_lock(&ensoniq->reg_lock);
2174 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2175 while (mask) {
2176 status = inb(ES_REG(ensoniq, UART_STATUS));
2177 if ((status & mask) == 0)
2178 break;
2179 byte = inb(ES_REG(ensoniq, UART_DATA));
2180 spin_unlock(&ensoniq->reg_lock);
2181 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2182 spin_lock(&ensoniq->reg_lock);
2183 }
2184 spin_unlock(&ensoniq->reg_lock);
2185
2186 /* do Tx at second */
2187 spin_lock(&ensoniq->reg_lock);
2188 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2189 while (mask) {
2190 status = inb(ES_REG(ensoniq, UART_STATUS));
2191 if ((status & mask) == 0)
2192 break;
2193 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2194 ensoniq->uartc &= ~ES_TXINTENM;
2195 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2196 mask &= ~ES_TXRDY;
2197 } else {
2198 outb(byte, ES_REG(ensoniq, UART_DATA));
2199 }
2200 }
2201 spin_unlock(&ensoniq->reg_lock);
2202}
2203
2204static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2205{
2206 ensoniq_t *ensoniq = substream->rmidi->private_data;
2207
2208// printk("Opening Ensoniq for MIDI input\n");
2209 spin_lock_irq(&ensoniq->reg_lock);
2210 ensoniq->uartm |= ES_MODE_INPUT;
2211 ensoniq->midi_input = substream;
2212 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2213 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2214 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2215 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2216 }
2217 spin_unlock_irq(&ensoniq->reg_lock);
2218 return 0;
2219}
2220
2221static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2222{
2223 ensoniq_t *ensoniq = substream->rmidi->private_data;
2224
2225// printk("Closing Ensoniq for MIDI input\n");
2226 spin_lock_irq(&ensoniq->reg_lock);
2227 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2228 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2229 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2230 } else {
2231 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2232 }
2233 ensoniq->midi_input = NULL;
2234 ensoniq->uartm &= ~ES_MODE_INPUT;
2235 spin_unlock_irq(&ensoniq->reg_lock);
2236 return 0;
2237}
2238
2239static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2240{
2241 ensoniq_t *ensoniq = substream->rmidi->private_data;
2242
2243// printk("Opening Ensoniq for MIDI output\n");
2244
2245 spin_lock_irq(&ensoniq->reg_lock);
2246 ensoniq->uartm |= ES_MODE_OUTPUT;
2247 ensoniq->midi_output = substream;
2248 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2249 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2250 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2251 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2252 }
2253 spin_unlock_irq(&ensoniq->reg_lock);
2254 return 0;
2255}
2256
2257static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2258{
2259 ensoniq_t *ensoniq = substream->rmidi->private_data;
2260
2261// printk("Closing Ensoniq for MIDI output\n");
2262
2263 spin_lock_irq(&ensoniq->reg_lock);
2264 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2265 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2266 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2267 } else {
2268 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2269 }
2270 ensoniq->midi_output = NULL;
2271 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2272 spin_unlock_irq(&ensoniq->reg_lock);
2273 return 0;
2274}
2275
2276static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2277{
2278 unsigned long flags;
2279 ensoniq_t *ensoniq = substream->rmidi->private_data;
2280 int idx;
2281
2282// printk("Ensoniq MIDI input trigger\n");
2283
2284 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2285 if (up) {
2286 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2287 /* empty input FIFO */
2288 for (idx = 0; idx < 32; idx++)
2289 inb(ES_REG(ensoniq, UART_DATA));
2290 ensoniq->uartc |= ES_RXINTEN;
2291 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2292 }
2293 } else {
2294 if (ensoniq->uartc & ES_RXINTEN) {
2295 ensoniq->uartc &= ~ES_RXINTEN;
2296 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2297 }
2298 }
2299 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2300}
2301
2302static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2303{
2304 unsigned long flags;
2305 ensoniq_t *ensoniq = substream->rmidi->private_data;
2306 unsigned char byte;
2307
2308// printk("Ensoniq MIDI output trigger\n");
2309
2310 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2311 if (up) {
2312 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2313 ensoniq->uartc |= ES_TXINTENO(1);
2314 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2315 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2316 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2317 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2318 ensoniq->uartc &= ~ES_TXINTENM;
2319 } else {
2320 outb(byte, ES_REG(ensoniq, UART_DATA));
2321 }
2322 }
2323 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2324 }
2325 } else {
2326 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2327 ensoniq->uartc &= ~ES_TXINTENM;
2328 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2329 }
2330 }
2331 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2332}
2333
2334static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2335{
2336 snd_ensoniq_midi_output_open,
2337 snd_ensoniq_midi_output_close,
2338 snd_ensoniq_midi_output_trigger,
2339 0
2340};
2341
2342static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2343{
2344 snd_ensoniq_midi_input_open,
2345 snd_ensoniq_midi_input_close,
2346 snd_ensoniq_midi_input_trigger,
2347 0
2348};
2349
2350static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2351{
2352 snd_rawmidi_t *rmidi;
2353 int err;
2354
2355 if (rrawmidi)
2356 *rrawmidi = NULL;
2357 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2358 return err;
2359#ifdef CHIP1370
2360 strcpy(rmidi->name, "ES1370");
2361#else
2362 strcpy(rmidi->name, "ES1371");
2363#endif
2364 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2365 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2366 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2367 rmidi->private_data = ensoniq;
2368 ensoniq->rmidi = rmidi;
2369 if (rrawmidi)
2370 *rrawmidi = rmidi;
2371 return 0;
2372}
2373
2374/*
2375 * Interrupt handler
2376 */
2377
2378static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2379{
2380#ifdef TARGET_OS2
2381 int fOurIrq = FALSE;
2382#endif
2383
2384 ensoniq_t *ensoniq = dev_id;
2385 unsigned int status, sctrl;
2386
2387 if (ensoniq == NULL)
2388 return IRQ_NONE;
2389
2390 status = inl(ES_REG(ensoniq, STATUS));
2391 if (!(status & ES_INTR))
2392 return IRQ_NONE;
2393#ifdef TARGET_OS2
2394 if (status & (ES_INTR|ES_UART|ES_DAC1|ES_DAC2|ES_ADC))
2395 {
2396 fOurIrq = TRUE;
2397 }
2398#endif
2399
2400 spin_lock(&ensoniq->reg_lock);
2401 sctrl = ensoniq->sctrl;
2402 if (status & ES_DAC1)
2403 sctrl &= ~ES_P1_INT_EN;
2404 if (status & ES_DAC2)
2405 sctrl &= ~ES_P2_INT_EN;
2406 if (status & ES_ADC)
2407 sctrl &= ~ES_R1_INT_EN;
2408 outl(sctrl, ES_REG(ensoniq, SERIAL));
2409 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2410 spin_unlock(&ensoniq->reg_lock);
2411
2412 if (status & ES_UART)
2413 {
2414// printk("MIDI int\n");
2415 snd_ensoniq_midi_interrupt(ensoniq);
2416 }
2417 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2418 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2419 if ((status & ES_ADC) && ensoniq->capture_substream)
2420 snd_pcm_period_elapsed(ensoniq->capture_substream);
2421 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2422 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2423
2424#ifdef TARGET_OS2
2425 if (fOurIrq) {
2426 eoi_irq(irq);
2427 }
2428#endif //TARGET_OS2
2429 return IRQ_HANDLED;
2430}
2431
2432static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2433 const struct pci_device_id *pci_id)
2434{
2435 static int dev;
2436 snd_card_t *card;
2437 ensoniq_t *ensoniq;
2438 int err, pcm_devs[2];
2439
2440 if (dev >= SNDRV_CARDS)
2441 return -ENODEV;
2442 if (!enable[dev]) {
2443 dev++;
2444 return -ENOENT;
2445 }
2446
2447 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2448 if (card == NULL)
2449 return -ENOMEM;
2450
2451 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2452 snd_card_free(card);
2453 return err;
2454 }
2455
2456 pcm_devs[0] = 0; pcm_devs[1] = 1;
2457#ifdef CHIP1370
2458 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2459 snd_card_free(card);
2460 return err;
2461 }
2462#endif
2463#ifdef CHIP1371
2464 if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2465 snd_card_free(card);
2466 return err;
2467 }
2468#endif
2469 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2470 snd_card_free(card);
2471 return err;
2472 }
2473 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2474 snd_card_free(card);
2475 return err;
2476 }
2477 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2478 snd_card_free(card);
2479 return err;
2480 }
2481#ifdef CHIP1370
2482 strcpy(card->driver, "ENS1370");
2483#endif
2484#ifdef CHIP1371
2485 strcpy(card->driver, "ENS1371");
2486#endif
2487 strcpy(card->shortname, "Ensoniq AudioPCI");
2488 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2489 card->shortname,
2490 card->driver,
2491 ensoniq->port,
2492 ensoniq->irq);
2493
2494 if ((err = snd_card_register(card)) < 0) {
2495 snd_card_free(card);
2496 return err;
2497 }
2498
2499 pci_set_drvdata(pci, card);
2500 dev++;
2501 return 0;
2502}
2503
2504static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2505{
2506 snd_card_free(pci_get_drvdata(pci));
2507 pci_set_drvdata(pci, NULL);
2508}
2509
2510static struct pci_driver driver = {
2511 0, 0, 0,
2512 "Ensoniq AudioPCI",
2513 snd_audiopci_ids,
2514 snd_audiopci_probe,
2515 snd_audiopci_remove,
2516 0, 0
2517};
2518
2519
2520static int __init alsa_card_ens137x_init(void)
2521{
2522 int err;
2523
2524 if ((err = pci_module_init(&driver)) < 0) {
2525#ifdef MODULE
2526 // snd_printk("Ensoniq AudioPCI soundcard not found or device busy\n");
2527#endif
2528 return err;
2529 }
2530 return 0;
2531}
2532
2533static void __exit alsa_card_ens137x_exit(void)
2534{
2535 pci_unregister_driver(&driver);
2536}
2537
2538module_init(alsa_card_ens137x_init)
2539module_exit(alsa_card_ens137x_exit)
2540
2541#ifndef MODULE
2542
2543/* format is: snd-card-ens1370=snd_enable,snd_index,snd_id */
2544
2545static int __init alsa_card_ens137x_setup(char *str)
2546{
2547 static unsigned __initdata nr_dev = 0;
2548
2549 if (nr_dev >= SNDRV_CARDS)
2550 return 0;
2551 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
2552 get_option(&str,&index[nr_dev]) == 2 &&
2553 get_id(&str,&id[nr_dev]) == 2);
2554 nr_dev++;
2555 return 1;
2556}
2557
2558#if defined(CHIP1370)
2559__setup("snd-ens1370=", alsa_card_ens137x_setup);
2560#elif defined(CHIP1371)
2561__setup("snd-ens1371=", alsa_card_ens137x_setup);
2562#endif
2563
2564#endif /* ifndef MODULE */
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