source: GPL/trunk/alsa-kernel/pci/ens1370.c@ 114

Last change on this file since 114 was 73, checked in by vladest, 20 years ago

Fixed compile issues
Fixed SB128 driver
File size: 83.0 KB
Line 
1/*
2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 * Thomas Sailer <sailer@ife.ee.ethz.ch>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22/* Power-Management-Code ( CONFIG_PM )
23 * for ens1371 only ( FIXME )
24 * derived from cs4281.c, atiixp.c and via82xx.c
25 * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
26 * by Kurt J. Bosch
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36//#include <linux/gameport.h>
37#include <linux/moduleparam.h>
38#include <sound/core.h>
39#include <sound/control.h>
40#include <sound/pcm.h>
41#include <sound/rawmidi.h>
42#ifdef CHIP1371
43#include <sound/ac97_codec.h>
44#else
45#include <sound/ak4531_codec.h>
46#endif
47#include <sound/initval.h>
48#include <sound/asoundef.h>
49
50#ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
51#define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
52#endif
53
54#ifndef CHIP1371
55#undef CHIP1370
56#define CHIP1370
57#endif
58
59#ifdef CHIP1370
60#define DRIVER_NAME "ENS1370"
61#else
62#define DRIVER_NAME "ENS1371"
63#endif
64
65
66MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
67MODULE_LICENSE("GPL");
68#ifdef CHIP1370
69MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
70MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
71 "{Creative Labs,SB PCI64/128 (ES1370)}}");
72#endif
73#ifdef CHIP1371
74MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
75MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
76 "{Ensoniq,AudioPCI ES1373},"
77 "{Creative Labs,Ectiva EV1938},"
78 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
79 "{Creative Labs,Vibra PCI128},"
80 "{Ectiva,EV1938}}");
81#endif
82
83#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
84#define SUPPORT_JOYSTICK
85#endif
86
87static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
88static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
89static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
90#ifdef SUPPORT_JOYSTICK
91#ifdef CHIP1371
92static int joystick_port[SNDRV_CARDS];
93#else
94static int joystick[SNDRV_CARDS];
95#endif
96#endif
97#ifdef CHIP1371
98static int spdif[SNDRV_CARDS];
99static int lineio[SNDRV_CARDS];
100#endif
101
102//module_param_array(index, int, NULL, 0444);
103MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
104//module_param_array(id, charp, NULL, 0444);
105MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
106//module_param_array(enable, bool, NULL, 0444);
107MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
108#ifdef SUPPORT_JOYSTICK
109#ifdef CHIP1371
110//module_param_array(joystick_port, int, NULL, 0444);
111MODULE_PARM_DESC(joystick_port, "Joystick port address.");
112#else
113//module_param_array(joystick, bool, NULL, 0444);
114MODULE_PARM_DESC(joystick, "Enable joystick.");
115#endif
116#endif /* SUPPORT_JOYSTICK */
117#ifdef CHIP1371
118//module_param_array(spdif, int, NULL, 0444);
119MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
120//module_param_array(lineio, int, NULL, 0444);
121MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
122#endif
123
124/* ES1371 chip ID */
125/* This is a little confusing because all ES1371 compatible chips have the
126 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
127 This is only significant if you want to enable features on the later parts.
128 Yes, I know it's stupid and why didn't we use the sub IDs?
129*/
130#define ES1371REV_ES1373_A 0x04
131#define ES1371REV_ES1373_B 0x06
132#define ES1371REV_CT5880_A 0x07
133#define CT5880REV_CT5880_C 0x02
134#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
135#define CT5880REV_CT5880_E 0x04 /* mw */
136#define ES1371REV_ES1371_B 0x09
137#define EV1938REV_EV1938_A 0x00
138#define ES1371REV_ES1373_8 0x08
139
140/*
141 * Direct registers
142 */
143
144#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
145
146#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
147#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
148#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
149#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
150#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
151#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
152#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
153#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
154#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
155#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
156#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
157#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
158#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
159#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
160#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
161#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
162#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
163#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
164#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
165#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
166#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
167#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
168#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
169#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
170#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
171#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
172#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
173#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
174#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
175#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
176#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
177#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
178#define ES_BREQ (1<<7) /* memory bus request enable */
179#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
180#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
181#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
182#define ES_UART_EN (1<<3) /* UART enable */
183#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
184#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
185#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
186#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
187#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
188#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
189#define ES_INTR (1<<31) /* Interrupt is pending */
190#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
191#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
192#define ES_1373_REAR_BIT26 (1<<26)
193#define ES_1373_REAR_BIT24 (1<<24)
194#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
195#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
196#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
197#define ES_1371_TEST (1<<16) /* test ASIC */
198#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
199#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
200#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
201#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
202#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
203#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
204#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
205#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
206#define ES_MCCB (1<<4) /* CCB interrupt pending */
207#define ES_UART (1<<3) /* UART interrupt pending */
208#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
209#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
210#define ES_ADC (1<<0) /* ADC channel interrupt pending */
211#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
212#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
213#define ES_RXINT (1<<7) /* RX interrupt occurred */
214#define ES_TXINT (1<<2) /* TX interrupt occurred */
215#define ES_TXRDY (1<<1) /* transmitter ready */
216#define ES_RXRDY (1<<0) /* receiver ready */
217#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
218#define ES_RXINTEN (1<<7) /* RX interrupt enable */
219#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
220#define ES_TXINTENM (0x03<<5) /* mask for above */
221#define ES_TXINTENI(i) (((i)>>5)&0x03)
222#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
223#define ES_CNTRLM (0x03<<0) /* mask for above */
224#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
225#define ES_TEST_MODE (1<<0) /* test mode enabled */
226#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
227#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
228#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
229#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
230#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
231#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
232#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
233#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
234#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
235#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
236#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
237#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
238#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
239
240#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
241#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
242#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
243#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
244#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
245#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
246#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
247#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
248#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
249#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
250#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
251#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
252#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
253
254#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
255#define ES_1371_JFAST (1<<31) /* fast joystick timing */
256#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
257#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
258#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
259#define ES_1371_VMPUM (0x03<<27) /* mask for above */
260#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
261#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
262#define ES_1371_VCDCM (0x03<<25) /* mask for above */
263#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
264#define ES_1371_FIRQ (1<<24) /* force an interrupt */
265#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
266#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
267#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
268#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
269#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
270#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
271#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
272#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
273#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
274#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
275#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
276#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
277
278#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
279
280#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
281#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
282#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
283#define ES_P2_END_INCM (0x07<<19) /* mask for above */
284#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
285#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
286#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
287#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
288#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
289#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
290#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
291#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
292#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
293#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
294#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
295#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
296#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
297#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
298#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
299#define ES_R1_MODEM (0x03<<4) /* mask for above */
300#define ES_R1_MODEI(i) (((i)>>4)&0x03)
301#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
302#define ES_P2_MODEM (0x03<<2) /* mask for above */
303#define ES_P2_MODEI(i) (((i)>>2)&0x03)
304#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
305#define ES_P1_MODEM (0x03<<0) /* mask for above */
306#define ES_P1_MODEI(i) (((i)>>0)&0x03)
307
308#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
309#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
310#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
311#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
312#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
313#define ES_REG_COUNTM (0xffff<<0)
314#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
315
316#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
317#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
318#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
319#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
320#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
321#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
322#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
323#define ES_REG_FCURR_COUNTM (0xffff<<16)
324#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
325#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
326#define ES_REG_FSIZEM (0xffff<<0)
327#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
328#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
329#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
330
331#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
332#define ES_REG_UF_VALID (1<<8)
333#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
334#define ES_REG_UF_BYTEM (0xff<<0)
335#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
336
337
338/*
339 * Pages
340 */
341
342#define ES_PAGE_DAC 0x0c
343#define ES_PAGE_ADC 0x0d
344#define ES_PAGE_UART 0x0e
345#define ES_PAGE_UART1 0x0f
346
347/*
348 * Sample rate converter addresses
349 */
350
351#define ES_SMPREG_DAC1 0x70
352#define ES_SMPREG_DAC2 0x74
353#define ES_SMPREG_ADC 0x78
354#define ES_SMPREG_VOL_ADC 0x6c
355#define ES_SMPREG_VOL_DAC1 0x7c
356#define ES_SMPREG_VOL_DAC2 0x7e
357#define ES_SMPREG_TRUNC_N 0x00
358#define ES_SMPREG_INT_REGS 0x01
359#define ES_SMPREG_ACCUM_FRAC 0x02
360#define ES_SMPREG_VFREQ_FRAC 0x03
361
362/*
363 * Some contants
364 */
365
366#define ES_1370_SRCLOCK 1411200
367#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
368
369/*
370 * Open modes
371 */
372
373#define ES_MODE_PLAY1 0x0001
374#define ES_MODE_PLAY2 0x0002
375#define ES_MODE_CAPTURE 0x0004
376
377#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
378#define ES_MODE_INPUT 0x0002 /* for MIDI */
379
380/*
381
382 */
383
384struct ensoniq {
385 spinlock_t reg_lock;
386 struct semaphore src_mutex;
387
388 int irq;
389
390 unsigned long playback1size;
391 unsigned long playback2size;
392 unsigned long capture3size;
393
394 unsigned long port;
395 unsigned int mode;
396 unsigned int uartm; /* UART mode */
397
398 unsigned int ctrl; /* control register */
399 unsigned int sctrl; /* serial control register */
400 unsigned int cssr; /* control status register */
401 unsigned int uartc; /* uart control register */
402 unsigned int rev; /* chip revision */
403
404 union {
405#ifdef CHIP1371
406 struct {
407 struct snd_ac97 *ac97;
408 } es1371;
409#else
410 struct {
411 int pclkdiv_lock;
412 struct snd_ak4531 *ak4531;
413 } es1370;
414#endif
415 } u;
416
417 struct pci_dev *pci;
418 unsigned short subsystem_vendor_id;
419 unsigned short subsystem_device_id;
420 struct snd_card *card;
421 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
422 struct snd_pcm *pcm2; /* DAC2 PCM */
423 struct snd_pcm_substream *playback1_substream;
424 struct snd_pcm_substream *playback2_substream;
425 struct snd_pcm_substream *capture_substream;
426 unsigned int p1_dma_size;
427 unsigned int p2_dma_size;
428 unsigned int c_dma_size;
429 unsigned int p1_period_size;
430 unsigned int p2_period_size;
431 unsigned int c_period_size;
432 struct snd_rawmidi *rmidi;
433 struct snd_rawmidi_substream *midi_input;
434 struct snd_rawmidi_substream *midi_output;
435
436 unsigned int spdif;
437 unsigned int spdif_default;
438 unsigned int spdif_stream;
439
440#ifdef CHIP1370
441 struct snd_dma_buffer dma_bug;
442#endif
443
444#ifdef SUPPORT_JOYSTICK
445 struct gameport *gameport;
446#endif
447};
448
449static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
450
451static struct pci_device_id snd_audiopci_ids[] = {
452#ifdef CHIP1370
453 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */
454#endif
455#ifdef CHIP1371
456 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */
457 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */
458 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */
459#endif
460 { 0, }
461};
462
463MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
464
465/*
466 * constants
467 */
468
469#define POLL_COUNT 0xa000
470
471#ifdef CHIP1370
472static unsigned int snd_es1370_fixed_rates[] =
473 {5512, 11025, 22050, 44100};
474static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
475 .count = 4,
476 .list = snd_es1370_fixed_rates,
477 .mask = 0,
478};
479static struct snd_ratnum es1370_clock = {
480 .num = ES_1370_SRCLOCK,
481 .den_min = 29,
482 .den_max = 353,
483 .den_step = 1,
484};
485static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
486 .nrats = 1,
487 .rats = &es1370_clock,
488};
489#else
490static struct snd_ratden es1371_dac_clock = {
491 .num_min = 3000 * (1 << 15),
492 .num_max = 48000 * (1 << 15),
493 .num_step = 3000,
494 .den = 1 << 15,
495};
496static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
497 .nrats = 1,
498 .rats = &es1371_dac_clock,
499};
500static struct snd_ratnum es1371_adc_clock = {
501 .num = 48000 << 15,
502 .den_min = 32768,
503 .den_max = 393216,
504 .den_step = 1,
505};
506static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
507 .nrats = 1,
508 .rats = &es1371_adc_clock,
509};
510#endif
511static const unsigned int snd_ensoniq_sample_shift[] =
512 {0, 1, 1, 2};
513
514/*
515 * common I/O routines
516 */
517
518#ifdef CHIP1371
519
520static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
521{
522 unsigned int t, r = 0;
523
524 for (t = 0; t < POLL_COUNT; t++) {
525 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
526 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
527 return r;
528 cond_resched();
529 }
530 snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n",
531 ES_REG(ensoniq, 1371_SMPRATE), r);
532 return 0;
533}
534
535static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
536{
537 unsigned int temp, i, orig, r;
538
539 /* wait for ready */
540 temp = orig = snd_es1371_wait_src_ready(ensoniq);
541
542 /* expose the SRC state bits */
543 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
544 ES_1371_DIS_P2 | ES_1371_DIS_R1);
545 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
546 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
547
548 /* now, wait for busy and the correct time to read */
549 temp = snd_es1371_wait_src_ready(ensoniq);
550
551 if ((temp & 0x00870000) != 0x00010000) {
552 /* wait for the right state */
553 for (i = 0; i < POLL_COUNT; i++) {
554 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
555 if ((temp & 0x00870000) == 0x00010000)
556 break;
557 }
558 }
559
560 /* hide the state bits */
561 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
562 ES_1371_DIS_P2 | ES_1371_DIS_R1);
563 r |= ES_1371_SRC_RAM_ADDRO(reg);
564 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
565
566 return temp;
567}
568
569static void snd_es1371_src_write(struct ensoniq * ensoniq,
570 unsigned short reg, unsigned short data)
571{
572 unsigned int r;
573
574 r = snd_es1371_wait_src_ready(ensoniq) &
575 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
576 ES_1371_DIS_P2 | ES_1371_DIS_R1);
577 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
578 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
579}
580
581#endif /* CHIP1371 */
582
583#ifdef CHIP1370
584
585static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
586 unsigned short reg, unsigned short val)
587{
588 struct ensoniq *ensoniq = ak4531->private_data;
589 unsigned long end_time = jiffies + HZ / 10;
590
591#if 0
592 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
593 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
594#endif
595 do {
596 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
597 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
598 return;
599 }
600 schedule_timeout_uninterruptible(1);
601 } while (time_after(end_time, jiffies));
602 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
603 inl(ES_REG(ensoniq, STATUS)));
604}
605
606#endif /* CHIP1370 */
607
608#ifdef CHIP1371
609
610static void snd_es1371_codec_write(struct snd_ac97 *ac97,
611 unsigned short reg, unsigned short val)
612{
613 struct ensoniq *ensoniq = ac97->private_data;
614 unsigned int t, x;
615
616 down(&ensoniq->src_mutex);
617 for (t = 0; t < POLL_COUNT; t++) {
618 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
619 /* save the current state for latter */
620 x = snd_es1371_wait_src_ready(ensoniq);
621 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
622 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
623 ES_REG(ensoniq, 1371_SMPRATE));
624 /* wait for not busy (state 0) first to avoid
625 transition states */
626 for (t = 0; t < POLL_COUNT; t++) {
627 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
628 0x00000000)
629 break;
630 }
631 /* wait for a SAFE time to write addr/data and then do it, dammit */
632 for (t = 0; t < POLL_COUNT; t++) {
633 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
634 0x00010000)
635 break;
636 }
637 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
638 /* restore SRC reg */
639 snd_es1371_wait_src_ready(ensoniq);
640 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
641 up(&ensoniq->src_mutex);
642 return;
643 }
644 }
645 up(&ensoniq->src_mutex);
646 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
647 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
648}
649
650static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
651 unsigned short reg)
652{
653 struct ensoniq *ensoniq = ac97->private_data;
654 unsigned int t, x, fail = 0;
655
656 __again:
657 down(&ensoniq->src_mutex);
658 for (t = 0; t < POLL_COUNT; t++) {
659 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
660 /* save the current state for latter */
661 x = snd_es1371_wait_src_ready(ensoniq);
662 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
663 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
664 ES_REG(ensoniq, 1371_SMPRATE));
665 /* wait for not busy (state 0) first to avoid
666 transition states */
667 for (t = 0; t < POLL_COUNT; t++) {
668 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
669 0x00000000)
670 break;
671 }
672 /* wait for a SAFE time to write addr/data and then do it, dammit */
673 for (t = 0; t < POLL_COUNT; t++) {
674 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
675 0x00010000)
676 break;
677 }
678 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
679 /* restore SRC reg */
680 snd_es1371_wait_src_ready(ensoniq);
681 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
682 /* wait for WIP again */
683 for (t = 0; t < POLL_COUNT; t++) {
684 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
685 break;
686 }
687 /* now wait for the stinkin' data (RDY) */
688 for (t = 0; t < POLL_COUNT; t++) {
689 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
690 up(&ensoniq->src_mutex);
691 return ES_1371_CODEC_READ(x);
692 }
693 }
694 up(&ensoniq->src_mutex);
695 if (++fail > 10) {
696 snd_printk(KERN_ERR "codec read timeout (final) "
697 "at 0x%lx, reg = 0x%x [0x%x]\n",
698 ES_REG(ensoniq, 1371_CODEC), reg,
699 inl(ES_REG(ensoniq, 1371_CODEC)));
700 return 0;
701 }
702 goto __again;
703 }
704 }
705 up(&ensoniq->src_mutex);
706 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
707 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
708 return 0;
709}
710
711static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
712{
713 msleep(750);
714 snd_es1371_codec_read(ac97, AC97_RESET);
715 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
716 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
717 msleep(50);
718}
719
720static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
721{
722 unsigned int n, truncm, freq, result;
723
724 down(&ensoniq->src_mutex);
725 n = rate / 3000;
726 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
727 n--;
728 truncm = (21 * n - 1) | 1;
729 freq = ((48000UL << 15) / rate) * n;
730 result = (48000UL << 15) / (freq / n);
731 if (rate >= 24000) {
732 if (truncm > 239)
733 truncm = 239;
734 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
735 (((239 - truncm) >> 1) << 9) | (n << 4));
736 } else {
737 if (truncm > 119)
738 truncm = 119;
739 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
740 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
741 }
742 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
743 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
744 ES_SMPREG_INT_REGS) & 0x00ff) |
745 ((freq >> 5) & 0xfc00));
746 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
747 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
748 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
749 up(&ensoniq->src_mutex);
750}
751
752static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
753{
754 unsigned int freq, r;
755
756 down(&ensoniq->src_mutex);
757 freq = ((rate << 15) + 1500) / 3000;
758 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
759 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
760 ES_1371_DIS_P1;
761 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
762 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
763 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
764 ES_SMPREG_INT_REGS) & 0x00ff) |
765 ((freq >> 5) & 0xfc00));
766 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
767 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
768 ES_1371_DIS_P2 | ES_1371_DIS_R1));
769 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
770 up(&ensoniq->src_mutex);
771}
772
773static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
774{
775 unsigned int freq, r;
776
777 down(&ensoniq->src_mutex);
778 freq = ((rate << 15) + 1500) / 3000;
779 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
780 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
781 ES_1371_DIS_P2;
782 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
783 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
784 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
785 ES_SMPREG_INT_REGS) & 0x00ff) |
786 ((freq >> 5) & 0xfc00));
787 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
788 freq & 0x7fff);
789 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
790 ES_1371_DIS_P1 | ES_1371_DIS_R1));
791 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
792 up(&ensoniq->src_mutex);
793}
794
795#endif /* CHIP1371 */
796
797static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
798{
799 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
800 switch (cmd) {
801 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
802 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
803 {
804 unsigned int what = 0;
805 struct list_head *pos;
806 struct snd_pcm_substream *s;
807 snd_pcm_group_for_each(pos, substream) {
808 s = snd_pcm_group_substream_entry(pos);
809 if (s == ensoniq->playback1_substream) {
810 what |= ES_P1_PAUSE;
811 snd_pcm_trigger_done(s, substream);
812 } else if (s == ensoniq->playback2_substream) {
813 what |= ES_P2_PAUSE;
814 snd_pcm_trigger_done(s, substream);
815 } else if (s == ensoniq->capture_substream)
816 return -EINVAL;
817 }
818 spin_lock(&ensoniq->reg_lock);
819 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
820 ensoniq->sctrl |= what;
821 else
822 ensoniq->sctrl &= ~what;
823 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
824 spin_unlock(&ensoniq->reg_lock);
825 break;
826 }
827 case SNDRV_PCM_TRIGGER_START:
828 case SNDRV_PCM_TRIGGER_STOP:
829 {
830 unsigned int what = 0;
831 struct list_head *pos;
832 struct snd_pcm_substream *s;
833 snd_pcm_group_for_each(pos, substream) {
834 s = snd_pcm_group_substream_entry(pos);
835 if (s == ensoniq->playback1_substream) {
836 what |= ES_DAC1_EN;
837 snd_pcm_trigger_done(s, substream);
838 } else if (s == ensoniq->playback2_substream) {
839 what |= ES_DAC2_EN;
840 snd_pcm_trigger_done(s, substream);
841 } else if (s == ensoniq->capture_substream) {
842 what |= ES_ADC_EN;
843 snd_pcm_trigger_done(s, substream);
844 }
845 }
846 spin_lock(&ensoniq->reg_lock);
847 if (cmd == SNDRV_PCM_TRIGGER_START)
848 ensoniq->ctrl |= what;
849 else
850 ensoniq->ctrl &= ~what;
851 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
852 spin_unlock(&ensoniq->reg_lock);
853 break;
854 }
855 default:
856 return -EINVAL;
857 }
858 return 0;
859}
860
861/*
862 * PCM part
863 */
864
865static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
866 struct snd_pcm_hw_params *hw_params)
867{
868 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
869}
870
871static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
872{
873 return snd_pcm_lib_free_pages(substream);
874}
875
876static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
877{
878 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
879 struct snd_pcm_runtime *runtime = substream->runtime;
880 unsigned int mode = 0;
881
882 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
883 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
884 if (snd_pcm_format_width(runtime->format) == 16)
885 mode |= 0x02;
886 if (runtime->channels > 1)
887 mode |= 0x01;
888 spin_lock_irq(&ensoniq->reg_lock);
889 ensoniq->ctrl &= ~ES_DAC1_EN;
890#ifdef CHIP1371
891 /* 48k doesn't need SRC (it breaks AC3-passthru) */
892 if (runtime->rate == 48000)
893 ensoniq->ctrl |= ES_1373_BYPASS_P1;
894 else
895 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
896#endif
897 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
898 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
899 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
900 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
901 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
902 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
903 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
904 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
905 ES_REG(ensoniq, DAC1_COUNT));
906#ifdef CHIP1370
907 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
908 switch (runtime->rate) {
909 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
910 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
911 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
912 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
913 default: snd_BUG();
914 }
915#endif
916 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
917 spin_unlock_irq(&ensoniq->reg_lock);
918#ifndef CHIP1370
919 snd_es1371_dac1_rate(ensoniq, runtime->rate);
920#endif
921 return 0;
922}
923
924static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
925{
926 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
927 struct snd_pcm_runtime *runtime = substream->runtime;
928 unsigned int mode = 0;
929
930 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
931 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
932 if (snd_pcm_format_width(runtime->format) == 16)
933 mode |= 0x02;
934 if (runtime->channels > 1)
935 mode |= 0x01;
936 spin_lock_irq(&ensoniq->reg_lock);
937 ensoniq->ctrl &= ~ES_DAC2_EN;
938 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
939 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
940 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
941 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
942 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
943 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
944 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
945 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
946 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
947 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
948 ES_REG(ensoniq, DAC2_COUNT));
949#ifdef CHIP1370
950 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
951 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
952 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
953 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
954 }
955#endif
956 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
957 spin_unlock_irq(&ensoniq->reg_lock);
958#ifndef CHIP1370
959 snd_es1371_dac2_rate(ensoniq, runtime->rate);
960#endif
961 return 0;
962}
963
964static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
965{
966 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
967 struct snd_pcm_runtime *runtime = substream->runtime;
968 unsigned int mode = 0;
969
970 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
971 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
972 if (snd_pcm_format_width(runtime->format) == 16)
973 mode |= 0x02;
974 if (runtime->channels > 1)
975 mode |= 0x01;
976 spin_lock_irq(&ensoniq->reg_lock);
977 ensoniq->ctrl &= ~ES_ADC_EN;
978 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
979 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
980 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
981 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
982 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
983 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
984 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
985 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
986 ES_REG(ensoniq, ADC_COUNT));
987#ifdef CHIP1370
988 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
989 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
990 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
991 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
992 }
993#endif
994 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
995 spin_unlock_irq(&ensoniq->reg_lock);
996#ifndef CHIP1370
997 snd_es1371_adc_rate(ensoniq, runtime->rate);
998#endif
999 return 0;
1000}
1001
1002static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1003{
1004 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1005 size_t ptr;
1006
1007 spin_lock(&ensoniq->reg_lock);
1008 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1009 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1010 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1011 ptr = bytes_to_frames(substream->runtime, ptr);
1012 } else {
1013 ptr = 0;
1014 }
1015 spin_unlock(&ensoniq->reg_lock);
1016 return ptr;
1017}
1018
1019static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1020{
1021 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1022 size_t ptr;
1023
1024 spin_lock(&ensoniq->reg_lock);
1025 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1026 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1027 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1028 ptr = bytes_to_frames(substream->runtime, ptr);
1029 } else {
1030 ptr = 0;
1031 }
1032 spin_unlock(&ensoniq->reg_lock);
1033 return ptr;
1034}
1035
1036static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1037{
1038 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1039 size_t ptr;
1040
1041 spin_lock(&ensoniq->reg_lock);
1042 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1043 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1044 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1045 ptr = bytes_to_frames(substream->runtime, ptr);
1046 } else {
1047 ptr = 0;
1048 }
1049 spin_unlock(&ensoniq->reg_lock);
1050 return ptr;
1051}
1052
1053static struct snd_pcm_hardware snd_ensoniq_playback1 =
1054{
1055 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1056 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1057 SNDRV_PCM_INFO_MMAP_VALID |
1058 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1059 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1060 .rates =
1061#ifndef CHIP1370
1062 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1063#else
1064 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1065 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1066 SNDRV_PCM_RATE_44100),
1067#endif
1068 .rate_min = 4000,
1069 .rate_max = 48000,
1070 .channels_min = 1,
1071 .channels_max = 2,
1072 .buffer_bytes_max = (128*1024),
1073 .period_bytes_min = 64,
1074 .period_bytes_max = (128*1024),
1075 .periods_min = 1,
1076 .periods_max = 1024,
1077 .fifo_size = 0,
1078};
1079
1080static struct snd_pcm_hardware snd_ensoniq_playback2 =
1081{
1082 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1083 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1084 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1085 SNDRV_PCM_INFO_SYNC_START),
1086 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1087 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1088 .rate_min = 4000,
1089 .rate_max = 48000,
1090 .channels_min = 1,
1091 .channels_max = 2,
1092 .buffer_bytes_max = (128*1024),
1093 .period_bytes_min = 64,
1094 .period_bytes_max = (128*1024),
1095 .periods_min = 1,
1096 .periods_max = 1024,
1097 .fifo_size = 0,
1098};
1099
1100static struct snd_pcm_hardware snd_ensoniq_capture =
1101{
1102 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1103 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1104 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1105 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1106 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1107 .rate_min = 4000,
1108 .rate_max = 48000,
1109 .channels_min = 1,
1110 .channels_max = 2,
1111 .buffer_bytes_max = (128*1024),
1112 .period_bytes_min = 64,
1113 .period_bytes_max = (128*1024),
1114 .periods_min = 1,
1115 .periods_max = 1024,
1116 .fifo_size = 0,
1117};
1118
1119static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1120{
1121 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1122 struct snd_pcm_runtime *runtime = substream->runtime;
1123
1124 ensoniq->mode |= ES_MODE_PLAY1;
1125 ensoniq->playback1_substream = substream;
1126 runtime->hw = snd_ensoniq_playback1;
1127 snd_pcm_set_sync(substream);
1128 spin_lock_irq(&ensoniq->reg_lock);
1129 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1130 ensoniq->spdif_stream = ensoniq->spdif_default;
1131 spin_unlock_irq(&ensoniq->reg_lock);
1132#ifdef CHIP1370
1133 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1134 &snd_es1370_hw_constraints_rates);
1135#else
1136// snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1137// &snd_es1371_hw_constraints_dac_clock);
1138#endif
1139 return 0;
1140}
1141
1142static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1143{
1144 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1145 struct snd_pcm_runtime *runtime = substream->runtime;
1146
1147 ensoniq->mode |= ES_MODE_PLAY2;
1148 ensoniq->playback2_substream = substream;
1149 runtime->hw = snd_ensoniq_playback2;
1150 snd_pcm_set_sync(substream);
1151 spin_lock_irq(&ensoniq->reg_lock);
1152 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1153 ensoniq->spdif_stream = ensoniq->spdif_default;
1154 spin_unlock_irq(&ensoniq->reg_lock);
1155#ifdef CHIP1370
1156 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1157 &snd_es1370_hw_constraints_clock);
1158#else
1159// snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1160// &snd_es1371_hw_constraints_dac_clock);
1161#endif
1162 return 0;
1163}
1164
1165static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1166{
1167 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1168 struct snd_pcm_runtime *runtime = substream->runtime;
1169
1170 ensoniq->mode |= ES_MODE_CAPTURE;
1171 ensoniq->capture_substream = substream;
1172 runtime->hw = snd_ensoniq_capture;
1173 snd_pcm_set_sync(substream);
1174#ifdef CHIP1370
1175 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1176 &snd_es1370_hw_constraints_clock);
1177#else
1178 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1179 &snd_es1371_hw_constraints_adc_clock);
1180#endif
1181 return 0;
1182}
1183
1184static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1185{
1186 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1187
1188 ensoniq->playback1_substream = NULL;
1189 ensoniq->mode &= ~ES_MODE_PLAY1;
1190 return 0;
1191}
1192
1193static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1194{
1195 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1196
1197 ensoniq->playback2_substream = NULL;
1198 spin_lock_irq(&ensoniq->reg_lock);
1199#ifdef CHIP1370
1200 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1201#endif
1202 ensoniq->mode &= ~ES_MODE_PLAY2;
1203 spin_unlock_irq(&ensoniq->reg_lock);
1204 return 0;
1205}
1206
1207static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1208{
1209 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1210
1211 ensoniq->capture_substream = NULL;
1212 spin_lock_irq(&ensoniq->reg_lock);
1213#ifdef CHIP1370
1214 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1215#endif
1216 ensoniq->mode &= ~ES_MODE_CAPTURE;
1217 spin_unlock_irq(&ensoniq->reg_lock);
1218 return 0;
1219}
1220
1221static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1222 .open = snd_ensoniq_playback1_open,
1223 .close = snd_ensoniq_playback1_close,
1224 .ioctl = snd_pcm_lib_ioctl,
1225 .hw_params = snd_ensoniq_hw_params,
1226 .hw_free = snd_ensoniq_hw_free,
1227 .prepare = snd_ensoniq_playback1_prepare,
1228 .trigger = snd_ensoniq_trigger,
1229 .pointer = snd_ensoniq_playback1_pointer,
1230};
1231
1232static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1233 .open = snd_ensoniq_playback2_open,
1234 .close = snd_ensoniq_playback2_close,
1235 .ioctl = snd_pcm_lib_ioctl,
1236 .hw_params = snd_ensoniq_hw_params,
1237 .hw_free = snd_ensoniq_hw_free,
1238 .prepare = snd_ensoniq_playback2_prepare,
1239 .trigger = snd_ensoniq_trigger,
1240 .pointer = snd_ensoniq_playback2_pointer,
1241};
1242
1243static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1244 .open = snd_ensoniq_capture_open,
1245 .close = snd_ensoniq_capture_close,
1246 .ioctl = snd_pcm_lib_ioctl,
1247 .hw_params = snd_ensoniq_hw_params,
1248 .hw_free = snd_ensoniq_hw_free,
1249 .prepare = snd_ensoniq_capture_prepare,
1250 .trigger = snd_ensoniq_trigger,
1251 .pointer = snd_ensoniq_capture_pointer,
1252};
1253
1254static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1255 struct snd_pcm ** rpcm)
1256{
1257 struct snd_pcm *pcm;
1258 int err;
1259
1260 if (rpcm)
1261 *rpcm = NULL;
1262#ifdef CHIP1370
1263 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1264#else
1265 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1266#endif
1267 if (err < 0)
1268 return err;
1269
1270#ifdef CHIP1370
1271 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1272#else
1273 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1274#endif
1275 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1276
1277 pcm->private_data = ensoniq;
1278 pcm->info_flags = 0;
1279#ifdef CHIP1370
1280 strcpy(pcm->name, "ES1370 DAC2/ADC");
1281#else
1282 strcpy(pcm->name, "ES1371 DAC2/ADC");
1283#endif
1284 ensoniq->pcm1 = pcm;
1285
1286 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1287 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1288
1289 if (rpcm)
1290 *rpcm = pcm;
1291 return 0;
1292}
1293
1294static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1295 struct snd_pcm ** rpcm)
1296{
1297 struct snd_pcm *pcm;
1298 int err;
1299
1300 if (rpcm)
1301 *rpcm = NULL;
1302#ifdef CHIP1370
1303 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1304#else
1305 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1306#endif
1307 if (err < 0)
1308 return err;
1309
1310#ifdef CHIP1370
1311 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1312#else
1313 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1314#endif
1315 pcm->private_data = ensoniq;
1316 pcm->info_flags = 0;
1317#ifdef CHIP1370
1318 strcpy(pcm->name, "ES1370 DAC1");
1319#else
1320 strcpy(pcm->name, "ES1371 DAC1");
1321#endif
1322 ensoniq->pcm2 = pcm;
1323
1324 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1325 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1326
1327 if (rpcm)
1328 *rpcm = pcm;
1329 return 0;
1330}
1331
1332/*
1333 * Mixer section
1334 */
1335
1336/*
1337 * ENS1371 mixer (including SPDIF interface)
1338 */
1339#ifdef CHIP1371
1340static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1341 struct snd_ctl_elem_info *uinfo)
1342{
1343 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1344 uinfo->count = 1;
1345 return 0;
1346}
1347
1348static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1349 struct snd_ctl_elem_value *ucontrol)
1350{
1351 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1352 spin_lock_irq(&ensoniq->reg_lock);
1353 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1354 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1355 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1356 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1357 spin_unlock_irq(&ensoniq->reg_lock);
1358 return 0;
1359}
1360
1361static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1362 struct snd_ctl_elem_value *ucontrol)
1363{
1364 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1365 unsigned int val;
1366 int change;
1367
1368 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1369 ((u32)ucontrol->value.iec958.status[1] << 8) |
1370 ((u32)ucontrol->value.iec958.status[2] << 16) |
1371 ((u32)ucontrol->value.iec958.status[3] << 24);
1372 spin_lock_irq(&ensoniq->reg_lock);
1373 change = ensoniq->spdif_default != val;
1374 ensoniq->spdif_default = val;
1375 if (change && ensoniq->playback1_substream == NULL &&
1376 ensoniq->playback2_substream == NULL)
1377 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1378 spin_unlock_irq(&ensoniq->reg_lock);
1379 return change;
1380}
1381
1382static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1383 struct snd_ctl_elem_value *ucontrol)
1384{
1385 ucontrol->value.iec958.status[0] = 0xff;
1386 ucontrol->value.iec958.status[1] = 0xff;
1387 ucontrol->value.iec958.status[2] = 0xff;
1388 ucontrol->value.iec958.status[3] = 0xff;
1389 return 0;
1390}
1391
1392static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1393 struct snd_ctl_elem_value *ucontrol)
1394{
1395 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1396 spin_lock_irq(&ensoniq->reg_lock);
1397 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1398 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1399 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1400 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1401 spin_unlock_irq(&ensoniq->reg_lock);
1402 return 0;
1403}
1404
1405static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1406 struct snd_ctl_elem_value *ucontrol)
1407{
1408 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1409 unsigned int val;
1410 int change;
1411
1412 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1413 ((u32)ucontrol->value.iec958.status[1] << 8) |
1414 ((u32)ucontrol->value.iec958.status[2] << 16) |
1415 ((u32)ucontrol->value.iec958.status[3] << 24);
1416 spin_lock_irq(&ensoniq->reg_lock);
1417 change = ensoniq->spdif_stream != val;
1418 ensoniq->spdif_stream = val;
1419 if (change && (ensoniq->playback1_substream != NULL ||
1420 ensoniq->playback2_substream != NULL))
1421 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1422 spin_unlock_irq(&ensoniq->reg_lock);
1423 return change;
1424}
1425
1426#define ES1371_SPDIF(xname) \
1427{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1428 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1429
1430static int snd_es1371_spdif_info(struct snd_kcontrol *kcontrol,
1431 struct snd_ctl_elem_info *uinfo)
1432{
1433 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1434 uinfo->count = 1;
1435 uinfo->value.integer.min = 0;
1436 uinfo->value.integer.max = 1;
1437 return 0;
1438}
1439
1440static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1441 struct snd_ctl_elem_value *ucontrol)
1442{
1443 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1444
1445 spin_lock_irq(&ensoniq->reg_lock);
1446 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1447 spin_unlock_irq(&ensoniq->reg_lock);
1448 return 0;
1449}
1450
1451static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1452 struct snd_ctl_elem_value *ucontrol)
1453{
1454 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1455 unsigned int nval1, nval2;
1456 int change;
1457
1458 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1459 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1460 spin_lock_irq(&ensoniq->reg_lock);
1461 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1462 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1463 ensoniq->ctrl |= nval1;
1464 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1465 ensoniq->cssr |= nval2;
1466 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1467 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1468 spin_unlock_irq(&ensoniq->reg_lock);
1469 return change;
1470}
1471
1472
1473/* spdif controls */
1474static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1475 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1476 {
1477 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1478 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1479 .info = snd_ens1373_spdif_info,
1480 .get = snd_ens1373_spdif_default_get,
1481 .put = snd_ens1373_spdif_default_put,
1482 },
1483 {
1484 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1485 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1486 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1487 .info = snd_ens1373_spdif_info,
1488 .get = snd_ens1373_spdif_mask_get
1489 },
1490 {
1491 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1492 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1493 .info = snd_ens1373_spdif_info,
1494 .get = snd_ens1373_spdif_stream_get,
1495 .put = snd_ens1373_spdif_stream_put
1496 },
1497};
1498
1499
1500static int snd_es1373_rear_info(struct snd_kcontrol *kcontrol,
1501 struct snd_ctl_elem_info *uinfo)
1502{
1503 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1504 uinfo->count = 1;
1505 uinfo->value.integer.min = 0;
1506 uinfo->value.integer.max = 1;
1507 return 0;
1508}
1509
1510static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1511 struct snd_ctl_elem_value *ucontrol)
1512{
1513 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1514 int val = 0;
1515
1516 spin_lock_irq(&ensoniq->reg_lock);
1517 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1518 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1519 val = 1;
1520 ucontrol->value.integer.value[0] = val;
1521 spin_unlock_irq(&ensoniq->reg_lock);
1522 return 0;
1523}
1524
1525static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1526 struct snd_ctl_elem_value *ucontrol)
1527{
1528 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1529 unsigned int nval1;
1530 int change;
1531
1532 nval1 = ucontrol->value.integer.value[0] ?
1533 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1534 spin_lock_irq(&ensoniq->reg_lock);
1535 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1536 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1537 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1538 ensoniq->cssr |= nval1;
1539 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1540 spin_unlock_irq(&ensoniq->reg_lock);
1541 return change;
1542}
1543
1544static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1545{
1546 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1547 .name = "AC97 2ch->4ch Copy Switch",
1548 .info = snd_es1373_rear_info,
1549 .get = snd_es1373_rear_get,
1550 .put = snd_es1373_rear_put,
1551};
1552
1553static int snd_es1373_line_info(struct snd_kcontrol *kcontrol,
1554 struct snd_ctl_elem_info *uinfo)
1555{
1556 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1557 uinfo->count = 1;
1558 uinfo->value.integer.min = 0;
1559 uinfo->value.integer.max = 1;
1560 return 0;
1561}
1562
1563static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1564 struct snd_ctl_elem_value *ucontrol)
1565{
1566 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1567 int val = 0;
1568
1569 spin_lock_irq(&ensoniq->reg_lock);
1570 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1571 val = 1;
1572 ucontrol->value.integer.value[0] = val;
1573 spin_unlock_irq(&ensoniq->reg_lock);
1574 return 0;
1575}
1576
1577static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1578 struct snd_ctl_elem_value *ucontrol)
1579{
1580 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1581 int changed;
1582 unsigned int ctrl;
1583
1584 spin_lock_irq(&ensoniq->reg_lock);
1585 ctrl = ensoniq->ctrl;
1586 if (ucontrol->value.integer.value[0])
1587 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1588 else
1589 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1590 changed = (ctrl != ensoniq->ctrl);
1591 if (changed)
1592 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1593 spin_unlock_irq(&ensoniq->reg_lock);
1594 return changed;
1595}
1596
1597static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1598{
1599 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1600 .name = "Line In->Rear Out Switch",
1601 .info = snd_es1373_line_info,
1602 .get = snd_es1373_line_get,
1603 .put = snd_es1373_line_put,
1604};
1605
1606static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1607{
1608 struct ensoniq *ensoniq = ac97->private_data;
1609 ensoniq->u.es1371.ac97 = NULL;
1610}
1611
1612static struct {
1613 unsigned short vid; /* vendor ID */
1614 unsigned short did; /* device ID */
1615 unsigned char rev; /* revision */
1616} es1371_spdif_present[] __devinitdata = {
1617 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1618 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1619 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1620 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1621 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1622 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1623};
1624
1625static int snd_ensoniq_1371_mixer(struct ensoniq * ensoniq, int has_spdif, int has_line)
1626{
1627 struct snd_card *card = ensoniq->card;
1628 struct snd_ac97_bus *pbus;
1629 struct snd_ac97_template ac97;
1630 int err, idx;
1631 static struct snd_ac97_bus_ops ops = {
1632 .write = snd_es1371_codec_write,
1633 .read = snd_es1371_codec_read,
1634 .wait = snd_es1371_codec_wait,
1635 };
1636
1637 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1638 return err;
1639
1640 memset(&ac97, 0, sizeof(ac97));
1641 ac97.private_data = ensoniq;
1642 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1643 ac97.scaps = AC97_SCAP_AUDIO;
1644 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1645 return err;
1646 for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1647 if ((ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1648 ensoniq->pci->device == es1371_spdif_present[idx].did &&
1649 ensoniq->rev == es1371_spdif_present[idx].rev) || has_spdif > 0) {
1650 struct snd_kcontrol *kctl;
1651 int i, index = 0;
1652
1653 if (has_spdif < 0)
1654 break;
1655
1656 ensoniq->spdif_default = ensoniq->spdif_stream =
1657 SNDRV_PCM_DEFAULT_CON_SPDIF;
1658 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1659
1660 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1661 index++;
1662
1663 for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1664 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1665 if (! kctl)
1666 return -ENOMEM;
1667 kctl->id.index = index;
1668 if ((err = snd_ctl_add(card, kctl)) < 0)
1669 return err;
1670 }
1671 break;
1672 }
1673 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1674 /* mirror rear to front speakers */
1675 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1676 ensoniq->cssr |= ES_1373_REAR_BIT26;
1677 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1678 if (err < 0)
1679 return err;
1680 }
1681 if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1682 (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1683 ((ensoniq->subsystem_vendor_id == 0x1458) &&
1684 (ensoniq->subsystem_device_id == 0xa000)) || /* GA-8IEXP */
1685 has_line > 0) {
1686 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1687 if (err < 0)
1688 return err;
1689 }
1690
1691 return 0;
1692}
1693
1694#endif /* CHIP1371 */
1695
1696/* generic control callbacks for ens1370 */
1697#ifdef CHIP1370
1698#define ENSONIQ_CONTROL(xname, mask) \
1699{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1700 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1701 .private_value = mask }
1702
1703static int snd_ensoniq_control_info(struct snd_kcontrol *kcontrol,
1704 struct snd_ctl_elem_info *uinfo)
1705{
1706 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1707 uinfo->count = 1;
1708 uinfo->value.integer.min = 0;
1709 uinfo->value.integer.max = 1;
1710 return 0;
1711}
1712
1713static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1714 struct snd_ctl_elem_value *ucontrol)
1715{
1716 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1717 int mask = kcontrol->private_value;
1718
1719 spin_lock_irq(&ensoniq->reg_lock);
1720 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1721 spin_unlock_irq(&ensoniq->reg_lock);
1722 return 0;
1723}
1724
1725static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1726 struct snd_ctl_elem_value *ucontrol)
1727{
1728 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1729 int mask = kcontrol->private_value;
1730 unsigned int nval;
1731 int change;
1732
1733 nval = ucontrol->value.integer.value[0] ? mask : 0;
1734 spin_lock_irq(&ensoniq->reg_lock);
1735 change = (ensoniq->ctrl & mask) != nval;
1736 ensoniq->ctrl &= ~mask;
1737 ensoniq->ctrl |= nval;
1738 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1739 spin_unlock_irq(&ensoniq->reg_lock);
1740 return change;
1741}
1742
1743/*
1744 * ENS1370 mixer
1745 */
1746
1747static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1748ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1749ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1750};
1751
1752#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1753
1754static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1755{
1756 struct ensoniq *ensoniq = ak4531->private_data;
1757 ensoniq->u.es1370.ak4531 = NULL;
1758}
1759
1760static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1761{
1762 struct snd_card *card = ensoniq->card;
1763 struct snd_ak4531 ak4531;
1764 unsigned int idx;
1765 int err;
1766
1767 /* try reset AK4531 */
1768 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1769 inw(ES_REG(ensoniq, 1370_CODEC));
1770 udelay(100);
1771 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1772 inw(ES_REG(ensoniq, 1370_CODEC));
1773 udelay(100);
1774
1775 memset(&ak4531, 0, sizeof(ak4531));
1776 ak4531.write = snd_es1370_codec_write;
1777 ak4531.private_data = ensoniq;
1778 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1779 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1780 return err;
1781 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1782 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1783 if (err < 0)
1784 return err;
1785 }
1786 return 0;
1787}
1788
1789#endif /* CHIP1370 */
1790
1791#ifdef SUPPORT_JOYSTICK
1792
1793#ifdef CHIP1371
1794static int __devinit snd_ensoniq_get_joystick_port(int dev)
1795{
1796 switch (joystick_port[dev]) {
1797 case 0: /* disabled */
1798 case 1: /* auto-detect */
1799 case 0x200:
1800 case 0x208:
1801 case 0x210:
1802 case 0x218:
1803 return joystick_port[dev];
1804
1805 default:
1806 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1807 return 0;
1808 }
1809}
1810#else
1811static inline int snd_ensoniq_get_joystick_port(int dev)
1812{
1813 return joystick[dev] ? 0x200 : 0;
1814}
1815#endif
1816
1817static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1818{
1819 struct gameport *gp;
1820 int io_port;
1821
1822 io_port = snd_ensoniq_get_joystick_port(dev);
1823
1824 switch (io_port) {
1825 case 0:
1826 return -ENOSYS;
1827
1828 case 1: /* auto_detect */
1829 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1830 if (request_region(io_port, 8, "ens137x: gameport"))
1831 break;
1832 if (io_port > 0x218) {
1833 printk(KERN_WARNING "ens137x: no gameport ports available\n");
1834 return -EBUSY;
1835 }
1836 break;
1837
1838 default:
1839 if (!request_region(io_port, 8, "ens137x: gameport")) {
1840 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1841 io_port);
1842 return -EBUSY;
1843 }
1844 break;
1845 }
1846
1847 ensoniq->gameport = gp = gameport_allocate_port();
1848 if (!gp) {
1849 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1850 release_region(io_port, 8);
1851 return -ENOMEM;
1852 }
1853
1854 gameport_set_name(gp, "ES137x");
1855 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1856 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1857 gp->io = io_port;
1858
1859 ensoniq->ctrl |= ES_JYSTK_EN;
1860#ifdef CHIP1371
1861 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1862 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1863#endif
1864 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1865
1866 gameport_register_port(ensoniq->gameport);
1867
1868 return 0;
1869}
1870
1871static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1872{
1873 if (ensoniq->gameport) {
1874 int port = ensoniq->gameport->io;
1875
1876 gameport_unregister_port(ensoniq->gameport);
1877 ensoniq->gameport = NULL;
1878 ensoniq->ctrl &= ~ES_JYSTK_EN;
1879 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1880 release_region(port, 8);
1881 }
1882}
1883#else
1884static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1885static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1886#endif /* SUPPORT_JOYSTICK */
1887
1888/*
1889
1890 */
1891
1892static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1893 struct snd_info_buffer *buffer)
1894{
1895 struct ensoniq *ensoniq = entry->private_data;
1896
1897#ifdef CHIP1370
1898 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1899#else
1900 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1901#endif
1902 snd_iprintf(buffer, "Joystick enable : %s\n",
1903 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1904#ifdef CHIP1370
1905 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1906 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1907 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1908 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1909#else
1910 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1911 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1912#endif
1913}
1914
1915static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1916{
1917 struct snd_info_entry *entry;
1918
1919 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1920 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1921}
1922
1923/*
1924
1925 */
1926
1927static int snd_ensoniq_free(struct ensoniq *ensoniq)
1928{
1929 snd_ensoniq_free_gameport(ensoniq);
1930 if (ensoniq->irq < 0)
1931 goto __hw_end;
1932#ifdef CHIP1370
1933 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1934 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1935#else
1936 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1937 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1938#endif
1939 synchronize_irq(ensoniq->irq);
1940 pci_set_power_state(ensoniq->pci, 3);
1941 __hw_end:
1942#ifdef CHIP1370
1943 if (ensoniq->dma_bug.area)
1944 snd_dma_free_pages(&ensoniq->dma_bug);
1945#endif
1946 if (ensoniq->irq >= 0)
1947 free_irq(ensoniq->irq, ensoniq);
1948 pci_release_regions(ensoniq->pci);
1949 pci_disable_device(ensoniq->pci);
1950 kfree(ensoniq);
1951 return 0;
1952}
1953
1954static int snd_ensoniq_dev_free(struct snd_device *device)
1955{
1956 struct ensoniq *ensoniq = device->device_data;
1957 return snd_ensoniq_free(ensoniq);
1958}
1959
1960#ifdef CHIP1371
1961static struct {
1962 unsigned short svid; /* subsystem vendor ID */
1963 unsigned short sdid; /* subsystem device ID */
1964} es1371_amplifier_hack[] = {
1965 { .svid = 0x107b, .sdid = 0x2150 }, /* Gateway Solo 2150 */
1966 { .svid = 0x13bd, .sdid = 0x100c }, /* EV1938 on Mebius PC-MJ100V */
1967 { .svid = 0x1102, .sdid = 0x5938 }, /* Targa Xtender300 */
1968 { .svid = 0x1102, .sdid = 0x8938 }, /* IPC Topnote G notebook */
1969 { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1970};
1971static struct {
1972 unsigned short vid; /* vendor ID */
1973 unsigned short did; /* device ID */
1974 unsigned char rev; /* revision */
1975} es1371_ac97_reset_hack[] = {
1976 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1977 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1978 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1979 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1980 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1981 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1982};
1983#endif
1984
1985static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1986{
1987#ifdef CHIP1371
1988 int idx;
1989 struct pci_dev *pci = ensoniq->pci;
1990#endif
1991 /* this code was part of snd_ensoniq_create before intruduction
1992 * of suspend/resume
1993 */
1994#ifdef CHIP1370
1995 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1996 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1997 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1998 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1999 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
2000#else
2001 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2002 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2003 outl(0, ES_REG(ensoniq, 1371_LEGACY));
2004 for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2005 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2006 pci->device == es1371_ac97_reset_hack[idx].did &&
2007 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2008 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2009 /* need to delay around 20ms(bleech) to give
2010 some CODECs enough time to wakeup */
2011 msleep(20);
2012 break;
2013 }
2014 /* AC'97 warm reset to start the bitclk */
2015 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2016 inl(ES_REG(ensoniq, CONTROL));
2017 udelay(20);
2018 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2019 /* Init the sample rate converter */
2020 snd_es1371_wait_src_ready(ensoniq);
2021 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2022 for (idx = 0; idx < 0x80; idx++)
2023 snd_es1371_src_write(ensoniq, idx, 0);
2024 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2025 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2026 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2027 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2028 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2029 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2030 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2031 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2032 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2033 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2034 snd_es1371_adc_rate(ensoniq, 22050);
2035 snd_es1371_dac1_rate(ensoniq, 22050);
2036 snd_es1371_dac2_rate(ensoniq, 22050);
2037 /* WARNING:
2038 * enabling the sample rate converter without properly programming
2039 * its parameters causes the chip to lock up (the SRC busy bit will
2040 * be stuck high, and I've found no way to rectify this other than
2041 * power cycle) - Thomas Sailer
2042 */
2043 snd_es1371_wait_src_ready(ensoniq);
2044 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2045 /* try reset codec directly */
2046 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2047#endif
2048 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2049 outb(0x00, ES_REG(ensoniq, UART_RES));
2050 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2051 synchronize_irq(ensoniq->irq);
2052}
2053
2054#ifdef CONFIG_PM
2055static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
2056{
2057 struct snd_card *card = pci_get_drvdata(pci);
2058 struct ensoniq *ensoniq = card->private_data;
2059
2060 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2061
2062 snd_pcm_suspend_all(ensoniq->pcm1);
2063 snd_pcm_suspend_all(ensoniq->pcm2);
2064
2065#ifdef CHIP1371
2066 snd_ac97_suspend(ensoniq->u.es1371.ac97);
2067#else
2068 /* try to reset AK4531 */
2069 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2070 inw(ES_REG(ensoniq, 1370_CODEC));
2071 udelay(100);
2072 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2073 inw(ES_REG(ensoniq, 1370_CODEC));
2074 udelay(100);
2075 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2076#endif
2077 pci_set_power_state(pci, PCI_D3hot);
2078 pci_disable_device(pci);
2079 pci_save_state(pci);
2080 return 0;
2081}
2082
2083static int snd_ensoniq_resume(struct pci_dev *pci)
2084{
2085 struct snd_card *card = pci_get_drvdata(pci);
2086 struct ensoniq *ensoniq = card->private_data;
2087
2088 pci_restore_state(pci);
2089 pci_enable_device(pci);
2090 pci_set_power_state(pci, PCI_D0);
2091 pci_set_master(pci);
2092
2093 snd_ensoniq_chip_init(ensoniq);
2094
2095#ifdef CHIP1371
2096 snd_ac97_resume(ensoniq->u.es1371.ac97);
2097#else
2098 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2099#endif
2100 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2101 return 0;
2102}
2103#endif /* CONFIG_PM */
2104
2105
2106static int __devinit snd_ensoniq_create(struct snd_card *card,
2107 struct pci_dev *pci,
2108 struct ensoniq ** rensoniq)
2109{
2110 struct ensoniq *ensoniq;
2111 unsigned short cmdw;
2112 unsigned char cmdb;
2113#ifdef CHIP1371
2114 int idx;
2115#endif
2116 int err;
2117 static struct snd_device_ops ops = {
2118 .dev_free = snd_ensoniq_dev_free,
2119 };
2120
2121 *rensoniq = NULL;
2122 if ((err = pci_enable_device(pci)) < 0)
2123 return err;
2124 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2125 if (ensoniq == NULL) {
2126 pci_disable_device(pci);
2127 return -ENOMEM;
2128 }
2129 spin_lock_init(&ensoniq->reg_lock);
2130 init_MUTEX(&ensoniq->src_mutex);
2131 ensoniq->card = card;
2132 ensoniq->pci = pci;
2133 ensoniq->irq = -1;
2134 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2135 kfree(ensoniq);
2136 pci_disable_device(pci);
2137 return err;
2138 }
2139 ensoniq->port = pci_resource_start(pci, 0);
2140 if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ,
2141 "Ensoniq AudioPCI", ensoniq)) {
2142 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2143 snd_ensoniq_free(ensoniq);
2144 return -EBUSY;
2145 }
2146 ensoniq->irq = pci->irq;
2147#ifdef CHIP1370
2148 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2149 16, &ensoniq->dma_bug) < 0) {
2150 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2151 snd_ensoniq_free(ensoniq);
2152 return -EBUSY;
2153 }
2154#endif
2155 pci_set_master(pci);
2156 pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
2157 ensoniq->rev = cmdb;
2158 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
2159 ensoniq->subsystem_vendor_id = cmdw;
2160 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
2161 ensoniq->subsystem_device_id = cmdw;
2162#ifdef CHIP1370
2163#if 0
2164 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2165 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2166#else /* get microphone working */
2167 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2168#endif
2169 ensoniq->sctrl = 0;
2170#else
2171 ensoniq->ctrl = 0;
2172 ensoniq->sctrl = 0;
2173 ensoniq->cssr = 0;
2174 for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2175 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2176 ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2177 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2178 break;
2179 }
2180 for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2181 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2182 pci->device == es1371_ac97_reset_hack[idx].did &&
2183 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2184 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2185 break;
2186 }
2187#endif
2188
2189 snd_ensoniq_chip_init(ensoniq);
2190
2191 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2192 snd_ensoniq_free(ensoniq);
2193 return err;
2194 }
2195
2196 snd_ensoniq_proc_init(ensoniq);
2197
2198 snd_card_set_dev(card, &pci->dev);
2199
2200 *rensoniq = ensoniq;
2201 return 0;
2202}
2203
2204/*
2205 * MIDI section
2206 */
2207
2208static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2209{
2210 struct snd_rawmidi *rmidi = ensoniq->rmidi;
2211 unsigned char status, mask, byte;
2212
2213 if (rmidi == NULL)
2214 return;
2215 /* do Rx at first */
2216 spin_lock(&ensoniq->reg_lock);
2217 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2218 while (mask) {
2219 status = inb(ES_REG(ensoniq, UART_STATUS));
2220 if ((status & mask) == 0)
2221 break;
2222 byte = inb(ES_REG(ensoniq, UART_DATA));
2223 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2224 }
2225 spin_unlock(&ensoniq->reg_lock);
2226
2227 /* do Tx at second */
2228 spin_lock(&ensoniq->reg_lock);
2229 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2230 while (mask) {
2231 status = inb(ES_REG(ensoniq, UART_STATUS));
2232 if ((status & mask) == 0)
2233 break;
2234 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2235 ensoniq->uartc &= ~ES_TXINTENM;
2236 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2237 mask &= ~ES_TXRDY;
2238 } else {
2239 outb(byte, ES_REG(ensoniq, UART_DATA));
2240 }
2241 }
2242 spin_unlock(&ensoniq->reg_lock);
2243}
2244
2245static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2246{
2247 struct ensoniq *ensoniq = substream->rmidi->private_data;
2248
2249 spin_lock_irq(&ensoniq->reg_lock);
2250 ensoniq->uartm |= ES_MODE_INPUT;
2251 ensoniq->midi_input = substream;
2252 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2253 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2254 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2255 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2256 }
2257 spin_unlock_irq(&ensoniq->reg_lock);
2258 return 0;
2259}
2260
2261static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2262{
2263 struct ensoniq *ensoniq = substream->rmidi->private_data;
2264
2265 spin_lock_irq(&ensoniq->reg_lock);
2266 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2267 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2268 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2269 } else {
2270 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2271 }
2272 ensoniq->midi_input = NULL;
2273 ensoniq->uartm &= ~ES_MODE_INPUT;
2274 spin_unlock_irq(&ensoniq->reg_lock);
2275 return 0;
2276}
2277
2278static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2279{
2280 struct ensoniq *ensoniq = substream->rmidi->private_data;
2281
2282 spin_lock_irq(&ensoniq->reg_lock);
2283 ensoniq->uartm |= ES_MODE_OUTPUT;
2284 ensoniq->midi_output = substream;
2285 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2286 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2287 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2288 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2289 }
2290 spin_unlock_irq(&ensoniq->reg_lock);
2291 return 0;
2292}
2293
2294static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2295{
2296 struct ensoniq *ensoniq = substream->rmidi->private_data;
2297
2298 spin_lock_irq(&ensoniq->reg_lock);
2299 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2300 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2301 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2302 } else {
2303 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2304 }
2305 ensoniq->midi_output = NULL;
2306 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2307 spin_unlock_irq(&ensoniq->reg_lock);
2308 return 0;
2309}
2310
2311static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2312{
2313 unsigned long flags;
2314 struct ensoniq *ensoniq = substream->rmidi->private_data;
2315 int idx;
2316
2317 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2318 if (up) {
2319 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2320 /* empty input FIFO */
2321 for (idx = 0; idx < 32; idx++)
2322 inb(ES_REG(ensoniq, UART_DATA));
2323 ensoniq->uartc |= ES_RXINTEN;
2324 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2325 }
2326 } else {
2327 if (ensoniq->uartc & ES_RXINTEN) {
2328 ensoniq->uartc &= ~ES_RXINTEN;
2329 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2330 }
2331 }
2332 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2333}
2334
2335static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2336{
2337 unsigned long flags;
2338 struct ensoniq *ensoniq = substream->rmidi->private_data;
2339 unsigned char byte;
2340
2341 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2342 if (up) {
2343 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2344 ensoniq->uartc |= ES_TXINTENO(1);
2345 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2346 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2347 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2348 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2349 ensoniq->uartc &= ~ES_TXINTENM;
2350 } else {
2351 outb(byte, ES_REG(ensoniq, UART_DATA));
2352 }
2353 }
2354 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2355 }
2356 } else {
2357 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2358 ensoniq->uartc &= ~ES_TXINTENM;
2359 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2360 }
2361 }
2362 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2363}
2364
2365static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2366{
2367 .open = snd_ensoniq_midi_output_open,
2368 .close = snd_ensoniq_midi_output_close,
2369 .trigger = snd_ensoniq_midi_output_trigger,
2370};
2371
2372static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2373{
2374 .open = snd_ensoniq_midi_input_open,
2375 .close = snd_ensoniq_midi_input_close,
2376 .trigger = snd_ensoniq_midi_input_trigger,
2377};
2378
2379static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2380 struct snd_rawmidi **rrawmidi)
2381{
2382 struct snd_rawmidi *rmidi;
2383 int err;
2384
2385 if (rrawmidi)
2386 *rrawmidi = NULL;
2387 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2388 return err;
2389#ifdef CHIP1370
2390 strcpy(rmidi->name, "ES1370");
2391#else
2392 strcpy(rmidi->name, "ES1371");
2393#endif
2394 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2395 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2396 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2397 SNDRV_RAWMIDI_INFO_DUPLEX;
2398 rmidi->private_data = ensoniq;
2399 ensoniq->rmidi = rmidi;
2400 if (rrawmidi)
2401 *rrawmidi = rmidi;
2402 return 0;
2403}
2404
2405/*
2406 * Interrupt handler
2407 */
2408
2409static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2410{
2411 struct ensoniq *ensoniq = dev_id;
2412 unsigned int status, sctrl;
2413
2414 if (ensoniq == NULL)
2415 return IRQ_NONE;
2416
2417 status = inl(ES_REG(ensoniq, STATUS));
2418 if (!(status & ES_INTR))
2419 return IRQ_NONE;
2420
2421 spin_lock(&ensoniq->reg_lock);
2422 sctrl = ensoniq->sctrl;
2423 if (status & ES_DAC1)
2424 sctrl &= ~ES_P1_INT_EN;
2425 if (status & ES_DAC2)
2426 sctrl &= ~ES_P2_INT_EN;
2427 if (status & ES_ADC)
2428 sctrl &= ~ES_R1_INT_EN;
2429 outl(sctrl, ES_REG(ensoniq, SERIAL));
2430 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2431 spin_unlock(&ensoniq->reg_lock);
2432
2433 if (status & ES_UART)
2434 snd_ensoniq_midi_interrupt(ensoniq);
2435 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2436 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2437 if ((status & ES_ADC) && ensoniq->capture_substream)
2438 snd_pcm_period_elapsed(ensoniq->capture_substream);
2439 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2440 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2441 return IRQ_HANDLED;
2442}
2443
2444static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2445 const struct pci_device_id *pci_id)
2446{
2447 static int dev;
2448 struct snd_card *card;
2449 struct ensoniq *ensoniq;
2450 int err, pcm_devs[2];
2451
2452 if (dev >= SNDRV_CARDS)
2453 return -ENODEV;
2454 if (!enable[dev]) {
2455 dev++;
2456 return -ENOENT;
2457 }
2458
2459 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2460 if (card == NULL)
2461 return -ENOMEM;
2462
2463 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2464 snd_card_free(card);
2465 return err;
2466 }
2467 card->private_data = ensoniq;
2468
2469 pcm_devs[0] = 0; pcm_devs[1] = 1;
2470#ifdef CHIP1370
2471 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2472 snd_card_free(card);
2473 return err;
2474 }
2475#endif
2476#ifdef CHIP1371
2477 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2478 snd_card_free(card);
2479 return err;
2480 }
2481#endif
2482 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2483 snd_card_free(card);
2484 return err;
2485 }
2486 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2487 snd_card_free(card);
2488 return err;
2489 }
2490 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2491 snd_card_free(card);
2492 return err;
2493 }
2494
2495 snd_ensoniq_create_gameport(ensoniq, dev);
2496
2497 strcpy(card->driver, DRIVER_NAME);
2498
2499 strcpy(card->shortname, "Ensoniq AudioPCI");
2500 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2501 card->shortname,
2502 card->driver,
2503 ensoniq->port,
2504 ensoniq->irq);
2505
2506 if ((err = snd_card_register(card)) < 0) {
2507 snd_card_free(card);
2508 return err;
2509 }
2510
2511 pci_set_drvdata(pci, card);
2512 dev++;
2513 return 0;
2514}
2515
2516static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2517{
2518 snd_card_free(pci_get_drvdata(pci));
2519 pci_set_drvdata(pci, NULL);
2520}
2521
2522static struct pci_driver driver = {
2523 .name = DRIVER_NAME,
2524 .id_table = snd_audiopci_ids,
2525 .probe = snd_audiopci_probe,
2526 .remove = snd_audiopci_remove,
2527#ifdef CONFIG_PM
2528 .suspend = snd_ensoniq_suspend,
2529 .resume = snd_ensoniq_resume,
2530#endif
2531};
2532
2533static int __init alsa_card_ens137x_init(void)
2534{
2535 return pci_register_driver(&driver);
2536}
2537
2538static void __exit alsa_card_ens137x_exit(void)
2539{
2540 pci_unregister_driver(&driver);
2541}
2542
2543module_init(alsa_card_ens137x_init)
2544module_exit(alsa_card_ens137x_exit)
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