source: GPL/trunk/alsa-kernel/pci/ens1370.c

Last change on this file was 777, checked in by David Azarewicz, 6 months ago

Merge from uniaud32-exp branch
File size: 78.1 KB
RevLine 
[679]1// SPDX-License-Identifier: GPL-2.0-or-later
[358]2/*
3 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 * Thomas Sailer <sailer@ife.ee.ethz.ch>
6 */
7
8/* Power-Management-Code ( CONFIG_PM )
9 * for ens1371 only ( FIXME )
10 * derived from cs4281.c, atiixp.c and via82xx.c
[772]11 * using https://www.kernel.org/doc/html/latest/sound/kernel-api/writing-an-alsa-driver.html
[358]12 * by Kurt J. Bosch
13 */
14
[679]15#include <linux/io.h>
[358]16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/slab.h>
21#include <linux/gameport.h>
[679]22#include <linux/module.h>
[358]23#include <linux/mutex.h>
24
25#include <sound/core.h>
26#include <sound/control.h>
27#include <sound/pcm.h>
28#include <sound/rawmidi.h>
29#ifdef CHIP1371
30#include <sound/ac97_codec.h>
31#else
32#include <sound/ak4531_codec.h>
33#endif
34#include <sound/initval.h>
35#include <sound/asoundef.h>
36
37#ifndef CHIP1371
38#undef CHIP1370
39#define CHIP1370
40#endif
41
42#ifdef CHIP1370
43#define DRIVER_NAME "ENS1370"
[679]44#define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
[358]45#else
46#define DRIVER_NAME "ENS1371"
[679]47#define CHIP_NAME "ES1371"
[358]48#endif
49
50
[679]51#ifdef TARGET_OS2
52#define KBUILD_MODNAME "ens137x"
53#endif
[358]54MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
55MODULE_LICENSE("GPL");
56#ifdef CHIP1370
57MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
58#endif
59#ifdef CHIP1371
60MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
61#endif
62
[679]63#if IS_REACHABLE(CONFIG_GAMEPORT)
[358]64#define SUPPORT_JOYSTICK
65#endif
66
67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
[679]69static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
[358]70#ifdef SUPPORT_JOYSTICK
71#ifdef CHIP1371
72static int joystick_port[SNDRV_CARDS];
73#else
[679]74static bool joystick[SNDRV_CARDS];
[358]75#endif
76#endif
77#ifdef CHIP1371
78static int spdif[SNDRV_CARDS];
79static int lineio[SNDRV_CARDS];
80#endif
81
82module_param_array(index, int, NULL, 0444);
83MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
84module_param_array(id, charp, NULL, 0444);
85MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
86module_param_array(enable, bool, NULL, 0444);
87MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
88#ifdef SUPPORT_JOYSTICK
89#ifdef CHIP1371
[679]90module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
[358]91MODULE_PARM_DESC(joystick_port, "Joystick port address.");
92#else
93module_param_array(joystick, bool, NULL, 0444);
94MODULE_PARM_DESC(joystick, "Enable joystick.");
95#endif
96#endif /* SUPPORT_JOYSTICK */
97#ifdef CHIP1371
98module_param_array(spdif, int, NULL, 0444);
99MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
100module_param_array(lineio, int, NULL, 0444);
101MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
102#endif
103
104/* ES1371 chip ID */
105/* This is a little confusing because all ES1371 compatible chips have the
106 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
107 This is only significant if you want to enable features on the later parts.
108 Yes, I know it's stupid and why didn't we use the sub IDs?
109*/
110#define ES1371REV_ES1373_A 0x04
111#define ES1371REV_ES1373_B 0x06
112#define ES1371REV_CT5880_A 0x07
113#define CT5880REV_CT5880_C 0x02
114#define CT5880REV_CT5880_D 0x03 /* ??? -jk */
115#define CT5880REV_CT5880_E 0x04 /* mw */
116#define ES1371REV_ES1371_B 0x09
117#define EV1938REV_EV1938_A 0x00
118#define ES1371REV_ES1373_8 0x08
119
120/*
121 * Direct registers
122 */
123
124#define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
125
126#define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
127#define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
128#define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
129#define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
130#define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
131#define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
132#define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
133#define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
134#define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
135#define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
136#define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
137#define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
138#define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
139#define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
140#define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
141#define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
142#define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
143#define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
144#define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
145#define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
146#define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
147#define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
148#define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
149#define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
150#define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
151#define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
152#define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
153#define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
154#define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
155#define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
156#define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
157#define ES_1371_PDLEVM (0x03<<8) /* mask for above */
158#define ES_BREQ (1<<7) /* memory bus request enable */
159#define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
160#define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
161#define ES_ADC_EN (1<<4) /* ADC capture channel enable */
162#define ES_UART_EN (1<<3) /* UART enable */
163#define ES_JYSTK_EN (1<<2) /* Joystick module enable */
164#define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
165#define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
166#define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
167#define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
168#define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
169#define ES_INTR (1<<31) /* Interrupt is pending */
170#define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
171#define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
172#define ES_1373_REAR_BIT26 (1<<26)
173#define ES_1373_REAR_BIT24 (1<<24)
174#define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
175#define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
176#define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
177#define ES_1371_TEST (1<<16) /* test ASIC */
178#define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
179#define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
180#define ES_1370_CBUSY (1<<9) /* CODEC is busy */
181#define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
182#define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
183#define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
184#define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
185#define ES_1371_MPWR (1<<5) /* power level interrupt pending */
186#define ES_MCCB (1<<4) /* CCB interrupt pending */
187#define ES_UART (1<<3) /* UART interrupt pending */
188#define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
189#define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
190#define ES_ADC (1<<0) /* ADC channel interrupt pending */
191#define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
192#define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
193#define ES_RXINT (1<<7) /* RX interrupt occurred */
194#define ES_TXINT (1<<2) /* TX interrupt occurred */
195#define ES_TXRDY (1<<1) /* transmitter ready */
196#define ES_RXRDY (1<<0) /* receiver ready */
197#define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
198#define ES_RXINTEN (1<<7) /* RX interrupt enable */
199#define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
200#define ES_TXINTENM (0x03<<5) /* mask for above */
201#define ES_TXINTENI(i) (((i)>>5)&0x03)
202#define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
203#define ES_CNTRLM (0x03<<0) /* mask for above */
204#define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
205#define ES_TEST_MODE (1<<0) /* test mode enabled */
206#define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
207#define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
208#define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
209#define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
210#define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
211#define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
212#define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
213#define ES_1371_CODEC_RDY (1<<31) /* codec ready */
214#define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
[679]215#define EV_1938_CODEC_MAGIC (1<<26)
[358]216#define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
217#define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
218#define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
219#define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
220
221#define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
222#define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
223#define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
224#define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
225#define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
226#define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
227#define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
228#define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
229#define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
230#define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
231#define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
232#define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
233#define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
234
235#define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
236#define ES_1371_JFAST (1<<31) /* fast joystick timing */
237#define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
238#define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
239#define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
240#define ES_1371_VMPUM (0x03<<27) /* mask for above */
241#define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
242#define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
243#define ES_1371_VCDCM (0x03<<25) /* mask for above */
244#define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
245#define ES_1371_FIRQ (1<<24) /* force an interrupt */
246#define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
247#define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
248#define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
249#define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
250#define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
251#define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
252#define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
253#define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
254#define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
255#define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
256#define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
257#define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
258
259#define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
260
261#define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
262#define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
263#define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
264#define ES_P2_END_INCM (0x07<<19) /* mask for above */
265#define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
266#define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
267#define ES_P2_ST_INCM (0x07<<16) /* mask for above */
268#define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
269#define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
270#define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
271#define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
272#define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
273#define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
274#define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
275#define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
276#define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
277#define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
278#define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
279#define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
280#define ES_R1_MODEM (0x03<<4) /* mask for above */
281#define ES_R1_MODEI(i) (((i)>>4)&0x03)
282#define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
283#define ES_P2_MODEM (0x03<<2) /* mask for above */
284#define ES_P2_MODEI(i) (((i)>>2)&0x03)
285#define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
286#define ES_P1_MODEM (0x03<<0) /* mask for above */
287#define ES_P1_MODEI(i) (((i)>>0)&0x03)
288
289#define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
290#define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
291#define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
292#define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
293#define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
294#define ES_REG_COUNTM (0xffff<<0)
295#define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
296
297#define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
298#define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
299#define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
300#define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
301#define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
302#define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
303#define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
304#define ES_REG_FCURR_COUNTM (0xffff<<16)
305#define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
306#define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
307#define ES_REG_FSIZEM (0xffff<<0)
308#define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
309#define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
310#define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
311
312#define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
313#define ES_REG_UF_VALID (1<<8)
314#define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
315#define ES_REG_UF_BYTEM (0xff<<0)
316#define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
317
318
319/*
320 * Pages
321 */
322
323#define ES_PAGE_DAC 0x0c
324#define ES_PAGE_ADC 0x0d
325#define ES_PAGE_UART 0x0e
326#define ES_PAGE_UART1 0x0f
327
328/*
329 * Sample rate converter addresses
330 */
331
332#define ES_SMPREG_DAC1 0x70
333#define ES_SMPREG_DAC2 0x74
334#define ES_SMPREG_ADC 0x78
335#define ES_SMPREG_VOL_ADC 0x6c
336#define ES_SMPREG_VOL_DAC1 0x7c
337#define ES_SMPREG_VOL_DAC2 0x7e
338#define ES_SMPREG_TRUNC_N 0x00
339#define ES_SMPREG_INT_REGS 0x01
340#define ES_SMPREG_ACCUM_FRAC 0x02
341#define ES_SMPREG_VFREQ_FRAC 0x03
342
343/*
344 * Some contants
345 */
346
347#define ES_1370_SRCLOCK 1411200
348#define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
349
350/*
351 * Open modes
352 */
353
354#define ES_MODE_PLAY1 0x0001
355#define ES_MODE_PLAY2 0x0002
356#define ES_MODE_CAPTURE 0x0004
357
358#define ES_MODE_OUTPUT 0x0001 /* for MIDI */
359#define ES_MODE_INPUT 0x0002 /* for MIDI */
360
361/*
362
363 */
364
365struct ensoniq {
366 spinlock_t reg_lock;
367 struct mutex src_mutex;
368
369 int irq;
370
371 unsigned long playback1size;
372 unsigned long playback2size;
373 unsigned long capture3size;
374
375 unsigned long port;
376 unsigned int mode;
377 unsigned int uartm; /* UART mode */
378
379 unsigned int ctrl; /* control register */
380 unsigned int sctrl; /* serial control register */
381 unsigned int cssr; /* control status register */
382 unsigned int uartc; /* uart control register */
383 unsigned int rev; /* chip revision */
384
385 union {
386#ifdef CHIP1371
387 struct {
388 struct snd_ac97 *ac97;
389 } es1371;
390#else
391 struct {
392 int pclkdiv_lock;
393 struct snd_ak4531 *ak4531;
394 } es1370;
395#endif
396 } u;
397
398 struct pci_dev *pci;
399 struct snd_card *card;
400 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
401 struct snd_pcm *pcm2; /* DAC2 PCM */
402 struct snd_pcm_substream *playback1_substream;
403 struct snd_pcm_substream *playback2_substream;
404 struct snd_pcm_substream *capture_substream;
405 unsigned int p1_dma_size;
406 unsigned int p2_dma_size;
407 unsigned int c_dma_size;
408 unsigned int p1_period_size;
409 unsigned int p2_period_size;
410 unsigned int c_period_size;
411 struct snd_rawmidi *rmidi;
412 struct snd_rawmidi_substream *midi_input;
413 struct snd_rawmidi_substream *midi_output;
414
415 unsigned int spdif;
416 unsigned int spdif_default;
417 unsigned int spdif_stream;
418
419#ifdef CHIP1370
[717]420 struct snd_dma_buffer *dma_bug;
[358]421#endif
422
423#ifdef SUPPORT_JOYSTICK
424 struct gameport *gameport;
425#endif
426};
427
428static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
429
[679]430static const struct pci_device_id snd_audiopci_ids[] = {
[358]431#ifdef CHIP1370
[464]432 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
[358]433#endif
434#ifdef CHIP1371
[464]435 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
436 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
437 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
[358]438#endif
439 { 0, }
440};
441
442MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
443
444/*
445 * constants
446 */
447
448#define POLL_COUNT 0xa000
449
450#ifdef CHIP1370
[679]451static const unsigned int snd_es1370_fixed_rates[] =
[358]452 {5512, 11025, 22050, 44100};
[679]453static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
454 .count = 4,
[358]455 .list = snd_es1370_fixed_rates,
456 .mask = 0,
457};
[679]458static const struct snd_ratnum es1370_clock = {
[358]459 .num = ES_1370_SRCLOCK,
[679]460 .den_min = 29,
[358]461 .den_max = 353,
462 .den_step = 1,
463};
[679]464static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
[358]465 .nrats = 1,
466 .rats = &es1370_clock,
467};
468#else
[679]469static const struct snd_ratden es1371_dac_clock = {
[358]470 .num_min = 3000 * (1 << 15),
471 .num_max = 48000 * (1 << 15),
472 .num_step = 3000,
473 .den = 1 << 15,
474};
[679]475static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
[358]476 .nrats = 1,
477 .rats = &es1371_dac_clock,
478};
[679]479static const struct snd_ratnum es1371_adc_clock = {
[358]480 .num = 48000 << 15,
[679]481 .den_min = 32768,
[358]482 .den_max = 393216,
483 .den_step = 1,
484};
[679]485static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
[358]486 .nrats = 1,
487 .rats = &es1371_adc_clock,
488};
489#endif
490static const unsigned int snd_ensoniq_sample_shift[] =
491 {0, 1, 1, 2};
492
493/*
494 * common I/O routines
495 */
496
497#ifdef CHIP1371
498
499static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
500{
501 unsigned int t, r = 0;
502
503 for (t = 0; t < POLL_COUNT; t++) {
504 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
505 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
506 return r;
507 cond_resched();
508 }
[679]509 dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
[358]510 ES_REG(ensoniq, 1371_SMPRATE), r);
511 return 0;
512}
513
514static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
515{
516 unsigned int temp, i, orig, r;
517
518 /* wait for ready */
519 temp = orig = snd_es1371_wait_src_ready(ensoniq);
520
521 /* expose the SRC state bits */
522 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
523 ES_1371_DIS_P2 | ES_1371_DIS_R1);
524 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
525 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
526
527 /* now, wait for busy and the correct time to read */
528 temp = snd_es1371_wait_src_ready(ensoniq);
529
530 if ((temp & 0x00870000) != 0x00010000) {
531 /* wait for the right state */
532 for (i = 0; i < POLL_COUNT; i++) {
533 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
534 if ((temp & 0x00870000) == 0x00010000)
535 break;
536 }
537 }
538
539 /* hide the state bits */
540 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
541 ES_1371_DIS_P2 | ES_1371_DIS_R1);
542 r |= ES_1371_SRC_RAM_ADDRO(reg);
543 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
544
545 return temp;
546}
547
548static void snd_es1371_src_write(struct ensoniq * ensoniq,
549 unsigned short reg, unsigned short data)
550{
551 unsigned int r;
552
553 r = snd_es1371_wait_src_ready(ensoniq) &
554 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
555 ES_1371_DIS_P2 | ES_1371_DIS_R1);
556 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
557 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
558}
559
560#endif /* CHIP1371 */
561
562#ifdef CHIP1370
563
564static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
565 unsigned short reg, unsigned short val)
566{
567 struct ensoniq *ensoniq = ak4531->private_data;
568 unsigned long end_time = jiffies + HZ / 10;
569
570#if 0
[679]571 dev_dbg(ensoniq->card->dev,
[426]572 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
[358]573 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
574#endif
575 do {
576 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
577 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
578 return;
579 }
580 schedule_timeout_uninterruptible(1);
581 } while (time_after(end_time, jiffies));
[679]582 dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
[358]583 inl(ES_REG(ensoniq, STATUS)));
584}
585
586#endif /* CHIP1370 */
587
588#ifdef CHIP1371
589
[679]590static inline bool is_ev1938(struct ensoniq *ensoniq)
591{
592 return ensoniq->pci->device == 0x8938;
593}
594
[358]595static void snd_es1371_codec_write(struct snd_ac97 *ac97,
596 unsigned short reg, unsigned short val)
597{
598 struct ensoniq *ensoniq = ac97->private_data;
[679]599 unsigned int t, x, flag;
[358]600
[679]601 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
[358]602 mutex_lock(&ensoniq->src_mutex);
603 for (t = 0; t < POLL_COUNT; t++) {
604 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
605 /* save the current state for latter */
606 x = snd_es1371_wait_src_ready(ensoniq);
607 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
608 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
609 ES_REG(ensoniq, 1371_SMPRATE));
610 /* wait for not busy (state 0) first to avoid
611 transition states */
612 for (t = 0; t < POLL_COUNT; t++) {
613 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
614 0x00000000)
615 break;
616 }
617 /* wait for a SAFE time to write addr/data and then do it, dammit */
618 for (t = 0; t < POLL_COUNT; t++) {
619 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
620 0x00010000)
621 break;
622 }
[679]623 outl(ES_1371_CODEC_WRITE(reg, val) | flag,
624 ES_REG(ensoniq, 1371_CODEC));
[358]625 /* restore SRC reg */
626 snd_es1371_wait_src_ready(ensoniq);
627 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
628 mutex_unlock(&ensoniq->src_mutex);
629 return;
630 }
631 }
632 mutex_unlock(&ensoniq->src_mutex);
[679]633 dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
[358]634 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
635}
636
637static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
638 unsigned short reg)
639{
640 struct ensoniq *ensoniq = ac97->private_data;
[679]641 unsigned int t, x, flag, fail = 0;
[358]642
[679]643 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
[358]644 __again:
645 mutex_lock(&ensoniq->src_mutex);
646 for (t = 0; t < POLL_COUNT; t++) {
647 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
648 /* save the current state for latter */
649 x = snd_es1371_wait_src_ready(ensoniq);
650 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
651 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
652 ES_REG(ensoniq, 1371_SMPRATE));
653 /* wait for not busy (state 0) first to avoid
654 transition states */
655 for (t = 0; t < POLL_COUNT; t++) {
656 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
657 0x00000000)
658 break;
659 }
660 /* wait for a SAFE time to write addr/data and then do it, dammit */
661 for (t = 0; t < POLL_COUNT; t++) {
662 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
663 0x00010000)
664 break;
665 }
[679]666 outl(ES_1371_CODEC_READS(reg) | flag,
667 ES_REG(ensoniq, 1371_CODEC));
[358]668 /* restore SRC reg */
669 snd_es1371_wait_src_ready(ensoniq);
670 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
671 /* wait for WIP again */
672 for (t = 0; t < POLL_COUNT; t++) {
673 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
674 break;
675 }
676 /* now wait for the stinkin' data (RDY) */
677 for (t = 0; t < POLL_COUNT; t++) {
[703]678 x = inl(ES_REG(ensoniq, 1371_CODEC));
679 if (x & ES_1371_CODEC_RDY) {
[679]680 if (is_ev1938(ensoniq)) {
681 for (t = 0; t < 100; t++)
682 inl(ES_REG(ensoniq, CONTROL));
683 x = inl(ES_REG(ensoniq, 1371_CODEC));
684 }
[358]685 mutex_unlock(&ensoniq->src_mutex);
686 return ES_1371_CODEC_READ(x);
687 }
688 }
689 mutex_unlock(&ensoniq->src_mutex);
690 if (++fail > 10) {
[679]691 dev_err(ensoniq->card->dev,
692 "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
[358]693 ES_REG(ensoniq, 1371_CODEC), reg,
694 inl(ES_REG(ensoniq, 1371_CODEC)));
695 return 0;
696 }
697 goto __again;
698 }
699 }
700 mutex_unlock(&ensoniq->src_mutex);
[679]701 dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
[358]702 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
703 return 0;
704}
705
706static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
707{
708 msleep(750);
709 snd_es1371_codec_read(ac97, AC97_RESET);
710 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
711 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
712 msleep(50);
713}
714
715static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
716{
[679]717 unsigned int n, truncm, freq;
[358]718
719 mutex_lock(&ensoniq->src_mutex);
720 n = rate / 3000;
721 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
722 n--;
723 truncm = (21 * n - 1) | 1;
724 freq = ((48000UL << 15) / rate) * n;
725 if (rate >= 24000) {
726 if (truncm > 239)
727 truncm = 239;
728 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
729 (((239 - truncm) >> 1) << 9) | (n << 4));
730 } else {
731 if (truncm > 119)
732 truncm = 119;
733 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
734 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
735 }
736 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
737 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
738 ES_SMPREG_INT_REGS) & 0x00ff) |
739 ((freq >> 5) & 0xfc00));
740 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
741 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
742 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
743 mutex_unlock(&ensoniq->src_mutex);
744}
745
746static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
747{
748 unsigned int freq, r;
749
750 mutex_lock(&ensoniq->src_mutex);
[772]751#ifndef TARGET_OS2
[695]752 freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
[772]753#else
754 freq = ((rate << 15) + 1500) / 3000;
755#endif
[358]756 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
757 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
758 ES_1371_DIS_P1;
759 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
760 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
761 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
762 ES_SMPREG_INT_REGS) & 0x00ff) |
763 ((freq >> 5) & 0xfc00));
764 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
765 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
766 ES_1371_DIS_P2 | ES_1371_DIS_R1));
767 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
768 mutex_unlock(&ensoniq->src_mutex);
769}
770
771static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
772{
773 unsigned int freq, r;
774
775 mutex_lock(&ensoniq->src_mutex);
[772]776#ifndef TARGET_OS2
[695]777 freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
[772]778#else
779 freq = ((rate << 15) + 1500) / 3000;
780#endif
[358]781 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
782 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
783 ES_1371_DIS_P2;
784 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
785 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
786 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
787 ES_SMPREG_INT_REGS) & 0x00ff) |
788 ((freq >> 5) & 0xfc00));
789 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
790 freq & 0x7fff);
791 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
792 ES_1371_DIS_P1 | ES_1371_DIS_R1));
793 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
794 mutex_unlock(&ensoniq->src_mutex);
795}
796
797#endif /* CHIP1371 */
798
799static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
800{
801 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
802 switch (cmd) {
803 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
804 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
805 {
806 unsigned int what = 0;
807 struct snd_pcm_substream *s;
808 snd_pcm_group_for_each_entry(s, substream) {
809 if (s == ensoniq->playback1_substream) {
810 what |= ES_P1_PAUSE;
811 snd_pcm_trigger_done(s, substream);
812 } else if (s == ensoniq->playback2_substream) {
813 what |= ES_P2_PAUSE;
814 snd_pcm_trigger_done(s, substream);
815 } else if (s == ensoniq->capture_substream)
816 return -EINVAL;
817 }
818 spin_lock(&ensoniq->reg_lock);
819 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
820 ensoniq->sctrl |= what;
821 else
822 ensoniq->sctrl &= ~what;
823 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
824 spin_unlock(&ensoniq->reg_lock);
825 break;
826 }
827 case SNDRV_PCM_TRIGGER_START:
828 case SNDRV_PCM_TRIGGER_STOP:
829 {
830 unsigned int what = 0;
831 struct snd_pcm_substream *s;
832 snd_pcm_group_for_each_entry(s, substream) {
833 if (s == ensoniq->playback1_substream) {
834 what |= ES_DAC1_EN;
835 snd_pcm_trigger_done(s, substream);
836 } else if (s == ensoniq->playback2_substream) {
837 what |= ES_DAC2_EN;
838 snd_pcm_trigger_done(s, substream);
839 } else if (s == ensoniq->capture_substream) {
840 what |= ES_ADC_EN;
841 snd_pcm_trigger_done(s, substream);
842 }
843 }
844 spin_lock(&ensoniq->reg_lock);
845 if (cmd == SNDRV_PCM_TRIGGER_START)
846 ensoniq->ctrl |= what;
847 else
848 ensoniq->ctrl &= ~what;
849 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
850 spin_unlock(&ensoniq->reg_lock);
851 break;
852 }
853 default:
854 return -EINVAL;
855 }
856 return 0;
857}
858
859/*
860 * PCM part
861 */
862
863static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
864{
865 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
866 struct snd_pcm_runtime *runtime = substream->runtime;
867 unsigned int mode = 0;
868
869 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
870 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
871 if (snd_pcm_format_width(runtime->format) == 16)
872 mode |= 0x02;
873 if (runtime->channels > 1)
874 mode |= 0x01;
875 spin_lock_irq(&ensoniq->reg_lock);
876 ensoniq->ctrl &= ~ES_DAC1_EN;
877#ifdef CHIP1371
878 /* 48k doesn't need SRC (it breaks AC3-passthru) */
879 if (runtime->rate == 48000)
880 ensoniq->ctrl |= ES_1373_BYPASS_P1;
881 else
882 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
883#endif
884 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
885 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
886 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
887 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
888 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
889 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
890 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
891 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
892 ES_REG(ensoniq, DAC1_COUNT));
893#ifdef CHIP1370
894 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
895 switch (runtime->rate) {
896 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
897 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
898 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
899 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
900 default: snd_BUG();
901 }
902#endif
903 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
904 spin_unlock_irq(&ensoniq->reg_lock);
905#ifndef CHIP1370
906 snd_es1371_dac1_rate(ensoniq, runtime->rate);
907#endif
908 return 0;
909}
910
911static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
912{
913 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
914 struct snd_pcm_runtime *runtime = substream->runtime;
915 unsigned int mode = 0;
916
917 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
918 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
919 if (snd_pcm_format_width(runtime->format) == 16)
920 mode |= 0x02;
921 if (runtime->channels > 1)
922 mode |= 0x01;
923 spin_lock_irq(&ensoniq->reg_lock);
924 ensoniq->ctrl &= ~ES_DAC2_EN;
925 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
926 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
927 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
928 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
929 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
930 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
931 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
932 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
933 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
934 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
935 ES_REG(ensoniq, DAC2_COUNT));
936#ifdef CHIP1370
937 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
938 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
939 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
940 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
941 }
942#endif
943 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
944 spin_unlock_irq(&ensoniq->reg_lock);
945#ifndef CHIP1370
946 snd_es1371_dac2_rate(ensoniq, runtime->rate);
947#endif
948 return 0;
949}
950
951static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
952{
953 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
954 struct snd_pcm_runtime *runtime = substream->runtime;
955 unsigned int mode = 0;
956
957 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
958 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
959 if (snd_pcm_format_width(runtime->format) == 16)
960 mode |= 0x02;
961 if (runtime->channels > 1)
962 mode |= 0x01;
963 spin_lock_irq(&ensoniq->reg_lock);
964 ensoniq->ctrl &= ~ES_ADC_EN;
965 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
966 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
967 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
968 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
969 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
970 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
971 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
972 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
973 ES_REG(ensoniq, ADC_COUNT));
974#ifdef CHIP1370
975 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
976 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
977 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
978 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
979 }
980#endif
981 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
982 spin_unlock_irq(&ensoniq->reg_lock);
983#ifndef CHIP1370
984 snd_es1371_adc_rate(ensoniq, runtime->rate);
985#endif
986 return 0;
987}
988
989static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
990{
991 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
992 size_t ptr;
993
994 spin_lock(&ensoniq->reg_lock);
995 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
996 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
997 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
998 ptr = bytes_to_frames(substream->runtime, ptr);
999 } else {
1000 ptr = 0;
1001 }
1002 spin_unlock(&ensoniq->reg_lock);
1003 return ptr;
1004}
1005
1006static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1007{
1008 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1009 size_t ptr;
1010
1011 spin_lock(&ensoniq->reg_lock);
1012 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1013 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1014 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1015 ptr = bytes_to_frames(substream->runtime, ptr);
1016 } else {
1017 ptr = 0;
1018 }
1019 spin_unlock(&ensoniq->reg_lock);
1020 return ptr;
1021}
1022
1023static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1024{
1025 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1026 size_t ptr;
1027
1028 spin_lock(&ensoniq->reg_lock);
1029 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1030 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1031 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1032 ptr = bytes_to_frames(substream->runtime, ptr);
1033 } else {
1034 ptr = 0;
1035 }
1036 spin_unlock(&ensoniq->reg_lock);
1037 return ptr;
1038}
1039
[679]1040static const struct snd_pcm_hardware snd_ensoniq_playback1 =
[358]1041{
1042 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1043 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1044 SNDRV_PCM_INFO_MMAP_VALID |
1045 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1046 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1047 .rates =
1048#ifndef CHIP1370
1049 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1050#else
1051 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
[679]1052 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
[358]1053 SNDRV_PCM_RATE_44100),
1054#endif
1055 .rate_min = 4000,
1056 .rate_max = 48000,
1057 .channels_min = 1,
1058 .channels_max = 2,
1059 .buffer_bytes_max = (128*1024),
1060 .period_bytes_min = 64,
1061 .period_bytes_max = (128*1024),
1062 .periods_min = 1,
1063 .periods_max = 1024,
1064 .fifo_size = 0,
1065};
1066
[679]1067static const struct snd_pcm_hardware snd_ensoniq_playback2 =
[358]1068{
1069 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1070 SNDRV_PCM_INFO_BLOCK_TRANSFER |
[679]1071 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
[358]1072 SNDRV_PCM_INFO_SYNC_START),
1073 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1074 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1075 .rate_min = 4000,
1076 .rate_max = 48000,
1077 .channels_min = 1,
1078 .channels_max = 2,
1079 .buffer_bytes_max = (128*1024),
1080 .period_bytes_min = 64,
1081 .period_bytes_max = (128*1024),
1082 .periods_min = 1,
1083 .periods_max = 1024,
1084 .fifo_size = 0,
1085};
1086
[679]1087static const struct snd_pcm_hardware snd_ensoniq_capture =
[358]1088{
1089 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1090 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1091 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1092 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1093 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1094 .rate_min = 4000,
1095 .rate_max = 48000,
1096 .channels_min = 1,
1097 .channels_max = 2,
1098 .buffer_bytes_max = (128*1024),
1099 .period_bytes_min = 64,
1100 .period_bytes_max = (128*1024),
1101 .periods_min = 1,
1102 .periods_max = 1024,
1103 .fifo_size = 0,
1104};
1105
1106static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1107{
1108 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1109 struct snd_pcm_runtime *runtime = substream->runtime;
1110
1111 ensoniq->mode |= ES_MODE_PLAY1;
1112 ensoniq->playback1_substream = substream;
1113 runtime->hw = snd_ensoniq_playback1;
1114 snd_pcm_set_sync(substream);
1115 spin_lock_irq(&ensoniq->reg_lock);
1116 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1117 ensoniq->spdif_stream = ensoniq->spdif_default;
1118 spin_unlock_irq(&ensoniq->reg_lock);
1119#ifdef CHIP1370
1120 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1121 &snd_es1370_hw_constraints_rates);
1122#else
1123 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1124 &snd_es1371_hw_constraints_dac_clock);
1125#endif
1126 return 0;
1127}
1128
1129static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1130{
1131 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1132 struct snd_pcm_runtime *runtime = substream->runtime;
1133
1134 ensoniq->mode |= ES_MODE_PLAY2;
1135 ensoniq->playback2_substream = substream;
1136 runtime->hw = snd_ensoniq_playback2;
1137 snd_pcm_set_sync(substream);
1138 spin_lock_irq(&ensoniq->reg_lock);
1139 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1140 ensoniq->spdif_stream = ensoniq->spdif_default;
1141 spin_unlock_irq(&ensoniq->reg_lock);
1142#ifdef CHIP1370
1143 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1144 &snd_es1370_hw_constraints_clock);
1145#else
1146 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1147 &snd_es1371_hw_constraints_dac_clock);
1148#endif
1149 return 0;
1150}
1151
1152static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1153{
1154 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1155 struct snd_pcm_runtime *runtime = substream->runtime;
1156
1157 ensoniq->mode |= ES_MODE_CAPTURE;
1158 ensoniq->capture_substream = substream;
1159 runtime->hw = snd_ensoniq_capture;
1160 snd_pcm_set_sync(substream);
1161#ifdef CHIP1370
1162 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1163 &snd_es1370_hw_constraints_clock);
1164#else
1165 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1166 &snd_es1371_hw_constraints_adc_clock);
1167#endif
1168 return 0;
1169}
1170
1171static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1172{
1173 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1174
1175 ensoniq->playback1_substream = NULL;
1176 ensoniq->mode &= ~ES_MODE_PLAY1;
1177 return 0;
1178}
1179
1180static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1181{
1182 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1183
1184 ensoniq->playback2_substream = NULL;
1185 spin_lock_irq(&ensoniq->reg_lock);
1186#ifdef CHIP1370
1187 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1188#endif
1189 ensoniq->mode &= ~ES_MODE_PLAY2;
1190 spin_unlock_irq(&ensoniq->reg_lock);
1191 return 0;
1192}
1193
1194static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1195{
1196 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1197
1198 ensoniq->capture_substream = NULL;
1199 spin_lock_irq(&ensoniq->reg_lock);
1200#ifdef CHIP1370
1201 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1202#endif
1203 ensoniq->mode &= ~ES_MODE_CAPTURE;
1204 spin_unlock_irq(&ensoniq->reg_lock);
1205 return 0;
1206}
1207
[679]1208static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
[358]1209 .open = snd_ensoniq_playback1_open,
1210 .close = snd_ensoniq_playback1_close,
1211 .prepare = snd_ensoniq_playback1_prepare,
1212 .trigger = snd_ensoniq_trigger,
1213 .pointer = snd_ensoniq_playback1_pointer,
1214};
1215
[679]1216static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
[358]1217 .open = snd_ensoniq_playback2_open,
1218 .close = snd_ensoniq_playback2_close,
1219 .prepare = snd_ensoniq_playback2_prepare,
1220 .trigger = snd_ensoniq_trigger,
1221 .pointer = snd_ensoniq_playback2_pointer,
1222};
1223
[679]1224static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
[358]1225 .open = snd_ensoniq_capture_open,
1226 .close = snd_ensoniq_capture_close,
1227 .prepare = snd_ensoniq_capture_prepare,
1228 .trigger = snd_ensoniq_trigger,
1229 .pointer = snd_ensoniq_capture_pointer,
1230};
1231
[679]1232static const struct snd_pcm_chmap_elem surround_map[] = {
1233 { .channels = 1,
1234 .map = { SNDRV_CHMAP_MONO } },
1235 { .channels = 2,
1236 .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1237 {0}
1238};
1239
1240static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
[358]1241{
1242 struct snd_pcm *pcm;
1243 int err;
1244
[679]1245 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
[358]1246 if (err < 0)
1247 return err;
1248
1249#ifdef CHIP1370
1250 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1251#else
1252 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1253#endif
1254 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1255
1256 pcm->private_data = ensoniq;
1257 pcm->info_flags = 0;
[679]1258 strcpy(pcm->name, CHIP_NAME " DAC2/ADC");
1259 ensoniq->pcm1 = pcm;
1260
1261 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1262 &ensoniq->pci->dev, 64*1024, 128*1024);
1263
[358]1264#ifdef CHIP1370
[679]1265 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1266 surround_map, 2, 0, NULL);
[358]1267#else
[679]1268 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1269 snd_pcm_std_chmaps, 2, 0, NULL);
[358]1270#endif
[679]1271 return err;
[358]1272}
1273
[679]1274static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
[358]1275{
1276 struct snd_pcm *pcm;
1277 int err;
1278
[679]1279 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
[358]1280 if (err < 0)
1281 return err;
1282
1283#ifdef CHIP1370
1284 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1285#else
1286 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1287#endif
1288 pcm->private_data = ensoniq;
1289 pcm->info_flags = 0;
[679]1290 strcpy(pcm->name, CHIP_NAME " DAC1");
1291 ensoniq->pcm2 = pcm;
1292
1293 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1294 &ensoniq->pci->dev, 64*1024, 128*1024);
1295
[358]1296#ifdef CHIP1370
[679]1297 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1298 snd_pcm_std_chmaps, 2, 0, NULL);
[358]1299#else
[679]1300 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1301 surround_map, 2, 0, NULL);
[358]1302#endif
[679]1303 return err;
[358]1304}
1305
1306/*
1307 * Mixer section
1308 */
1309
1310/*
1311 * ENS1371 mixer (including SPDIF interface)
1312 */
1313#ifdef CHIP1371
1314static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1315 struct snd_ctl_elem_info *uinfo)
1316{
1317 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1318 uinfo->count = 1;
1319 return 0;
1320}
1321
1322static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1323 struct snd_ctl_elem_value *ucontrol)
1324{
1325 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1326 spin_lock_irq(&ensoniq->reg_lock);
1327 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1328 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1329 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1330 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1331 spin_unlock_irq(&ensoniq->reg_lock);
1332 return 0;
1333}
1334
1335static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1336 struct snd_ctl_elem_value *ucontrol)
1337{
1338 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1339 unsigned int val;
1340 int change;
1341
1342 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1343 ((u32)ucontrol->value.iec958.status[1] << 8) |
1344 ((u32)ucontrol->value.iec958.status[2] << 16) |
1345 ((u32)ucontrol->value.iec958.status[3] << 24);
1346 spin_lock_irq(&ensoniq->reg_lock);
1347 change = ensoniq->spdif_default != val;
1348 ensoniq->spdif_default = val;
1349 if (change && ensoniq->playback1_substream == NULL &&
1350 ensoniq->playback2_substream == NULL)
1351 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1352 spin_unlock_irq(&ensoniq->reg_lock);
1353 return change;
1354}
1355
1356static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1357 struct snd_ctl_elem_value *ucontrol)
1358{
1359 ucontrol->value.iec958.status[0] = 0xff;
1360 ucontrol->value.iec958.status[1] = 0xff;
1361 ucontrol->value.iec958.status[2] = 0xff;
1362 ucontrol->value.iec958.status[3] = 0xff;
1363 return 0;
1364}
1365
1366static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1367 struct snd_ctl_elem_value *ucontrol)
1368{
1369 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1370 spin_lock_irq(&ensoniq->reg_lock);
1371 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1372 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1373 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1374 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1375 spin_unlock_irq(&ensoniq->reg_lock);
1376 return 0;
1377}
1378
1379static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1380 struct snd_ctl_elem_value *ucontrol)
1381{
1382 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1383 unsigned int val;
1384 int change;
1385
1386 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1387 ((u32)ucontrol->value.iec958.status[1] << 8) |
1388 ((u32)ucontrol->value.iec958.status[2] << 16) |
1389 ((u32)ucontrol->value.iec958.status[3] << 24);
1390 spin_lock_irq(&ensoniq->reg_lock);
1391 change = ensoniq->spdif_stream != val;
1392 ensoniq->spdif_stream = val;
1393 if (change && (ensoniq->playback1_substream != NULL ||
1394 ensoniq->playback2_substream != NULL))
1395 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1396 spin_unlock_irq(&ensoniq->reg_lock);
1397 return change;
1398}
1399
1400#define ES1371_SPDIF(xname) \
1401{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1402 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1403
1404#define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1405
1406static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1407 struct snd_ctl_elem_value *ucontrol)
1408{
1409 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1410
1411 spin_lock_irq(&ensoniq->reg_lock);
1412 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1413 spin_unlock_irq(&ensoniq->reg_lock);
1414 return 0;
1415}
1416
1417static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1418 struct snd_ctl_elem_value *ucontrol)
1419{
1420 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1421 unsigned int nval1, nval2;
1422 int change;
1423
1424 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1425 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1426 spin_lock_irq(&ensoniq->reg_lock);
1427 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1428 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1429 ensoniq->ctrl |= nval1;
1430 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1431 ensoniq->cssr |= nval2;
1432 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1433 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1434 spin_unlock_irq(&ensoniq->reg_lock);
1435 return change;
1436}
1437
1438
1439/* spdif controls */
[679]1440static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
[358]1441 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1442 {
1443 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1444 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1445 .info = snd_ens1373_spdif_info,
1446 .get = snd_ens1373_spdif_default_get,
1447 .put = snd_ens1373_spdif_default_put,
1448 },
1449 {
1450 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1451 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1452 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1453 .info = snd_ens1373_spdif_info,
1454 .get = snd_ens1373_spdif_mask_get
1455 },
1456 {
1457 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1458 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1459 .info = snd_ens1373_spdif_info,
1460 .get = snd_ens1373_spdif_stream_get,
1461 .put = snd_ens1373_spdif_stream_put
1462 },
1463};
1464
1465
1466#define snd_es1373_rear_info snd_ctl_boolean_mono_info
1467
1468static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1469 struct snd_ctl_elem_value *ucontrol)
1470{
1471 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1472 int val = 0;
1473
1474 spin_lock_irq(&ensoniq->reg_lock);
1475 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1476 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1477 val = 1;
1478 ucontrol->value.integer.value[0] = val;
1479 spin_unlock_irq(&ensoniq->reg_lock);
1480 return 0;
1481}
1482
1483static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1484 struct snd_ctl_elem_value *ucontrol)
1485{
1486 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1487 unsigned int nval1;
1488 int change;
1489
1490 nval1 = ucontrol->value.integer.value[0] ?
1491 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1492 spin_lock_irq(&ensoniq->reg_lock);
1493 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1494 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1495 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1496 ensoniq->cssr |= nval1;
1497 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1498 spin_unlock_irq(&ensoniq->reg_lock);
1499 return change;
1500}
1501
[679]1502static const struct snd_kcontrol_new snd_ens1373_rear =
[358]1503{
1504 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1505 .name = "AC97 2ch->4ch Copy Switch",
1506 .info = snd_es1373_rear_info,
1507 .get = snd_es1373_rear_get,
1508 .put = snd_es1373_rear_put,
1509};
1510
1511#define snd_es1373_line_info snd_ctl_boolean_mono_info
1512
1513static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1514 struct snd_ctl_elem_value *ucontrol)
1515{
1516 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1517 int val = 0;
1518
1519 spin_lock_irq(&ensoniq->reg_lock);
[679]1520 if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
[358]1521 val = 1;
1522 ucontrol->value.integer.value[0] = val;
1523 spin_unlock_irq(&ensoniq->reg_lock);
1524 return 0;
1525}
1526
1527static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1528 struct snd_ctl_elem_value *ucontrol)
1529{
1530 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1531 int changed;
1532 unsigned int ctrl;
1533
1534 spin_lock_irq(&ensoniq->reg_lock);
1535 ctrl = ensoniq->ctrl;
1536 if (ucontrol->value.integer.value[0])
1537 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1538 else
1539 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1540 changed = (ctrl != ensoniq->ctrl);
1541 if (changed)
1542 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1543 spin_unlock_irq(&ensoniq->reg_lock);
1544 return changed;
1545}
1546
[679]1547static const struct snd_kcontrol_new snd_ens1373_line =
[358]1548{
1549 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1550 .name = "Line In->Rear Out Switch",
1551 .info = snd_es1373_line_info,
1552 .get = snd_es1373_line_get,
1553 .put = snd_es1373_line_put,
1554};
1555
1556static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1557{
1558 struct ensoniq *ensoniq = ac97->private_data;
1559 ensoniq->u.es1371.ac97 = NULL;
1560}
1561
1562struct es1371_quirk {
1563 unsigned short vid; /* vendor ID */
1564 unsigned short did; /* device ID */
1565 unsigned char rev; /* revision */
1566};
1567
1568static int es1371_quirk_lookup(struct ensoniq *ensoniq,
[679]1569 const struct es1371_quirk *list)
[358]1570{
1571 while (list->vid != (unsigned short)PCI_ANY_ID) {
1572 if (ensoniq->pci->vendor == list->vid &&
1573 ensoniq->pci->device == list->did &&
1574 ensoniq->rev == list->rev)
1575 return 1;
1576 list++;
1577 }
1578 return 0;
1579}
1580
[679]1581static const struct es1371_quirk es1371_spdif_present[] = {
[358]1582 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1583 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1584 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1585 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1586 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1587 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1588};
1589
[679]1590static const struct snd_pci_quirk ens1373_line_quirk[] = {
[358]1591 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1592 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1593 {0} /* end */
1594};
1595
[679]1596static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1597 int has_spdif, int has_line)
[358]1598{
1599 struct snd_card *card = ensoniq->card;
1600 struct snd_ac97_bus *pbus;
1601 struct snd_ac97_template ac97;
1602 int err;
[679]1603 static const struct snd_ac97_bus_ops ops = {
[358]1604 .write = snd_es1371_codec_write,
1605 .read = snd_es1371_codec_read,
1606 .wait = snd_es1371_codec_wait,
1607 };
1608
[703]1609 err = snd_ac97_bus(card, 0, &ops, NULL, &pbus);
1610 if (err < 0)
[358]1611 return err;
1612
1613 memset(&ac97, 0, sizeof(ac97));
1614 ac97.private_data = ensoniq;
1615 ac97.private_free = snd_ensoniq_mixer_free_ac97;
[399]1616 ac97.pci = ensoniq->pci;
[358]1617 ac97.scaps = AC97_SCAP_AUDIO;
[703]1618 err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97);
1619 if (err < 0)
[358]1620 return err;
1621 if (has_spdif > 0 ||
1622 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1623 struct snd_kcontrol *kctl;
1624 int i, is_spdif = 0;
1625
1626 ensoniq->spdif_default = ensoniq->spdif_stream =
1627 SNDRV_PCM_DEFAULT_CON_SPDIF;
1628 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1629
1630 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1631 is_spdif++;
1632
1633 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1634 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1635 if (!kctl)
1636 return -ENOMEM;
1637 kctl->id.index = is_spdif;
1638 err = snd_ctl_add(card, kctl);
1639 if (err < 0)
1640 return err;
1641 }
1642 }
1643 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1644 /* mirror rear to front speakers */
1645 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1646 ensoniq->cssr |= ES_1373_REAR_BIT26;
1647 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1648 if (err < 0)
1649 return err;
1650 }
1651 if (has_line > 0 ||
1652 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1653 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1654 ensoniq));
1655 if (err < 0)
1656 return err;
1657 }
1658
1659 return 0;
1660}
1661
1662#endif /* CHIP1371 */
1663
1664/* generic control callbacks for ens1370 */
1665#ifdef CHIP1370
1666#define ENSONIQ_CONTROL(xname, mask) \
1667{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1668 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1669 .private_value = mask }
1670
1671#define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1672
1673static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1674 struct snd_ctl_elem_value *ucontrol)
1675{
1676 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1677 int mask = kcontrol->private_value;
1678
1679 spin_lock_irq(&ensoniq->reg_lock);
1680 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1681 spin_unlock_irq(&ensoniq->reg_lock);
1682 return 0;
1683}
1684
1685static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1686 struct snd_ctl_elem_value *ucontrol)
1687{
1688 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1689 int mask = kcontrol->private_value;
1690 unsigned int nval;
1691 int change;
1692
1693 nval = ucontrol->value.integer.value[0] ? mask : 0;
1694 spin_lock_irq(&ensoniq->reg_lock);
1695 change = (ensoniq->ctrl & mask) != nval;
1696 ensoniq->ctrl &= ~mask;
1697 ensoniq->ctrl |= nval;
1698 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1699 spin_unlock_irq(&ensoniq->reg_lock);
1700 return change;
1701}
1702
1703/*
1704 * ENS1370 mixer
1705 */
1706
[679]1707static const struct snd_kcontrol_new snd_es1370_controls[2] = {
[358]1708ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1709ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1710};
1711
1712#define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1713
1714static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1715{
1716 struct ensoniq *ensoniq = ak4531->private_data;
1717 ensoniq->u.es1370.ak4531 = NULL;
1718}
1719
[679]1720static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
[358]1721{
1722 struct snd_card *card = ensoniq->card;
1723 struct snd_ak4531 ak4531;
1724 unsigned int idx;
1725 int err;
1726
1727 /* try reset AK4531 */
1728 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1729 inw(ES_REG(ensoniq, 1370_CODEC));
1730 udelay(100);
1731 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1732 inw(ES_REG(ensoniq, 1370_CODEC));
1733 udelay(100);
1734
1735 memset(&ak4531, 0, sizeof(ak4531));
1736 ak4531.write = snd_es1370_codec_write;
1737 ak4531.private_data = ensoniq;
1738 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
[703]1739 err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531);
1740 if (err < 0)
[358]1741 return err;
1742 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1743 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1744 if (err < 0)
1745 return err;
1746 }
1747 return 0;
1748}
1749
1750#endif /* CHIP1370 */
1751
1752#ifdef SUPPORT_JOYSTICK
1753
1754#ifdef CHIP1371
[679]1755static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
[358]1756{
1757 switch (joystick_port[dev]) {
1758 case 0: /* disabled */
1759 case 1: /* auto-detect */
1760 case 0x200:
1761 case 0x208:
1762 case 0x210:
1763 case 0x218:
1764 return joystick_port[dev];
1765
1766 default:
[679]1767 dev_err(ensoniq->card->dev,
1768 "invalid joystick port %#x", joystick_port[dev]);
[358]1769 return 0;
1770 }
1771}
1772#else
[679]1773static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
[358]1774{
1775 return joystick[dev] ? 0x200 : 0;
1776}
1777#endif
1778
[679]1779static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
[358]1780{
1781 struct gameport *gp;
1782 int io_port;
1783
[679]1784 io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
[358]1785
1786 switch (io_port) {
1787 case 0:
1788 return -ENOSYS;
1789
1790 case 1: /* auto_detect */
1791 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1792 if (request_region(io_port, 8, "ens137x: gameport"))
1793 break;
1794 if (io_port > 0x218) {
[679]1795 dev_warn(ensoniq->card->dev,
1796 "no gameport ports available\n");
[358]1797 return -EBUSY;
1798 }
1799 break;
1800
1801 default:
1802 if (!request_region(io_port, 8, "ens137x: gameport")) {
[679]1803 dev_warn(ensoniq->card->dev,
1804 "gameport io port %#x in use\n",
[358]1805 io_port);
1806 return -EBUSY;
1807 }
1808 break;
1809 }
1810
1811 ensoniq->gameport = gp = gameport_allocate_port();
1812 if (!gp) {
[679]1813 dev_err(ensoniq->card->dev,
1814 "cannot allocate memory for gameport\n");
[358]1815 release_region(io_port, 8);
1816 return -ENOMEM;
1817 }
1818
1819 gameport_set_name(gp, "ES137x");
1820 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1821 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1822 gp->io = io_port;
1823
1824 ensoniq->ctrl |= ES_JYSTK_EN;
1825#ifdef CHIP1371
1826 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1827 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1828#endif
1829 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1830
1831 gameport_register_port(ensoniq->gameport);
1832
1833 return 0;
1834}
1835
1836static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1837{
1838 if (ensoniq->gameport) {
1839 int port = ensoniq->gameport->io;
1840
1841 gameport_unregister_port(ensoniq->gameport);
1842 ensoniq->gameport = NULL;
1843 ensoniq->ctrl &= ~ES_JYSTK_EN;
1844 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1845 release_region(port, 8);
1846 }
1847}
1848#else
1849static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1850static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1851#endif /* SUPPORT_JOYSTICK */
1852
1853/*
1854
1855 */
1856
[679]1857static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
[358]1858 struct snd_info_buffer *buffer)
1859{
1860 struct ensoniq *ensoniq = entry->private_data;
1861
[679]1862 snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
[358]1863 snd_iprintf(buffer, "Joystick enable : %s\n",
1864 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1865#ifdef CHIP1370
1866 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1867 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1868 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1869 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1870#else
1871 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1872 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1873#endif
1874}
1875
[679]1876static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
[358]1877{
[679]1878 snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq,
1879 snd_ensoniq_proc_read);
[358]1880}
1881
1882/*
1883
1884 */
1885
[717]1886static void snd_ensoniq_free(struct snd_card *card)
[358]1887{
[717]1888 struct ensoniq *ensoniq = card->private_data;
1889
[358]1890 snd_ensoniq_free_gameport(ensoniq);
1891#ifdef CHIP1370
1892 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1893 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1894#else
1895 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1896 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1897#endif
1898}
1899
1900#ifdef CHIP1371
[679]1901static const struct snd_pci_quirk es1371_amplifier_hack[] = {
[358]1902 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1903 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1904 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1905 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1906 {0} /* end */
1907};
1908
[679]1909static const struct es1371_quirk es1371_ac97_reset_hack[] = {
[358]1910 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1911 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1912 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1913 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1914 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1915 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1916};
1917#endif
1918
1919static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1920{
1921#ifdef CHIP1371
1922 int idx;
1923#endif
1924 /* this code was part of snd_ensoniq_create before intruduction
1925 * of suspend/resume
1926 */
1927#ifdef CHIP1370
1928 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1929 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1930 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
[717]1931 outl(ensoniq->dma_bug->addr, ES_REG(ensoniq, PHANTOM_FRAME));
[358]1932 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1933#else
1934 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1935 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1936 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1937 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1938 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1939 /* need to delay around 20ms(bleech) to give
1940 some CODECs enough time to wakeup */
1941 msleep(20);
1942 }
1943 /* AC'97 warm reset to start the bitclk */
1944 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1945 inl(ES_REG(ensoniq, CONTROL));
1946 udelay(20);
1947 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1948 /* Init the sample rate converter */
1949 snd_es1371_wait_src_ready(ensoniq);
1950 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1951 for (idx = 0; idx < 0x80; idx++)
1952 snd_es1371_src_write(ensoniq, idx, 0);
1953 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1954 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1955 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1956 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1957 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1958 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1959 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1960 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1961 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1962 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1963 snd_es1371_adc_rate(ensoniq, 22050);
1964 snd_es1371_dac1_rate(ensoniq, 22050);
1965 snd_es1371_dac2_rate(ensoniq, 22050);
1966 /* WARNING:
1967 * enabling the sample rate converter without properly programming
1968 * its parameters causes the chip to lock up (the SRC busy bit will
1969 * be stuck high, and I've found no way to rectify this other than
1970 * power cycle) - Thomas Sailer
1971 */
1972 snd_es1371_wait_src_ready(ensoniq);
1973 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
1974 /* try reset codec directly */
1975 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
1976#endif
1977 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
1978 outb(0x00, ES_REG(ensoniq, UART_RES));
1979 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1980}
1981
[679]1982static int snd_ensoniq_suspend(struct device *dev)
[358]1983{
[679]1984 struct snd_card *card = dev_get_drvdata(dev);
[358]1985 struct ensoniq *ensoniq = card->private_data;
1986
1987 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1988
1989#ifdef CHIP1371
1990 snd_ac97_suspend(ensoniq->u.es1371.ac97);
1991#else
1992 /* try to reset AK4531 */
1993 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1994 inw(ES_REG(ensoniq, 1370_CODEC));
1995 udelay(100);
1996 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1997 inw(ES_REG(ensoniq, 1370_CODEC));
1998 udelay(100);
1999 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2000#endif
2001 return 0;
2002}
2003
[679]2004static int snd_ensoniq_resume(struct device *dev)
[358]2005{
[679]2006 struct snd_card *card = dev_get_drvdata(dev);
[358]2007 struct ensoniq *ensoniq = card->private_data;
2008
2009 snd_ensoniq_chip_init(ensoniq);
2010
2011#ifdef CHIP1371
2012 snd_ac97_resume(ensoniq->u.es1371.ac97);
2013#else
2014 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2015#endif
2016 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2017 return 0;
2018}
2019
[777]2020static DEFINE_SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
[358]2021
[679]2022static int snd_ensoniq_create(struct snd_card *card,
[717]2023 struct pci_dev *pci)
[358]2024{
[717]2025 struct ensoniq *ensoniq = card->private_data;
[358]2026 int err;
2027
[717]2028 err = pcim_enable_device(pci);
[703]2029 if (err < 0)
[358]2030 return err;
2031 spin_lock_init(&ensoniq->reg_lock);
2032 mutex_init(&ensoniq->src_mutex);
2033 ensoniq->card = card;
2034 ensoniq->pci = pci;
2035 ensoniq->irq = -1;
[703]2036 err = pci_request_regions(pci, "Ensoniq AudioPCI");
[717]2037 if (err < 0)
[358]2038 return err;
[717]2039 ensoniq->port = pci_resource_start(pci, 0);
2040 if (devm_request_irq(&pci->dev, pci->irq, snd_audiopci_interrupt,
2041 IRQF_SHARED, KBUILD_MODNAME, ensoniq)) {
2042 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2043 return -EBUSY;
[358]2044 }
2045 ensoniq->irq = pci->irq;
[679]2046 card->sync_irq = ensoniq->irq;
[358]2047#ifdef CHIP1370
[717]2048 ensoniq->dma_bug =
2049 snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, 16);
2050 if (!ensoniq->dma_bug)
2051 return -ENOMEM;
[358]2052#endif
2053 pci_set_master(pci);
2054#ifndef TARGET_OS2
2055 ensoniq->rev = pci->revision;
2056#else
2057 ensoniq->rev = snd_pci_revision(pci);
2058#endif
2059#ifdef CHIP1370
2060#if 0
2061 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2062 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2063#else /* get microphone working */
2064 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2065#endif
2066 ensoniq->sctrl = 0;
2067#else
2068 ensoniq->ctrl = 0;
2069 ensoniq->sctrl = 0;
2070 ensoniq->cssr = 0;
2071 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2072 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2073
2074 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2075 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2076#endif
2077
[717]2078 card->private_free = snd_ensoniq_free;
[358]2079 snd_ensoniq_chip_init(ensoniq);
2080
2081 snd_ensoniq_proc_init(ensoniq);
2082 return 0;
2083}
2084
2085/*
2086 * MIDI section
2087 */
2088
2089static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2090{
2091 struct snd_rawmidi *rmidi = ensoniq->rmidi;
2092 unsigned char status, mask, byte;
2093
2094 if (rmidi == NULL)
2095 return;
2096 /* do Rx at first */
2097 spin_lock(&ensoniq->reg_lock);
2098 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2099 while (mask) {
2100 status = inb(ES_REG(ensoniq, UART_STATUS));
2101 if ((status & mask) == 0)
2102 break;
2103 byte = inb(ES_REG(ensoniq, UART_DATA));
2104 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2105 }
2106 spin_unlock(&ensoniq->reg_lock);
2107
2108 /* do Tx at second */
2109 spin_lock(&ensoniq->reg_lock);
2110 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2111 while (mask) {
2112 status = inb(ES_REG(ensoniq, UART_STATUS));
2113 if ((status & mask) == 0)
2114 break;
2115 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2116 ensoniq->uartc &= ~ES_TXINTENM;
2117 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2118 mask &= ~ES_TXRDY;
2119 } else {
2120 outb(byte, ES_REG(ensoniq, UART_DATA));
2121 }
2122 }
2123 spin_unlock(&ensoniq->reg_lock);
2124}
2125
2126static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2127{
2128 struct ensoniq *ensoniq = substream->rmidi->private_data;
2129
2130 spin_lock_irq(&ensoniq->reg_lock);
2131 ensoniq->uartm |= ES_MODE_INPUT;
2132 ensoniq->midi_input = substream;
2133 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2134 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2135 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2136 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2137 }
2138 spin_unlock_irq(&ensoniq->reg_lock);
2139 return 0;
2140}
2141
2142static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2143{
2144 struct ensoniq *ensoniq = substream->rmidi->private_data;
2145
2146 spin_lock_irq(&ensoniq->reg_lock);
2147 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2148 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2149 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2150 } else {
2151 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2152 }
2153 ensoniq->midi_input = NULL;
2154 ensoniq->uartm &= ~ES_MODE_INPUT;
2155 spin_unlock_irq(&ensoniq->reg_lock);
2156 return 0;
2157}
2158
2159static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2160{
2161 struct ensoniq *ensoniq = substream->rmidi->private_data;
2162
2163 spin_lock_irq(&ensoniq->reg_lock);
2164 ensoniq->uartm |= ES_MODE_OUTPUT;
2165 ensoniq->midi_output = substream;
2166 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2167 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2168 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2169 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2170 }
2171 spin_unlock_irq(&ensoniq->reg_lock);
2172 return 0;
2173}
2174
2175static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2176{
2177 struct ensoniq *ensoniq = substream->rmidi->private_data;
2178
2179 spin_lock_irq(&ensoniq->reg_lock);
2180 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2181 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2182 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2183 } else {
2184 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2185 }
2186 ensoniq->midi_output = NULL;
2187 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2188 spin_unlock_irq(&ensoniq->reg_lock);
2189 return 0;
2190}
2191
2192static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2193{
2194 unsigned long flags;
2195 struct ensoniq *ensoniq = substream->rmidi->private_data;
2196 int idx;
2197
2198 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2199 if (up) {
2200 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2201 /* empty input FIFO */
2202 for (idx = 0; idx < 32; idx++)
2203 inb(ES_REG(ensoniq, UART_DATA));
2204 ensoniq->uartc |= ES_RXINTEN;
2205 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2206 }
2207 } else {
2208 if (ensoniq->uartc & ES_RXINTEN) {
2209 ensoniq->uartc &= ~ES_RXINTEN;
2210 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2211 }
2212 }
2213 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2214}
2215
2216static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2217{
2218 unsigned long flags;
2219 struct ensoniq *ensoniq = substream->rmidi->private_data;
2220 unsigned char byte;
2221
2222 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2223 if (up) {
2224 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2225 ensoniq->uartc |= ES_TXINTENO(1);
2226 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2227 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2228 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2229 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2230 ensoniq->uartc &= ~ES_TXINTENM;
2231 } else {
2232 outb(byte, ES_REG(ensoniq, UART_DATA));
2233 }
2234 }
2235 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2236 }
2237 } else {
2238 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2239 ensoniq->uartc &= ~ES_TXINTENM;
2240 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2241 }
2242 }
2243 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2244}
2245
[679]2246static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
[358]2247{
2248 .open = snd_ensoniq_midi_output_open,
2249 .close = snd_ensoniq_midi_output_close,
2250 .trigger = snd_ensoniq_midi_output_trigger,
2251};
2252
[679]2253static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
[358]2254{
2255 .open = snd_ensoniq_midi_input_open,
2256 .close = snd_ensoniq_midi_input_close,
2257 .trigger = snd_ensoniq_midi_input_trigger,
2258};
2259
[679]2260static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
[358]2261{
2262 struct snd_rawmidi *rmidi;
2263 int err;
2264
[703]2265 err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi);
2266 if (err < 0)
[358]2267 return err;
[679]2268 strcpy(rmidi->name, CHIP_NAME);
[358]2269 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2270 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2271 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2272 SNDRV_RAWMIDI_INFO_DUPLEX;
2273 rmidi->private_data = ensoniq;
2274 ensoniq->rmidi = rmidi;
2275 return 0;
2276}
2277
2278/*
2279 * Interrupt handler
2280 */
2281
2282static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2283{
2284 struct ensoniq *ensoniq = dev_id;
2285 unsigned int status, sctrl;
2286
2287 if (ensoniq == NULL)
2288 return IRQ_NONE;
2289
2290 status = inl(ES_REG(ensoniq, STATUS));
2291 if (!(status & ES_INTR))
2292 return IRQ_NONE;
2293
2294 spin_lock(&ensoniq->reg_lock);
2295 sctrl = ensoniq->sctrl;
2296 if (status & ES_DAC1)
2297 sctrl &= ~ES_P1_INT_EN;
2298 if (status & ES_DAC2)
2299 sctrl &= ~ES_P2_INT_EN;
2300 if (status & ES_ADC)
2301 sctrl &= ~ES_R1_INT_EN;
2302 outl(sctrl, ES_REG(ensoniq, SERIAL));
2303 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2304 spin_unlock(&ensoniq->reg_lock);
2305
2306 if (status & ES_UART)
2307 snd_ensoniq_midi_interrupt(ensoniq);
2308 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2309 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2310 if ((status & ES_ADC) && ensoniq->capture_substream)
2311 snd_pcm_period_elapsed(ensoniq->capture_substream);
2312 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2313 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2314 return IRQ_HANDLED;
2315}
2316
[717]2317static int __snd_audiopci_probe(struct pci_dev *pci,
2318 const struct pci_device_id *pci_id)
[358]2319{
2320 static int dev;
2321 struct snd_card *card;
2322 struct ensoniq *ensoniq;
[679]2323 int err;
[358]2324
2325 if (dev >= SNDRV_CARDS)
2326 return -ENODEV;
2327 if (!enable[dev]) {
2328 dev++;
2329 return -ENOENT;
2330 }
2331
[717]2332 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2333 sizeof(*ensoniq), &card);
[410]2334 if (err < 0)
2335 return err;
[717]2336 ensoniq = card->private_data;
[358]2337
[717]2338 err = snd_ensoniq_create(card, pci);
2339 if (err < 0)
[358]2340 return err;
2341
2342#ifdef CHIP1370
[703]2343 err = snd_ensoniq_1370_mixer(ensoniq);
[717]2344 if (err < 0)
[358]2345 return err;
2346#endif
2347#ifdef CHIP1371
[703]2348 err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev]);
[717]2349 if (err < 0)
[358]2350 return err;
2351#endif
[703]2352 err = snd_ensoniq_pcm(ensoniq, 0);
[717]2353 if (err < 0)
[358]2354 return err;
[703]2355 err = snd_ensoniq_pcm2(ensoniq, 1);
[717]2356 if (err < 0)
[358]2357 return err;
[703]2358 err = snd_ensoniq_midi(ensoniq, 0);
[717]2359 if (err < 0)
[358]2360 return err;
2361
2362 snd_ensoniq_create_gameport(ensoniq, dev);
2363
2364 strcpy(card->driver, DRIVER_NAME);
2365
2366 strcpy(card->shortname, "Ensoniq AudioPCI");
2367 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2368 card->shortname,
2369 card->driver,
2370 ensoniq->port,
2371 ensoniq->irq);
2372
[703]2373 err = snd_card_register(card);
[717]2374 if (err < 0)
[358]2375 return err;
2376
2377 pci_set_drvdata(pci, card);
2378 dev++;
2379 return 0;
2380}
2381
[717]2382static int snd_audiopci_probe(struct pci_dev *pci,
2383 const struct pci_device_id *pci_id)
[358]2384{
[717]2385 return snd_card_free_on_error(&pci->dev, __snd_audiopci_probe(pci, pci_id));
[358]2386}
2387
[679]2388static struct pci_driver ens137x_driver = {
2389 .name = KBUILD_MODNAME,
[358]2390 .id_table = snd_audiopci_ids,
2391 .probe = snd_audiopci_probe,
[679]2392 .driver = {
[777]2393 .pm = &snd_ensoniq_pm,
[679]2394 },
[358]2395};
2396
[679]2397module_pci_driver(ens137x_driver);
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