source: GPL/trunk/alsa-kernel/pci/cs46xx/cs46xx_lib.c

Last change on this file was 772, checked in by David Azarewicz, 6 months ago

Merge in changes from 6.6-LTS branch.
Fixed additional 25+ problems.
File size: 109.7 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 * Abramo Bagnara <abramo@alsa-project.org>
5 * Cirrus Logic, Inc.
6 * Routines for control of Cirrus Logic CS461x chips
7 *
8 * KNOWN BUGS:
9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
10 * and the SPDIF get somewhat "distorcionated", or/and left right channel
11 * are swapped. To get around this problem when it happens, mute and unmute
12 * the SPDIF input mixer control.
13 * - On the Hercules Game Theater XP the amplifier are sometimes turned
14 * off on inadecuate moments which causes distorcions on sound.
15 *
16 * TODO:
17 * - Secondary CODEC on some soundcards
18 * - SPDIF input support for other sample rates then 48khz
19 * - Posibility to mix the SPDIF output with analog sources.
20 * - PCM channels for Center and LFE on secondary codec
21 *
22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
23 * is default configuration), no SPDIF, no secondary codec, no
24 * multi channel PCM. But known to work.
25 *
26 * FINALLY: A credit to the developers Tom and Jordan
27 * at Cirrus for have helping me out with the DSP, however we
28 * still don't have sufficient documentation and technical
29 * references to be able to implement all fancy feutures
30 * supported by the cs46xx DSP's.
31 * Benny <benny@hostmobility.com>
32 */
33
34#ifdef TARGET_OS2
35#define KBUILD_MODNAME "cs46xx"
36#endif
37
38#include <linux/delay.h>
39#include <linux/pci.h>
40#include <linux/pm.h>
41#include <linux/init.h>
42#include <linux/interrupt.h>
43#include <linux/slab.h>
44#include <linux/gameport.h>
45#include <linux/mutex.h>
46#include <linux/export.h>
47#include <linux/module.h>
48#include <linux/firmware.h>
49#include <linux/vmalloc.h>
50#include <linux/io.h>
51
52#include <sound/core.h>
53#include <sound/control.h>
54#include <sound/info.h>
55#include <sound/pcm.h>
56#include <sound/pcm_params.h>
57#include "cs46xx.h"
58
59#include "cs46xx_lib.h"
60#include "dsp_spos.h"
61
62static void amp_voyetra(struct snd_cs46xx *chip, int change);
63
64#ifdef CONFIG_SND_CS46XX_NEW_DSP
65static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
66static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
67static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
68static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
69static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
70static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
71#endif
72
73static const struct snd_pcm_ops snd_cs46xx_playback_ops;
74static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
75static const struct snd_pcm_ops snd_cs46xx_capture_ops;
76static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
77
78static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
79 unsigned short reg,
80 int codec_index)
81{
82 int count;
83 unsigned short result,tmp;
84 u32 offset = 0;
85
86 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
87 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
88 return 0xffff;
89
90 chip->active_ctrl(chip, 1);
91
92 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
93 offset = CS46XX_SECONDARY_CODEC_OFFSET;
94
95 /*
96 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
97 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
98 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
99 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
100 * 5. if DCV not cleared, break and return error
101 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
102 */
103
104 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
105
106 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
107 if ((tmp & ACCTL_VFRM) == 0) {
108 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp);
109 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
110 msleep(50);
111 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
112 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
113
114 }
115
116 /*
117 * Setup the AC97 control registers on the CS461x to send the
118 * appropriate command to the AC97 to perform the read.
119 * ACCAD = Command Address Register = 46Ch
120 * ACCDA = Command Data Register = 470h
121 * ACCTL = Control Register = 460h
122 * set DCV - will clear when process completed
123 * set CRW - Read command
124 * set VFRM - valid frame enabled
125 * set ESYN - ASYNC generation enabled
126 * set RSTN - ARST# inactive, AC97 codec not reset
127 */
128
129 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
130 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
131 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
132 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
133 ACCTL_VFRM | ACCTL_ESYN |
134 ACCTL_RSTN);
135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
136 ACCTL_VFRM | ACCTL_ESYN |
137 ACCTL_RSTN);
138 } else {
139 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
140 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
141 ACCTL_RSTN);
142 }
143
144 /*
145 * Wait for the read to occur.
146 */
147 for (count = 0; count < 1000; count++) {
148 /*
149 * First, we want to wait for a short time.
150 */
151 udelay(10);
152 /*
153 * Now, check to see if the read has completed.
154 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
155 */
156 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
157 goto ok1;
158 }
159
160 dev_err(chip->card->dev,
161 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
162 result = 0xffff;
163 goto end;
164
165 ok1:
166 /*
167 * Wait for the valid status bit to go active.
168 */
169 for (count = 0; count < 100; count++) {
170 /*
171 * Read the AC97 status register.
172 * ACSTS = Status Register = 464h
173 * VSTS - Valid Status
174 */
175 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
176 goto ok2;
177 udelay(10);
178 }
179
180 dev_err(chip->card->dev,
181 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
182 codec_index, reg);
183 result = 0xffff;
184 goto end;
185
186 ok2:
187 /*
188 * Read the data returned from the AC97 register.
189 * ACSDA = Status Data Register = 474h
190 */
191#if 0
192 dev_dbg(chip->card->dev,
193 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
194 snd_cs46xx_peekBA0(chip, BA0_ACSDA),
195 snd_cs46xx_peekBA0(chip, BA0_ACCAD));
196#endif
197
198 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
199 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
200 end:
201 chip->active_ctrl(chip, -1);
202 return result;
203}
204
205static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
206 unsigned short reg)
207{
208 struct snd_cs46xx *chip = ac97->private_data;
209 unsigned short val;
210 int codec_index = ac97->num;
211
212 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
213 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
214 return 0xffff;
215
216 val = snd_cs46xx_codec_read(chip, reg, codec_index);
217
218 return val;
219}
220
221
222static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
223 unsigned short reg,
224 unsigned short val,
225 int codec_index)
226{
227 int count;
228
229 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
230 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
231 return;
232
233 chip->active_ctrl(chip, 1);
234
235 /*
236 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
237 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
238 * 3. Write ACCTL = Control Register = 460h for initiating the write
239 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
240 * 5. if DCV not cleared, break and return error
241 */
242
243 /*
244 * Setup the AC97 control registers on the CS461x to send the
245 * appropriate command to the AC97 to perform the read.
246 * ACCAD = Command Address Register = 46Ch
247 * ACCDA = Command Data Register = 470h
248 * ACCTL = Control Register = 460h
249 * set DCV - will clear when process completed
250 * reset CRW - Write command
251 * set VFRM - valid frame enabled
252 * set ESYN - ASYNC generation enabled
253 * set RSTN - ARST# inactive, AC97 codec not reset
254 */
255 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
256 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
257 snd_cs46xx_peekBA0(chip, BA0_ACCTL);
258
259 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
260 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
261 ACCTL_ESYN | ACCTL_RSTN);
262 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
263 ACCTL_ESYN | ACCTL_RSTN);
264 } else {
265 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
266 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
267 }
268
269 for (count = 0; count < 4000; count++) {
270 /*
271 * First, we want to wait for a short time.
272 */
273 udelay(10);
274 /*
275 * Now, check to see if the write has completed.
276 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
277 */
278 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
279 goto end;
280 }
281 }
282 dev_err(chip->card->dev,
283 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
284 codec_index, reg, val);
285 end:
286 chip->active_ctrl(chip, -1);
287}
288
289static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
290 unsigned short reg,
291 unsigned short val)
292{
293 struct snd_cs46xx *chip = ac97->private_data;
294 int codec_index = ac97->num;
295
296 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
297 codec_index != CS46XX_SECONDARY_CODEC_INDEX))
298 return;
299
300 snd_cs46xx_codec_write(chip, reg, val, codec_index);
301}
302
303
304/*
305 * Chip initialization
306 */
307
308int snd_cs46xx_download(struct snd_cs46xx *chip,
309 u32 *src,
310 unsigned long offset,
311 unsigned long len)
312{
313 void __iomem *dst;
314 unsigned int bank = offset >> 16;
315 offset = offset & 0xffff;
316
317 if (snd_BUG_ON((offset & 3) || (len & 3)))
318 return -EINVAL;
319 dst = chip->region.idx[bank+1].remap_addr + offset;
320 len /= sizeof(u32);
321
322 /* writel already converts 32-bit value to right endianess */
323 while (len-- > 0) {
324 writel(*src++, dst);
325 dst += sizeof(u32);
326 }
327 return 0;
328}
329
330static inline void memcpy_le32(void *dst, const void *src, unsigned int len)
331{
332#ifdef __LITTLE_ENDIAN
333 memcpy(dst, src, len);
334#else
335 u32 *_dst = dst;
336 const __le32 *_src = src;
337 len /= 4;
338 while (len-- > 0)
339 *_dst++ = le32_to_cpu(*_src++);
340#endif
341}
342
343#ifdef CONFIG_SND_CS46XX_NEW_DSP
344
345static const char *module_names[CS46XX_DSP_MODULES] = {
346 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
347};
348
349MODULE_FIRMWARE("cs46xx/cwc4630");
350MODULE_FIRMWARE("cs46xx/cwcasync");
351MODULE_FIRMWARE("cs46xx/cwcsnoop");
352MODULE_FIRMWARE("cs46xx/cwcbinhack");
353MODULE_FIRMWARE("cs46xx/cwcdma");
354
355static void free_module_desc(struct dsp_module_desc *module)
356{
357 if (!module)
358 return;
359 kfree(module->module_name);
360 kfree(module->symbol_table.symbols);
361 if (module->segments) {
362 int i;
363 for (i = 0; i < module->nsegments; i++)
364 kfree(module->segments[i].data);
365 kfree(module->segments);
366 }
367 kfree(module);
368}
369
370/* firmware binary format:
371 * le32 nsymbols;
372 * struct {
373 * le32 address;
374 * char symbol_name[DSP_MAX_SYMBOL_NAME];
375 * le32 symbol_type;
376 * } symbols[nsymbols];
377 * le32 nsegments;
378 * struct {
379 * le32 segment_type;
380 * le32 offset;
381 * le32 size;
382 * le32 data[size];
383 * } segments[nsegments];
384 */
385
386static int load_firmware(struct snd_cs46xx *chip,
387 struct dsp_module_desc **module_ret,
388 const char *fw_name)
389{
390 int i, err;
391 unsigned int nums, fwlen, fwsize;
392 const __le32 *fwdat;
393 struct dsp_module_desc *module = NULL;
394 const struct firmware *fw;
395 char fw_path[32];
396
397 sprintf(fw_path, "cs46xx/%s", fw_name);
398 err = request_firmware(&fw, fw_path, &chip->pci->dev);
399 if (err < 0)
400 return err;
401 fwsize = fw->size / 4;
402 if (fwsize < 2) {
403 err = -EINVAL;
404 goto error;
405 }
406
407 err = -ENOMEM;
408 module = kzalloc(sizeof(*module), GFP_KERNEL);
409 if (!module)
410 goto error;
411 module->module_name = kstrdup(fw_name, GFP_KERNEL);
412 if (!module->module_name)
413 goto error;
414
415 fwlen = 0;
416 fwdat = (const __le32 *)fw->data;
417 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]);
418 if (nums >= 40)
419 goto error_inval;
420 module->symbol_table.symbols =
421 kcalloc(nums, sizeof(struct dsp_symbol_entry), GFP_KERNEL);
422 if (!module->symbol_table.symbols)
423 goto error;
424 for (i = 0; i < nums; i++) {
425 struct dsp_symbol_entry *entry =
426 &module->symbol_table.symbols[i];
427 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize)
428 goto error_inval;
429 entry->address = le32_to_cpu(fwdat[fwlen++]);
430 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1);
431 fwlen += DSP_MAX_SYMBOL_NAME / 4;
432 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]);
433 }
434
435 if (fwlen >= fwsize)
436 goto error_inval;
437 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]);
438 if (nums > 10)
439 goto error_inval;
440 module->segments =
441 kcalloc(nums, sizeof(struct dsp_segment_desc), GFP_KERNEL);
442 if (!module->segments)
443 goto error;
444 for (i = 0; i < nums; i++) {
445 struct dsp_segment_desc *entry = &module->segments[i];
446 if (fwlen + 3 > fwsize)
447 goto error_inval;
448 entry->segment_type = le32_to_cpu(fwdat[fwlen++]);
449 entry->offset = le32_to_cpu(fwdat[fwlen++]);
450 entry->size = le32_to_cpu(fwdat[fwlen++]);
451 if (fwlen + entry->size > fwsize)
452 goto error_inval;
453 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL);
454 if (!entry->data)
455 goto error;
456 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4);
457 fwlen += entry->size;
458 }
459
460 *module_ret = module;
461 release_firmware(fw);
462 return 0;
463
464 error_inval:
465 err = -EINVAL;
466 error:
467 free_module_desc(module);
468 release_firmware(fw);
469 return err;
470}
471
472int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
473 unsigned long offset,
474 unsigned long len)
475{
476 void __iomem *dst;
477 unsigned int bank = offset >> 16;
478 offset = offset & 0xffff;
479
480 if (snd_BUG_ON((offset & 3) || (len & 3)))
481 return -EINVAL;
482 dst = chip->region.idx[bank+1].remap_addr + offset;
483 len /= sizeof(u32);
484
485 /* writel already converts 32-bit value to right endianess */
486 while (len-- > 0) {
487 writel(0, dst);
488 dst += sizeof(u32);
489 }
490 return 0;
491}
492
493#else /* old DSP image */
494
495struct ba1_struct {
496 struct {
497 u32 offset;
498 u32 size;
499 } memory[BA1_MEMORY_COUNT];
500 u32 map[BA1_DWORD_SIZE];
501};
502
503MODULE_FIRMWARE("cs46xx/ba1");
504
505static int load_firmware(struct snd_cs46xx *chip)
506{
507 const struct firmware *fw;
508 int i, size, err;
509
510 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev);
511 if (err < 0)
512 return err;
513 if (fw->size != sizeof(*chip->ba1)) {
514 err = -EINVAL;
515 goto error;
516 }
517
518 chip->ba1 = vmalloc(sizeof(*chip->ba1));
519 if (!chip->ba1) {
520 err = -ENOMEM;
521 goto error;
522 }
523
524 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1));
525
526 /* sanity check */
527 size = 0;
528 for (i = 0; i < BA1_MEMORY_COUNT; i++)
529 size += chip->ba1->memory[i].size;
530 if (size > BA1_DWORD_SIZE * 4)
531 err = -EINVAL;
532
533 error:
534 release_firmware(fw);
535 return err;
536}
537
538static __maybe_unused int snd_cs46xx_download_image(struct snd_cs46xx *chip)
539{
540 int idx, err;
541 unsigned int offset = 0;
542 struct ba1_struct *ba1 = chip->ba1;
543
544 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
545 err = snd_cs46xx_download(chip,
546 &ba1->map[offset],
547 ba1->memory[idx].offset,
548 ba1->memory[idx].size);
549 if (err < 0)
550 return err;
551 offset += ba1->memory[idx].size >> 2;
552 }
553 return 0;
554}
555#endif /* CONFIG_SND_CS46XX_NEW_DSP */
556
557/*
558 * Chip reset
559 */
560
561static void snd_cs46xx_reset(struct snd_cs46xx *chip)
562{
563 int idx;
564
565 /*
566 * Write the reset bit of the SP control register.
567 */
568 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
569
570 /*
571 * Write the control register.
572 */
573 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
574
575 /*
576 * Clear the trap registers.
577 */
578 for (idx = 0; idx < 8; idx++) {
579 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
580 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
581 }
582 snd_cs46xx_poke(chip, BA1_DREG, 0);
583
584 /*
585 * Set the frame timer to reflect the number of cycles per frame.
586 */
587 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
588}
589
590static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
591{
592 u32 i, status = 0;
593 /*
594 * Make sure the previous FIFO write operation has completed.
595 */
596 for(i = 0; i < 50; i++){
597 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
598
599 if( !(status & SERBST_WBSY) )
600 break;
601
602 mdelay(retry_timeout);
603 }
604
605 if(status & SERBST_WBSY) {
606 dev_err(chip->card->dev,
607 "failure waiting for FIFO command to complete\n");
608 return -EINVAL;
609 }
610
611 return 0;
612}
613
614static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
615{
616 int idx, powerdown = 0;
617 unsigned int tmp;
618
619 /*
620 * See if the devices are powered down. If so, we must power them up first
621 * or they will not respond.
622 */
623 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
624 if (!(tmp & CLKCR1_SWCE)) {
625 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
626 powerdown = 1;
627 }
628
629 /*
630 * We want to clear out the serial port FIFOs so we don't end up playing
631 * whatever random garbage happens to be in them. We fill the sample FIFOS
632 * with zero (silence).
633 */
634 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
635
636 /*
637 * Fill all 256 sample FIFO locations.
638 */
639 for (idx = 0; idx < 0xFF; idx++) {
640 /*
641 * Make sure the previous FIFO write operation has completed.
642 */
643 if (cs46xx_wait_for_fifo(chip,1)) {
644 dev_dbg(chip->card->dev,
645 "failed waiting for FIFO at addr (%02X)\n",
646 idx);
647
648 if (powerdown)
649 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
650
651 break;
652 }
653 /*
654 * Write the serial port FIFO index.
655 */
656 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
657 /*
658 * Tell the serial port to load the new value into the FIFO location.
659 */
660 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
661 }
662 /*
663 * Now, if we powered up the devices, then power them back down again.
664 * This is kinda ugly, but should never happen.
665 */
666 if (powerdown)
667 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
668}
669
670static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
671{
672 int cnt;
673
674 /*
675 * Set the frame timer to reflect the number of cycles per frame.
676 */
677 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
678 /*
679 * Turn on the run, run at frame, and DMA enable bits in the local copy of
680 * the SP control register.
681 */
682 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
683 /*
684 * Wait until the run at frame bit resets itself in the SP control
685 * register.
686 */
687 for (cnt = 0; cnt < 25; cnt++) {
688 udelay(50);
689 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
690 break;
691 }
692
693 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
694 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n");
695}
696
697static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
698{
699 /*
700 * Turn off the run, run at frame, and DMA enable bits in the local copy of
701 * the SP control register.
702 */
703 snd_cs46xx_poke(chip, BA1_SPCR, 0);
704}
705
706/*
707 * Sample rate routines
708 */
709
710#define GOF_PER_SEC 200
711
712static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
713{
714 unsigned long flags;
715 unsigned int tmp1, tmp2;
716 unsigned int phiIncr;
717 unsigned int correctionPerGOF, correctionPerSec;
718
719 /*
720 * Compute the values used to drive the actual sample rate conversion.
721 * The following formulas are being computed, using inline assembly
722 * since we need to use 64 bit arithmetic to compute the values:
723 *
724 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
725 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
726 * GOF_PER_SEC)
727 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
728 * GOF_PER_SEC * correctionPerGOF
729 *
730 * i.e.
731 *
732 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
733 * correctionPerGOF:correctionPerSec =
734 * dividend:remainder(ulOther / GOF_PER_SEC)
735 */
736 tmp1 = rate << 16;
737 phiIncr = tmp1 / 48000;
738 tmp1 -= phiIncr * 48000;
739 tmp1 <<= 10;
740 phiIncr <<= 10;
741 tmp2 = tmp1 / 48000;
742 phiIncr += tmp2;
743 tmp1 -= tmp2 * 48000;
744 correctionPerGOF = tmp1 / GOF_PER_SEC;
745 tmp1 -= correctionPerGOF * GOF_PER_SEC;
746 correctionPerSec = tmp1;
747
748 /*
749 * Fill in the SampleRateConverter control block.
750 */
751 spin_lock_irqsave(&chip->reg_lock, flags);
752 snd_cs46xx_poke(chip, BA1_PSRC,
753 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
754 snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
755 spin_unlock_irqrestore(&chip->reg_lock, flags);
756}
757
758static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
759{
760 unsigned long flags;
761 unsigned int phiIncr, coeffIncr, tmp1, tmp2;
762 unsigned int correctionPerGOF, correctionPerSec, initialDelay;
763 unsigned int frameGroupLength, cnt;
764
765 /*
766 * We can only decimate by up to a factor of 1/9th the hardware rate.
767 * Correct the value if an attempt is made to stray outside that limit.
768 */
769 if ((rate * 9) < 48000)
770 rate = 48000 / 9;
771
772 /*
773 * We can not capture at a rate greater than the Input Rate (48000).
774 * Return an error if an attempt is made to stray outside that limit.
775 */
776 if (rate > 48000)
777 rate = 48000;
778
779 /*
780 * Compute the values used to drive the actual sample rate conversion.
781 * The following formulas are being computed, using inline assembly
782 * since we need to use 64 bit arithmetic to compute the values:
783 *
784 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
785 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
786 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
787 * GOF_PER_SEC)
788 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
789 * GOF_PER_SEC * correctionPerGOF
790 * initialDelay = ceil((24 * Fs,in) / Fs,out)
791 *
792 * i.e.
793 *
794 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
795 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
796 * correctionPerGOF:correctionPerSec =
797 * dividend:remainder(ulOther / GOF_PER_SEC)
798 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
799 */
800
801 tmp1 = rate << 16;
802 coeffIncr = tmp1 / 48000;
803 tmp1 -= coeffIncr * 48000;
804 tmp1 <<= 7;
805 coeffIncr <<= 7;
806 coeffIncr += tmp1 / 48000;
807 coeffIncr ^= 0xFFFFFFFF;
808 coeffIncr++;
809 tmp1 = 48000 << 16;
810 phiIncr = tmp1 / rate;
811 tmp1 -= phiIncr * rate;
812 tmp1 <<= 10;
813 phiIncr <<= 10;
814 tmp2 = tmp1 / rate;
815 phiIncr += tmp2;
816 tmp1 -= tmp2 * rate;
817 correctionPerGOF = tmp1 / GOF_PER_SEC;
818 tmp1 -= correctionPerGOF * GOF_PER_SEC;
819 correctionPerSec = tmp1;
820 initialDelay = DIV_ROUND_UP(48000 * 24, rate);
821
822 /*
823 * Fill in the VariDecimate control block.
824 */
825 spin_lock_irqsave(&chip->reg_lock, flags);
826 snd_cs46xx_poke(chip, BA1_CSRC,
827 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
828 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
829 snd_cs46xx_poke(chip, BA1_CD,
830 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
831 snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
832 spin_unlock_irqrestore(&chip->reg_lock, flags);
833
834 /*
835 * Figure out the frame group length for the write back task. Basically,
836 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
837 * the output sample rate.
838 */
839 frameGroupLength = 1;
840 for (cnt = 2; cnt <= 64; cnt *= 2) {
841 if (((rate / cnt) * cnt) != rate)
842 frameGroupLength *= 2;
843 }
844 if (((rate / 3) * 3) != rate) {
845 frameGroupLength *= 3;
846 }
847 for (cnt = 5; cnt <= 125; cnt *= 5) {
848 if (((rate / cnt) * cnt) != rate)
849 frameGroupLength *= 5;
850 }
851
852 /*
853 * Fill in the WriteBack control block.
854 */
855 spin_lock_irqsave(&chip->reg_lock, flags);
856 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
857 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
858 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
859 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
860 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
861 spin_unlock_irqrestore(&chip->reg_lock, flags);
862}
863
864/*
865 * PCM part
866 */
867
868static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
869 struct snd_pcm_indirect *rec, size_t bytes)
870{
871 struct snd_pcm_runtime *runtime = substream->runtime;
872 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
873 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
874}
875
876static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
877{
878 struct snd_pcm_runtime *runtime = substream->runtime;
879 struct snd_cs46xx_pcm * cpcm = runtime->private_data;
880 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec,
881 snd_cs46xx_pb_trans_copy);
882}
883
884static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
885 struct snd_pcm_indirect *rec, size_t bytes)
886{
887 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
888 struct snd_pcm_runtime *runtime = substream->runtime;
889 memcpy(runtime->dma_area + rec->sw_data,
890 chip->capt.hw_buf.area + rec->hw_data, bytes);
891}
892
893static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
894{
895 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
896 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec,
897 snd_cs46xx_cp_trans_copy);
898}
899
900static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
901{
902 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
903 size_t ptr;
904 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
905
906 if (snd_BUG_ON(!cpcm->pcm_channel))
907 return -ENXIO;
908
909#ifdef CONFIG_SND_CS46XX_NEW_DSP
910 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
911#else
912 ptr = snd_cs46xx_peek(chip, BA1_PBA);
913#endif
914 ptr -= cpcm->hw_buf.addr;
915 return ptr >> cpcm->shift;
916}
917
918static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
919{
920 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
921 size_t ptr;
922 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
923
924#ifdef CONFIG_SND_CS46XX_NEW_DSP
925 if (snd_BUG_ON(!cpcm->pcm_channel))
926 return -ENXIO;
927 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
928#else
929 ptr = snd_cs46xx_peek(chip, BA1_PBA);
930#endif
931 ptr -= cpcm->hw_buf.addr;
932 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
933}
934
935static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
936{
937 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
938 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
939 return ptr >> chip->capt.shift;
940}
941
942static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
943{
944 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
945 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
946 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
947}
948
949static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
950 int cmd)
951{
952 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
953 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
954 int result = 0;
955
956#ifdef CONFIG_SND_CS46XX_NEW_DSP
957 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
958 if (! cpcm->pcm_channel) {
959 return -ENXIO;
960 }
961#endif
962 switch (cmd) {
963 case SNDRV_PCM_TRIGGER_START:
964 case SNDRV_PCM_TRIGGER_RESUME:
965#ifdef CONFIG_SND_CS46XX_NEW_DSP
966 /* magic value to unmute PCM stream playback volume */
967 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
968 SCBVolumeCtrl) << 2, 0x80008000);
969
970 if (cpcm->pcm_channel->unlinked)
971 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
972
973 if (substream->runtime->periods != CS46XX_FRAGS)
974 snd_cs46xx_playback_transfer(substream);
975#else
976 spin_lock(&chip->reg_lock);
977 if (substream->runtime->periods != CS46XX_FRAGS)
978 snd_cs46xx_playback_transfer(substream);
979 { unsigned int tmp;
980 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
981 tmp &= 0x0000ffff;
982 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
983 }
984 spin_unlock(&chip->reg_lock);
985#endif
986 break;
987 case SNDRV_PCM_TRIGGER_STOP:
988 case SNDRV_PCM_TRIGGER_SUSPEND:
989#ifdef CONFIG_SND_CS46XX_NEW_DSP
990 /* magic mute channel */
991 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
992 SCBVolumeCtrl) << 2, 0xffffffff);
993
994 if (!cpcm->pcm_channel->unlinked)
995 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
996#else
997 spin_lock(&chip->reg_lock);
998 { unsigned int tmp;
999 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
1000 tmp &= 0x0000ffff;
1001 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
1002 }
1003 spin_unlock(&chip->reg_lock);
1004#endif
1005 break;
1006 default:
1007 result = -EINVAL;
1008 break;
1009 }
1010
1011 return result;
1012}
1013
1014static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
1015 int cmd)
1016{
1017 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1018 unsigned int tmp;
1019 int result = 0;
1020
1021 spin_lock(&chip->reg_lock);
1022 switch (cmd) {
1023 case SNDRV_PCM_TRIGGER_START:
1024 case SNDRV_PCM_TRIGGER_RESUME:
1025 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1026 tmp &= 0xffff0000;
1027 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
1028 break;
1029 case SNDRV_PCM_TRIGGER_STOP:
1030 case SNDRV_PCM_TRIGGER_SUSPEND:
1031 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
1032 tmp &= 0xffff0000;
1033 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
1034 break;
1035 default:
1036 result = -EINVAL;
1037 break;
1038 }
1039 spin_unlock(&chip->reg_lock);
1040
1041 return result;
1042}
1043
1044#ifdef CONFIG_SND_CS46XX_NEW_DSP
1045static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
1046 int sample_rate)
1047{
1048
1049 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1050 if ( cpcm->pcm_channel == NULL) {
1051 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
1052 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
1053 if (cpcm->pcm_channel == NULL) {
1054 dev_err(chip->card->dev,
1055 "failed to create virtual PCM channel\n");
1056 return -ENOMEM;
1057 }
1058 cpcm->pcm_channel->sample_rate = sample_rate;
1059 } else
1060 /* if sample rate is changed */
1061 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
1062 int unlinked = cpcm->pcm_channel->unlinked;
1063 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
1064
1065 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm,
1066 cpcm->hw_buf.addr,
1067 cpcm->pcm_channel_id);
1068 if (!cpcm->pcm_channel) {
1069 dev_err(chip->card->dev,
1070 "failed to re-create virtual PCM channel\n");
1071 return -ENOMEM;
1072 }
1073
1074 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
1075 cpcm->pcm_channel->sample_rate = sample_rate;
1076 }
1077
1078 return 0;
1079}
1080#endif
1081
1082
1083static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
1084 struct snd_pcm_hw_params *hw_params)
1085{
1086 struct snd_pcm_runtime *runtime = substream->runtime;
1087 struct snd_cs46xx_pcm *cpcm;
1088 int err;
1089#ifdef CONFIG_SND_CS46XX_NEW_DSP
1090 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1091 int sample_rate = params_rate(hw_params);
1092 int period_size = params_period_bytes(hw_params);
1093#endif
1094 cpcm = runtime->private_data;
1095
1096#ifdef CONFIG_SND_CS46XX_NEW_DSP
1097 if (snd_BUG_ON(!sample_rate))
1098 return -ENXIO;
1099
1100 mutex_lock(&chip->spos_mutex);
1101
1102 if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
1103 mutex_unlock(&chip->spos_mutex);
1104 return -ENXIO;
1105 }
1106
1107 snd_BUG_ON(!cpcm->pcm_channel);
1108 if (!cpcm->pcm_channel) {
1109 mutex_unlock(&chip->spos_mutex);
1110 return -ENXIO;
1111 }
1112
1113
1114 if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
1115 mutex_unlock(&chip->spos_mutex);
1116 return -EINVAL;
1117 }
1118
1119 dev_dbg(chip->card->dev,
1120 "period_size (%d), periods (%d) buffer_size(%d)\n",
1121 period_size, params_periods(hw_params),
1122 params_buffer_bytes(hw_params));
1123#endif
1124
1125 if (params_periods(hw_params) == CS46XX_FRAGS) {
1126 if (runtime->dma_area != cpcm->hw_buf.area)
1127 snd_pcm_lib_free_pages(substream);
1128 snd_pcm_set_runtime_buffer(substream, &cpcm->hw_buf);
1129
1130
1131#ifdef CONFIG_SND_CS46XX_NEW_DSP
1132 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1133 substream->ops = &snd_cs46xx_playback_ops;
1134 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1135 substream->ops = &snd_cs46xx_playback_rear_ops;
1136 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1137 substream->ops = &snd_cs46xx_playback_clfe_ops;
1138 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1139 substream->ops = &snd_cs46xx_playback_iec958_ops;
1140 } else {
1141 snd_BUG();
1142 }
1143#else
1144 substream->ops = &snd_cs46xx_playback_ops;
1145#endif
1146
1147 } else {
1148 if (runtime->dma_area == cpcm->hw_buf.area)
1149 snd_pcm_set_runtime_buffer(substream, NULL);
1150 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1151 if (err < 0) {
1152#ifdef CONFIG_SND_CS46XX_NEW_DSP
1153 mutex_unlock(&chip->spos_mutex);
1154#endif
1155 return err;
1156 }
1157
1158#ifdef CONFIG_SND_CS46XX_NEW_DSP
1159 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
1160 substream->ops = &snd_cs46xx_playback_indirect_ops;
1161 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
1162 substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
1163 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
1164 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
1165 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
1166 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
1167 } else {
1168 snd_BUG();
1169 }
1170#else
1171 substream->ops = &snd_cs46xx_playback_indirect_ops;
1172#endif
1173
1174 }
1175
1176#ifdef CONFIG_SND_CS46XX_NEW_DSP
1177 mutex_unlock(&chip->spos_mutex);
1178#endif
1179
1180 return 0;
1181}
1182
1183static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1184{
1185 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1186 struct snd_pcm_runtime *runtime = substream->runtime;
1187 struct snd_cs46xx_pcm *cpcm;
1188
1189 cpcm = runtime->private_data;
1190
1191 /* if play_back open fails, then this function
1192 is called and cpcm can actually be NULL here */
1193 if (!cpcm) return -ENXIO;
1194
1195 if (runtime->dma_area != cpcm->hw_buf.area)
1196 snd_pcm_lib_free_pages(substream);
1197
1198 snd_pcm_set_runtime_buffer(substream, NULL);
1199
1200 return 0;
1201}
1202
1203static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1204{
1205 unsigned int tmp;
1206 unsigned int pfie;
1207 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1208 struct snd_pcm_runtime *runtime = substream->runtime;
1209 struct snd_cs46xx_pcm *cpcm;
1210
1211 cpcm = runtime->private_data;
1212
1213#ifdef CONFIG_SND_CS46XX_NEW_DSP
1214 if (snd_BUG_ON(!cpcm->pcm_channel))
1215 return -ENXIO;
1216
1217 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1218 pfie &= ~0x0000f03f;
1219#else
1220 /* old dsp */
1221 pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1222 pfie &= ~0x0000f03f;
1223#endif
1224
1225 cpcm->shift = 2;
1226 /* if to convert from stereo to mono */
1227 if (runtime->channels == 1) {
1228 cpcm->shift--;
1229 pfie |= 0x00002000;
1230 }
1231 /* if to convert from 8 bit to 16 bit */
1232 if (snd_pcm_format_width(runtime->format) == 8) {
1233 cpcm->shift--;
1234 pfie |= 0x00001000;
1235 }
1236 /* if to convert to unsigned */
1237 if (snd_pcm_format_unsigned(runtime->format))
1238 pfie |= 0x00008000;
1239
1240 /* Never convert byte order when sample stream is 8 bit */
1241 if (snd_pcm_format_width(runtime->format) != 8) {
1242 /* convert from big endian to little endian */
1243 if (snd_pcm_format_big_endian(runtime->format))
1244 pfie |= 0x00004000;
1245 }
1246
1247 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1248 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1249 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1250
1251#ifdef CONFIG_SND_CS46XX_NEW_DSP
1252
1253 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1254 tmp &= ~0x000003ff;
1255 tmp |= (4 << cpcm->shift) - 1;
1256 /* playback transaction count register */
1257 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1258
1259 /* playback format && interrupt enable */
1260 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1261#else
1262 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1263 tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1264 tmp &= ~0x000003ff;
1265 tmp |= (4 << cpcm->shift) - 1;
1266 snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1267 snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1268 snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1269#endif
1270
1271 return 0;
1272}
1273
1274static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1275 struct snd_pcm_hw_params *hw_params)
1276{
1277 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1278 struct snd_pcm_runtime *runtime = substream->runtime;
1279 int err;
1280
1281#ifdef CONFIG_SND_CS46XX_NEW_DSP
1282 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1283#endif
1284 if (runtime->periods == CS46XX_FRAGS) {
1285 if (runtime->dma_area != chip->capt.hw_buf.area)
1286 snd_pcm_lib_free_pages(substream);
1287 snd_pcm_set_runtime_buffer(substream, &chip->capt.hw_buf);
1288 substream->ops = &snd_cs46xx_capture_ops;
1289 } else {
1290 if (runtime->dma_area == chip->capt.hw_buf.area)
1291 snd_pcm_set_runtime_buffer(substream, NULL);
1292 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1293 if (err < 0)
1294 return err;
1295 substream->ops = &snd_cs46xx_capture_indirect_ops;
1296 }
1297
1298 return 0;
1299}
1300
1301static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1302{
1303 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1304 struct snd_pcm_runtime *runtime = substream->runtime;
1305
1306 if (runtime->dma_area != chip->capt.hw_buf.area)
1307 snd_pcm_lib_free_pages(substream);
1308 snd_pcm_set_runtime_buffer(substream, NULL);
1309
1310 return 0;
1311}
1312
1313static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1314{
1315 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1316 struct snd_pcm_runtime *runtime = substream->runtime;
1317
1318 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1319 chip->capt.shift = 2;
1320 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1321 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1322 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1323 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1324
1325 return 0;
1326}
1327
1328static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1329{
1330 struct snd_cs46xx *chip = dev_id;
1331 u32 status1;
1332#ifdef CONFIG_SND_CS46XX_NEW_DSP
1333 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1334 u32 status2;
1335 int i;
1336 struct snd_cs46xx_pcm *cpcm = NULL;
1337#endif
1338
1339 /*
1340 * Read the Interrupt Status Register to clear the interrupt
1341 */
1342 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1343 if ((status1 & 0x7fffffff) == 0) {
1344 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1345 return IRQ_NONE;
1346 }
1347
1348#ifdef CONFIG_SND_CS46XX_NEW_DSP
1349 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1350
1351 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1352 if (i <= 15) {
1353 if ( status1 & (1 << i) ) {
1354 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1355 if (chip->capt.substream)
1356 snd_pcm_period_elapsed(chip->capt.substream);
1357 } else {
1358 if (ins->pcm_channels[i].active &&
1359 ins->pcm_channels[i].private_data &&
1360 !ins->pcm_channels[i].unlinked) {
1361 cpcm = ins->pcm_channels[i].private_data;
1362 snd_pcm_period_elapsed(cpcm->substream);
1363 }
1364 }
1365 }
1366 } else {
1367 if ( status2 & (1 << (i - 16))) {
1368 if (ins->pcm_channels[i].active &&
1369 ins->pcm_channels[i].private_data &&
1370 !ins->pcm_channels[i].unlinked) {
1371 cpcm = ins->pcm_channels[i].private_data;
1372 snd_pcm_period_elapsed(cpcm->substream);
1373 }
1374 }
1375 }
1376 }
1377
1378#else
1379 /* old dsp */
1380 if ((status1 & HISR_VC0) && chip->playback_pcm) {
1381 if (chip->playback_pcm->substream)
1382 snd_pcm_period_elapsed(chip->playback_pcm->substream);
1383 }
1384 if ((status1 & HISR_VC1) && chip->pcm) {
1385 if (chip->capt.substream)
1386 snd_pcm_period_elapsed(chip->capt.substream);
1387 }
1388#endif
1389
1390 if ((status1 & HISR_MIDI) && chip->rmidi) {
1391 unsigned char c;
1392
1393 spin_lock(&chip->reg_lock);
1394 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1395 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1396 if ((chip->midcr & MIDCR_RIE) == 0)
1397 continue;
1398 snd_rawmidi_receive(chip->midi_input, &c, 1);
1399 }
1400 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1401 if ((chip->midcr & MIDCR_TIE) == 0)
1402 break;
1403 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1404 chip->midcr &= ~MIDCR_TIE;
1405 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1406 break;
1407 }
1408 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1409 }
1410 spin_unlock(&chip->reg_lock);
1411 }
1412 /*
1413 * EOI to the PCI part....reenables interrupts
1414 */
1415 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1416
1417 return IRQ_HANDLED;
1418}
1419
1420static const struct snd_pcm_hardware snd_cs46xx_playback =
1421{
1422 .info = (SNDRV_PCM_INFO_MMAP |
1423 SNDRV_PCM_INFO_INTERLEAVED |
1424 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1425 /*SNDRV_PCM_INFO_RESUME*/ |
1426 SNDRV_PCM_INFO_SYNC_APPLPTR),
1427 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1428 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1429 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1430 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1431 .rate_min = 5500,
1432 .rate_max = 48000,
1433 .channels_min = 1,
1434 .channels_max = 2,
1435 .buffer_bytes_max = (256 * 1024),
1436 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1437 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1438 .periods_min = CS46XX_FRAGS,
1439 .periods_max = 1024,
1440 .fifo_size = 0,
1441};
1442
1443static const struct snd_pcm_hardware snd_cs46xx_capture =
1444{
1445 .info = (SNDRV_PCM_INFO_MMAP |
1446 SNDRV_PCM_INFO_INTERLEAVED |
1447 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1448 /*SNDRV_PCM_INFO_RESUME*/ |
1449 SNDRV_PCM_INFO_SYNC_APPLPTR),
1450 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1451 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1452 .rate_min = 5500,
1453 .rate_max = 48000,
1454 .channels_min = 2,
1455 .channels_max = 2,
1456 .buffer_bytes_max = (256 * 1024),
1457 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
1458 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
1459 .periods_min = CS46XX_FRAGS,
1460 .periods_max = 1024,
1461 .fifo_size = 0,
1462};
1463
1464#ifdef CONFIG_SND_CS46XX_NEW_DSP
1465
1466static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1467
1468static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1469 .count = ARRAY_SIZE(period_sizes),
1470 .list = period_sizes,
1471 .mask = 0
1472};
1473
1474#endif
1475
1476static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1477{
1478 kfree(runtime->private_data);
1479}
1480
1481static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1482{
1483 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1484 struct snd_cs46xx_pcm * cpcm;
1485 struct snd_pcm_runtime *runtime = substream->runtime;
1486
1487 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1488 if (cpcm == NULL)
1489 return -ENOMEM;
1490 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1491 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1492 kfree(cpcm);
1493 return -ENOMEM;
1494 }
1495
1496 runtime->hw = snd_cs46xx_playback;
1497 runtime->private_data = cpcm;
1498 runtime->private_free = snd_cs46xx_pcm_free_substream;
1499
1500 cpcm->substream = substream;
1501#ifdef CONFIG_SND_CS46XX_NEW_DSP
1502 mutex_lock(&chip->spos_mutex);
1503 cpcm->pcm_channel = NULL;
1504 cpcm->pcm_channel_id = pcm_channel_id;
1505
1506
1507 snd_pcm_hw_constraint_list(runtime, 0,
1508 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1509 &hw_constraints_period_sizes);
1510
1511 mutex_unlock(&chip->spos_mutex);
1512#else
1513 chip->playback_pcm = cpcm; /* HACK */
1514#endif
1515
1516 if (chip->accept_valid)
1517 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1518 chip->active_ctrl(chip, 1);
1519
1520 return 0;
1521}
1522
1523static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1524{
1525 dev_dbg(substream->pcm->card->dev, "open front channel\n");
1526 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1527}
1528
1529#ifdef CONFIG_SND_CS46XX_NEW_DSP
1530static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1531{
1532 dev_dbg(substream->pcm->card->dev, "open rear channel\n");
1533 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1534}
1535
1536static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1537{
1538 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n");
1539 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1540}
1541
1542static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1543{
1544 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1545
1546 dev_dbg(chip->card->dev, "open raw iec958 channel\n");
1547
1548 mutex_lock(&chip->spos_mutex);
1549 cs46xx_iec958_pre_open (chip);
1550 mutex_unlock(&chip->spos_mutex);
1551
1552 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1553}
1554
1555static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1556
1557static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1558{
1559 int err;
1560 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1561
1562 dev_dbg(chip->card->dev, "close raw iec958 channel\n");
1563
1564 err = snd_cs46xx_playback_close(substream);
1565
1566 mutex_lock(&chip->spos_mutex);
1567 cs46xx_iec958_post_close (chip);
1568 mutex_unlock(&chip->spos_mutex);
1569
1570 return err;
1571}
1572#endif
1573
1574static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1575{
1576 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1577
1578 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
1579 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1580 return -ENOMEM;
1581 chip->capt.substream = substream;
1582 substream->runtime->hw = snd_cs46xx_capture;
1583
1584 if (chip->accept_valid)
1585 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1586
1587 chip->active_ctrl(chip, 1);
1588
1589#ifdef CONFIG_SND_CS46XX_NEW_DSP
1590 snd_pcm_hw_constraint_list(substream->runtime, 0,
1591 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1592 &hw_constraints_period_sizes);
1593#endif
1594 return 0;
1595}
1596
1597static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1598{
1599 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1600 struct snd_pcm_runtime *runtime = substream->runtime;
1601 struct snd_cs46xx_pcm * cpcm;
1602
1603 cpcm = runtime->private_data;
1604
1605 /* when playback_open fails, then cpcm can be NULL */
1606 if (!cpcm) return -ENXIO;
1607
1608#ifdef CONFIG_SND_CS46XX_NEW_DSP
1609 mutex_lock(&chip->spos_mutex);
1610 if (cpcm->pcm_channel) {
1611 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1612 cpcm->pcm_channel = NULL;
1613 }
1614 mutex_unlock(&chip->spos_mutex);
1615#else
1616 chip->playback_pcm = NULL;
1617#endif
1618
1619 cpcm->substream = NULL;
1620 snd_dma_free_pages(&cpcm->hw_buf);
1621 chip->active_ctrl(chip, -1);
1622
1623 return 0;
1624}
1625
1626static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1627{
1628 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1629
1630 chip->capt.substream = NULL;
1631 snd_dma_free_pages(&chip->capt.hw_buf);
1632 chip->active_ctrl(chip, -1);
1633
1634 return 0;
1635}
1636
1637#ifdef CONFIG_SND_CS46XX_NEW_DSP
1638static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1639 .open = snd_cs46xx_playback_open_rear,
1640 .close = snd_cs46xx_playback_close,
1641 .hw_params = snd_cs46xx_playback_hw_params,
1642 .hw_free = snd_cs46xx_playback_hw_free,
1643 .prepare = snd_cs46xx_playback_prepare,
1644 .trigger = snd_cs46xx_playback_trigger,
1645 .pointer = snd_cs46xx_playback_direct_pointer,
1646};
1647
1648static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1649 .open = snd_cs46xx_playback_open_rear,
1650 .close = snd_cs46xx_playback_close,
1651 .hw_params = snd_cs46xx_playback_hw_params,
1652 .hw_free = snd_cs46xx_playback_hw_free,
1653 .prepare = snd_cs46xx_playback_prepare,
1654 .trigger = snd_cs46xx_playback_trigger,
1655 .pointer = snd_cs46xx_playback_indirect_pointer,
1656 .ack = snd_cs46xx_playback_transfer,
1657};
1658
1659static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1660 .open = snd_cs46xx_playback_open_clfe,
1661 .close = snd_cs46xx_playback_close,
1662 .hw_params = snd_cs46xx_playback_hw_params,
1663 .hw_free = snd_cs46xx_playback_hw_free,
1664 .prepare = snd_cs46xx_playback_prepare,
1665 .trigger = snd_cs46xx_playback_trigger,
1666 .pointer = snd_cs46xx_playback_direct_pointer,
1667};
1668
1669static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1670 .open = snd_cs46xx_playback_open_clfe,
1671 .close = snd_cs46xx_playback_close,
1672 .hw_params = snd_cs46xx_playback_hw_params,
1673 .hw_free = snd_cs46xx_playback_hw_free,
1674 .prepare = snd_cs46xx_playback_prepare,
1675 .trigger = snd_cs46xx_playback_trigger,
1676 .pointer = snd_cs46xx_playback_indirect_pointer,
1677 .ack = snd_cs46xx_playback_transfer,
1678};
1679
1680static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1681 .open = snd_cs46xx_playback_open_iec958,
1682 .close = snd_cs46xx_playback_close_iec958,
1683 .hw_params = snd_cs46xx_playback_hw_params,
1684 .hw_free = snd_cs46xx_playback_hw_free,
1685 .prepare = snd_cs46xx_playback_prepare,
1686 .trigger = snd_cs46xx_playback_trigger,
1687 .pointer = snd_cs46xx_playback_direct_pointer,
1688};
1689
1690static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1691 .open = snd_cs46xx_playback_open_iec958,
1692 .close = snd_cs46xx_playback_close_iec958,
1693 .hw_params = snd_cs46xx_playback_hw_params,
1694 .hw_free = snd_cs46xx_playback_hw_free,
1695 .prepare = snd_cs46xx_playback_prepare,
1696 .trigger = snd_cs46xx_playback_trigger,
1697 .pointer = snd_cs46xx_playback_indirect_pointer,
1698 .ack = snd_cs46xx_playback_transfer,
1699};
1700
1701#endif
1702
1703static const struct snd_pcm_ops snd_cs46xx_playback_ops = {
1704 .open = snd_cs46xx_playback_open,
1705 .close = snd_cs46xx_playback_close,
1706 .hw_params = snd_cs46xx_playback_hw_params,
1707 .hw_free = snd_cs46xx_playback_hw_free,
1708 .prepare = snd_cs46xx_playback_prepare,
1709 .trigger = snd_cs46xx_playback_trigger,
1710 .pointer = snd_cs46xx_playback_direct_pointer,
1711};
1712
1713static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1714 .open = snd_cs46xx_playback_open,
1715 .close = snd_cs46xx_playback_close,
1716 .hw_params = snd_cs46xx_playback_hw_params,
1717 .hw_free = snd_cs46xx_playback_hw_free,
1718 .prepare = snd_cs46xx_playback_prepare,
1719 .trigger = snd_cs46xx_playback_trigger,
1720 .pointer = snd_cs46xx_playback_indirect_pointer,
1721 .ack = snd_cs46xx_playback_transfer,
1722};
1723
1724static const struct snd_pcm_ops snd_cs46xx_capture_ops = {
1725 .open = snd_cs46xx_capture_open,
1726 .close = snd_cs46xx_capture_close,
1727 .hw_params = snd_cs46xx_capture_hw_params,
1728 .hw_free = snd_cs46xx_capture_hw_free,
1729 .prepare = snd_cs46xx_capture_prepare,
1730 .trigger = snd_cs46xx_capture_trigger,
1731 .pointer = snd_cs46xx_capture_direct_pointer,
1732};
1733
1734static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1735 .open = snd_cs46xx_capture_open,
1736 .close = snd_cs46xx_capture_close,
1737 .hw_params = snd_cs46xx_capture_hw_params,
1738 .hw_free = snd_cs46xx_capture_hw_free,
1739 .prepare = snd_cs46xx_capture_prepare,
1740 .trigger = snd_cs46xx_capture_trigger,
1741 .pointer = snd_cs46xx_capture_indirect_pointer,
1742 .ack = snd_cs46xx_capture_transfer,
1743};
1744
1745#ifdef CONFIG_SND_CS46XX_NEW_DSP
1746#define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1747#else
1748#define MAX_PLAYBACK_CHANNELS 1
1749#endif
1750
1751int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device)
1752{
1753 struct snd_pcm *pcm;
1754 int err;
1755
1756 err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm);
1757 if (err < 0)
1758 return err;
1759
1760 pcm->private_data = chip;
1761
1762 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1763 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1764
1765 /* global setup */
1766 pcm->info_flags = 0;
1767 strcpy(pcm->name, "CS46xx");
1768 chip->pcm = pcm;
1769
1770 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1771 &chip->pci->dev,
1772 64*1024, 256*1024);
1773
1774 return 0;
1775}
1776
1777
1778#ifdef CONFIG_SND_CS46XX_NEW_DSP
1779int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device)
1780{
1781 struct snd_pcm *pcm;
1782 int err;
1783
1784 err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1785 if (err < 0)
1786 return err;
1787
1788 pcm->private_data = chip;
1789
1790 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1791
1792 /* global setup */
1793 pcm->info_flags = 0;
1794 strcpy(pcm->name, "CS46xx - Rear");
1795 chip->pcm_rear = pcm;
1796
1797 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1798 &chip->pci->dev,
1799 64*1024, 256*1024);
1800
1801 return 0;
1802}
1803
1804int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device)
1805{
1806 struct snd_pcm *pcm;
1807 int err;
1808
1809 err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm);
1810 if (err < 0)
1811 return err;
1812
1813 pcm->private_data = chip;
1814
1815 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1816
1817 /* global setup */
1818 pcm->info_flags = 0;
1819 strcpy(pcm->name, "CS46xx - Center LFE");
1820 chip->pcm_center_lfe = pcm;
1821
1822 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1823 &chip->pci->dev,
1824 64*1024, 256*1024);
1825
1826 return 0;
1827}
1828
1829int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device)
1830{
1831 struct snd_pcm *pcm;
1832 int err;
1833
1834 err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm);
1835 if (err < 0)
1836 return err;
1837
1838 pcm->private_data = chip;
1839
1840 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1841
1842 /* global setup */
1843 pcm->info_flags = 0;
1844 strcpy(pcm->name, "CS46xx - IEC958");
1845 chip->pcm_iec958 = pcm;
1846
1847 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1848 &chip->pci->dev,
1849 64*1024, 256*1024);
1850
1851 return 0;
1852}
1853#endif
1854
1855/*
1856 * Mixer routines
1857 */
1858static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1859{
1860 struct snd_cs46xx *chip = ac97->private_data;
1861
1862 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1863 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1864 return;
1865
1866 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1867 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1868 chip->eapd_switch = NULL;
1869 }
1870 else
1871 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1872}
1873
1874static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1875 struct snd_ctl_elem_info *uinfo)
1876{
1877 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1878 uinfo->count = 2;
1879 uinfo->value.integer.min = 0;
1880 uinfo->value.integer.max = 0x7fff;
1881 return 0;
1882}
1883
1884static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1885{
1886 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1887 int reg = kcontrol->private_value;
1888 unsigned int val = snd_cs46xx_peek(chip, reg);
1889 ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1890 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1891 return 0;
1892}
1893
1894static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1895{
1896 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1897 int reg = kcontrol->private_value;
1898 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1899 (0xffff - ucontrol->value.integer.value[1]));
1900 unsigned int old = snd_cs46xx_peek(chip, reg);
1901 int change = (old != val);
1902
1903 if (change) {
1904 snd_cs46xx_poke(chip, reg, val);
1905 }
1906
1907 return change;
1908}
1909
1910#ifdef CONFIG_SND_CS46XX_NEW_DSP
1911
1912static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1913{
1914 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1915
1916 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1917 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1918
1919 return 0;
1920}
1921
1922static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1923{
1924 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1925 int change = 0;
1926
1927 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1928 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1929 cs46xx_dsp_set_dac_volume(chip,
1930 ucontrol->value.integer.value[0],
1931 ucontrol->value.integer.value[1]);
1932 change = 1;
1933 }
1934
1935 return change;
1936}
1937
1938#if 0
1939static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1940{
1941 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1942
1943 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1944 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1945 return 0;
1946}
1947
1948static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1949{
1950 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1951 int change = 0;
1952
1953 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
1954 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1955 cs46xx_dsp_set_iec958_volume (chip,
1956 ucontrol->value.integer.value[0],
1957 ucontrol->value.integer.value[1]);
1958 change = 1;
1959 }
1960
1961 return change;
1962}
1963#endif
1964
1965#define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1966
1967static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1968 struct snd_ctl_elem_value *ucontrol)
1969{
1970 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1971 int reg = kcontrol->private_value;
1972
1973 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1974 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1975 else
1976 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1977
1978 return 0;
1979}
1980
1981static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1982 struct snd_ctl_elem_value *ucontrol)
1983{
1984 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1985 int change, res;
1986
1987 switch (kcontrol->private_value) {
1988 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1989 mutex_lock(&chip->spos_mutex);
1990 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1991 if (ucontrol->value.integer.value[0] && !change)
1992 cs46xx_dsp_enable_spdif_out(chip);
1993 else if (change && !ucontrol->value.integer.value[0])
1994 cs46xx_dsp_disable_spdif_out(chip);
1995
1996 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1997 mutex_unlock(&chip->spos_mutex);
1998 break;
1999 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
2000 change = chip->dsp_spos_instance->spdif_status_in;
2001 if (ucontrol->value.integer.value[0] && !change) {
2002 cs46xx_dsp_enable_spdif_in(chip);
2003 /* restore volume */
2004 }
2005 else if (change && !ucontrol->value.integer.value[0])
2006 cs46xx_dsp_disable_spdif_in(chip);
2007
2008 res = (change != chip->dsp_spos_instance->spdif_status_in);
2009 break;
2010 default:
2011 res = -EINVAL;
2012 snd_BUG(); /* should never happen ... */
2013 }
2014
2015 return res;
2016}
2017
2018static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
2019 struct snd_ctl_elem_value *ucontrol)
2020{
2021 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2022 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2023
2024 if (ins->adc_input != NULL)
2025 ucontrol->value.integer.value[0] = 1;
2026 else
2027 ucontrol->value.integer.value[0] = 0;
2028
2029 return 0;
2030}
2031
2032static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
2033 struct snd_ctl_elem_value *ucontrol)
2034{
2035 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2036 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2037 int change = 0;
2038
2039 if (ucontrol->value.integer.value[0] && !ins->adc_input) {
2040 cs46xx_dsp_enable_adc_capture(chip);
2041 change = 1;
2042 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
2043 cs46xx_dsp_disable_adc_capture(chip);
2044 change = 1;
2045 }
2046 return change;
2047}
2048
2049static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
2050 struct snd_ctl_elem_value *ucontrol)
2051{
2052 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2053 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2054
2055 if (ins->pcm_input != NULL)
2056 ucontrol->value.integer.value[0] = 1;
2057 else
2058 ucontrol->value.integer.value[0] = 0;
2059
2060 return 0;
2061}
2062
2063
2064static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
2065 struct snd_ctl_elem_value *ucontrol)
2066{
2067 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2068 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2069 int change = 0;
2070
2071 if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
2072 cs46xx_dsp_enable_pcm_capture(chip);
2073 change = 1;
2074 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
2075 cs46xx_dsp_disable_pcm_capture(chip);
2076 change = 1;
2077 }
2078
2079 return change;
2080}
2081
2082static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
2083 struct snd_ctl_elem_value *ucontrol)
2084{
2085 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2086
2087 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2088
2089 if (val1 & EGPIODR_GPOE0)
2090 ucontrol->value.integer.value[0] = 1;
2091 else
2092 ucontrol->value.integer.value[0] = 0;
2093
2094 return 0;
2095}
2096
2097/*
2098 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2099 */
2100static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
2101 struct snd_ctl_elem_value *ucontrol)
2102{
2103 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2104 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
2105 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
2106
2107 if (ucontrol->value.integer.value[0]) {
2108 /* optical is default */
2109 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
2110 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
2111 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
2112 EGPIOPTR_GPPT0 | val2); /* open-drain on output */
2113 } else {
2114 /* coaxial */
2115 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
2116 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
2117 }
2118
2119 /* checking diff from the EGPIO direction register
2120 should be enough */
2121 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
2122}
2123
2124
2125static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2126{
2127 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2128 uinfo->count = 1;
2129 return 0;
2130}
2131
2132static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
2133 struct snd_ctl_elem_value *ucontrol)
2134{
2135 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2136 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2137
2138 mutex_lock(&chip->spos_mutex);
2139 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2140 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2141 ucontrol->value.iec958.status[2] = 0;
2142 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2143 mutex_unlock(&chip->spos_mutex);
2144
2145 return 0;
2146}
2147
2148static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2149 struct snd_ctl_elem_value *ucontrol)
2150{
2151 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2152 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2153 unsigned int val;
2154 int change;
2155
2156 mutex_lock(&chip->spos_mutex);
2157 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2158 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2159 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2160 /* left and right validity bit */
2161 (1 << 13) | (1 << 12);
2162
2163
2164 change = (unsigned int)ins->spdif_csuv_default != val;
2165 ins->spdif_csuv_default = val;
2166
2167 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2168 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2169
2170 mutex_unlock(&chip->spos_mutex);
2171
2172 return change;
2173}
2174
2175static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2176 struct snd_ctl_elem_value *ucontrol)
2177{
2178 ucontrol->value.iec958.status[0] = 0xff;
2179 ucontrol->value.iec958.status[1] = 0xff;
2180 ucontrol->value.iec958.status[2] = 0x00;
2181 ucontrol->value.iec958.status[3] = 0xff;
2182 return 0;
2183}
2184
2185static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2186 struct snd_ctl_elem_value *ucontrol)
2187{
2188 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2189 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2190
2191 mutex_lock(&chip->spos_mutex);
2192 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2193 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2194 ucontrol->value.iec958.status[2] = 0;
2195 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2196 mutex_unlock(&chip->spos_mutex);
2197
2198 return 0;
2199}
2200
2201static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2202 struct snd_ctl_elem_value *ucontrol)
2203{
2204 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2205 struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2206 unsigned int val;
2207 int change;
2208
2209 mutex_lock(&chip->spos_mutex);
2210 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2211 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2212 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2213 /* left and right validity bit */
2214 (1 << 13) | (1 << 12);
2215
2216
2217 change = ins->spdif_csuv_stream != val;
2218 ins->spdif_csuv_stream = val;
2219
2220 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2221 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2222
2223 mutex_unlock(&chip->spos_mutex);
2224
2225 return change;
2226}
2227
2228#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2229
2230
2231static const struct snd_kcontrol_new snd_cs46xx_controls[] = {
2232{
2233 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2234 .name = "DAC Volume",
2235 .info = snd_cs46xx_vol_info,
2236#ifndef CONFIG_SND_CS46XX_NEW_DSP
2237 .get = snd_cs46xx_vol_get,
2238 .put = snd_cs46xx_vol_put,
2239 .private_value = BA1_PVOL,
2240#else
2241 .get = snd_cs46xx_vol_dac_get,
2242 .put = snd_cs46xx_vol_dac_put,
2243#endif
2244},
2245
2246{
2247 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2248 .name = "ADC Volume",
2249 .info = snd_cs46xx_vol_info,
2250 .get = snd_cs46xx_vol_get,
2251 .put = snd_cs46xx_vol_put,
2252#ifndef CONFIG_SND_CS46XX_NEW_DSP
2253 .private_value = BA1_CVOL,
2254#else
2255 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2256#endif
2257},
2258#ifdef CONFIG_SND_CS46XX_NEW_DSP
2259{
2260 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2261 .name = "ADC Capture Switch",
2262 .info = snd_mixer_boolean_info,
2263 .get = snd_cs46xx_adc_capture_get,
2264 .put = snd_cs46xx_adc_capture_put
2265},
2266{
2267 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2268 .name = "DAC Capture Switch",
2269 .info = snd_mixer_boolean_info,
2270 .get = snd_cs46xx_pcm_capture_get,
2271 .put = snd_cs46xx_pcm_capture_put
2272},
2273{
2274 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2275 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2276 .info = snd_mixer_boolean_info,
2277 .get = snd_cs46xx_iec958_get,
2278 .put = snd_cs46xx_iec958_put,
2279 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2280},
2281{
2282 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2283 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2284 .info = snd_mixer_boolean_info,
2285 .get = snd_cs46xx_iec958_get,
2286 .put = snd_cs46xx_iec958_put,
2287 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2288},
2289#if 0
2290/* Input IEC958 volume does not work for the moment. (Benny) */
2291{
2292 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2293 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2294 .info = snd_cs46xx_vol_info,
2295 .get = snd_cs46xx_vol_iec958_get,
2296 .put = snd_cs46xx_vol_iec958_put,
2297 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2298},
2299#endif
2300{
2301 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2302 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2303 .info = snd_cs46xx_spdif_info,
2304 .get = snd_cs46xx_spdif_default_get,
2305 .put = snd_cs46xx_spdif_default_put,
2306},
2307{
2308 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2309 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2310 .info = snd_cs46xx_spdif_info,
2311 .get = snd_cs46xx_spdif_mask_get,
2312 .access = SNDRV_CTL_ELEM_ACCESS_READ
2313},
2314{
2315 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2316 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2317 .info = snd_cs46xx_spdif_info,
2318 .get = snd_cs46xx_spdif_stream_get,
2319 .put = snd_cs46xx_spdif_stream_put
2320},
2321
2322#endif
2323};
2324
2325#ifdef CONFIG_SND_CS46XX_NEW_DSP
2326/* set primary cs4294 codec into Extended Audio Mode */
2327static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2328 struct snd_ctl_elem_value *ucontrol)
2329{
2330 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2331 unsigned short val;
2332 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2333 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2334 return 0;
2335}
2336
2337static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2338 struct snd_ctl_elem_value *ucontrol)
2339{
2340 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2341 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2342 AC97_CSR_ACMODE, 0x200,
2343 ucontrol->value.integer.value[0] ? 0 : 0x200);
2344}
2345
2346static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2347 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2348 .name = "Duplicate Front",
2349 .info = snd_mixer_boolean_info,
2350 .get = snd_cs46xx_front_dup_get,
2351 .put = snd_cs46xx_front_dup_put,
2352};
2353#endif
2354
2355#ifdef CONFIG_SND_CS46XX_NEW_DSP
2356/* Only available on the Hercules Game Theater XP soundcard */
2357static const struct snd_kcontrol_new snd_hercules_controls[] = {
2358{
2359 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2360 .name = "Optical/Coaxial SPDIF Input Switch",
2361 .info = snd_mixer_boolean_info,
2362 .get = snd_herc_spdif_select_get,
2363 .put = snd_herc_spdif_select_put,
2364},
2365};
2366
2367
2368static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2369{
2370 unsigned long end_time;
2371 int err;
2372
2373 /* reset to defaults */
2374 snd_ac97_write(ac97, AC97_RESET, 0);
2375
2376 /* set the desired CODEC mode */
2377 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2378 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0);
2379 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2380 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2381 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3);
2382 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2383 } else {
2384 snd_BUG(); /* should never happen ... */
2385 }
2386
2387 udelay(50);
2388
2389 /* it's necessary to wait awhile until registers are accessible after RESET */
2390 /* because the PCM or MASTER volume registers can be modified, */
2391 /* the REC_GAIN register is used for tests */
2392 end_time = jiffies + HZ;
2393 do {
2394 unsigned short ext_mid;
2395
2396 /* use preliminary reads to settle the communication */
2397 snd_ac97_read(ac97, AC97_RESET);
2398 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2399 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2400 /* modem? */
2401 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2402 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2403 return;
2404
2405 /* test if we can write to the record gain volume register */
2406 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2407 err = snd_ac97_read(ac97, AC97_REC_GAIN);
2408 if (err == 0x8a05)
2409 return;
2410
2411 msleep(10);
2412 } while (time_after_eq(end_time, jiffies));
2413
2414 dev_err(ac97->bus->card->dev,
2415 "CS46xx secondary codec doesn't respond!\n");
2416}
2417#endif
2418
2419static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2420{
2421 int idx, err;
2422 struct snd_ac97_template ac97;
2423
2424 memset(&ac97, 0, sizeof(ac97));
2425 ac97.private_data = chip;
2426 ac97.private_free = snd_cs46xx_mixer_free_ac97;
2427 ac97.num = codec;
2428 if (chip->amplifier_ctrl == amp_voyetra)
2429 ac97.scaps = AC97_SCAP_INV_EAPD;
2430
2431 if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2432 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2433 udelay(10);
2434 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2435 dev_dbg(chip->card->dev,
2436 "secondary codec not present\n");
2437 return -ENXIO;
2438 }
2439 }
2440
2441 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2442 for (idx = 0; idx < 100; ++idx) {
2443 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2444 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2445 return err;
2446 }
2447 msleep(10);
2448 }
2449 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec);
2450 return -ENXIO;
2451}
2452
2453int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2454{
2455 struct snd_card *card = chip->card;
2456 int err;
2457 unsigned int idx;
2458 static const struct snd_ac97_bus_ops ops = {
2459#ifdef CONFIG_SND_CS46XX_NEW_DSP
2460 .reset = snd_cs46xx_codec_reset,
2461#endif
2462 .write = snd_cs46xx_ac97_write,
2463 .read = snd_cs46xx_ac97_read,
2464 };
2465
2466 /* detect primary codec */
2467 chip->nr_ac97_codecs = 0;
2468 dev_dbg(chip->card->dev, "detecting primary codec\n");
2469 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
2470 if (err < 0)
2471 return err;
2472
2473 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2474 return -ENXIO;
2475 chip->nr_ac97_codecs = 1;
2476
2477#ifdef CONFIG_SND_CS46XX_NEW_DSP
2478 dev_dbg(chip->card->dev, "detecting secondary codec\n");
2479 /* try detect a secondary codec */
2480 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2481 chip->nr_ac97_codecs = 2;
2482#endif /* CONFIG_SND_CS46XX_NEW_DSP */
2483
2484 /* add cs4630 mixer controls */
2485 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2486 struct snd_kcontrol *kctl;
2487 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2488 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2489 kctl->id.device = spdif_device;
2490 err = snd_ctl_add(card, kctl);
2491 if (err < 0)
2492 return err;
2493 }
2494
2495 /* get EAPD mixer switch (for voyetra hack) */
2496 chip->eapd_switch = snd_ctl_find_id_mixer(chip->card,
2497 "External Amplifier");
2498
2499#ifdef CONFIG_SND_CS46XX_NEW_DSP
2500 if (chip->nr_ac97_codecs == 1) {
2501 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2502 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */
2503 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2504 if (err < 0)
2505 return err;
2506 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2507 AC97_CSR_ACMODE, 0x200);
2508 }
2509 }
2510 /* do soundcard specific mixer setup */
2511 if (chip->mixer_init) {
2512 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n");
2513 chip->mixer_init(chip);
2514 }
2515#endif
2516
2517 /* turn on amplifier */
2518 chip->amplifier_ctrl(chip, 1);
2519
2520 return 0;
2521}
2522
2523/*
2524 * RawMIDI interface
2525 */
2526
2527static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2528{
2529 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2530 udelay(100);
2531 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2532}
2533
2534static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2535{
2536 struct snd_cs46xx *chip = substream->rmidi->private_data;
2537
2538 chip->active_ctrl(chip, 1);
2539 spin_lock_irq(&chip->reg_lock);
2540 chip->uartm |= CS46XX_MODE_INPUT;
2541 chip->midcr |= MIDCR_RXE;
2542 chip->midi_input = substream;
2543 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2544 snd_cs46xx_midi_reset(chip);
2545 } else {
2546 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2547 }
2548 spin_unlock_irq(&chip->reg_lock);
2549 return 0;
2550}
2551
2552static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2553{
2554 struct snd_cs46xx *chip = substream->rmidi->private_data;
2555
2556 spin_lock_irq(&chip->reg_lock);
2557 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2558 chip->midi_input = NULL;
2559 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2560 snd_cs46xx_midi_reset(chip);
2561 } else {
2562 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2563 }
2564 chip->uartm &= ~CS46XX_MODE_INPUT;
2565 spin_unlock_irq(&chip->reg_lock);
2566 chip->active_ctrl(chip, -1);
2567 return 0;
2568}
2569
2570static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2571{
2572 struct snd_cs46xx *chip = substream->rmidi->private_data;
2573
2574 chip->active_ctrl(chip, 1);
2575
2576 spin_lock_irq(&chip->reg_lock);
2577 chip->uartm |= CS46XX_MODE_OUTPUT;
2578 chip->midcr |= MIDCR_TXE;
2579 chip->midi_output = substream;
2580 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2581 snd_cs46xx_midi_reset(chip);
2582 } else {
2583 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2584 }
2585 spin_unlock_irq(&chip->reg_lock);
2586 return 0;
2587}
2588
2589static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2590{
2591 struct snd_cs46xx *chip = substream->rmidi->private_data;
2592
2593 spin_lock_irq(&chip->reg_lock);
2594 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2595 chip->midi_output = NULL;
2596 if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2597 snd_cs46xx_midi_reset(chip);
2598 } else {
2599 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2600 }
2601 chip->uartm &= ~CS46XX_MODE_OUTPUT;
2602 spin_unlock_irq(&chip->reg_lock);
2603 chip->active_ctrl(chip, -1);
2604 return 0;
2605}
2606
2607static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2608{
2609 unsigned long flags;
2610 struct snd_cs46xx *chip = substream->rmidi->private_data;
2611
2612 spin_lock_irqsave(&chip->reg_lock, flags);
2613 if (up) {
2614 if ((chip->midcr & MIDCR_RIE) == 0) {
2615 chip->midcr |= MIDCR_RIE;
2616 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2617 }
2618 } else {
2619 if (chip->midcr & MIDCR_RIE) {
2620 chip->midcr &= ~MIDCR_RIE;
2621 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2622 }
2623 }
2624 spin_unlock_irqrestore(&chip->reg_lock, flags);
2625}
2626
2627static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2628{
2629 unsigned long flags;
2630 struct snd_cs46xx *chip = substream->rmidi->private_data;
2631 unsigned char byte;
2632
2633 spin_lock_irqsave(&chip->reg_lock, flags);
2634 if (up) {
2635 if ((chip->midcr & MIDCR_TIE) == 0) {
2636 chip->midcr |= MIDCR_TIE;
2637 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2638 while ((chip->midcr & MIDCR_TIE) &&
2639 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2640 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2641 chip->midcr &= ~MIDCR_TIE;
2642 } else {
2643 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2644 }
2645 }
2646 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2647 }
2648 } else {
2649 if (chip->midcr & MIDCR_TIE) {
2650 chip->midcr &= ~MIDCR_TIE;
2651 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2652 }
2653 }
2654 spin_unlock_irqrestore(&chip->reg_lock, flags);
2655}
2656
2657static const struct snd_rawmidi_ops snd_cs46xx_midi_output =
2658{
2659 .open = snd_cs46xx_midi_output_open,
2660 .close = snd_cs46xx_midi_output_close,
2661 .trigger = snd_cs46xx_midi_output_trigger,
2662};
2663
2664static const struct snd_rawmidi_ops snd_cs46xx_midi_input =
2665{
2666 .open = snd_cs46xx_midi_input_open,
2667 .close = snd_cs46xx_midi_input_close,
2668 .trigger = snd_cs46xx_midi_input_trigger,
2669};
2670
2671int snd_cs46xx_midi(struct snd_cs46xx *chip, int device)
2672{
2673 struct snd_rawmidi *rmidi;
2674 int err;
2675
2676 err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi);
2677 if (err < 0)
2678 return err;
2679 strcpy(rmidi->name, "CS46XX");
2680 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2681 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2682 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2683 rmidi->private_data = chip;
2684 chip->rmidi = rmidi;
2685 return 0;
2686}
2687
2688
2689/*
2690 * gameport interface
2691 */
2692
2693#if IS_REACHABLE(CONFIG_GAMEPORT)
2694
2695static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2696{
2697 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2698
2699 if (snd_BUG_ON(!chip))
2700 return;
2701 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
2702}
2703
2704static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2705{
2706 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2707
2708 if (snd_BUG_ON(!chip))
2709 return 0;
2710 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2711}
2712
2713static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2714{
2715 struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2716 unsigned js1, js2, jst;
2717
2718 if (snd_BUG_ON(!chip))
2719 return 0;
2720
2721 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2722 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2723 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2724
2725 *buttons = (~jst >> 4) & 0x0F;
2726
2727 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2728 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2729 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2730 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2731
2732 for(jst=0;jst<4;++jst)
2733 if(axes[jst]==0xFFFF) axes[jst] = -1;
2734 return 0;
2735}
2736
2737static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2738{
2739 switch (mode) {
2740 case GAMEPORT_MODE_COOKED:
2741 return 0;
2742 case GAMEPORT_MODE_RAW:
2743 return 0;
2744 default:
2745 return -1;
2746 }
2747 return 0;
2748}
2749
2750int snd_cs46xx_gameport(struct snd_cs46xx *chip)
2751{
2752 struct gameport *gp;
2753
2754 chip->gameport = gp = gameport_allocate_port();
2755 if (!gp) {
2756 dev_err(chip->card->dev,
2757 "cannot allocate memory for gameport\n");
2758 return -ENOMEM;
2759 }
2760
2761 gameport_set_name(gp, "CS46xx Gameport");
2762 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2763 gameport_set_dev_parent(gp, &chip->pci->dev);
2764 gameport_set_port_data(gp, chip);
2765
2766 gp->open = snd_cs46xx_gameport_open;
2767 gp->read = snd_cs46xx_gameport_read;
2768 gp->trigger = snd_cs46xx_gameport_trigger;
2769 gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2770
2771 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2772 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2773
2774 gameport_register_port(gp);
2775
2776 return 0;
2777}
2778
2779static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2780{
2781 if (chip->gameport) {
2782 gameport_unregister_port(chip->gameport);
2783 chip->gameport = NULL;
2784 }
2785}
2786#else
2787int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2788static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2789#endif /* CONFIG_GAMEPORT */
2790
2791#ifdef CONFIG_SND_PROC_FS
2792/*
2793 * proc interface
2794 */
2795
2796static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2797 void *file_private_data,
2798 struct file *file, char __user *buf,
2799 size_t count, loff_t pos)
2800{
2801 struct snd_cs46xx_region *region = entry->private_data;
2802
2803 if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2804 return -EFAULT;
2805 return count;
2806}
2807
2808static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2809 .read = snd_cs46xx_io_read,
2810};
2811
2812static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2813{
2814 struct snd_info_entry *entry;
2815 int idx;
2816
2817 for (idx = 0; idx < 5; idx++) {
2818 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2819 if (! snd_card_proc_new(card, region->name, &entry)) {
2820 entry->content = SNDRV_INFO_CONTENT_DATA;
2821 entry->private_data = chip;
2822 entry->c.ops = &snd_cs46xx_proc_io_ops;
2823 entry->size = region->size;
2824 entry->mode = S_IFREG | 0400;
2825 }
2826 }
2827#ifdef CONFIG_SND_CS46XX_NEW_DSP
2828 cs46xx_dsp_proc_init(card, chip);
2829#endif
2830 return 0;
2831}
2832
2833static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2834{
2835#ifdef CONFIG_SND_CS46XX_NEW_DSP
2836 cs46xx_dsp_proc_done(chip);
2837#endif
2838 return 0;
2839}
2840#else /* !CONFIG_SND_PROC_FS */
2841#define snd_cs46xx_proc_init(card, chip)
2842#define snd_cs46xx_proc_done(chip)
2843#endif
2844
2845/*
2846 * stop the h/w
2847 */
2848static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2849{
2850 unsigned int tmp;
2851
2852 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2853 tmp &= ~0x0000f03f;
2854 tmp |= 0x00000010;
2855 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
2856
2857 tmp = snd_cs46xx_peek(chip, BA1_CIE);
2858 tmp &= ~0x0000003f;
2859 tmp |= 0x00000011;
2860 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
2861
2862 /*
2863 * Stop playback DMA.
2864 */
2865 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2866 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2867
2868 /*
2869 * Stop capture DMA.
2870 */
2871 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2872 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2873
2874 /*
2875 * Reset the processor.
2876 */
2877 snd_cs46xx_reset(chip);
2878
2879 snd_cs46xx_proc_stop(chip);
2880
2881 /*
2882 * Power down the PLL.
2883 */
2884 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2885
2886 /*
2887 * Turn off the Processor by turning off the software clock enable flag in
2888 * the clock control register.
2889 */
2890 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2891 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2892}
2893
2894
2895static void snd_cs46xx_free(struct snd_card *card)
2896{
2897 struct snd_cs46xx *chip = card->private_data;
2898#ifdef CONFIG_SND_CS46XX_NEW_DSP
2899 int idx;
2900#endif
2901
2902 if (chip->active_ctrl)
2903 chip->active_ctrl(chip, 1);
2904
2905 snd_cs46xx_remove_gameport(chip);
2906
2907 if (chip->amplifier_ctrl)
2908 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2909
2910 snd_cs46xx_proc_done(chip);
2911
2912 snd_cs46xx_hw_stop(chip);
2913
2914 if (chip->active_ctrl)
2915 chip->active_ctrl(chip, -chip->amplifier);
2916
2917#ifdef CONFIG_SND_CS46XX_NEW_DSP
2918 if (chip->dsp_spos_instance) {
2919 cs46xx_dsp_spos_destroy(chip);
2920 chip->dsp_spos_instance = NULL;
2921 }
2922 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++)
2923 free_module_desc(chip->modules[idx]);
2924#else
2925 vfree(chip->ba1);
2926#endif
2927}
2928
2929/*
2930 * initialize chip
2931 */
2932static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2933{
2934 int timeout;
2935
2936 /*
2937 * First, blast the clock control register to zero so that the PLL starts
2938 * out in a known state, and blast the master serial port control register
2939 * to zero so that the serial ports also start out in a known state.
2940 */
2941 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2942 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2943
2944 /*
2945 * If we are in AC97 mode, then we must set the part to a host controlled
2946 * AC-link. Otherwise, we won't be able to bring up the link.
2947 */
2948#ifdef CONFIG_SND_CS46XX_NEW_DSP
2949 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2950 SERACC_TWO_CODECS); /* 2.00 dual codecs */
2951 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2952#else
2953 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2954#endif
2955
2956 /*
2957 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2958 * spec) and then drive it high. This is done for non AC97 modes since
2959 * there might be logic external to the CS461x that uses the ARST# line
2960 * for a reset.
2961 */
2962 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2963#ifdef CONFIG_SND_CS46XX_NEW_DSP
2964 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2965#endif
2966 udelay(50);
2967 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2968#ifdef CONFIG_SND_CS46XX_NEW_DSP
2969 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2970#endif
2971
2972 /*
2973 * The first thing we do here is to enable sync generation. As soon
2974 * as we start receiving bit clock, we'll start producing the SYNC
2975 * signal.
2976 */
2977 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2978#ifdef CONFIG_SND_CS46XX_NEW_DSP
2979 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2980#endif
2981
2982 /*
2983 * Now wait for a short while to allow the AC97 part to start
2984 * generating bit clock (so we don't try to start the PLL without an
2985 * input clock).
2986 */
2987 mdelay(10);
2988
2989 /*
2990 * Set the serial port timing configuration, so that
2991 * the clock control circuit gets its clock from the correct place.
2992 */
2993 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2994
2995 /*
2996 * Write the selected clock control setup to the hardware. Do not turn on
2997 * SWCE yet (if requested), so that the devices clocked by the output of
2998 * PLL are not clocked until the PLL is stable.
2999 */
3000 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
3001 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
3002 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
3003
3004 /*
3005 * Power up the PLL.
3006 */
3007 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
3008
3009 /*
3010 * Wait until the PLL has stabilized.
3011 */
3012 msleep(100);
3013
3014 /*
3015 * Turn on clocking of the core so that we can setup the serial ports.
3016 */
3017 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
3018
3019 /*
3020 * Enable FIFO Host Bypass
3021 */
3022 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3023
3024 /*
3025 * Fill the serial port FIFOs with silence.
3026 */
3027 snd_cs46xx_clear_serial_FIFOs(chip);
3028
3029 /*
3030 * Set the serial port FIFO pointer to the first sample in the FIFO.
3031 */
3032 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3033
3034 /*
3035 * Write the serial port configuration to the part. The master
3036 * enable bit is not set until all other values have been written.
3037 */
3038 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3039 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3040 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3041
3042
3043#ifdef CONFIG_SND_CS46XX_NEW_DSP
3044 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3045 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3046 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3047 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3048 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3049#endif
3050
3051 mdelay(5);
3052
3053
3054 /*
3055 * Wait for the codec ready signal from the AC97 codec.
3056 */
3057 timeout = 150;
3058 while (timeout-- > 0) {
3059 /*
3060 * Read the AC97 status register to see if we've seen a CODEC READY
3061 * signal from the AC97 codec.
3062 */
3063 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3064 goto ok1;
3065 msleep(10);
3066 }
3067
3068
3069 dev_err(chip->card->dev,
3070 "create - never read codec ready from AC'97\n");
3071 dev_err(chip->card->dev,
3072 "it is not probably bug, try to use CS4236 driver\n");
3073 return -EIO;
3074 ok1:
3075#ifdef CONFIG_SND_CS46XX_NEW_DSP
3076 {
3077 int count;
3078 for (count = 0; count < 150; count++) {
3079 /* First, we want to wait for a short time. */
3080 udelay(25);
3081
3082 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3083 break;
3084 }
3085
3086 /*
3087 * Make sure CODEC is READY.
3088 */
3089 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3090 dev_dbg(chip->card->dev,
3091 "never read card ready from secondary AC'97\n");
3092 }
3093#endif
3094
3095 /*
3096 * Assert the vaid frame signal so that we can start sending commands
3097 * to the AC97 codec.
3098 */
3099 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3100#ifdef CONFIG_SND_CS46XX_NEW_DSP
3101 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3102#endif
3103
3104
3105 /*
3106 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3107 * the codec is pumping ADC data across the AC-link.
3108 */
3109 timeout = 150;
3110 while (timeout-- > 0) {
3111 /*
3112 * Read the input slot valid register and see if input slots 3 and
3113 * 4 are valid yet.
3114 */
3115 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3116 goto ok2;
3117 msleep(10);
3118 }
3119
3120#ifndef CONFIG_SND_CS46XX_NEW_DSP
3121 dev_err(chip->card->dev,
3122 "create - never read ISV3 & ISV4 from AC'97\n");
3123 return -EIO;
3124#else
3125 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3126 Reloading the driver may help, if there's other soundcards
3127 with the same problem I would like to know. (Benny) */
3128
3129 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n");
3130 dev_err(chip->card->dev,
3131 "Try reloading the ALSA driver, if you find something\n");
3132 dev_err(chip->card->dev,
3133 "broken or not working on your soundcard upon\n");
3134 dev_err(chip->card->dev,
3135 "this message please report to alsa-devel@alsa-project.org\n");
3136
3137 return -EIO;
3138#endif
3139 ok2:
3140
3141 /*
3142 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3143 * commense the transfer of digital audio data to the AC97 codec.
3144 */
3145
3146 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3147
3148
3149 /*
3150 * Power down the DAC and ADC. We will power them up (if) when we need
3151 * them.
3152 */
3153 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3154
3155 /*
3156 * Turn off the Processor by turning off the software clock enable flag in
3157 * the clock control register.
3158 */
3159 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3160 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3161
3162 return 0;
3163}
3164
3165/*
3166 * start and load DSP
3167 */
3168
3169static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3170{
3171 unsigned int tmp;
3172
3173 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3174
3175 tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3176 tmp &= ~0x0000f03f;
3177 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
3178
3179 tmp = snd_cs46xx_peek(chip, BA1_CIE);
3180 tmp &= ~0x0000003f;
3181 tmp |= 0x00000001;
3182 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
3183}
3184
3185int snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3186{
3187 unsigned int tmp;
3188#ifdef CONFIG_SND_CS46XX_NEW_DSP
3189 int i;
3190#endif
3191 int err;
3192
3193 /*
3194 * Reset the processor.
3195 */
3196 snd_cs46xx_reset(chip);
3197 /*
3198 * Download the image to the processor.
3199 */
3200#ifdef CONFIG_SND_CS46XX_NEW_DSP
3201 for (i = 0; i < CS46XX_DSP_MODULES; i++) {
3202 err = load_firmware(chip, &chip->modules[i], module_names[i]);
3203 if (err < 0) {
3204 dev_err(chip->card->dev, "firmware load error [%s]\n",
3205 module_names[i]);
3206 return err;
3207 }
3208 err = cs46xx_dsp_load_module(chip, chip->modules[i]);
3209 if (err < 0) {
3210 dev_err(chip->card->dev, "image download error [%s]\n",
3211 module_names[i]);
3212 return err;
3213 }
3214 }
3215
3216 if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3217 return -EIO;
3218#else
3219 err = load_firmware(chip);
3220 if (err < 0)
3221 return err;
3222
3223 /* old image */
3224 err = snd_cs46xx_download_image(chip);
3225 if (err < 0) {
3226 dev_err(chip->card->dev, "image download error\n");
3227 return err;
3228 }
3229
3230 /*
3231 * Stop playback DMA.
3232 */
3233 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3234 chip->play_ctl = tmp & 0xffff0000;
3235 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3236#endif
3237
3238 /*
3239 * Stop capture DMA.
3240 */
3241 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3242 chip->capt.ctl = tmp & 0x0000ffff;
3243 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3244
3245 mdelay(5);
3246
3247 snd_cs46xx_set_play_sample_rate(chip, 8000);
3248 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3249
3250 snd_cs46xx_proc_start(chip);
3251
3252 cs46xx_enable_stream_irqs(chip);
3253
3254#ifndef CONFIG_SND_CS46XX_NEW_DSP
3255 /* set the attenuation to 0dB */
3256 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3257 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3258#endif
3259
3260 return 0;
3261}
3262
3263
3264/*
3265 * AMP control - null AMP
3266 */
3267
3268static void amp_none(struct snd_cs46xx *chip, int change)
3269{
3270}
3271
3272#ifdef CONFIG_SND_CS46XX_NEW_DSP
3273static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3274{
3275
3276 u32 idx, valid_slots,tmp,powerdown = 0;
3277 u16 modem_power,pin_config,logic_type;
3278
3279 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n");
3280
3281 /*
3282 * See if the devices are powered down. If so, we must power them up first
3283 * or they will not respond.
3284 */
3285 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3286
3287 if (!(tmp & CLKCR1_SWCE)) {
3288 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3289 powerdown = 1;
3290 }
3291
3292 /*
3293 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3294 * stuff.
3295 */
3296 if(chip->nr_ac97_codecs != 2) {
3297 dev_err(chip->card->dev,
3298 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3299 return -EINVAL;
3300 }
3301
3302 modem_power = snd_cs46xx_codec_read (chip,
3303 AC97_EXTENDED_MSTATUS,
3304 CS46XX_SECONDARY_CODEC_INDEX);
3305 modem_power &=0xFEFF;
3306
3307 snd_cs46xx_codec_write(chip,
3308 AC97_EXTENDED_MSTATUS, modem_power,
3309 CS46XX_SECONDARY_CODEC_INDEX);
3310
3311 /*
3312 * Set GPIO pin's 7 and 8 so that they are configured for output.
3313 */
3314 pin_config = snd_cs46xx_codec_read (chip,
3315 AC97_GPIO_CFG,
3316 CS46XX_SECONDARY_CODEC_INDEX);
3317 pin_config &=0x27F;
3318
3319 snd_cs46xx_codec_write(chip,
3320 AC97_GPIO_CFG, pin_config,
3321 CS46XX_SECONDARY_CODEC_INDEX);
3322
3323 /*
3324 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3325 */
3326
3327 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3328 CS46XX_SECONDARY_CODEC_INDEX);
3329 logic_type &=0x27F;
3330
3331 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3332 CS46XX_SECONDARY_CODEC_INDEX);
3333
3334 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3335 valid_slots |= 0x200;
3336 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3337
3338 if ( cs46xx_wait_for_fifo(chip,1) ) {
3339 dev_dbg(chip->card->dev, "FIFO is busy\n");
3340
3341 return -EINVAL;
3342 }
3343
3344 /*
3345 * Fill slots 12 with the correct value for the GPIO pins.
3346 */
3347 for(idx = 0x90; idx <= 0x9F; idx++) {
3348 /*
3349 * Initialize the fifo so that bits 7 and 8 are on.
3350 *
3351 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3352 * the left. 0x1800 corresponds to bits 7 and 8.
3353 */
3354 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3355
3356 /*
3357 * Wait for command to complete
3358 */
3359 if ( cs46xx_wait_for_fifo(chip,200) ) {
3360 dev_dbg(chip->card->dev,
3361 "failed waiting for FIFO at addr (%02X)\n",
3362 idx);
3363
3364 return -EINVAL;
3365 }
3366
3367 /*
3368 * Write the serial port FIFO index.
3369 */
3370 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3371
3372 /*
3373 * Tell the serial port to load the new value into the FIFO location.
3374 */
3375 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3376 }
3377
3378 /* wait for last command to complete */
3379 cs46xx_wait_for_fifo(chip,200);
3380
3381 /*
3382 * Now, if we powered up the devices, then power them back down again.
3383 * This is kinda ugly, but should never happen.
3384 */
3385 if (powerdown)
3386 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3387
3388 return 0;
3389}
3390#endif
3391
3392/*
3393 * Crystal EAPD mode
3394 */
3395
3396static void amp_voyetra(struct snd_cs46xx *chip, int change)
3397{
3398 /* Manage the EAPD bit on the Crystal 4297
3399 and the Analog AD1885 */
3400
3401#ifdef CONFIG_SND_CS46XX_NEW_DSP
3402 int old = chip->amplifier;
3403#endif
3404 int oval, val;
3405
3406 chip->amplifier += change;
3407 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3408 CS46XX_PRIMARY_CODEC_INDEX);
3409 val = oval;
3410 if (chip->amplifier) {
3411 /* Turn the EAPD amp on */
3412 val |= 0x8000;
3413 } else {
3414 /* Turn the EAPD amp off */
3415 val &= ~0x8000;
3416 }
3417 if (val != oval) {
3418 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3419 CS46XX_PRIMARY_CODEC_INDEX);
3420 if (chip->eapd_switch)
3421 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3422 &chip->eapd_switch->id);
3423 }
3424
3425#ifdef CONFIG_SND_CS46XX_NEW_DSP
3426 if (chip->amplifier && !old) {
3427 voyetra_setup_eapd_slot(chip);
3428 }
3429#endif
3430}
3431
3432static void hercules_init(struct snd_cs46xx *chip)
3433{
3434 /* default: AMP off, and SPDIF input optical */
3435 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3436 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3437}
3438
3439
3440/*
3441 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3442 */
3443static void amp_hercules(struct snd_cs46xx *chip, int change)
3444{
3445 int old = chip->amplifier;
3446 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3447 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3448
3449 chip->amplifier += change;
3450 if (chip->amplifier && !old) {
3451 dev_dbg(chip->card->dev, "Hercules amplifier ON\n");
3452
3453 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3454 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
3455 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3456 EGPIOPTR_GPPT2 | val2); /* open-drain on output */
3457 } else if (old && !chip->amplifier) {
3458 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n");
3459 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
3460 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3461 }
3462}
3463
3464static void voyetra_mixer_init (struct snd_cs46xx *chip)
3465{
3466 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n");
3467
3468 /* Enable SPDIF out */
3469 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3470 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3471}
3472
3473static void hercules_mixer_init (struct snd_cs46xx *chip)
3474{
3475#ifdef CONFIG_SND_CS46XX_NEW_DSP
3476 unsigned int idx;
3477 int err;
3478 struct snd_card *card = chip->card;
3479#endif
3480
3481 /* set EGPIO to default */
3482 hercules_init(chip);
3483
3484 dev_dbg(chip->card->dev, "initializing Hercules mixer\n");
3485
3486#ifdef CONFIG_SND_CS46XX_NEW_DSP
3487 if (chip->in_suspend)
3488 return;
3489
3490 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3491 struct snd_kcontrol *kctl;
3492
3493 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3494 err = snd_ctl_add(card, kctl);
3495 if (err < 0) {
3496 dev_err(card->dev,
3497 "failed to initialize Hercules mixer (%d)\n",
3498 err);
3499 break;
3500 }
3501 }
3502#endif
3503}
3504
3505
3506#if 0
3507/*
3508 * Untested
3509 */
3510
3511static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3512{
3513 chip->amplifier += change;
3514
3515 if (chip->amplifier) {
3516 /* Switch the GPIO pins 7 and 8 to open drain */
3517 snd_cs46xx_codec_write(chip, 0x4C,
3518 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3519 snd_cs46xx_codec_write(chip, 0x4E,
3520 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3521 /* Now wake the AMP (this might be backwards) */
3522 snd_cs46xx_codec_write(chip, 0x54,
3523 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3524 } else {
3525 snd_cs46xx_codec_write(chip, 0x54,
3526 snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3527 }
3528}
3529#endif
3530
3531
3532/*
3533 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3534 * whenever we need to beat on the chip.
3535 *
3536 * The original idea and code for this hack comes from David Kaiser at
3537 * Linuxcare. Perhaps one day Crystal will document their chips well
3538 * enough to make them useful.
3539 */
3540
3541static void clkrun_hack(struct snd_cs46xx *chip, int change)
3542{
3543 u16 control, nval;
3544
3545 if (!chip->acpi_port)
3546 return;
3547
3548 chip->amplifier += change;
3549
3550 /* Read ACPI port */
3551 nval = control = inw(chip->acpi_port + 0x10);
3552
3553 /* Flip CLKRUN off while running */
3554 if (! chip->amplifier)
3555 nval |= 0x2000;
3556 else
3557 nval &= ~0x2000;
3558 if (nval != control)
3559 outw(nval, chip->acpi_port + 0x10);
3560}
3561
3562
3563/*
3564 * detect intel piix4
3565 */
3566static void clkrun_init(struct snd_cs46xx *chip)
3567{
3568 struct pci_dev *pdev;
3569 u8 pp;
3570
3571 chip->acpi_port = 0;
3572
3573 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3574 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3575 if (pdev == NULL)
3576 return; /* Not a thinkpad thats for sure */
3577
3578 /* Find the control port */
3579 pci_read_config_byte(pdev, 0x41, &pp);
3580 chip->acpi_port = pp << 8;
3581 pci_dev_put(pdev);
3582}
3583
3584
3585/*
3586 * Card subid table
3587 */
3588
3589struct cs_card_type
3590{
3591 u16 vendor;
3592 u16 id;
3593 char *name;
3594 void (*init)(struct snd_cs46xx *);
3595 void (*amp)(struct snd_cs46xx *, int);
3596 void (*active)(struct snd_cs46xx *, int);
3597 void (*mixer_init)(struct snd_cs46xx *);
3598};
3599
3600static struct cs_card_type cards[] = {
3601 {
3602 .vendor = 0x1489,
3603 .id = 0x7001,
3604 .name = "Genius Soundmaker 128 value",
3605 /* nothing special */
3606 },
3607 {
3608 .vendor = 0x5053,
3609 .id = 0x3357,
3610 .name = "Voyetra",
3611 .amp = amp_voyetra,
3612 .mixer_init = voyetra_mixer_init,
3613 },
3614 {
3615 .vendor = 0x1071,
3616 .id = 0x6003,
3617 .name = "Mitac MI6020/21",
3618 .amp = amp_voyetra,
3619 },
3620 /* Hercules Game Theatre XP */
3621 {
3622 .vendor = 0x14af, /* Guillemot Corporation */
3623 .id = 0x0050,
3624 .name = "Hercules Game Theatre XP",
3625 .amp = amp_hercules,
3626 .mixer_init = hercules_mixer_init,
3627 },
3628 {
3629 .vendor = 0x1681,
3630 .id = 0x0050,
3631 .name = "Hercules Game Theatre XP",
3632 .amp = amp_hercules,
3633 .mixer_init = hercules_mixer_init,
3634 },
3635 {
3636 .vendor = 0x1681,
3637 .id = 0x0051,
3638 .name = "Hercules Game Theatre XP",
3639 .amp = amp_hercules,
3640 .mixer_init = hercules_mixer_init,
3641
3642 },
3643 {
3644 .vendor = 0x1681,
3645 .id = 0x0052,
3646 .name = "Hercules Game Theatre XP",
3647 .amp = amp_hercules,
3648 .mixer_init = hercules_mixer_init,
3649 },
3650 {
3651 .vendor = 0x1681,
3652 .id = 0x0053,
3653 .name = "Hercules Game Theatre XP",
3654 .amp = amp_hercules,
3655 .mixer_init = hercules_mixer_init,
3656 },
3657 {
3658 .vendor = 0x1681,
3659 .id = 0x0054,
3660 .name = "Hercules Game Theatre XP",
3661 .amp = amp_hercules,
3662 .mixer_init = hercules_mixer_init,
3663 },
3664 /* Herculess Fortissimo */
3665 {
3666 .vendor = 0x1681,
3667 .id = 0xa010,
3668 .name = "Hercules Gamesurround Fortissimo II",
3669 },
3670 {
3671 .vendor = 0x1681,
3672 .id = 0xa011,
3673 .name = "Hercules Gamesurround Fortissimo III 7.1",
3674 },
3675 /* Teratec */
3676 {
3677 .vendor = 0x153b,
3678 .id = 0x112e,
3679 .name = "Terratec DMX XFire 1024",
3680 },
3681 {
3682 .vendor = 0x153b,
3683 .id = 0x1136,
3684 .name = "Terratec SiXPack 5.1",
3685 },
3686 /* Not sure if the 570 needs the clkrun hack */
3687 {
3688 .vendor = PCI_VENDOR_ID_IBM,
3689 .id = 0x0132,
3690 .name = "Thinkpad 570",
3691 .init = clkrun_init,
3692 .active = clkrun_hack,
3693 },
3694 {
3695 .vendor = PCI_VENDOR_ID_IBM,
3696 .id = 0x0153,
3697 .name = "Thinkpad 600X/A20/T20",
3698 .init = clkrun_init,
3699 .active = clkrun_hack,
3700 },
3701 {
3702 .vendor = PCI_VENDOR_ID_IBM,
3703 .id = 0x1010,
3704 .name = "Thinkpad 600E (unsupported)",
3705 },
3706 {0} /* terminator */
3707};
3708
3709
3710/*
3711 * APM support
3712 */
3713#ifdef CONFIG_PM_SLEEP
3714static const unsigned int saved_regs[] = {
3715 BA0_ACOSV,
3716 /*BA0_ASER_FADDR,*/
3717 BA0_ASER_MASTER,
3718 BA1_PVOL,
3719 BA1_CVOL,
3720};
3721
3722static int snd_cs46xx_suspend(struct device *dev)
3723{
3724 struct snd_card *card = dev_get_drvdata(dev);
3725 struct snd_cs46xx *chip = card->private_data;
3726 int i, amp_saved;
3727
3728 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3729 chip->in_suspend = 1;
3730 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3731 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3732
3733 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3734 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3735
3736 /* save some registers */
3737 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3738 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3739
3740 amp_saved = chip->amplifier;
3741 /* turn off amp */
3742 chip->amplifier_ctrl(chip, -chip->amplifier);
3743 snd_cs46xx_hw_stop(chip);
3744 /* disable CLKRUN */
3745 chip->active_ctrl(chip, -chip->amplifier);
3746 chip->amplifier = amp_saved; /* restore the status */
3747 return 0;
3748}
3749
3750static int snd_cs46xx_resume(struct device *dev)
3751{
3752 struct snd_card *card = dev_get_drvdata(dev);
3753 struct snd_cs46xx *chip = card->private_data;
3754 int amp_saved;
3755#ifdef CONFIG_SND_CS46XX_NEW_DSP
3756 int i;
3757#endif
3758 unsigned int tmp;
3759
3760 amp_saved = chip->amplifier;
3761 chip->amplifier = 0;
3762 chip->active_ctrl(chip, 1); /* force to on */
3763
3764 snd_cs46xx_chip_init(chip);
3765
3766 snd_cs46xx_reset(chip);
3767#ifdef CONFIG_SND_CS46XX_NEW_DSP
3768 cs46xx_dsp_resume(chip);
3769 /* restore some registers */
3770 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3771 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3772#else
3773 snd_cs46xx_download_image(chip);
3774#endif
3775
3776#if 0
3777 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3778 chip->ac97_general_purpose);
3779 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3780 chip->ac97_powerdown);
3781 mdelay(10);
3782 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3783 chip->ac97_powerdown);
3784 mdelay(5);
3785#endif
3786
3787 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3788 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3789
3790 /*
3791 * Stop capture DMA.
3792 */
3793 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3794 chip->capt.ctl = tmp & 0x0000ffff;
3795 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3796
3797 mdelay(5);
3798
3799 /* reset playback/capture */
3800 snd_cs46xx_set_play_sample_rate(chip, 8000);
3801 snd_cs46xx_set_capture_sample_rate(chip, 8000);
3802 snd_cs46xx_proc_start(chip);
3803
3804 cs46xx_enable_stream_irqs(chip);
3805
3806 if (amp_saved)
3807 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3808 else
3809 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3810 chip->amplifier = amp_saved;
3811 chip->in_suspend = 0;
3812 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3813 return 0;
3814}
3815
3816SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3817#endif /* CONFIG_PM_SLEEP */
3818
3819
3820/*
3821 */
3822
3823int snd_cs46xx_create(struct snd_card *card,
3824 struct pci_dev *pci,
3825 int external_amp, int thinkpad)
3826{
3827 struct snd_cs46xx *chip = card->private_data;
3828 int err, idx;
3829 struct snd_cs46xx_region *region;
3830 struct cs_card_type *cp;
3831 u16 ss_card, ss_vendor;
3832
3833 /* enable PCI device */
3834 err = pcim_enable_device(pci);
3835 if (err < 0)
3836 return err;
3837
3838 spin_lock_init(&chip->reg_lock);
3839#ifdef CONFIG_SND_CS46XX_NEW_DSP
3840 mutex_init(&chip->spos_mutex);
3841#endif
3842 chip->card = card;
3843 chip->pci = pci;
3844 chip->irq = -1;
3845
3846 err = pci_request_regions(pci, "CS46xx");
3847 if (err < 0)
3848 return err;
3849 chip->ba0_addr = pci_resource_start(pci, 0);
3850 chip->ba1_addr = pci_resource_start(pci, 1);
3851 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3852 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3853 dev_err(chip->card->dev,
3854 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3855 chip->ba0_addr, chip->ba1_addr);
3856 return -ENOMEM;
3857 }
3858
3859 region = &chip->region.name.ba0;
3860 strcpy(region->name, "CS46xx_BA0");
3861 region->base = chip->ba0_addr;
3862 region->size = CS46XX_BA0_SIZE;
3863
3864 region = &chip->region.name.data0;
3865 strcpy(region->name, "CS46xx_BA1_data0");
3866 region->base = chip->ba1_addr + BA1_SP_DMEM0;
3867 region->size = CS46XX_BA1_DATA0_SIZE;
3868
3869 region = &chip->region.name.data1;
3870 strcpy(region->name, "CS46xx_BA1_data1");
3871 region->base = chip->ba1_addr + BA1_SP_DMEM1;
3872 region->size = CS46XX_BA1_DATA1_SIZE;
3873
3874 region = &chip->region.name.pmem;
3875 strcpy(region->name, "CS46xx_BA1_pmem");
3876 region->base = chip->ba1_addr + BA1_SP_PMEM;
3877 region->size = CS46XX_BA1_PRG_SIZE;
3878
3879 region = &chip->region.name.reg;
3880 strcpy(region->name, "CS46xx_BA1_reg");
3881 region->base = chip->ba1_addr + BA1_SP_REG;
3882 region->size = CS46XX_BA1_REG_SIZE;
3883
3884 /* set up amp and clkrun hack */
3885 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3886 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3887
3888 for (cp = &cards[0]; cp->name; cp++) {
3889 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3890 dev_dbg(chip->card->dev, "hack for %s enabled\n",
3891 cp->name);
3892
3893 chip->amplifier_ctrl = cp->amp;
3894 chip->active_ctrl = cp->active;
3895 chip->mixer_init = cp->mixer_init;
3896
3897 if (cp->init)
3898 cp->init(chip);
3899 break;
3900 }
3901 }
3902
3903 if (external_amp) {
3904 dev_info(chip->card->dev,
3905 "Crystal EAPD support forced on.\n");
3906 chip->amplifier_ctrl = amp_voyetra;
3907 }
3908
3909 if (thinkpad) {
3910 dev_info(chip->card->dev,
3911 "Activating CLKRUN hack for Thinkpad.\n");
3912 chip->active_ctrl = clkrun_hack;
3913 clkrun_init(chip);
3914 }
3915
3916 if (chip->amplifier_ctrl == NULL)
3917 chip->amplifier_ctrl = amp_none;
3918 if (chip->active_ctrl == NULL)
3919 chip->active_ctrl = amp_none;
3920
3921 chip->active_ctrl(chip, 1); /* enable CLKRUN */
3922
3923 pci_set_master(pci);
3924
3925 for (idx = 0; idx < 5; idx++) {
3926 region = &chip->region.idx[idx];
3927 region->remap_addr = devm_ioremap(&pci->dev, region->base,
3928 region->size);
3929 if (region->remap_addr == NULL) {
3930 dev_err(chip->card->dev,
3931 "%s ioremap problem\n", region->name);
3932 return -ENOMEM;
3933 }
3934 }
3935
3936 if (devm_request_irq(&pci->dev, pci->irq, snd_cs46xx_interrupt,
3937 IRQF_SHARED, KBUILD_MODNAME, chip)) {
3938 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq);
3939 return -EBUSY;
3940 }
3941 chip->irq = pci->irq;
3942 card->sync_irq = chip->irq;
3943 card->private_free = snd_cs46xx_free;
3944
3945#ifdef CONFIG_SND_CS46XX_NEW_DSP
3946 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3947 if (!chip->dsp_spos_instance)
3948 return -ENOMEM;
3949#endif
3950
3951 err = snd_cs46xx_chip_init(chip);
3952 if (err < 0)
3953 return err;
3954
3955 snd_cs46xx_proc_init(card, chip);
3956
3957#ifdef CONFIG_PM_SLEEP
3958 chip->saved_regs = devm_kmalloc_array(&pci->dev,
3959 ARRAY_SIZE(saved_regs),
3960 sizeof(*chip->saved_regs),
3961 GFP_KERNEL);
3962 if (!chip->saved_regs)
3963 return -ENOMEM;
3964#endif
3965
3966 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3967 return 0;
3968}
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