source: GPL/trunk/alsa-kernel/pci/cmipci.c@ 607

Last change on this file since 607 was 598, checked in by David Azarewicz, 9 years ago

Merged/reintegrated v2 branch into trunk. Trunk is now v2
File size: 105.7 KB
Line 
1/*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/* Does not work. Warning may block system in capture mode */
21/* #define USE_VAR48KRATE */
22
23#include <asm/io.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/gameport.h>
30#include <linux/moduleparam.h>
31#include <linux/mutex.h>
32#include <sound/core.h>
33#include <sound/info.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/rawmidi.h>
37#include <sound/mpu401.h>
38#include <sound/opl3.h>
39#include <sound/sb.h>
40#include <sound/asoundef.h>
41#include <sound/initval.h>
42
43MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45MODULE_LICENSE("GPL");
46MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52#define SUPPORT_JOYSTICK 1
53#endif
54
55static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58static long mpu_port[SNDRV_CARDS];
59#ifndef TARGET_OS2
60static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62#else
63static long fm_port[SNDRV_CARDS] = {0x388, -1,-1,-1,-1,-1,-1,-1};
64static int soft_ac3[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
65#endif
66#ifdef SUPPORT_JOYSTICK
67static int joystick_port[SNDRV_CARDS];
68#endif
69
70module_param_array(index, int, NULL, 0444);
71MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
72module_param_array(id, charp, NULL, 0444);
73MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
74module_param_array(enable, bool, NULL, 0444);
75MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
76module_param_array(mpu_port, long, NULL, 0444);
77MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
78module_param_array(fm_port, long, NULL, 0444);
79MODULE_PARM_DESC(fm_port, "FM port.");
80module_param_array(soft_ac3, bool, NULL, 0444);
81MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
82#ifdef SUPPORT_JOYSTICK
83module_param_array(joystick_port, int, NULL, 0444);
84MODULE_PARM_DESC(joystick_port, "Joystick port address.");
85#endif
86
87/*
88 * CM8x38 registers definition
89 */
90
91#define CM_REG_FUNCTRL0 0x00
92#define CM_RST_CH1 0x00080000
93#define CM_RST_CH0 0x00040000
94#define CM_CHEN1 0x00020000 /* ch1: enable */
95#define CM_CHEN0 0x00010000 /* ch0: enable */
96#define CM_PAUSE1 0x00000008 /* ch1: pause */
97#define CM_PAUSE0 0x00000004 /* ch0: pause */
98#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
99#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
100
101#define CM_REG_FUNCTRL1 0x04
102#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
103#define CM_DSFC_SHIFT 13
104#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
105#define CM_ASFC_SHIFT 10
106#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
107#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
108#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
109#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
110#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
111#define CM_BREQ 0x00000010 /* bus master enabled */
112#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
113#define CM_UART_EN 0x00000004 /* legacy UART */
114#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
115#define CM_ZVPORT 0x00000001 /* ZVPORT */
116
117#define CM_REG_CHFORMAT 0x08
118
119#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
120#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
121#define CM_CHB3D 0x20000000 /* 4 channels */
122
123#define CM_CHIP_MASK1 0x1f000000
124#define CM_CHIP_037 0x01000000
125#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
126#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
127#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
128#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
129#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
130#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
131/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
132
133#define CM_ADCBITLEN_MASK 0x0000C000
134#define CM_ADCBITLEN_16 0x00000000
135#define CM_ADCBITLEN_15 0x00004000
136#define CM_ADCBITLEN_14 0x00008000
137#define CM_ADCBITLEN_13 0x0000C000
138
139#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
140#define CM_ADCDACLEN_060 0x00000000
141#define CM_ADCDACLEN_066 0x00001000
142#define CM_ADCDACLEN_130 0x00002000
143#define CM_ADCDACLEN_280 0x00003000
144
145#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
146#define CM_ADCDLEN_ORIGINAL 0x00000000
147#define CM_ADCDLEN_EXTRA 0x00001000
148#define CM_ADCDLEN_24K 0x00002000
149#define CM_ADCDLEN_WEIGHT 0x00003000
150
151#define CM_CH1_SRATE_176K 0x00000800
152#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
153#define CM_CH1_SRATE_88K 0x00000400
154#define CM_CH0_SRATE_176K 0x00000200
155#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
156#define CM_CH0_SRATE_88K 0x00000100
157#define CM_CH0_SRATE_128K 0x00000300
158#define CM_CH0_SRATE_MASK 0x00000300
159
160#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
161#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
162#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
163#define CM_SPDLOCKED 0x00000010
164
165#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
166#define CM_CH1FMT_SHIFT 2
167#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
168#define CM_CH0FMT_SHIFT 0
169
170#define CM_REG_INT_HLDCLR 0x0C
171#define CM_CHIP_MASK2 0xff000000
172#define CM_CHIP_8768 0x20000000
173#define CM_CHIP_055 0x08000000
174#define CM_CHIP_039 0x04000000
175#define CM_CHIP_039_6CH 0x01000000
176#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
177#define CM_TDMA_INT_EN 0x00040000
178#define CM_CH1_INT_EN 0x00020000
179#define CM_CH0_INT_EN 0x00010000
180
181#define CM_REG_INT_STATUS 0x10
182#define CM_INTR 0x80000000
183#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
184#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
185#define CM_UARTINT 0x00010000
186#define CM_LTDMAINT 0x00008000
187#define CM_HTDMAINT 0x00004000
188#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
189#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
190#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
191#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
192#define CM_CH1BUSY 0x00000008
193#define CM_CH0BUSY 0x00000004
194#define CM_CHINT1 0x00000002
195#define CM_CHINT0 0x00000001
196
197#define CM_REG_LEGACY_CTRL 0x14
198#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
199#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
200#define CM_VMPU_330 0x00000000
201#define CM_VMPU_320 0x20000000
202#define CM_VMPU_310 0x40000000
203#define CM_VMPU_300 0x60000000
204#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
205#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
206#define CM_VSBSEL_220 0x00000000
207#define CM_VSBSEL_240 0x04000000
208#define CM_VSBSEL_260 0x08000000
209#define CM_VSBSEL_280 0x0C000000
210#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
211#define CM_FMSEL_388 0x00000000
212#define CM_FMSEL_3C8 0x01000000
213#define CM_FMSEL_3E0 0x02000000
214#define CM_FMSEL_3E8 0x03000000
215#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
216#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
217#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
218#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
219#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
220#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
221#define CM_C_EECS 0x00040000
222#define CM_C_EEDI46 0x00020000
223#define CM_C_EECK46 0x00010000
224#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
225#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
226#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
227#define CM_EXBASEN 0x00001000 /* external bass input enable */
228
229#define CM_REG_MISC_CTRL 0x18
230#define CM_PWD 0x80000000 /* power down */
231#define CM_RESET 0x40000000
232#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
233#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
234#define CM_TXVX 0x08000000 /* model 037? */
235#define CM_N4SPK3D 0x04000000 /* copy front to rear */
236#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
237#define CM_SPDIF48K 0x01000000 /* write */
238#define CM_SPATUS48K 0x01000000 /* read */
239#define CM_ENDBDAC 0x00800000 /* enable double dac */
240#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
241#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
242#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
243#define CM_FM_EN 0x00080000 /* enable legacy FM */
244#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
245#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
246#define CM_VIDWPDSB 0x00010000 /* model 037? */
247#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
248#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
249#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
250#define CM_VIDWPPRT 0x00002000 /* model 037? */
251#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
252#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
253#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
254#define CM_ENCENTER 0x00000080
255#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
256#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
257#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
258#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
259#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
260#define CM_UPDDMA_2048 0x00000000
261#define CM_UPDDMA_1024 0x00000004
262#define CM_UPDDMA_512 0x00000008
263#define CM_UPDDMA_256 0x0000000C
264#define CM_TWAIT_MASK 0x00000003 /* model 037 */
265#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
266#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
267
268#define CM_REG_TDMA_POSITION 0x1C
269#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
270#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
271
272 /* byte */
273#define CM_REG_MIXER0 0x20
274#define CM_REG_SBVR 0x20 /* write: sb16 version */
275#define CM_REG_DEV 0x20 /* read: hardware device version */
276
277#define CM_REG_MIXER21 0x21
278#define CM_UNKNOWN_21_MASK 0x78 /* ? */
279#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
280#define CM_PROINV 0x02 /* SBPro left/right channel switching */
281#define CM_X_SB16 0x01 /* SB16 compatible */
282
283#define CM_REG_SB16_DATA 0x22
284#define CM_REG_SB16_ADDR 0x23
285
286#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
287#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
288#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
289#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
290
291#define CM_REG_MIXER1 0x24
292#define CM_FMMUTE 0x80 /* mute FM */
293#define CM_FMMUTE_SHIFT 7
294#define CM_WSMUTE 0x40 /* mute PCM */
295#define CM_WSMUTE_SHIFT 6
296#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
297#define CM_REAR2LIN_SHIFT 5
298#define CM_REAR2FRONT 0x10 /* exchange rear/front */
299#define CM_REAR2FRONT_SHIFT 4
300#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
301#define CM_WAVEINL_SHIFT 3
302#define CM_WAVEINR 0x04 /* digical wave rec. right */
303#define CM_WAVEINR_SHIFT 2
304#define CM_X3DEN 0x02 /* 3D surround enable */
305#define CM_X3DEN_SHIFT 1
306#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
307#define CM_CDPLAY_SHIFT 0
308
309#define CM_REG_MIXER2 0x25
310#define CM_RAUXREN 0x80 /* AUX right capture */
311#define CM_RAUXREN_SHIFT 7
312#define CM_RAUXLEN 0x40 /* AUX left capture */
313#define CM_RAUXLEN_SHIFT 6
314#define CM_VAUXRM 0x20 /* AUX right mute */
315#define CM_VAUXRM_SHIFT 5
316#define CM_VAUXLM 0x10 /* AUX left mute */
317#define CM_VAUXLM_SHIFT 4
318#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
319#define CM_VADMIC_SHIFT 1
320#define CM_MICGAINZ 0x01 /* mic boost */
321#define CM_MICGAINZ_SHIFT 0
322
323#define CM_REG_MIXER3 0x24
324#define CM_REG_AUX_VOL 0x26
325#define CM_VAUXL_MASK 0xf0
326#define CM_VAUXR_MASK 0x0f
327
328#define CM_REG_MISC 0x27
329#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
330#define CM_XGPO1 0x20
331// #define CM_XGPBIO 0x04
332#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
333#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
334#define CM_SPDVALID 0x02 /* spdif input valid check */
335#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
336
337#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
338/*
339 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
340 * or identical with AC97 codec?
341 */
342#define CM_REG_EXTERN_CODEC CM_REG_AC97
343
344/*
345 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
346 */
347#define CM_REG_MPU_PCI 0x40
348
349/*
350 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
351 */
352#define CM_REG_FM_PCI 0x50
353
354/*
355 * access from SB-mixer port
356 */
357#define CM_REG_EXTENT_IND 0xf0
358#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
359#define CM_VPHONE_SHIFT 5
360#define CM_VPHOM 0x10 /* Phone mute control */
361#define CM_VSPKM 0x08 /* Speaker mute control, default high */
362#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
363#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
364#define CM_VADMIC3 0x01 /* Mic record boost */
365
366/*
367 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
368 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
369 * unit (readonly?).
370 */
371#define CM_REG_PLL 0xf8
372
373/*
374 * extended registers
375 */
376#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
377#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
378#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
379#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
380
381#define CM_REG_EXT_MISC 0x90
382#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
383#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
384#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
385#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
386#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
387#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
388#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
389#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
390
391/*
392 * size of i/o region
393 */
394#define CM_EXTENT_CODEC 0x100
395#define CM_EXTENT_MIDI 0x2
396#define CM_EXTENT_SYNTH 0x4
397
398
399/*
400 * channels for playback / capture
401 */
402#define CM_CH_PLAY 0
403#define CM_CH_CAPT 1
404
405/*
406 * flags to check device open/close
407 */
408#define CM_OPEN_NONE 0
409#define CM_OPEN_CH_MASK 0x01
410#define CM_OPEN_DAC 0x10
411#define CM_OPEN_ADC 0x20
412#define CM_OPEN_SPDIF 0x40
413#define CM_OPEN_MCHAN 0x80
414#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
415#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
416#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
417#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
418#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
419#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
420
421
422#if CM_CH_PLAY == 1
423#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
424#define CM_PLAYBACK_SPDF CM_SPDF_1
425#define CM_CAPTURE_SPDF CM_SPDF_0
426#else
427#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
428#define CM_PLAYBACK_SPDF CM_SPDF_0
429#define CM_CAPTURE_SPDF CM_SPDF_1
430#endif
431
432
433/*
434 * driver data
435 */
436
437struct cmipci_pcm {
438 struct snd_pcm_substream *substream;
439 u8 running; /* dac/adc running? */
440 u8 fmt; /* format bits */
441 u8 is_dac;
442 u8 needs_silencing;
443 unsigned int dma_size; /* in frames */
444 unsigned int shift;
445 unsigned int ch; /* channel (0/1) */
446 unsigned int offset; /* physical address of the buffer */
447};
448
449/* mixer elements toggled/resumed during ac3 playback */
450struct cmipci_mixer_auto_switches {
451 const char *name; /* switch to toggle */
452 int toggle_on; /* value to change when ac3 mode */
453};
454static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
455 {"PCM Playback Switch", 0},
456 {"IEC958 Output Switch", 1},
457 {"IEC958 Mix Analog", 0},
458 // {"IEC958 Out To DAC", 1}, // no longer used
459 {"IEC958 Loop", 0},
460};
461#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
462
463struct cmipci {
464 struct snd_card *card;
465
466 struct pci_dev *pci;
467 unsigned int device; /* device ID */
468 int irq;
469
470 unsigned long iobase;
471 unsigned int ctrl; /* FUNCTRL0 current value */
472
473 struct snd_pcm *pcm; /* DAC/ADC PCM */
474 struct snd_pcm *pcm2; /* 2nd DAC */
475 struct snd_pcm *pcm_spdif; /* SPDIF */
476
477 int chip_version;
478 int max_channels;
479 unsigned int can_ac3_sw: 1;
480 unsigned int can_ac3_hw: 1;
481 unsigned int can_multi_ch: 1;
482 unsigned int can_96k: 1; /* samplerate above 48k */
483 unsigned int do_soft_ac3: 1;
484
485 unsigned int spdif_playback_avail: 1; /* spdif ready? */
486 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
487 int spdif_counter; /* for software AC3 */
488
489 unsigned int dig_status;
490 unsigned int dig_pcm_status;
491
492 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
493
494 int opened[2]; /* open mode */
495 struct mutex open_mutex;
496
497 unsigned int mixer_insensitive: 1;
498 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
499 int mixer_res_status[CM_SAVED_MIXERS];
500
501 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
502
503 /* external MIDI */
504 struct snd_rawmidi *rmidi;
505
506#ifdef SUPPORT_JOYSTICK
507 struct gameport *gameport;
508#endif
509
510 spinlock_t reg_lock;
511
512#ifdef CONFIG_PM
513 unsigned int saved_regs[0x20];
514 unsigned char saved_mixers[0x20];
515#endif
516};
517
518
519/* read/write operations for dword register */
520static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
521{
522 outl(data, cm->iobase + cmd);
523}
524
525static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
526{
527 return inl(cm->iobase + cmd);
528}
529
530/* read/write operations for word register */
531static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
532{
533 outw(data, cm->iobase + cmd);
534}
535
536static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
537{
538 return inw(cm->iobase + cmd);
539}
540
541/* read/write operations for byte register */
542static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
543{
544 outb(data, cm->iobase + cmd);
545}
546
547static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
548{
549 return inb(cm->iobase + cmd);
550}
551
552/* bit operations for dword register */
553static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
554{
555 unsigned int val, oval;
556 val = oval = inl(cm->iobase + cmd);
557 val |= flag;
558 if (val == oval)
559 return 0;
560 outl(val, cm->iobase + cmd);
561 return 1;
562}
563
564static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
565{
566 unsigned int val, oval;
567 val = oval = inl(cm->iobase + cmd);
568 val &= ~flag;
569 if (val == oval)
570 return 0;
571 outl(val, cm->iobase + cmd);
572 return 1;
573}
574
575/* bit operations for byte register */
576static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
577{
578 unsigned char val, oval;
579 val = oval = inb(cm->iobase + cmd);
580 val |= flag;
581 if (val == oval)
582 return 0;
583 outb(val, cm->iobase + cmd);
584 return 1;
585}
586
587static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
588{
589 unsigned char val, oval;
590 val = oval = inb(cm->iobase + cmd);
591 val &= ~flag;
592 if (val == oval)
593 return 0;
594 outb(val, cm->iobase + cmd);
595 return 1;
596}
597
598
599/*
600 * PCM interface
601 */
602
603/*
604 * calculate frequency
605 */
606
607static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
608
609static unsigned int snd_cmipci_rate_freq(unsigned int rate)
610{
611 unsigned int i;
612
613 for (i = 0; i < ARRAY_SIZE(rates); i++) {
614 if (rates[i] == rate)
615 return i;
616 }
617 snd_BUG();
618 return 0;
619}
620
621#ifdef USE_VAR48KRATE
622/*
623 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
624 * does it this way .. maybe not. Never get any information from C-Media about
625 * that <werner@suse.de>.
626 */
627static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
628{
629 unsigned int delta, tolerance;
630 int xm, xn, xr;
631
632 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
633 rate <<= 1;
634 *n = -1;
635 if (*r > 0xff)
636 goto out;
637 tolerance = rate*CM_TOLERANCE_RATE;
638
639 for (xn = (1+2); xn < (0x1f+2); xn++) {
640 for (xm = (1+2); xm < (0xff+2); xm++) {
641 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
642
643 if (xr < rate)
644 delta = rate - xr;
645 else
646 delta = xr - rate;
647
648 /*
649 * If we found one, remember this,
650 * and try to find a closer one
651 */
652 if (delta < tolerance) {
653 tolerance = delta;
654 *m = xm - 2;
655 *n = xn - 2;
656 }
657 }
658 }
659out:
660 return (*n > -1);
661}
662
663/*
664 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
665 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
666 * at the register CM_REG_FUNCTRL1 (0x04).
667 * Problem: other ways are also possible (any information about that?)
668 */
669static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
670{
671 unsigned int reg = CM_REG_PLL + slot;
672 /*
673 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
674 * for DSFC/ASFC (000 upto 111).
675 */
676
677 /* FIXME: Init (Do we've to set an other register first before programming?) */
678
679 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
680 snd_cmipci_write_b(cm, reg, rate>>8);
681 snd_cmipci_write_b(cm, reg, rate&0xff);
682
683 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
684}
685#endif /* USE_VAR48KRATE */
686
687static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *hw_params)
689{
690 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
691}
692
693static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
694 struct snd_pcm_hw_params *hw_params)
695{
696 struct cmipci *cm = snd_pcm_substream_chip(substream);
697 if (params_channels(hw_params) > 2) {
698 mutex_lock(&cm->open_mutex);
699 if (cm->opened[CM_CH_PLAY]) {
700 mutex_unlock(&cm->open_mutex);
701 return -EBUSY;
702 }
703 /* reserve the channel A */
704 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
705 mutex_unlock(&cm->open_mutex);
706 }
707 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
708}
709
710static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
711{
712 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
713 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
714 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
715 udelay(10);
716}
717
718static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
719{
720 return snd_pcm_lib_free_pages(substream);
721}
722
723
724/*
725 */
726
727static unsigned int hw_channels[] = {1, 2, 4, 6, 8};
728static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
729 .count = 3,
730 .list = hw_channels,
731 .mask = 0,
732};
733static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
734 .count = 4,
735 .list = hw_channels,
736 .mask = 0,
737};
738static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
739 .count = 5,
740 .list = hw_channels,
741 .mask = 0,
742};
743
744static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
745{
746 if (channels > 2) {
747 if (!cm->can_multi_ch || !rec->ch)
748 return -EINVAL;
749 if (rec->fmt != 0x03) /* stereo 16bit only */
750 return -EINVAL;
751 }
752
753 if (cm->can_multi_ch) {
754 spin_lock_irq(&cm->reg_lock);
755 if (channels > 2) {
756 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
757 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
758 } else {
759 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
760 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
761 }
762 if (channels == 8)
763 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
764 else
765 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
766 if (channels == 6) {
767 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
768 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
769 } else {
770 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
771 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
772 }
773 if (channels == 4)
774 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
775 else
776 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
777 spin_unlock_irq(&cm->reg_lock);
778 }
779 return 0;
780}
781
782
783/*
784 * prepare playback/capture channel
785 * channel to be used must have been set in rec->ch.
786 */
787static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
788 struct snd_pcm_substream *substream)
789{
790 unsigned int reg, freq, freq_ext, val;
791 unsigned int period_size;
792 struct snd_pcm_runtime *runtime = substream->runtime;
793
794 rec->fmt = 0;
795 rec->shift = 0;
796 if (snd_pcm_format_width(runtime->format) >= 16) {
797 rec->fmt |= 0x02;
798 if (snd_pcm_format_width(runtime->format) > 16)
799 rec->shift++; /* 24/32bit */
800 }
801 if (runtime->channels > 1)
802 rec->fmt |= 0x01;
803 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
804 snd_printd("cannot set dac channels\n");
805 return -EINVAL;
806 }
807
808 rec->offset = runtime->dma_addr;
809 /* buffer and period sizes in frame */
810 rec->dma_size = runtime->buffer_size << rec->shift;
811 period_size = runtime->period_size << rec->shift;
812 if (runtime->channels > 2) {
813 /* multi-channels */
814 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
815 period_size = (period_size * runtime->channels) / 2;
816 }
817
818 spin_lock_irq(&cm->reg_lock);
819
820 /* set buffer address */
821 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
822 snd_cmipci_write(cm, reg, rec->offset);
823 /* program sample counts */
824 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
825 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
826 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
827
828 /* set adc/dac flag */
829 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
830 if (rec->is_dac)
831 cm->ctrl &= ~val;
832 else
833 cm->ctrl |= val;
834 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
835 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
836
837 /* set sample rate */
838 freq = 0;
839 freq_ext = 0;
840 if (runtime->rate > 48000)
841 switch (runtime->rate) {
842 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
843 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
844 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
845 default: snd_BUG(); break;
846 }
847 else
848 freq = snd_cmipci_rate_freq(runtime->rate);
849 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
850 if (rec->ch) {
851 val &= ~CM_DSFC_MASK;
852 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
853 } else {
854 val &= ~CM_ASFC_MASK;
855 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
856 }
857 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
858 //snd_printd("cmipci: functrl1 = %08x\n", val);
859
860 /* set format */
861 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
862 if (rec->ch) {
863 val &= ~CM_CH1FMT_MASK;
864 val |= rec->fmt << CM_CH1FMT_SHIFT;
865 } else {
866 val &= ~CM_CH0FMT_MASK;
867 val |= rec->fmt << CM_CH0FMT_SHIFT;
868 }
869 if (cm->can_96k) {
870 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
871 val |= freq_ext << (rec->ch * 2);
872 }
873 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
874 //snd_printd("cmipci: chformat = %08x\n", val);
875
876 if (!rec->is_dac && cm->chip_version) {
877 if (runtime->rate > 44100)
878 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
879 else
880 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
881 }
882
883 rec->running = 0;
884 spin_unlock_irq(&cm->reg_lock);
885
886 return 0;
887}
888
889/*
890 * PCM trigger/stop
891 */
892static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
893 int cmd)
894{
895 unsigned int inthld, chen, reset, pause;
896 int result = 0;
897
898 inthld = CM_CH0_INT_EN << rec->ch;
899 chen = CM_CHEN0 << rec->ch;
900 reset = CM_RST_CH0 << rec->ch;
901 pause = CM_PAUSE0 << rec->ch;
902
903 spin_lock(&cm->reg_lock);
904 switch (cmd) {
905 case SNDRV_PCM_TRIGGER_START:
906 rec->running = 1;
907 /* set interrupt */
908 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
909 cm->ctrl |= chen;
910 /* enable channel */
911 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
912 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
913 break;
914 case SNDRV_PCM_TRIGGER_STOP:
915 rec->running = 0;
916 /* disable interrupt */
917 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
918 /* reset */
919 cm->ctrl &= ~chen;
920 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
921 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
922 rec->needs_silencing = rec->is_dac;
923 break;
924 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
925 case SNDRV_PCM_TRIGGER_SUSPEND:
926 cm->ctrl |= pause;
927 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
928 break;
929 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
930 case SNDRV_PCM_TRIGGER_RESUME:
931 cm->ctrl &= ~pause;
932 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
933 break;
934 default:
935 result = -EINVAL;
936 break;
937 }
938 spin_unlock(&cm->reg_lock);
939 return result;
940}
941
942/*
943 * return the current pointer
944 */
945static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
946 struct snd_pcm_substream *substream)
947{
948 size_t ptr;
949 unsigned int reg, rem, tries;
950
951 if (!rec->running)
952 return 0;
953#if 1 // this seems better..
954 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
955 for (tries = 0; tries < 3; tries++) {
956 rem = snd_cmipci_read_w(cm, reg);
957 if (rem < rec->dma_size)
958 goto ok;
959 }
960 printk(KERN_ERR "cmipci: invalid PCM pointer: %#x\n", rem);
961 return SNDRV_PCM_POS_XRUN;
962ok:
963 ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
964#else
965 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
966 ptr = snd_cmipci_read(cm, reg) - rec->offset;
967 ptr = bytes_to_frames(substream->runtime, ptr);
968#endif
969 if (substream->runtime->channels > 2)
970 ptr = (ptr * 2) / substream->runtime->channels;
971 return ptr;
972}
973
974/*
975 * playback
976 */
977
978static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
979 int cmd)
980{
981 struct cmipci *cm = snd_pcm_substream_chip(substream);
982 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
983}
984
985static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
986{
987 struct cmipci *cm = snd_pcm_substream_chip(substream);
988 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
989}
990
991
992
993/*
994 * capture
995 */
996
997static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
998 int cmd)
999{
1000 struct cmipci *cm = snd_pcm_substream_chip(substream);
1001 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
1002}
1003
1004static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
1005{
1006 struct cmipci *cm = snd_pcm_substream_chip(substream);
1007 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
1008}
1009
1010
1011/*
1012 * hw preparation for spdif
1013 */
1014
1015static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_info *uinfo)
1017{
1018 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1019 uinfo->count = 1;
1020 return 0;
1021}
1022
1023static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1024 struct snd_ctl_elem_value *ucontrol)
1025{
1026 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1027 int i;
1028
1029 spin_lock_irq(&chip->reg_lock);
1030 for (i = 0; i < 4; i++)
1031 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1032 spin_unlock_irq(&chip->reg_lock);
1033 return 0;
1034}
1035
1036static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1037 struct snd_ctl_elem_value *ucontrol)
1038{
1039 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1040 int i, change;
1041 unsigned int val;
1042
1043 val = 0;
1044 spin_lock_irq(&chip->reg_lock);
1045 for (i = 0; i < 4; i++)
1046 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1047 change = val != chip->dig_status;
1048 chip->dig_status = val;
1049 spin_unlock_irq(&chip->reg_lock);
1050 return change;
1051}
1052
1053static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
1054{
1055 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1056 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1057 .info = snd_cmipci_spdif_default_info,
1058 .get = snd_cmipci_spdif_default_get,
1059 .put = snd_cmipci_spdif_default_put
1060};
1061
1062static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1063 struct snd_ctl_elem_info *uinfo)
1064{
1065 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1066 uinfo->count = 1;
1067 return 0;
1068}
1069
1070static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1071 struct snd_ctl_elem_value *ucontrol)
1072{
1073 ucontrol->value.iec958.status[0] = 0xff;
1074 ucontrol->value.iec958.status[1] = 0xff;
1075 ucontrol->value.iec958.status[2] = 0xff;
1076 ucontrol->value.iec958.status[3] = 0xff;
1077 return 0;
1078}
1079
1080static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1081{
1082 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1083 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1084 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1085 .info = snd_cmipci_spdif_mask_info,
1086 .get = snd_cmipci_spdif_mask_get,
1087};
1088
1089static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1090 struct snd_ctl_elem_info *uinfo)
1091{
1092 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1093 uinfo->count = 1;
1094 return 0;
1095}
1096
1097static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1098 struct snd_ctl_elem_value *ucontrol)
1099{
1100 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1101 int i;
1102
1103 spin_lock_irq(&chip->reg_lock);
1104 for (i = 0; i < 4; i++)
1105 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1106 spin_unlock_irq(&chip->reg_lock);
1107 return 0;
1108}
1109
1110static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1111 struct snd_ctl_elem_value *ucontrol)
1112{
1113 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1114 int i, change;
1115 unsigned int val;
1116
1117 val = 0;
1118 spin_lock_irq(&chip->reg_lock);
1119 for (i = 0; i < 4; i++)
1120 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1121 change = val != chip->dig_pcm_status;
1122 chip->dig_pcm_status = val;
1123 spin_unlock_irq(&chip->reg_lock);
1124 return change;
1125}
1126
1127static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1128{
1129 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1130 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1131 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1132 .info = snd_cmipci_spdif_stream_info,
1133 .get = snd_cmipci_spdif_stream_get,
1134 .put = snd_cmipci_spdif_stream_put
1135};
1136
1137/*
1138 */
1139
1140/* save mixer setting and mute for AC3 playback */
1141static int save_mixer_state(struct cmipci *cm)
1142{
1143 if (! cm->mixer_insensitive) {
1144 struct snd_ctl_elem_value *val;
1145 unsigned int i;
1146
1147 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1148 if (!val)
1149 return -ENOMEM;
1150 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1151 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1152 if (ctl) {
1153 int event;
1154 memset(val, 0, sizeof(*val));
1155 ctl->get(ctl, val);
1156 cm->mixer_res_status[i] = val->value.integer.value[0];
1157 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1158 event = SNDRV_CTL_EVENT_MASK_INFO;
1159 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1160 ctl->put(ctl, val); /* toggle */
1161 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1162 }
1163 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1164 snd_ctl_notify(cm->card, event, &ctl->id);
1165 }
1166 }
1167 kfree(val);
1168 cm->mixer_insensitive = 1;
1169 }
1170 return 0;
1171}
1172
1173
1174/* restore the previously saved mixer status */
1175static void restore_mixer_state(struct cmipci *cm)
1176{
1177 if (cm->mixer_insensitive) {
1178 struct snd_ctl_elem_value *val;
1179 unsigned int i;
1180
1181 val = kmalloc(sizeof(*val), GFP_KERNEL);
1182 if (!val)
1183 return;
1184 cm->mixer_insensitive = 0; /* at first clear this;
1185 otherwise the changes will be ignored */
1186 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1187 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1188 if (ctl) {
1189 int event;
1190
1191 memset(val, 0, sizeof(*val));
1192 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1193 ctl->get(ctl, val);
1194 event = SNDRV_CTL_EVENT_MASK_INFO;
1195 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1196 val->value.integer.value[0] = cm->mixer_res_status[i];
1197 ctl->put(ctl, val);
1198 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1199 }
1200 snd_ctl_notify(cm->card, event, &ctl->id);
1201 }
1202 }
1203 kfree(val);
1204 }
1205}
1206
1207/* spinlock held! */
1208static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1209{
1210 if (do_ac3) {
1211 /* AC3EN for 037 */
1212 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1213 /* AC3EN for 039 */
1214 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1215
1216 if (cm->can_ac3_hw) {
1217 /* SPD24SEL for 037, 0x02 */
1218 /* SPD24SEL for 039, 0x20, but cannot be set */
1219 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1220 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1221 } else { /* can_ac3_sw */
1222 /* SPD32SEL for 037 & 039, 0x20 */
1223 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1224 /* set 176K sample rate to fix 033 HW bug */
1225 if (cm->chip_version == 33) {
1226 if (rate >= 48000) {
1227 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1228 } else {
1229 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1230 }
1231 }
1232 }
1233
1234 } else {
1235 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1236 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1237
1238 if (cm->can_ac3_hw) {
1239 /* chip model >= 37 */
1240 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1241 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1242 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1243 } else {
1244 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1245 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1246 }
1247 } else {
1248 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1249 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1250 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1251 }
1252 }
1253}
1254
1255static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1256{
1257 int rate, err;
1258
1259 rate = subs->runtime->rate;
1260
1261 if (up && do_ac3)
1262 if ((err = save_mixer_state(cm)) < 0)
1263 return err;
1264
1265 spin_lock_irq(&cm->reg_lock);
1266 cm->spdif_playback_avail = up;
1267 if (up) {
1268 /* they are controlled via "IEC958 Output Switch" */
1269 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1270 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1271 if (cm->spdif_playback_enabled)
1272 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1273 setup_ac3(cm, subs, do_ac3, rate);
1274
1275 if (rate == 48000 || rate == 96000)
1276 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1277 else
1278 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1279 if (rate > 48000)
1280 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1281 else
1282 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1283 } else {
1284 /* they are controlled via "IEC958 Output Switch" */
1285 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1286 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1287 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1288 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1289 setup_ac3(cm, subs, 0, 0);
1290 }
1291 spin_unlock_irq(&cm->reg_lock);
1292 return 0;
1293}
1294
1295
1296/*
1297 * preparation
1298 */
1299
1300/* playback - enable spdif only on the certain condition */
1301static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1302{
1303 struct cmipci *cm = snd_pcm_substream_chip(substream);
1304 int rate = substream->runtime->rate;
1305 int err, do_spdif, do_ac3 = 0;
1306
1307 do_spdif = (rate >= 44100 && rate <= 96000 &&
1308 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1309 substream->runtime->channels == 2);
1310 if (do_spdif && cm->can_ac3_hw)
1311 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1312 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1313 return err;
1314 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1315}
1316
1317/* playback (via device #2) - enable spdif always */
1318static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1319{
1320 struct cmipci *cm = snd_pcm_substream_chip(substream);
1321 int err, do_ac3;
1322
1323 if (cm->can_ac3_hw)
1324 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1325 else
1326 do_ac3 = 1; /* doesn't matter */
1327 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1328 return err;
1329 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1330}
1331
1332/*
1333 * Apparently, the samples last played on channel A stay in some buffer, even
1334 * after the channel is reset, and get added to the data for the rear DACs when
1335 * playing a multichannel stream on channel B. This is likely to generate
1336 * wraparounds and thus distortions.
1337 * To avoid this, we play at least one zero sample after the actual stream has
1338 * stopped.
1339 */
1340static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1341{
1342 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1343 unsigned int reg, val;
1344
1345 if (rec->needs_silencing && runtime && runtime->dma_area) {
1346 /* set up a small silence buffer */
1347 memset(runtime->dma_area, 0, PAGE_SIZE);
1348 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1349 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1350 snd_cmipci_write(cm, reg, val);
1351
1352 /* configure for 16 bits, 2 channels, 8 kHz */
1353 if (runtime->channels > 2)
1354 set_dac_channels(cm, rec, 2);
1355 spin_lock_irq(&cm->reg_lock);
1356 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1357 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1358 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1359 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1360 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1361 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1362 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1363 if (cm->can_96k)
1364 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1365 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1366
1367 /* start stream (we don't need interrupts) */
1368 cm->ctrl |= CM_CHEN0 << rec->ch;
1369 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1370 spin_unlock_irq(&cm->reg_lock);
1371
1372 msleep(1);
1373
1374 /* stop and reset stream */
1375 spin_lock_irq(&cm->reg_lock);
1376 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1377 val = CM_RST_CH0 << rec->ch;
1378 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1379 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1380 spin_unlock_irq(&cm->reg_lock);
1381
1382 rec->needs_silencing = 0;
1383 }
1384}
1385
1386static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1387{
1388 struct cmipci *cm = snd_pcm_substream_chip(substream);
1389 setup_spdif_playback(cm, substream, 0, 0);
1390 restore_mixer_state(cm);
1391 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1392 return snd_cmipci_hw_free(substream);
1393}
1394
1395static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1396{
1397 struct cmipci *cm = snd_pcm_substream_chip(substream);
1398 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1399 return snd_cmipci_hw_free(substream);
1400}
1401
1402/* capture */
1403static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1404{
1405 struct cmipci *cm = snd_pcm_substream_chip(substream);
1406 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1407}
1408
1409/* capture with spdif (via device #2) */
1410static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1411{
1412 struct cmipci *cm = snd_pcm_substream_chip(substream);
1413
1414 spin_lock_irq(&cm->reg_lock);
1415 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1416 if (cm->can_96k) {
1417 if (substream->runtime->rate > 48000)
1418 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1419 else
1420 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1421 }
1422 if (snd_pcm_format_width(substream->runtime->format) > 16)
1423 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1424 else
1425 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1426
1427 spin_unlock_irq(&cm->reg_lock);
1428
1429 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1430}
1431
1432static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1433{
1434 struct cmipci *cm = snd_pcm_substream_chip(subs);
1435
1436 spin_lock_irq(&cm->reg_lock);
1437 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1438 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1439 spin_unlock_irq(&cm->reg_lock);
1440
1441 return snd_cmipci_hw_free(subs);
1442}
1443
1444
1445/*
1446 * interrupt handler
1447 */
1448static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1449{
1450 struct cmipci *cm = dev_id;
1451 unsigned int status, mask = 0;
1452
1453 /* fastpath out, to ease interrupt sharing */
1454 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1455 if (!(status & CM_INTR))
1456 return IRQ_NONE;
1457
1458 /* acknowledge interrupt */
1459 spin_lock(&cm->reg_lock);
1460 if (status & CM_CHINT0)
1461 mask |= CM_CH0_INT_EN;
1462 if (status & CM_CHINT1)
1463 mask |= CM_CH1_INT_EN;
1464 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1465 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1466 spin_unlock(&cm->reg_lock);
1467
1468 if (cm->rmidi && (status & CM_UARTINT))
1469 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1470
1471 if (cm->pcm) {
1472 if ((status & CM_CHINT0) && cm->channel[0].running)
1473 snd_pcm_period_elapsed(cm->channel[0].substream);
1474 if ((status & CM_CHINT1) && cm->channel[1].running)
1475 snd_pcm_period_elapsed(cm->channel[1].substream);
1476 }
1477 return IRQ_HANDLED;
1478}
1479
1480/*
1481 * h/w infos
1482 */
1483
1484/* playback on channel A */
1485static struct snd_pcm_hardware snd_cmipci_playback =
1486{
1487 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1488 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1489 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1490 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1491 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1492 .rate_min = 5512,
1493 .rate_max = 48000,
1494 .channels_min = 1,
1495 .channels_max = 2,
1496 .buffer_bytes_max = (128*1024),
1497 .period_bytes_min = 64,
1498 .period_bytes_max = (128*1024),
1499 .periods_min = 2,
1500 .periods_max = 1024,
1501 .fifo_size = 0,
1502};
1503
1504/* capture on channel B */
1505static struct snd_pcm_hardware snd_cmipci_capture =
1506{
1507 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1508 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1509 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1510 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1511 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1512 .rate_min = 5512,
1513 .rate_max = 48000,
1514 .channels_min = 1,
1515 .channels_max = 2,
1516 .buffer_bytes_max = (128*1024),
1517 .period_bytes_min = 64,
1518 .period_bytes_max = (128*1024),
1519 .periods_min = 2,
1520 .periods_max = 1024,
1521 .fifo_size = 0,
1522};
1523
1524/* playback on channel B - stereo 16bit only? */
1525static struct snd_pcm_hardware snd_cmipci_playback2 =
1526{
1527 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1528 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1529 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1530 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1531 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1532 .rate_min = 5512,
1533 .rate_max = 48000,
1534 .channels_min = 2,
1535 .channels_max = 2,
1536 .buffer_bytes_max = (128*1024),
1537 .period_bytes_min = 64,
1538 .period_bytes_max = (128*1024),
1539 .periods_min = 2,
1540 .periods_max = 1024,
1541 .fifo_size = 0,
1542};
1543
1544/* spdif playback on channel A */
1545static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1546{
1547 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1548 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1549 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1550 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1551 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1552 .rate_min = 44100,
1553 .rate_max = 48000,
1554 .channels_min = 2,
1555 .channels_max = 2,
1556 .buffer_bytes_max = (128*1024),
1557 .period_bytes_min = 64,
1558 .period_bytes_max = (128*1024),
1559 .periods_min = 2,
1560 .periods_max = 1024,
1561 .fifo_size = 0,
1562};
1563
1564/* spdif playback on channel A (32bit, IEC958 subframes) */
1565static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1566{
1567 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1568 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1569 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1570 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1571 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1572 .rate_min = 44100,
1573 .rate_max = 48000,
1574 .channels_min = 2,
1575 .channels_max = 2,
1576 .buffer_bytes_max = (128*1024),
1577 .period_bytes_min = 64,
1578 .period_bytes_max = (128*1024),
1579 .periods_min = 2,
1580 .periods_max = 1024,
1581 .fifo_size = 0,
1582};
1583
1584/* spdif capture on channel B */
1585static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1586{
1587 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1588 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1589 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1590 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1591 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1592 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1593 .rate_min = 44100,
1594 .rate_max = 48000,
1595 .channels_min = 2,
1596 .channels_max = 2,
1597 .buffer_bytes_max = (128*1024),
1598 .period_bytes_min = 64,
1599 .period_bytes_max = (128*1024),
1600 .periods_min = 2,
1601 .periods_max = 1024,
1602 .fifo_size = 0,
1603};
1604
1605static unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1606 32000, 44100, 48000, 88200, 96000, 128000 };
1607static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1608 .count = ARRAY_SIZE(rate_constraints),
1609 .list = rate_constraints,
1610 .mask = 0,
1611};
1612
1613/*
1614 * check device open/close
1615 */
1616static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1617{
1618 int ch = mode & CM_OPEN_CH_MASK;
1619
1620 /* FIXME: a file should wait until the device becomes free
1621 * when it's opened on blocking mode. however, since the current
1622 * pcm framework doesn't pass file pointer before actually opened,
1623 * we can't know whether blocking mode or not in open callback..
1624 */
1625 mutex_lock(&cm->open_mutex);
1626 if (cm->opened[ch]) {
1627 mutex_unlock(&cm->open_mutex);
1628 return -EBUSY;
1629 }
1630 cm->opened[ch] = mode;
1631 cm->channel[ch].substream = subs;
1632 if (! (mode & CM_OPEN_DAC)) {
1633 /* disable dual DAC mode */
1634 cm->channel[ch].is_dac = 0;
1635 spin_lock_irq(&cm->reg_lock);
1636 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1637 spin_unlock_irq(&cm->reg_lock);
1638 }
1639 mutex_unlock(&cm->open_mutex);
1640 return 0;
1641}
1642
1643static void close_device_check(struct cmipci *cm, int mode)
1644{
1645 int ch = mode & CM_OPEN_CH_MASK;
1646
1647 mutex_lock(&cm->open_mutex);
1648 if (cm->opened[ch] == mode) {
1649 if (cm->channel[ch].substream) {
1650 snd_cmipci_ch_reset(cm, ch);
1651 cm->channel[ch].running = 0;
1652 cm->channel[ch].substream = NULL;
1653 }
1654 cm->opened[ch] = 0;
1655 if (! cm->channel[ch].is_dac) {
1656 /* enable dual DAC mode again */
1657 cm->channel[ch].is_dac = 1;
1658 spin_lock_irq(&cm->reg_lock);
1659 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1660 spin_unlock_irq(&cm->reg_lock);
1661 }
1662 }
1663 mutex_unlock(&cm->open_mutex);
1664}
1665
1666/*
1667 */
1668
1669static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1670{
1671 struct cmipci *cm = snd_pcm_substream_chip(substream);
1672 struct snd_pcm_runtime *runtime = substream->runtime;
1673 int err;
1674
1675 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1676 return err;
1677 runtime->hw = snd_cmipci_playback;
1678 if (cm->chip_version == 68) {
1679 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1680 SNDRV_PCM_RATE_96000;
1681 runtime->hw.rate_max = 96000;
1682 } else if (cm->chip_version == 55) {
1683 err = snd_pcm_hw_constraint_list(runtime, 0,
1684 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1685 if (err < 0)
1686 return err;
1687 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1688 runtime->hw.rate_max = 128000;
1689 }
1690 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1691 cm->dig_pcm_status = cm->dig_status;
1692 return 0;
1693}
1694
1695static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1696{
1697 struct cmipci *cm = snd_pcm_substream_chip(substream);
1698 struct snd_pcm_runtime *runtime = substream->runtime;
1699 int err;
1700
1701 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1702 return err;
1703 runtime->hw = snd_cmipci_capture;
1704 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1705 runtime->hw.rate_min = 41000;
1706 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1707 } else if (cm->chip_version == 55) {
1708 err = snd_pcm_hw_constraint_list(runtime, 0,
1709 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1710 if (err < 0)
1711 return err;
1712 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1713 runtime->hw.rate_max = 128000;
1714 }
1715 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1716 return 0;
1717}
1718
1719static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1720{
1721 struct cmipci *cm = snd_pcm_substream_chip(substream);
1722 struct snd_pcm_runtime *runtime = substream->runtime;
1723 int err;
1724
1725 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1726 return err;
1727 runtime->hw = snd_cmipci_playback2;
1728 mutex_lock(&cm->open_mutex);
1729 if (! cm->opened[CM_CH_PLAY]) {
1730 if (cm->can_multi_ch) {
1731 runtime->hw.channels_max = cm->max_channels;
1732 if (cm->max_channels == 4)
1733 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1734 else if (cm->max_channels == 6)
1735 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1736 else if (cm->max_channels == 8)
1737 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1738 }
1739 }
1740 mutex_unlock(&cm->open_mutex);
1741 if (cm->chip_version == 68) {
1742 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1743 SNDRV_PCM_RATE_96000;
1744 runtime->hw.rate_max = 96000;
1745 } else if (cm->chip_version == 55) {
1746 err = snd_pcm_hw_constraint_list(runtime, 0,
1747 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1748 if (err < 0)
1749 return err;
1750 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1751 runtime->hw.rate_max = 128000;
1752 }
1753 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1754 return 0;
1755}
1756
1757static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1758{
1759 struct cmipci *cm = snd_pcm_substream_chip(substream);
1760 struct snd_pcm_runtime *runtime = substream->runtime;
1761 int err;
1762
1763 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1764 return err;
1765 if (cm->can_ac3_hw) {
1766 runtime->hw = snd_cmipci_playback_spdif;
1767 if (cm->chip_version >= 37) {
1768 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1769 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1770 }
1771 if (cm->can_96k) {
1772 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1773 SNDRV_PCM_RATE_96000;
1774 runtime->hw.rate_max = 96000;
1775 }
1776 } else {
1777 runtime->hw = snd_cmipci_playback_iec958_subframe;
1778 }
1779 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1780 cm->dig_pcm_status = cm->dig_status;
1781 return 0;
1782}
1783
1784static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1785{
1786 struct cmipci *cm = snd_pcm_substream_chip(substream);
1787 struct snd_pcm_runtime *runtime = substream->runtime;
1788 int err;
1789
1790 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1791 return err;
1792 runtime->hw = snd_cmipci_capture_spdif;
1793 if (cm->can_96k && !(cm->chip_version == 68)) {
1794 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1795 SNDRV_PCM_RATE_96000;
1796 runtime->hw.rate_max = 96000;
1797 }
1798 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1799 return 0;
1800}
1801
1802
1803/*
1804 */
1805
1806static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1807{
1808 struct cmipci *cm = snd_pcm_substream_chip(substream);
1809 close_device_check(cm, CM_OPEN_PLAYBACK);
1810 return 0;
1811}
1812
1813static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1814{
1815 struct cmipci *cm = snd_pcm_substream_chip(substream);
1816 close_device_check(cm, CM_OPEN_CAPTURE);
1817 return 0;
1818}
1819
1820static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1821{
1822 struct cmipci *cm = snd_pcm_substream_chip(substream);
1823 close_device_check(cm, CM_OPEN_PLAYBACK2);
1824 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1825 return 0;
1826}
1827
1828static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1829{
1830 struct cmipci *cm = snd_pcm_substream_chip(substream);
1831 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1832 return 0;
1833}
1834
1835static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1836{
1837 struct cmipci *cm = snd_pcm_substream_chip(substream);
1838 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1839 return 0;
1840}
1841
1842
1843/*
1844 */
1845
1846static struct snd_pcm_ops snd_cmipci_playback_ops = {
1847 .open = snd_cmipci_playback_open,
1848 .close = snd_cmipci_playback_close,
1849 .ioctl = snd_pcm_lib_ioctl,
1850 .hw_params = snd_cmipci_hw_params,
1851 .hw_free = snd_cmipci_playback_hw_free,
1852 .prepare = snd_cmipci_playback_prepare,
1853 .trigger = snd_cmipci_playback_trigger,
1854 .pointer = snd_cmipci_playback_pointer,
1855};
1856
1857static struct snd_pcm_ops snd_cmipci_capture_ops = {
1858 .open = snd_cmipci_capture_open,
1859 .close = snd_cmipci_capture_close,
1860 .ioctl = snd_pcm_lib_ioctl,
1861 .hw_params = snd_cmipci_hw_params,
1862 .hw_free = snd_cmipci_hw_free,
1863 .prepare = snd_cmipci_capture_prepare,
1864 .trigger = snd_cmipci_capture_trigger,
1865 .pointer = snd_cmipci_capture_pointer,
1866};
1867
1868static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1869 .open = snd_cmipci_playback2_open,
1870 .close = snd_cmipci_playback2_close,
1871 .ioctl = snd_pcm_lib_ioctl,
1872 .hw_params = snd_cmipci_playback2_hw_params,
1873 .hw_free = snd_cmipci_playback2_hw_free,
1874 .prepare = snd_cmipci_capture_prepare, /* channel B */
1875 .trigger = snd_cmipci_capture_trigger, /* channel B */
1876 .pointer = snd_cmipci_capture_pointer, /* channel B */
1877};
1878
1879static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1880 .open = snd_cmipci_playback_spdif_open,
1881 .close = snd_cmipci_playback_spdif_close,
1882 .ioctl = snd_pcm_lib_ioctl,
1883 .hw_params = snd_cmipci_hw_params,
1884 .hw_free = snd_cmipci_playback_hw_free,
1885 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1886 .trigger = snd_cmipci_playback_trigger,
1887 .pointer = snd_cmipci_playback_pointer,
1888};
1889
1890static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1891 .open = snd_cmipci_capture_spdif_open,
1892 .close = snd_cmipci_capture_spdif_close,
1893 .ioctl = snd_pcm_lib_ioctl,
1894 .hw_params = snd_cmipci_hw_params,
1895 .hw_free = snd_cmipci_capture_spdif_hw_free,
1896 .prepare = snd_cmipci_capture_spdif_prepare,
1897 .trigger = snd_cmipci_capture_trigger,
1898 .pointer = snd_cmipci_capture_pointer,
1899};
1900
1901
1902/*
1903 */
1904
1905static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1906{
1907 struct snd_pcm *pcm;
1908 int err;
1909
1910 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1911 if (err < 0)
1912 return err;
1913
1914 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1915 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1916
1917 pcm->private_data = cm;
1918 pcm->info_flags = 0;
1919 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1920 cm->pcm = pcm;
1921
1922 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1923 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1924
1925 return 0;
1926}
1927
1928static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1929{
1930 struct snd_pcm *pcm;
1931 int err;
1932
1933 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1934 if (err < 0)
1935 return err;
1936
1937 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1938
1939 pcm->private_data = cm;
1940 pcm->info_flags = 0;
1941 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1942 cm->pcm2 = pcm;
1943
1944 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1945 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1946
1947 return 0;
1948}
1949
1950static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1951{
1952 struct snd_pcm *pcm;
1953 int err;
1954
1955 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1956 if (err < 0)
1957 return err;
1958
1959 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1960 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1961
1962 pcm->private_data = cm;
1963 pcm->info_flags = 0;
1964 strcpy(pcm->name, "C-Media PCI IEC958");
1965 cm->pcm_spdif = pcm;
1966
1967 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1968 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1969
1970 return 0;
1971}
1972
1973/*
1974 * mixer interface:
1975 * - CM8338/8738 has a compatible mixer interface with SB16, but
1976 * lack of some elements like tone control, i/o gain and AGC.
1977 * - Access to native registers:
1978 * - A 3D switch
1979 * - Output mute switches
1980 */
1981
1982static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1983{
1984 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1985 outb(data, s->iobase + CM_REG_SB16_DATA);
1986}
1987
1988static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1989{
1990 unsigned char v;
1991
1992 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1993 v = inb(s->iobase + CM_REG_SB16_DATA);
1994 return v;
1995}
1996
1997/*
1998 * general mixer element
1999 */
2000struct cmipci_sb_reg {
2001 unsigned int left_reg, right_reg;
2002 unsigned int left_shift, right_shift;
2003 unsigned int mask;
2004 unsigned int invert: 1;
2005 unsigned int stereo: 1;
2006};
2007
2008#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
2009 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
2010
2011#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
2012{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2013 .info = snd_cmipci_info_volume, \
2014 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2015 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2016}
2017
2018#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2019#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2020#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2021#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2022
2023static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2024{
2025 r->left_reg = val & 0xff;
2026 r->right_reg = (val >> 8) & 0xff;
2027 r->left_shift = (val >> 16) & 0x07;
2028 r->right_shift = (val >> 19) & 0x07;
2029 r->invert = (val >> 22) & 1;
2030 r->stereo = (val >> 23) & 1;
2031 r->mask = (val >> 24) & 0xff;
2032}
2033
2034static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2035 struct snd_ctl_elem_info *uinfo)
2036{
2037 struct cmipci_sb_reg reg;
2038
2039 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2040 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2041 uinfo->count = reg.stereo + 1;
2042 uinfo->value.integer.min = 0;
2043 uinfo->value.integer.max = reg.mask;
2044 return 0;
2045}
2046
2047static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2048 struct snd_ctl_elem_value *ucontrol)
2049{
2050 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2051 struct cmipci_sb_reg reg;
2052 int val;
2053
2054 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2055 spin_lock_irq(&cm->reg_lock);
2056 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2057 if (reg.invert)
2058 val = reg.mask - val;
2059 ucontrol->value.integer.value[0] = val;
2060 if (reg.stereo) {
2061 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2062 if (reg.invert)
2063 val = reg.mask - val;
2064 ucontrol->value.integer.value[1] = val;
2065 }
2066 spin_unlock_irq(&cm->reg_lock);
2067 return 0;
2068}
2069
2070static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2071 struct snd_ctl_elem_value *ucontrol)
2072{
2073 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2074 struct cmipci_sb_reg reg;
2075 int change;
2076 int left, right, oleft, oright;
2077
2078 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2079 left = ucontrol->value.integer.value[0] & reg.mask;
2080 if (reg.invert)
2081 left = reg.mask - left;
2082 left <<= reg.left_shift;
2083 if (reg.stereo) {
2084 right = ucontrol->value.integer.value[1] & reg.mask;
2085 if (reg.invert)
2086 right = reg.mask - right;
2087 right <<= reg.right_shift;
2088 } else
2089 right = 0;
2090 spin_lock_irq(&cm->reg_lock);
2091 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2092 left |= oleft & ~(reg.mask << reg.left_shift);
2093 change = left != oleft;
2094 if (reg.stereo) {
2095 if (reg.left_reg != reg.right_reg) {
2096 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2097 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2098 } else
2099 oright = left;
2100 right |= oright & ~(reg.mask << reg.right_shift);
2101 change |= right != oright;
2102 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2103 } else
2104 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2105 spin_unlock_irq(&cm->reg_lock);
2106 return change;
2107}
2108
2109/*
2110 * input route (left,right) -> (left,right)
2111 */
2112#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2113{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2114 .info = snd_cmipci_info_input_sw, \
2115 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2116 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2117}
2118
2119static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2120 struct snd_ctl_elem_info *uinfo)
2121{
2122 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2123 uinfo->count = 4;
2124 uinfo->value.integer.min = 0;
2125 uinfo->value.integer.max = 1;
2126 return 0;
2127}
2128
2129static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2130 struct snd_ctl_elem_value *ucontrol)
2131{
2132 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2133 struct cmipci_sb_reg reg;
2134 int val1, val2;
2135
2136 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2137 spin_lock_irq(&cm->reg_lock);
2138 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2139 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2140 spin_unlock_irq(&cm->reg_lock);
2141 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2142 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2143 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2144 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2145 return 0;
2146}
2147
2148static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2149 struct snd_ctl_elem_value *ucontrol)
2150{
2151 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2152 struct cmipci_sb_reg reg;
2153 int change;
2154 int val1, val2, oval1, oval2;
2155
2156 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2157 spin_lock_irq(&cm->reg_lock);
2158 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2159 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2160 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2161 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2162 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2163 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2164 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2165 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2166 change = val1 != oval1 || val2 != oval2;
2167 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2168 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2169 spin_unlock_irq(&cm->reg_lock);
2170 return change;
2171}
2172
2173/*
2174 * native mixer switches/volumes
2175 */
2176
2177#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2178{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2179 .info = snd_cmipci_info_native_mixer, \
2180 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2181 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2182}
2183
2184#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2185{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2186 .info = snd_cmipci_info_native_mixer, \
2187 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2188 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2189}
2190
2191#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2192{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2193 .info = snd_cmipci_info_native_mixer, \
2194 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2195 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2196}
2197
2198#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2199{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2200 .info = snd_cmipci_info_native_mixer, \
2201 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2202 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2203}
2204
2205static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2206 struct snd_ctl_elem_info *uinfo)
2207{
2208 struct cmipci_sb_reg reg;
2209
2210 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2211 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2212 uinfo->count = reg.stereo + 1;
2213 uinfo->value.integer.min = 0;
2214 uinfo->value.integer.max = reg.mask;
2215 return 0;
2216
2217}
2218
2219static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2220 struct snd_ctl_elem_value *ucontrol)
2221{
2222 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2223 struct cmipci_sb_reg reg;
2224 unsigned char oreg, val;
2225
2226 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2227 spin_lock_irq(&cm->reg_lock);
2228 oreg = inb(cm->iobase + reg.left_reg);
2229 val = (oreg >> reg.left_shift) & reg.mask;
2230 if (reg.invert)
2231 val = reg.mask - val;
2232 ucontrol->value.integer.value[0] = val;
2233 if (reg.stereo) {
2234 val = (oreg >> reg.right_shift) & reg.mask;
2235 if (reg.invert)
2236 val = reg.mask - val;
2237 ucontrol->value.integer.value[1] = val;
2238 }
2239 spin_unlock_irq(&cm->reg_lock);
2240 return 0;
2241}
2242
2243static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2244 struct snd_ctl_elem_value *ucontrol)
2245{
2246 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2247 struct cmipci_sb_reg reg;
2248 unsigned char oreg, nreg, val;
2249
2250 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2251 spin_lock_irq(&cm->reg_lock);
2252 oreg = inb(cm->iobase + reg.left_reg);
2253 val = ucontrol->value.integer.value[0] & reg.mask;
2254 if (reg.invert)
2255 val = reg.mask - val;
2256 nreg = oreg & ~(reg.mask << reg.left_shift);
2257 nreg |= (val << reg.left_shift);
2258 if (reg.stereo) {
2259 val = ucontrol->value.integer.value[1] & reg.mask;
2260 if (reg.invert)
2261 val = reg.mask - val;
2262 nreg &= ~(reg.mask << reg.right_shift);
2263 nreg |= (val << reg.right_shift);
2264 }
2265 outb(nreg, cm->iobase + reg.left_reg);
2266 spin_unlock_irq(&cm->reg_lock);
2267 return (nreg != oreg);
2268}
2269
2270/*
2271 * special case - check mixer sensitivity
2272 */
2273static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2274 struct snd_ctl_elem_value *ucontrol)
2275{
2276 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2277 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2278}
2279
2280static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2281 struct snd_ctl_elem_value *ucontrol)
2282{
2283 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2284 if (cm->mixer_insensitive) {
2285 /* ignored */
2286 return 0;
2287 }
2288 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2289}
2290
2291
2292static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2293 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2294 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2295 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2296 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2297 { /* switch with sensitivity */
2298 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2299 .name = "PCM Playback Switch",
2300 .info = snd_cmipci_info_native_mixer,
2301 .get = snd_cmipci_get_native_mixer_sensitive,
2302 .put = snd_cmipci_put_native_mixer_sensitive,
2303 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2304 },
2305 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2306 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2307 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2308 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2309 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2310 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2311 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2312 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2313 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2314 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2315 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2316 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2317 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2318 CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2319 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2320 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2321 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2322 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2323 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2324 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2325 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2326 CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2327 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2328};
2329
2330/*
2331 * other switches
2332 */
2333
2334struct cmipci_switch_args {
2335 int reg; /* register index */
2336 unsigned int mask; /* mask bits */
2337 unsigned int mask_on; /* mask bits to turn on */
2338 unsigned int is_byte: 1; /* byte access? */
2339 unsigned int ac3_sensitive: 1; /* access forbidden during
2340 * non-audio operation?
2341 */
2342};
2343
2344#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2345
2346static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2347 struct snd_ctl_elem_value *ucontrol,
2348 struct cmipci_switch_args *args)
2349{
2350 unsigned int val;
2351 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2352
2353 spin_lock_irq(&cm->reg_lock);
2354 if (args->ac3_sensitive && cm->mixer_insensitive) {
2355 ucontrol->value.integer.value[0] = 0;
2356 spin_unlock_irq(&cm->reg_lock);
2357 return 0;
2358 }
2359 if (args->is_byte)
2360 val = inb(cm->iobase + args->reg);
2361 else
2362 val = snd_cmipci_read(cm, args->reg);
2363 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2364 spin_unlock_irq(&cm->reg_lock);
2365 return 0;
2366}
2367
2368static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2369 struct snd_ctl_elem_value *ucontrol)
2370{
2371 struct cmipci_switch_args *args;
2372 args = (struct cmipci_switch_args *)kcontrol->private_value;
2373 if (snd_BUG_ON(!args))
2374 return -EINVAL;
2375 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2376}
2377
2378static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2379 struct snd_ctl_elem_value *ucontrol,
2380 struct cmipci_switch_args *args)
2381{
2382 unsigned int val;
2383 int change;
2384 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2385
2386 spin_lock_irq(&cm->reg_lock);
2387 if (args->ac3_sensitive && cm->mixer_insensitive) {
2388 /* ignored */
2389 spin_unlock_irq(&cm->reg_lock);
2390 return 0;
2391 }
2392 if (args->is_byte)
2393 val = inb(cm->iobase + args->reg);
2394 else
2395 val = snd_cmipci_read(cm, args->reg);
2396 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2397 args->mask_on : (args->mask & ~args->mask_on));
2398 if (change) {
2399 val &= ~args->mask;
2400 if (ucontrol->value.integer.value[0])
2401 val |= args->mask_on;
2402 else
2403 val |= (args->mask & ~args->mask_on);
2404 if (args->is_byte)
2405 outb((unsigned char)val, cm->iobase + args->reg);
2406 else
2407 snd_cmipci_write(cm, args->reg, val);
2408 }
2409 spin_unlock_irq(&cm->reg_lock);
2410 return change;
2411}
2412
2413static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2414 struct snd_ctl_elem_value *ucontrol)
2415{
2416 struct cmipci_switch_args *args;
2417 args = (struct cmipci_switch_args *)kcontrol->private_value;
2418 if (snd_BUG_ON(!args))
2419 return -EINVAL;
2420 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2421}
2422
2423#ifndef TARGET_OS2
2424#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2425static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2426 .reg = xreg, \
2427 .mask = xmask, \
2428 .mask_on = xmask_on, \
2429 .is_byte = xis_byte, \
2430 .ac3_sensitive = xac3, \
2431}
2432#else
2433#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2434 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2435 xreg, \
2436 xmask, \
2437 xmask_on, \
2438 xis_byte, \
2439 xac3, \
2440 }
2441#endif
2442
2443#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2444 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2445
2446#if 0 /* these will be controlled in pcm device */
2447DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2448DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2449#endif
2450DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2451DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2452DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2453DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2454DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2455DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2456DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2457DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2458// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2459DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2460DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2461/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2462DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2463DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2464#if CM_CH_PLAY == 1
2465DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2466#else
2467DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2468#endif
2469DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2470// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2471// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2472// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2473DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2474
2475#define DEFINE_SWITCH(sname, stype, sarg) \
2476{ .name = sname, \
2477 .iface = stype, \
2478 .info = snd_cmipci_uswitch_info, \
2479 .get = snd_cmipci_uswitch_get, \
2480 .put = snd_cmipci_uswitch_put, \
2481 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2482}
2483
2484#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2485#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2486
2487
2488/*
2489 * callbacks for spdif output switch
2490 * needs toggle two registers..
2491 */
2492static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2493 struct snd_ctl_elem_value *ucontrol)
2494{
2495 int changed;
2496 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2497 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2498 return changed;
2499}
2500
2501static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2502 struct snd_ctl_elem_value *ucontrol)
2503{
2504 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2505 int changed;
2506 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2507 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2508 if (changed) {
2509 if (ucontrol->value.integer.value[0]) {
2510 if (chip->spdif_playback_avail)
2511 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2512 } else {
2513 if (chip->spdif_playback_avail)
2514 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2515 }
2516 }
2517 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2518 return changed;
2519}
2520
2521
2522static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2523 struct snd_ctl_elem_info *uinfo)
2524{
2525 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2526 static const char *const texts[3] = {
2527 "Line-In", "Rear Output", "Bass Output"
2528 };
2529
2530 return snd_ctl_enum_info(uinfo, 1,
2531 cm->chip_version >= 39 ? 3 : 2, texts);
2532}
2533
2534static inline unsigned int get_line_in_mode(struct cmipci *cm)
2535{
2536 unsigned int val;
2537 if (cm->chip_version >= 39) {
2538 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2539 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2540 return 2;
2541 }
2542 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2543 if (val & CM_REAR2LIN)
2544 return 1;
2545 return 0;
2546}
2547
2548static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2549 struct snd_ctl_elem_value *ucontrol)
2550{
2551 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2552
2553 spin_lock_irq(&cm->reg_lock);
2554 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2555 spin_unlock_irq(&cm->reg_lock);
2556 return 0;
2557}
2558
2559static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2560 struct snd_ctl_elem_value *ucontrol)
2561{
2562 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2563 int change;
2564
2565 spin_lock_irq(&cm->reg_lock);
2566 if (ucontrol->value.enumerated.item[0] == 2)
2567 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2568 else
2569 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2570 if (ucontrol->value.enumerated.item[0] == 1)
2571 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2572 else
2573 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2574 spin_unlock_irq(&cm->reg_lock);
2575 return change;
2576}
2577
2578static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2579 struct snd_ctl_elem_info *uinfo)
2580{
2581 static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2582
2583 return snd_ctl_enum_info(uinfo, 1, 2, texts);
2584}
2585
2586static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2587 struct snd_ctl_elem_value *ucontrol)
2588{
2589 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2590 /* same bit as spdi_phase */
2591 spin_lock_irq(&cm->reg_lock);
2592 ucontrol->value.enumerated.item[0] =
2593 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2594 spin_unlock_irq(&cm->reg_lock);
2595 return 0;
2596}
2597
2598static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2599 struct snd_ctl_elem_value *ucontrol)
2600{
2601 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2602 int change;
2603
2604 spin_lock_irq(&cm->reg_lock);
2605 if (ucontrol->value.enumerated.item[0])
2606 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2607 else
2608 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2609 spin_unlock_irq(&cm->reg_lock);
2610 return change;
2611}
2612
2613/* both for CM8338/8738 */
2614static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2615 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2616 {
2617 .name = "Line-In Mode",
2618 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2619 .info = snd_cmipci_line_in_mode_info,
2620 .get = snd_cmipci_line_in_mode_get,
2621 .put = snd_cmipci_line_in_mode_put,
2622 },
2623};
2624
2625/* for non-multichannel chips */
2626static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2627DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2628
2629/* only for CM8738 */
2630static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2631#if 0 /* controlled in pcm device */
2632 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2633 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2634 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2635#endif
2636 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2637 { .name = "IEC958 Output Switch",
2638 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2639 .info = snd_cmipci_uswitch_info,
2640 .get = snd_cmipci_spdout_enable_get,
2641 .put = snd_cmipci_spdout_enable_put,
2642 },
2643 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2644 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2645 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2646// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2647 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2648 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2649};
2650
2651/* only for model 033/037 */
2652static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2653 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2654 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2655 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2656};
2657
2658/* only for model 039 or later */
2659static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2660 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2661 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2662 {
2663 .name = "Mic-In Mode",
2664 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2665 .info = snd_cmipci_mic_in_mode_info,
2666 .get = snd_cmipci_mic_in_mode_get,
2667 .put = snd_cmipci_mic_in_mode_put,
2668 }
2669};
2670
2671/* card control switches */
2672static struct snd_kcontrol_new snd_cmipci_modem_switch __devinitdata =
2673DEFINE_CARD_SWITCH("Modem", modem);
2674
2675
2676static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2677{
2678 struct snd_card *card;
2679 struct snd_kcontrol_new *sw;
2680 struct snd_kcontrol *kctl;
2681 unsigned int idx;
2682 int err;
2683
2684 if (snd_BUG_ON(!cm || !cm->card))
2685 return -EINVAL;
2686
2687 card = cm->card;
2688
2689 strcpy(card->mixername, "CMedia PCI");
2690
2691 spin_lock_irq(&cm->reg_lock);
2692 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2693 spin_unlock_irq(&cm->reg_lock);
2694
2695 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2696 if (cm->chip_version == 68) { // 8768 has no PCM volume
2697 if (!strcmp(snd_cmipci_mixers[idx].name,
2698 "PCM Playback Volume"))
2699 continue;
2700 }
2701 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2702 return err;
2703 }
2704
2705 /* mixer switches */
2706 sw = snd_cmipci_mixer_switches;
2707 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2708 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2709 if (err < 0)
2710 return err;
2711 }
2712 if (! cm->can_multi_ch) {
2713 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2714 if (err < 0)
2715 return err;
2716 }
2717 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2718 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2719 sw = snd_cmipci_8738_mixer_switches;
2720 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2721 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2722 if (err < 0)
2723 return err;
2724 }
2725 if (cm->can_ac3_hw) {
2726 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2727 return err;
2728 kctl->id.device = pcm_spdif_device;
2729 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2730 return err;
2731 kctl->id.device = pcm_spdif_device;
2732 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2733 return err;
2734 kctl->id.device = pcm_spdif_device;
2735 }
2736 if (cm->chip_version <= 37) {
2737 sw = snd_cmipci_old_mixer_switches;
2738 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2739 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2740 if (err < 0)
2741 return err;
2742 }
2743 }
2744 }
2745 if (cm->chip_version >= 39) {
2746 sw = snd_cmipci_extra_mixer_switches;
2747 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2748 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2749 if (err < 0)
2750 return err;
2751 }
2752 }
2753
2754 /* card switches */
2755 /*
2756 * newer chips don't have the register bits to force modem link
2757 * detection; the bit that was FLINKON now mutes CH1
2758 */
2759 if (cm->chip_version < 39) {
2760 err = snd_ctl_add(cm->card,
2761 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2762 if (err < 0)
2763 return err;
2764 }
2765
2766 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2767 struct snd_ctl_elem_id elem_id;
2768 struct snd_kcontrol *ctl;
2769 memset(&elem_id, 0, sizeof(elem_id));
2770 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2771 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2772 ctl = snd_ctl_find_id(cm->card, &elem_id);
2773 if (ctl)
2774 cm->mixer_res_ctl[idx] = ctl;
2775 }
2776
2777 return 0;
2778}
2779
2780
2781/*
2782 * proc interface
2783 */
2784
2785#ifdef CONFIG_PROC_FS
2786static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2787 struct snd_info_buffer *buffer)
2788{
2789 struct cmipci *cm = entry->private_data;
2790 int i, v;
2791
2792 snd_iprintf(buffer, "%s\n", cm->card->longname);
2793 for (i = 0; i < 0x94; i++) {
2794 if (i == 0x28)
2795 i = 0x90;
2796 v = inb(cm->iobase + i);
2797 if (i % 4 == 0)
2798 snd_iprintf(buffer, "\n%02x:", i);
2799 snd_iprintf(buffer, " %02x", v);
2800 }
2801 snd_iprintf(buffer, "\n");
2802}
2803
2804static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2805{
2806 struct snd_info_entry *entry;
2807
2808 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2809 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2810}
2811#else /* !CONFIG_PROC_FS */
2812static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2813#endif
2814
2815
2816static DEFINE_PCI_DEVICE_TABLE(snd_cmipci_ids) = {
2817 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2818 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2819 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2820 {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2821 {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2822 {0,},
2823};
2824
2825
2826/*
2827 * check chip version and capabilities
2828 * driver name is modified according to the chip model
2829 */
2830static void __devinit query_chip(struct cmipci *cm)
2831{
2832 unsigned int detect;
2833
2834 /* check reg 0Ch, bit 24-31 */
2835 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2836 if (! detect) {
2837 /* check reg 08h, bit 24-28 */
2838 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2839 switch (detect) {
2840 case 0:
2841 cm->chip_version = 33;
2842 if (cm->do_soft_ac3)
2843 cm->can_ac3_sw = 1;
2844 else
2845 cm->can_ac3_hw = 1;
2846 break;
2847 case CM_CHIP_037:
2848 cm->chip_version = 37;
2849 cm->can_ac3_hw = 1;
2850 break;
2851 default:
2852 cm->chip_version = 39;
2853 cm->can_ac3_hw = 1;
2854 break;
2855 }
2856 cm->max_channels = 2;
2857 } else {
2858 if (detect & CM_CHIP_039) {
2859 cm->chip_version = 39;
2860 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2861 cm->max_channels = 6;
2862 else
2863 cm->max_channels = 4;
2864 } else if (detect & CM_CHIP_8768) {
2865 cm->chip_version = 68;
2866 cm->max_channels = 8;
2867 cm->can_96k = 1;
2868 } else {
2869 cm->chip_version = 55;
2870 cm->max_channels = 6;
2871 cm->can_96k = 1;
2872 }
2873 cm->can_ac3_hw = 1;
2874 cm->can_multi_ch = 1;
2875 }
2876}
2877
2878#ifdef SUPPORT_JOYSTICK
2879static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2880{
2881 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2882 struct gameport *gp;
2883 struct resource *r = NULL;
2884 int i, io_port = 0;
2885
2886 if (joystick_port[dev] == 0)
2887 return -ENODEV;
2888
2889 if (joystick_port[dev] == 1) { /* auto-detect */
2890 for (i = 0; ports[i]; i++) {
2891 io_port = ports[i];
2892 r = request_region(io_port, 1, "CMIPCI gameport");
2893 if (r)
2894 break;
2895 }
2896 } else {
2897 io_port = joystick_port[dev];
2898 r = request_region(io_port, 1, "CMIPCI gameport");
2899 }
2900
2901 if (!r) {
2902 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2903 return -EBUSY;
2904 }
2905
2906 cm->gameport = gp = gameport_allocate_port();
2907 if (!gp) {
2908 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2909 release_and_free_resource(r);
2910 return -ENOMEM;
2911 }
2912 gameport_set_name(gp, "C-Media Gameport");
2913 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2914 gameport_set_dev_parent(gp, &cm->pci->dev);
2915 gp->io = io_port;
2916 gameport_set_port_data(gp, r);
2917
2918 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2919
2920 gameport_register_port(cm->gameport);
2921
2922 return 0;
2923}
2924
2925static void snd_cmipci_free_gameport(struct cmipci *cm)
2926{
2927 if (cm->gameport) {
2928 struct resource *r = gameport_get_port_data(cm->gameport);
2929
2930 gameport_unregister_port(cm->gameport);
2931 cm->gameport = NULL;
2932
2933 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2934 release_and_free_resource(r);
2935 }
2936}
2937#else
2938static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2939static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2940#endif
2941
2942static int snd_cmipci_free(struct cmipci *cm)
2943{
2944 if (cm->irq >= 0) {
2945 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2946 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2947 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2948 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2949 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2950 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2951 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2952
2953 /* reset mixer */
2954 snd_cmipci_mixer_write(cm, 0, 0);
2955
2956 free_irq(cm->irq, cm);
2957 }
2958
2959 snd_cmipci_free_gameport(cm);
2960 pci_release_regions(cm->pci);
2961 pci_disable_device(cm->pci);
2962 kfree(cm);
2963 return 0;
2964}
2965
2966static int snd_cmipci_dev_free(struct snd_device *device)
2967{
2968 struct cmipci *cm = device->device_data;
2969 return snd_cmipci_free(cm);
2970}
2971
2972static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2973{
2974 long iosynth;
2975 unsigned int val;
2976 struct snd_opl3 *opl3;
2977 int err;
2978
2979 if (!fm_port)
2980 goto disable_fm;
2981
2982 if (cm->chip_version >= 39) {
2983 /* first try FM regs in PCI port range */
2984 iosynth = cm->iobase + CM_REG_FM_PCI;
2985 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2986 OPL3_HW_OPL3, 1, &opl3);
2987 } else {
2988 err = -EIO;
2989 }
2990 if (err < 0) {
2991 /* then try legacy ports */
2992 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2993 iosynth = fm_port;
2994 switch (iosynth) {
2995 case 0x3E8: val |= CM_FMSEL_3E8; break;
2996 case 0x3E0: val |= CM_FMSEL_3E0; break;
2997 case 0x3C8: val |= CM_FMSEL_3C8; break;
2998 case 0x388: val |= CM_FMSEL_388; break;
2999 default:
3000 goto disable_fm;
3001 }
3002 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3003 /* enable FM */
3004 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3005
3006 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
3007 OPL3_HW_OPL3, 0, &opl3) < 0) {
3008 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
3009 "skipping...\n", iosynth);
3010 goto disable_fm;
3011 }
3012 }
3013 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
3014 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
3015 return err;
3016 }
3017 return 0;
3018
3019 disable_fm:
3020 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
3021 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3022 return 0;
3023}
3024
3025static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
3026 int dev, struct cmipci **rcmipci)
3027{
3028 struct cmipci *cm;
3029 int err;
3030 static struct snd_device_ops ops = {
3031 .dev_free = snd_cmipci_dev_free,
3032 };
3033 unsigned int val;
3034 long iomidi = 0;
3035 int integrated_midi = 0;
3036 char modelstr[16];
3037 int pcm_index, pcm_spdif_index;
3038 static DEFINE_PCI_DEVICE_TABLE(intel_82437vx) = {
3039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3040 {0},
3041 };
3042
3043 *rcmipci = NULL;
3044
3045 if ((err = pci_enable_device(pci)) < 0)
3046 return err;
3047
3048 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3049 if (cm == NULL) {
3050 pci_disable_device(pci);
3051 return -ENOMEM;
3052 }
3053
3054 spin_lock_init(&cm->reg_lock);
3055 mutex_init(&cm->open_mutex);
3056 cm->device = pci->device;
3057 cm->card = card;
3058 cm->pci = pci;
3059 cm->irq = -1;
3060 cm->channel[0].ch = 0;
3061 cm->channel[1].ch = 1;
3062 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3063
3064 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3065 kfree(cm);
3066 pci_disable_device(pci);
3067 return err;
3068 }
3069 cm->iobase = pci_resource_start(pci, 0);
3070
3071 if (request_irq(pci->irq, snd_cmipci_interrupt,
3072 IRQF_SHARED, card->driver, cm)) {
3073 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3074 snd_cmipci_free(cm);
3075 return -EBUSY;
3076 }
3077 cm->irq = pci->irq;
3078
3079 pci_set_master(cm->pci);
3080
3081 /*
3082 * check chip version, max channels and capabilities
3083 */
3084
3085 cm->chip_version = 0;
3086 cm->max_channels = 2;
3087 cm->do_soft_ac3 = soft_ac3[dev];
3088
3089 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3090 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3091 query_chip(cm);
3092 /* added -MCx suffix for chip supporting multi-channels */
3093 if (cm->can_multi_ch)
3094 sprintf(cm->card->driver + strlen(cm->card->driver),
3095 "-MC%d", cm->max_channels);
3096 else if (cm->can_ac3_sw)
3097 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3098
3099 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3100 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3101
3102#if CM_CH_PLAY == 1
3103 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3104#else
3105 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3106#endif
3107
3108 /* initialize codec registers */
3109 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3110 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3111 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3112 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3113 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3114 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3115 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3116
3117 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3118 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3119#if CM_CH_PLAY == 1
3120 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3121#else
3122 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3123#endif
3124 if (cm->chip_version) {
3125 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3126 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3127 }
3128 /* Set Bus Master Request */
3129 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3130
3131 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3132 switch (pci->device) {
3133 case PCI_DEVICE_ID_CMEDIA_CM8738:
3134 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3135 if (!pci_dev_present(intel_82437vx))
3136 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3137 break;
3138 default:
3139 break;
3140 }
3141
3142 if (cm->chip_version < 68) {
3143 val = pci->device < 0x110 ? 8338 : 8738;
3144 } else {
3145 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3146 case 0:
3147 val = 8769;
3148 break;
3149 case 2:
3150 val = 8762;
3151 break;
3152 default:
3153 switch ((pci->subsystem_vendor << 16) |
3154 pci->subsystem_device) {
3155 case 0x13f69761:
3156 case 0x584d3741:
3157 case 0x584d3751:
3158 case 0x584d3761:
3159 case 0x584d3771:
3160 case 0x72848384:
3161 val = 8770;
3162 break;
3163 default:
3164 val = 8768;
3165 break;
3166 }
3167 }
3168 }
3169 sprintf(card->shortname, "C-Media CMI%d", val);
3170 if (cm->chip_version < 68)
3171 sprintf(modelstr, " (model %d)", cm->chip_version);
3172 else
3173 modelstr[0] = '\0';
3174 sprintf(card->longname, "%s%s at %#lx, irq %i",
3175 card->shortname, modelstr, cm->iobase, cm->irq);
3176
3177 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3178 snd_cmipci_free(cm);
3179 return err;
3180 }
3181
3182 if (cm->chip_version >= 39) {
3183 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3184 if (val != 0x00 && val != 0xff) {
3185 iomidi = cm->iobase + CM_REG_MPU_PCI;
3186 integrated_midi = 1;
3187 }
3188 }
3189 if (!integrated_midi) {
3190 val = 0;
3191 iomidi = mpu_port[dev];
3192 switch (iomidi) {
3193 case 0x320: val = CM_VMPU_320; break;
3194 case 0x310: val = CM_VMPU_310; break;
3195 case 0x300: val = CM_VMPU_300; break;
3196 case 0x330: val = CM_VMPU_330; break;
3197 default:
3198 iomidi = 0; break;
3199 }
3200 if (iomidi > 0) {
3201 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3202 /* enable UART */
3203 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3204 if (inb(iomidi + 1) == 0xff) {
3205 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3206 " at %#lx\n", iomidi);
3207 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3208 CM_UART_EN);
3209 iomidi = 0;
3210 }
3211 }
3212 }
3213
3214 if (cm->chip_version < 68) {
3215 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3216 if (err < 0)
3217 return err;
3218 }
3219
3220 /* reset mixer */
3221 snd_cmipci_mixer_write(cm, 0, 0);
3222
3223 snd_cmipci_proc_init(cm);
3224
3225 /* create pcm devices */
3226 pcm_index = pcm_spdif_index = 0;
3227 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3228 return err;
3229 pcm_index++;
3230 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3231 return err;
3232 pcm_index++;
3233 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3234 pcm_spdif_index = pcm_index;
3235 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3236 return err;
3237 }
3238
3239 /* create mixer interface & switches */
3240 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3241 return err;
3242
3243 if (iomidi > 0) {
3244 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3245 iomidi,
3246 (integrated_midi ?
3247 MPU401_INFO_INTEGRATED : 0),
3248 cm->irq, 0, &cm->rmidi)) < 0) {
3249 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3250 }
3251 }
3252
3253#ifdef USE_VAR48KRATE
3254 for (val = 0; val < ARRAY_SIZE(rates); val++)
3255 snd_cmipci_set_pll(cm, rates[val], val);
3256
3257 /*
3258 * (Re-)Enable external switch spdo_48k
3259 */
3260 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3261#endif /* USE_VAR48KRATE */
3262
3263 if (snd_cmipci_create_gameport(cm, dev) < 0)
3264 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3265
3266 snd_card_set_dev(card, &pci->dev);
3267
3268 *rcmipci = cm;
3269 return 0;
3270}
3271
3272/*
3273 */
3274
3275MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3276
3277static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3278 const struct pci_device_id *pci_id)
3279{
3280 static int dev;
3281 struct snd_card *card;
3282 struct cmipci *cm;
3283 int err;
3284
3285 if (dev >= SNDRV_CARDS)
3286 return -ENODEV;
3287 if (! enable[dev]) {
3288 dev++;
3289 return -ENOENT;
3290 }
3291
3292 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3293 if (err < 0)
3294 return err;
3295
3296 switch (pci->device) {
3297 case PCI_DEVICE_ID_CMEDIA_CM8738:
3298 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3299 strcpy(card->driver, "CMI8738");
3300 break;
3301 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3302 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3303 strcpy(card->driver, "CMI8338");
3304 break;
3305 default:
3306 strcpy(card->driver, "CMIPCI");
3307 break;
3308 }
3309
3310 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3311 snd_card_free(card);
3312 return err;
3313 }
3314 card->private_data = cm;
3315
3316 if ((err = snd_card_register(card)) < 0) {
3317 snd_card_free(card);
3318 return err;
3319 }
3320 pci_set_drvdata(pci, card);
3321 dev++;
3322 return 0;
3323
3324}
3325
3326static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3327{
3328 snd_card_free(pci_get_drvdata(pci));
3329 pci_set_drvdata(pci, NULL);
3330}
3331
3332
3333#ifdef CONFIG_PM
3334/*
3335 * power management
3336 */
3337static unsigned char saved_regs[] = {
3338 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3339 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3340 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3341 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3342 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3343};
3344
3345static unsigned char saved_mixers[] = {
3346 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3347 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3348 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3349 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3350 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3351 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3352 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3353 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3354};
3355
3356static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3357{
3358 struct snd_card *card = pci_get_drvdata(pci);
3359 struct cmipci *cm = card->private_data;
3360 int i;
3361
3362 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3363
3364 snd_pcm_suspend_all(cm->pcm);
3365 snd_pcm_suspend_all(cm->pcm2);
3366 snd_pcm_suspend_all(cm->pcm_spdif);
3367
3368 /* save registers */
3369 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3370 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3371 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3372 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3373
3374 /* disable ints */
3375 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3376
3377 pci_disable_device(pci);
3378 pci_save_state(pci);
3379 pci_set_power_state(pci, pci_choose_state(pci, state));
3380 return 0;
3381}
3382
3383static int snd_cmipci_resume(struct pci_dev *pci)
3384{
3385 struct snd_card *card = pci_get_drvdata(pci);
3386 struct cmipci *cm = card->private_data;
3387 int i;
3388
3389 pci_set_power_state(pci, PCI_D0);
3390 pci_restore_state(pci);
3391 if (pci_enable_device(pci) < 0) {
3392 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3393 "disabling device\n");
3394 snd_card_disconnect(card);
3395 return -EIO;
3396 }
3397 pci_set_master(pci);
3398
3399 /* reset / initialize to a sane state */
3400 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3401 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3402 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3403 snd_cmipci_mixer_write(cm, 0, 0);
3404
3405 /* restore registers */
3406 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3407 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3408 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3409 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3410
3411 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3412 return 0;
3413}
3414#endif /* CONFIG_PM */
3415
3416static struct pci_driver driver = {
3417 .name = "C-Media PCI",
3418 .id_table = snd_cmipci_ids,
3419 .probe = snd_cmipci_probe,
3420 .remove = __devexit_p(snd_cmipci_remove),
3421#ifdef CONFIG_PM
3422 .suspend = snd_cmipci_suspend,
3423 .resume = snd_cmipci_resume,
3424#endif
3425};
3426
3427static int __init alsa_card_cmipci_init(void)
3428{
3429 return pci_register_driver(&driver);
3430}
3431
3432static void __exit alsa_card_cmipci_exit(void)
3433{
3434 pci_unregister_driver(&driver);
3435}
3436
3437module_init(alsa_card_cmipci_init)
3438module_exit(alsa_card_cmipci_exit)
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