source: GPL/trunk/alsa-kernel/pci/cmipci.c@ 424

Last change on this file since 424 was 410, checked in by Paul Smedley, 17 years ago

Update ALSA core to 1.0.19 level
File size: 106.2 KB
Line 
1/*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/* Does not work. Warning may block system in capture mode */
21/* #define USE_VAR48KRATE */
22
23#include <asm/io.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/gameport.h>
30#include <linux/moduleparam.h>
31#include <linux/mutex.h>
32#include <sound/core.h>
33#include <sound/info.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/rawmidi.h>
37#include <sound/mpu401.h>
38#include <sound/opl3.h>
39#include <sound/sb.h>
40#include <sound/asoundef.h>
41#include <sound/initval.h>
42
43MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45MODULE_LICENSE("GPL");
46MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
47 "{C-Media,CMI8738B},"
48 "{C-Media,CMI8338A},"
49 "{C-Media,CMI8338B}}");
50
51#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52#define SUPPORT_JOYSTICK 1
53#endif
54
55static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
58static long mpu_port[SNDRV_CARDS];
59#ifndef TARGET_OS2
60static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62#else
63static long fm_port[SNDRV_CARDS] = {0x388, -1,-1,-1,-1,-1,-1,-1};
64static int soft_ac3[SNDRV_CARDS] = {0,1,1,1,1,1,1,1};
65#endif
66#ifdef SUPPORT_JOYSTICK
67static int joystick_port[SNDRV_CARDS];
68#endif
69
70module_param_array(index, int, NULL, 0444);
71MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
72module_param_array(id, charp, NULL, 0444);
73MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
74module_param_array(enable, bool, NULL, 0444);
75MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
76module_param_array(mpu_port, long, NULL, 0444);
77MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
78module_param_array(fm_port, long, NULL, 0444);
79MODULE_PARM_DESC(fm_port, "FM port.");
80module_param_array(soft_ac3, bool, NULL, 0444);
81MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
82#ifdef SUPPORT_JOYSTICK
83module_param_array(joystick_port, int, NULL, 0444);
84MODULE_PARM_DESC(joystick_port, "Joystick port address.");
85#endif
86
87/*
88 * CM8x38 registers definition
89 */
90
91#define CM_REG_FUNCTRL0 0x00
92#define CM_RST_CH1 0x00080000
93#define CM_RST_CH0 0x00040000
94#define CM_CHEN1 0x00020000 /* ch1: enable */
95#define CM_CHEN0 0x00010000 /* ch0: enable */
96#define CM_PAUSE1 0x00000008 /* ch1: pause */
97#define CM_PAUSE0 0x00000004 /* ch0: pause */
98#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
99#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
100
101#define CM_REG_FUNCTRL1 0x04
102#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
103#define CM_DSFC_SHIFT 13
104#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
105#define CM_ASFC_SHIFT 10
106#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
107#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
108#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
109#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
110#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
111#define CM_BREQ 0x00000010 /* bus master enabled */
112#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
113#define CM_UART_EN 0x00000004 /* legacy UART */
114#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
115#define CM_ZVPORT 0x00000001 /* ZVPORT */
116
117#define CM_REG_CHFORMAT 0x08
118
119#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
120#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
121#define CM_CHB3D 0x20000000 /* 4 channels */
122
123#define CM_CHIP_MASK1 0x1f000000
124#define CM_CHIP_037 0x01000000
125#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
126#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
127#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
128#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
129#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
130#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
131/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
132
133#define CM_ADCBITLEN_MASK 0x0000C000
134#define CM_ADCBITLEN_16 0x00000000
135#define CM_ADCBITLEN_15 0x00004000
136#define CM_ADCBITLEN_14 0x00008000
137#define CM_ADCBITLEN_13 0x0000C000
138
139#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
140#define CM_ADCDACLEN_060 0x00000000
141#define CM_ADCDACLEN_066 0x00001000
142#define CM_ADCDACLEN_130 0x00002000
143#define CM_ADCDACLEN_280 0x00003000
144
145#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
146#define CM_ADCDLEN_ORIGINAL 0x00000000
147#define CM_ADCDLEN_EXTRA 0x00001000
148#define CM_ADCDLEN_24K 0x00002000
149#define CM_ADCDLEN_WEIGHT 0x00003000
150
151#define CM_CH1_SRATE_176K 0x00000800
152#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
153#define CM_CH1_SRATE_88K 0x00000400
154#define CM_CH0_SRATE_176K 0x00000200
155#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
156#define CM_CH0_SRATE_88K 0x00000100
157#define CM_CH0_SRATE_128K 0x00000300
158#define CM_CH0_SRATE_MASK 0x00000300
159
160#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
161#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
162#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
163#define CM_SPDLOCKED 0x00000010
164
165#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
166#define CM_CH1FMT_SHIFT 2
167#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
168#define CM_CH0FMT_SHIFT 0
169
170#define CM_REG_INT_HLDCLR 0x0C
171#define CM_CHIP_MASK2 0xff000000
172#define CM_CHIP_8768 0x20000000
173#define CM_CHIP_055 0x08000000
174#define CM_CHIP_039 0x04000000
175#define CM_CHIP_039_6CH 0x01000000
176#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
177#define CM_TDMA_INT_EN 0x00040000
178#define CM_CH1_INT_EN 0x00020000
179#define CM_CH0_INT_EN 0x00010000
180
181#define CM_REG_INT_STATUS 0x10
182#define CM_INTR 0x80000000
183#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
184#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
185#define CM_UARTINT 0x00010000
186#define CM_LTDMAINT 0x00008000
187#define CM_HTDMAINT 0x00004000
188#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
189#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
190#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
191#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
192#define CM_CH1BUSY 0x00000008
193#define CM_CH0BUSY 0x00000004
194#define CM_CHINT1 0x00000002
195#define CM_CHINT0 0x00000001
196
197#define CM_REG_LEGACY_CTRL 0x14
198#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
199#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
200#define CM_VMPU_330 0x00000000
201#define CM_VMPU_320 0x20000000
202#define CM_VMPU_310 0x40000000
203#define CM_VMPU_300 0x60000000
204#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
205#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
206#define CM_VSBSEL_220 0x00000000
207#define CM_VSBSEL_240 0x04000000
208#define CM_VSBSEL_260 0x08000000
209#define CM_VSBSEL_280 0x0C000000
210#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
211#define CM_FMSEL_388 0x00000000
212#define CM_FMSEL_3C8 0x01000000
213#define CM_FMSEL_3E0 0x02000000
214#define CM_FMSEL_3E8 0x03000000
215#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
216#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
217#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
218#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
219#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
220#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
221#define CM_C_EECS 0x00040000
222#define CM_C_EEDI46 0x00020000
223#define CM_C_EECK46 0x00010000
224#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
225#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
226#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
227#define CM_EXBASEN 0x00001000 /* external bass input enable */
228
229#define CM_REG_MISC_CTRL 0x18
230#define CM_PWD 0x80000000 /* power down */
231#define CM_RESET 0x40000000
232#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
233#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
234#define CM_TXVX 0x08000000 /* model 037? */
235#define CM_N4SPK3D 0x04000000 /* copy front to rear */
236#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
237#define CM_SPDIF48K 0x01000000 /* write */
238#define CM_SPATUS48K 0x01000000 /* read */
239#define CM_ENDBDAC 0x00800000 /* enable double dac */
240#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
241#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
242#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
243#define CM_FM_EN 0x00080000 /* enable legacy FM */
244#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
245#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
246#define CM_VIDWPDSB 0x00010000 /* model 037? */
247#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
248#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
249#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
250#define CM_VIDWPPRT 0x00002000 /* model 037? */
251#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
252#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
253#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
254#define CM_ENCENTER 0x00000080
255#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
256#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
257#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
258#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
259#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
260#define CM_UPDDMA_2048 0x00000000
261#define CM_UPDDMA_1024 0x00000004
262#define CM_UPDDMA_512 0x00000008
263#define CM_UPDDMA_256 0x0000000C
264#define CM_TWAIT_MASK 0x00000003 /* model 037 */
265#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
266#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
267
268#define CM_REG_TDMA_POSITION 0x1C
269#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
270#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
271
272 /* byte */
273#define CM_REG_MIXER0 0x20
274#define CM_REG_SBVR 0x20 /* write: sb16 version */
275#define CM_REG_DEV 0x20 /* read: hardware device version */
276
277#define CM_REG_MIXER21 0x21
278#define CM_UNKNOWN_21_MASK 0x78 /* ? */
279#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
280#define CM_PROINV 0x02 /* SBPro left/right channel switching */
281#define CM_X_SB16 0x01 /* SB16 compatible */
282
283#define CM_REG_SB16_DATA 0x22
284#define CM_REG_SB16_ADDR 0x23
285
286#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
287#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
288#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
289#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
290
291#define CM_REG_MIXER1 0x24
292#define CM_FMMUTE 0x80 /* mute FM */
293#define CM_FMMUTE_SHIFT 7
294#define CM_WSMUTE 0x40 /* mute PCM */
295#define CM_WSMUTE_SHIFT 6
296#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
297#define CM_REAR2LIN_SHIFT 5
298#define CM_REAR2FRONT 0x10 /* exchange rear/front */
299#define CM_REAR2FRONT_SHIFT 4
300#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
301#define CM_WAVEINL_SHIFT 3
302#define CM_WAVEINR 0x04 /* digical wave rec. right */
303#define CM_WAVEINR_SHIFT 2
304#define CM_X3DEN 0x02 /* 3D surround enable */
305#define CM_X3DEN_SHIFT 1
306#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
307#define CM_CDPLAY_SHIFT 0
308
309#define CM_REG_MIXER2 0x25
310#define CM_RAUXREN 0x80 /* AUX right capture */
311#define CM_RAUXREN_SHIFT 7
312#define CM_RAUXLEN 0x40 /* AUX left capture */
313#define CM_RAUXLEN_SHIFT 6
314#define CM_VAUXRM 0x20 /* AUX right mute */
315#define CM_VAUXRM_SHIFT 5
316#define CM_VAUXLM 0x10 /* AUX left mute */
317#define CM_VAUXLM_SHIFT 4
318#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
319#define CM_VADMIC_SHIFT 1
320#define CM_MICGAINZ 0x01 /* mic boost */
321#define CM_MICGAINZ_SHIFT 0
322
323#define CM_REG_MIXER3 0x24
324#define CM_REG_AUX_VOL 0x26
325#define CM_VAUXL_MASK 0xf0
326#define CM_VAUXR_MASK 0x0f
327
328#define CM_REG_MISC 0x27
329#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
330#define CM_XGPO1 0x20
331// #define CM_XGPBIO 0x04
332#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
333#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
334#define CM_SPDVALID 0x02 /* spdif input valid check */
335#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
336
337#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
338/*
339 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
340 * or identical with AC97 codec?
341 */
342#define CM_REG_EXTERN_CODEC CM_REG_AC97
343
344/*
345 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
346 */
347#define CM_REG_MPU_PCI 0x40
348
349/*
350 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
351 */
352#define CM_REG_FM_PCI 0x50
353
354/*
355 * access from SB-mixer port
356 */
357#define CM_REG_EXTENT_IND 0xf0
358#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
359#define CM_VPHONE_SHIFT 5
360#define CM_VPHOM 0x10 /* Phone mute control */
361#define CM_VSPKM 0x08 /* Speaker mute control, default high */
362#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
363#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
364#define CM_VADMIC3 0x01 /* Mic record boost */
365
366/*
367 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
368 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
369 * unit (readonly?).
370 */
371#define CM_REG_PLL 0xf8
372
373/*
374 * extended registers
375 */
376#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
377#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
378#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
379#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
380
381#define CM_REG_EXT_MISC 0x90
382#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
383#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
384#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
385#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
386#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
387#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
388#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
389#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
390
391/*
392 * size of i/o region
393 */
394#define CM_EXTENT_CODEC 0x100
395#define CM_EXTENT_MIDI 0x2
396#define CM_EXTENT_SYNTH 0x4
397
398
399/*
400 * channels for playback / capture
401 */
402#define CM_CH_PLAY 0
403#define CM_CH_CAPT 1
404
405/*
406 * flags to check device open/close
407 */
408#define CM_OPEN_NONE 0
409#define CM_OPEN_CH_MASK 0x01
410#define CM_OPEN_DAC 0x10
411#define CM_OPEN_ADC 0x20
412#define CM_OPEN_SPDIF 0x40
413#define CM_OPEN_MCHAN 0x80
414#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
415#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
416#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
417#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
418#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
419#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
420
421
422#if CM_CH_PLAY == 1
423#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
424#define CM_PLAYBACK_SPDF CM_SPDF_1
425#define CM_CAPTURE_SPDF CM_SPDF_0
426#else
427#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
428#define CM_PLAYBACK_SPDF CM_SPDF_0
429#define CM_CAPTURE_SPDF CM_SPDF_1
430#endif
431
432
433/*
434 * driver data
435 */
436
437struct cmipci_pcm {
438 struct snd_pcm_substream *substream;
439 u8 running; /* dac/adc running? */
440 u8 fmt; /* format bits */
441 u8 is_dac;
442 u8 needs_silencing;
443 unsigned int dma_size; /* in frames */
444 unsigned int shift;
445 unsigned int ch; /* channel (0/1) */
446 unsigned int offset; /* physical address of the buffer */
447};
448
449/* mixer elements toggled/resumed during ac3 playback */
450struct cmipci_mixer_auto_switches {
451 const char *name; /* switch to toggle */
452 int toggle_on; /* value to change when ac3 mode */
453};
454static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
455 {"PCM Playback Switch", 0},
456 {"IEC958 Output Switch", 1},
457 {"IEC958 Mix Analog", 0},
458 // {"IEC958 Out To DAC", 1}, // no longer used
459 {"IEC958 Loop", 0},
460};
461#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
462
463struct cmipci {
464 struct snd_card *card;
465
466 struct pci_dev *pci;
467 unsigned int device; /* device ID */
468 int irq;
469
470 unsigned long iobase;
471 unsigned int ctrl; /* FUNCTRL0 current value */
472
473 struct snd_pcm *pcm; /* DAC/ADC PCM */
474 struct snd_pcm *pcm2; /* 2nd DAC */
475 struct snd_pcm *pcm_spdif; /* SPDIF */
476
477 int chip_version;
478 int max_channels;
479 unsigned int can_ac3_sw: 1;
480 unsigned int can_ac3_hw: 1;
481 unsigned int can_multi_ch: 1;
482 unsigned int can_96k: 1; /* samplerate above 48k */
483 unsigned int do_soft_ac3: 1;
484
485 unsigned int spdif_playback_avail: 1; /* spdif ready? */
486 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
487 int spdif_counter; /* for software AC3 */
488
489 unsigned int dig_status;
490 unsigned int dig_pcm_status;
491
492 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
493
494 int opened[2]; /* open mode */
495 struct mutex open_mutex;
496
497 unsigned int mixer_insensitive: 1;
498 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
499 int mixer_res_status[CM_SAVED_MIXERS];
500
501 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
502
503 /* external MIDI */
504 struct snd_rawmidi *rmidi;
505
506#ifdef SUPPORT_JOYSTICK
507 struct gameport *gameport;
508#endif
509
510 spinlock_t reg_lock;
511
512#ifdef CONFIG_PM
513 unsigned int saved_regs[0x20];
514 unsigned char saved_mixers[0x20];
515#endif
516};
517
518
519/* read/write operations for dword register */
520static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
521{
522 outl(data, cm->iobase + cmd);
523}
524
525static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
526{
527 return inl(cm->iobase + cmd);
528}
529
530/* read/write operations for word register */
531static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
532{
533 outw(data, cm->iobase + cmd);
534}
535
536static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
537{
538 return inw(cm->iobase + cmd);
539}
540
541/* read/write operations for byte register */
542static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
543{
544 outb(data, cm->iobase + cmd);
545}
546
547static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
548{
549 return inb(cm->iobase + cmd);
550}
551
552/* bit operations for dword register */
553static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
554{
555 unsigned int val, oval;
556 val = oval = inl(cm->iobase + cmd);
557 val |= flag;
558 if (val == oval)
559 return 0;
560 outl(val, cm->iobase + cmd);
561 return 1;
562}
563
564static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
565{
566 unsigned int val, oval;
567 val = oval = inl(cm->iobase + cmd);
568 val &= ~flag;
569 if (val == oval)
570 return 0;
571 outl(val, cm->iobase + cmd);
572 return 1;
573}
574
575/* bit operations for byte register */
576static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
577{
578 unsigned char val, oval;
579 val = oval = inb(cm->iobase + cmd);
580 val |= flag;
581 if (val == oval)
582 return 0;
583 outb(val, cm->iobase + cmd);
584 return 1;
585}
586
587static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
588{
589 unsigned char val, oval;
590 val = oval = inb(cm->iobase + cmd);
591 val &= ~flag;
592 if (val == oval)
593 return 0;
594 outb(val, cm->iobase + cmd);
595 return 1;
596}
597
598
599/*
600 * PCM interface
601 */
602
603/*
604 * calculate frequency
605 */
606
607static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
608
609static unsigned int snd_cmipci_rate_freq(unsigned int rate)
610{
611 unsigned int i;
612
613 for (i = 0; i < ARRAY_SIZE(rates); i++) {
614 if (rates[i] == rate)
615 return i;
616 }
617 snd_BUG();
618 return 0;
619}
620
621#ifdef USE_VAR48KRATE
622/*
623 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
624 * does it this way .. maybe not. Never get any information from C-Media about
625 * that <werner@suse.de>.
626 */
627static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
628{
629 unsigned int delta, tolerance;
630 int xm, xn, xr;
631
632 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
633 rate <<= 1;
634 *n = -1;
635 if (*r > 0xff)
636 goto out;
637 tolerance = rate*CM_TOLERANCE_RATE;
638
639 for (xn = (1+2); xn < (0x1f+2); xn++) {
640 for (xm = (1+2); xm < (0xff+2); xm++) {
641 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
642
643 if (xr < rate)
644 delta = rate - xr;
645 else
646 delta = xr - rate;
647
648 /*
649 * If we found one, remember this,
650 * and try to find a closer one
651 */
652 if (delta < tolerance) {
653 tolerance = delta;
654 *m = xm - 2;
655 *n = xn - 2;
656 }
657 }
658 }
659out:
660 return (*n > -1);
661}
662
663/*
664 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
665 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
666 * at the register CM_REG_FUNCTRL1 (0x04).
667 * Problem: other ways are also possible (any information about that?)
668 */
669static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
670{
671 unsigned int reg = CM_REG_PLL + slot;
672 /*
673 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
674 * for DSFC/ASFC (000 upto 111).
675 */
676
677 /* FIXME: Init (Do we've to set an other register first before programming?) */
678
679 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
680 snd_cmipci_write_b(cm, reg, rate>>8);
681 snd_cmipci_write_b(cm, reg, rate&0xff);
682
683 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
684}
685#endif /* USE_VAR48KRATE */
686
687static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *hw_params)
689{
690 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
691}
692
693static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
694 struct snd_pcm_hw_params *hw_params)
695{
696 struct cmipci *cm = snd_pcm_substream_chip(substream);
697 if (params_channels(hw_params) > 2) {
698 mutex_lock(&cm->open_mutex);
699 if (cm->opened[CM_CH_PLAY]) {
700 mutex_unlock(&cm->open_mutex);
701 return -EBUSY;
702 }
703 /* reserve the channel A */
704 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
705 mutex_unlock(&cm->open_mutex);
706 }
707 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
708}
709
710static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
711{
712 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
713 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
714 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
715 udelay(10);
716}
717
718static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
719{
720 return snd_pcm_lib_free_pages(substream);
721}
722
723
724/*
725 */
726
727static unsigned int hw_channels[] = {1, 2, 4, 6, 8};
728static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
729 .count = 3,
730 .list = hw_channels,
731 .mask = 0,
732};
733static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
734 .count = 4,
735 .list = hw_channels,
736 .mask = 0,
737};
738static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
739 .count = 5,
740 .list = hw_channels,
741 .mask = 0,
742};
743
744static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
745{
746 if (channels > 2) {
747 if (!cm->can_multi_ch || !rec->ch)
748 return -EINVAL;
749 if (rec->fmt != 0x03) /* stereo 16bit only */
750 return -EINVAL;
751 }
752
753 if (cm->can_multi_ch) {
754 spin_lock_irq(&cm->reg_lock);
755 if (channels > 2) {
756 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
757 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
758 } else {
759 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
760 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
761 }
762 if (channels == 8)
763 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
764 else
765 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
766 if (channels == 6) {
767 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
768 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
769 } else {
770 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
771 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
772 }
773 if (channels == 4)
774 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
775 else
776 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
777 spin_unlock_irq(&cm->reg_lock);
778 }
779 return 0;
780}
781
782
783/*
784 * prepare playback/capture channel
785 * channel to be used must have been set in rec->ch.
786 */
787static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
788 struct snd_pcm_substream *substream)
789{
790 unsigned int reg, freq, freq_ext, val;
791 unsigned int period_size;
792 struct snd_pcm_runtime *runtime = substream->runtime;
793
794 rec->fmt = 0;
795 rec->shift = 0;
796 if (snd_pcm_format_width(runtime->format) >= 16) {
797 rec->fmt |= 0x02;
798 if (snd_pcm_format_width(runtime->format) > 16)
799 rec->shift++; /* 24/32bit */
800 }
801 if (runtime->channels > 1)
802 rec->fmt |= 0x01;
803 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
804 snd_printd("cannot set dac channels\n");
805 return -EINVAL;
806 }
807
808 rec->offset = runtime->dma_addr;
809 /* buffer and period sizes in frame */
810 rec->dma_size = runtime->buffer_size << rec->shift;
811 period_size = runtime->period_size << rec->shift;
812 if (runtime->channels > 2) {
813 /* multi-channels */
814 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
815 period_size = (period_size * runtime->channels) / 2;
816 }
817
818 spin_lock_irq(&cm->reg_lock);
819
820 /* set buffer address */
821 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
822 snd_cmipci_write(cm, reg, rec->offset);
823 /* program sample counts */
824 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
825 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
826 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
827
828 /* set adc/dac flag */
829 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
830 if (rec->is_dac)
831 cm->ctrl &= ~val;
832 else
833 cm->ctrl |= val;
834 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
835 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
836
837 /* set sample rate */
838 freq = 0;
839 freq_ext = 0;
840 if (runtime->rate > 48000)
841 switch (runtime->rate) {
842 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
843 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
844 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
845 default: snd_BUG(); break;
846 }
847 else
848 freq = snd_cmipci_rate_freq(runtime->rate);
849 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
850 if (rec->ch) {
851 val &= ~CM_DSFC_MASK;
852 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
853 } else {
854 val &= ~CM_ASFC_MASK;
855 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
856 }
857 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
858 //snd_printd("cmipci: functrl1 = %08x\n", val);
859
860 /* set format */
861 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
862 if (rec->ch) {
863 val &= ~CM_CH1FMT_MASK;
864 val |= rec->fmt << CM_CH1FMT_SHIFT;
865 } else {
866 val &= ~CM_CH0FMT_MASK;
867 val |= rec->fmt << CM_CH0FMT_SHIFT;
868 }
869 if (cm->can_96k) {
870 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
871 val |= freq_ext << (rec->ch * 2);
872 }
873 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
874 //snd_printd("cmipci: chformat = %08x\n", val);
875
876 if (!rec->is_dac && cm->chip_version) {
877 if (runtime->rate > 44100)
878 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
879 else
880 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
881 }
882
883 rec->running = 0;
884 spin_unlock_irq(&cm->reg_lock);
885
886 return 0;
887}
888
889/*
890 * PCM trigger/stop
891 */
892static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
893 int cmd)
894{
895 unsigned int inthld, chen, reset, pause;
896 int result = 0;
897
898 inthld = CM_CH0_INT_EN << rec->ch;
899 chen = CM_CHEN0 << rec->ch;
900 reset = CM_RST_CH0 << rec->ch;
901 pause = CM_PAUSE0 << rec->ch;
902
903 spin_lock(&cm->reg_lock);
904 switch (cmd) {
905 case SNDRV_PCM_TRIGGER_START:
906 rec->running = 1;
907 /* set interrupt */
908 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
909 cm->ctrl |= chen;
910 /* enable channel */
911 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
912 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
913 break;
914 case SNDRV_PCM_TRIGGER_STOP:
915 rec->running = 0;
916 /* disable interrupt */
917 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
918 /* reset */
919 cm->ctrl &= ~chen;
920 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
921 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
922 rec->needs_silencing = rec->is_dac;
923 break;
924 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
925 case SNDRV_PCM_TRIGGER_SUSPEND:
926 cm->ctrl |= pause;
927 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
928 break;
929 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
930 case SNDRV_PCM_TRIGGER_RESUME:
931 cm->ctrl &= ~pause;
932 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
933 break;
934 default:
935 result = -EINVAL;
936 break;
937 }
938 spin_unlock(&cm->reg_lock);
939 return result;
940}
941
942/*
943 * return the current pointer
944 */
945static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
946 struct snd_pcm_substream *substream)
947{
948 size_t ptr;
949 unsigned int reg;
950 if (!rec->running)
951 return 0;
952#if 1 // this seems better..
953 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
954 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
955 ptr >>= rec->shift;
956#else
957 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
958 ptr = snd_cmipci_read(cm, reg) - rec->offset;
959 ptr = bytes_to_frames(substream->runtime, ptr);
960#endif
961 if (substream->runtime->channels > 2)
962 ptr = (ptr * 2) / substream->runtime->channels;
963 return ptr;
964}
965
966/*
967 * playback
968 */
969
970static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
971 int cmd)
972{
973 struct cmipci *cm = snd_pcm_substream_chip(substream);
974 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
975}
976
977static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
978{
979 struct cmipci *cm = snd_pcm_substream_chip(substream);
980 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
981}
982
983
984
985/*
986 * capture
987 */
988
989static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
990 int cmd)
991{
992 struct cmipci *cm = snd_pcm_substream_chip(substream);
993 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
994}
995
996static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
997{
998 struct cmipci *cm = snd_pcm_substream_chip(substream);
999 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
1000}
1001
1002
1003/*
1004 * hw preparation for spdif
1005 */
1006
1007static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
1008 struct snd_ctl_elem_info *uinfo)
1009{
1010 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1011 uinfo->count = 1;
1012 return 0;
1013}
1014
1015static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1017{
1018 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1019 int i;
1020
1021 spin_lock_irq(&chip->reg_lock);
1022 for (i = 0; i < 4; i++)
1023 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1024 spin_unlock_irq(&chip->reg_lock);
1025 return 0;
1026}
1027
1028static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1029 struct snd_ctl_elem_value *ucontrol)
1030{
1031 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1032 int i, change;
1033 unsigned int val;
1034
1035 val = 0;
1036 spin_lock_irq(&chip->reg_lock);
1037 for (i = 0; i < 4; i++)
1038 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1039 change = val != chip->dig_status;
1040 chip->dig_status = val;
1041 spin_unlock_irq(&chip->reg_lock);
1042 return change;
1043}
1044
1045static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
1046{
1047 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1048 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1049 .info = snd_cmipci_spdif_default_info,
1050 .get = snd_cmipci_spdif_default_get,
1051 .put = snd_cmipci_spdif_default_put
1052};
1053
1054static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1055 struct snd_ctl_elem_info *uinfo)
1056{
1057 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1058 uinfo->count = 1;
1059 return 0;
1060}
1061
1062static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1063 struct snd_ctl_elem_value *ucontrol)
1064{
1065 ucontrol->value.iec958.status[0] = 0xff;
1066 ucontrol->value.iec958.status[1] = 0xff;
1067 ucontrol->value.iec958.status[2] = 0xff;
1068 ucontrol->value.iec958.status[3] = 0xff;
1069 return 0;
1070}
1071
1072static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1073{
1074 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1075 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1076 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1077 .info = snd_cmipci_spdif_mask_info,
1078 .get = snd_cmipci_spdif_mask_get,
1079};
1080
1081static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1082 struct snd_ctl_elem_info *uinfo)
1083{
1084 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1085 uinfo->count = 1;
1086 return 0;
1087}
1088
1089static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1090 struct snd_ctl_elem_value *ucontrol)
1091{
1092 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1093 int i;
1094
1095 spin_lock_irq(&chip->reg_lock);
1096 for (i = 0; i < 4; i++)
1097 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1098 spin_unlock_irq(&chip->reg_lock);
1099 return 0;
1100}
1101
1102static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1103 struct snd_ctl_elem_value *ucontrol)
1104{
1105 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1106 int i, change;
1107 unsigned int val;
1108
1109 val = 0;
1110 spin_lock_irq(&chip->reg_lock);
1111 for (i = 0; i < 4; i++)
1112 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1113 change = val != chip->dig_pcm_status;
1114 chip->dig_pcm_status = val;
1115 spin_unlock_irq(&chip->reg_lock);
1116 return change;
1117}
1118
1119static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1120{
1121 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1122 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1123 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1124 .info = snd_cmipci_spdif_stream_info,
1125 .get = snd_cmipci_spdif_stream_get,
1126 .put = snd_cmipci_spdif_stream_put
1127};
1128
1129/*
1130 */
1131
1132/* save mixer setting and mute for AC3 playback */
1133static int save_mixer_state(struct cmipci *cm)
1134{
1135 if (! cm->mixer_insensitive) {
1136 struct snd_ctl_elem_value *val;
1137 unsigned int i;
1138
1139 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1140 if (!val)
1141 return -ENOMEM;
1142 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1143 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1144 if (ctl) {
1145 int event;
1146 memset(val, 0, sizeof(*val));
1147 ctl->get(ctl, val);
1148 cm->mixer_res_status[i] = val->value.integer.value[0];
1149 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1150 event = SNDRV_CTL_EVENT_MASK_INFO;
1151 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1152 ctl->put(ctl, val); /* toggle */
1153 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1154 }
1155 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1156 snd_ctl_notify(cm->card, event, &ctl->id);
1157 }
1158 }
1159 kfree(val);
1160 cm->mixer_insensitive = 1;
1161 }
1162 return 0;
1163}
1164
1165
1166/* restore the previously saved mixer status */
1167static void restore_mixer_state(struct cmipci *cm)
1168{
1169 if (cm->mixer_insensitive) {
1170 struct snd_ctl_elem_value *val;
1171 unsigned int i;
1172
1173 val = kmalloc(sizeof(*val), GFP_KERNEL);
1174 if (!val)
1175 return;
1176 cm->mixer_insensitive = 0; /* at first clear this;
1177 otherwise the changes will be ignored */
1178 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1179 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1180 if (ctl) {
1181 int event;
1182
1183 memset(val, 0, sizeof(*val));
1184 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1185 ctl->get(ctl, val);
1186 event = SNDRV_CTL_EVENT_MASK_INFO;
1187 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1188 val->value.integer.value[0] = cm->mixer_res_status[i];
1189 ctl->put(ctl, val);
1190 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1191 }
1192 snd_ctl_notify(cm->card, event, &ctl->id);
1193 }
1194 }
1195 kfree(val);
1196 }
1197}
1198
1199/* spinlock held! */
1200static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1201{
1202 if (do_ac3) {
1203 /* AC3EN for 037 */
1204 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1205 /* AC3EN for 039 */
1206 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1207
1208 if (cm->can_ac3_hw) {
1209 /* SPD24SEL for 037, 0x02 */
1210 /* SPD24SEL for 039, 0x20, but cannot be set */
1211 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1212 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1213 } else { /* can_ac3_sw */
1214 /* SPD32SEL for 037 & 039, 0x20 */
1215 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1216 /* set 176K sample rate to fix 033 HW bug */
1217 if (cm->chip_version == 33) {
1218 if (rate >= 48000) {
1219 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1220 } else {
1221 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1222 }
1223 }
1224 }
1225
1226 } else {
1227 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1228 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1229
1230 if (cm->can_ac3_hw) {
1231 /* chip model >= 37 */
1232 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1233 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1234 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1235 } else {
1236 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1237 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1238 }
1239 } else {
1240 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1241 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1242 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1243 }
1244 }
1245}
1246
1247static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1248{
1249 int rate, err;
1250
1251 rate = subs->runtime->rate;
1252
1253 if (up && do_ac3)
1254 if ((err = save_mixer_state(cm)) < 0)
1255 return err;
1256
1257 spin_lock_irq(&cm->reg_lock);
1258 cm->spdif_playback_avail = up;
1259 if (up) {
1260 /* they are controlled via "IEC958 Output Switch" */
1261 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1262 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1263 if (cm->spdif_playback_enabled)
1264 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1265 setup_ac3(cm, subs, do_ac3, rate);
1266
1267 if (rate == 48000 || rate == 96000)
1268 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1269 else
1270 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1271 if (rate > 48000)
1272 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1273 else
1274 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1275 } else {
1276 /* they are controlled via "IEC958 Output Switch" */
1277 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1278 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1279 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1280 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1281 setup_ac3(cm, subs, 0, 0);
1282 }
1283 spin_unlock_irq(&cm->reg_lock);
1284 return 0;
1285}
1286
1287
1288/*
1289 * preparation
1290 */
1291
1292/* playback - enable spdif only on the certain condition */
1293static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1294{
1295 struct cmipci *cm = snd_pcm_substream_chip(substream);
1296 int rate = substream->runtime->rate;
1297 int err, do_spdif, do_ac3 = 0;
1298
1299 do_spdif = (rate >= 44100 && rate <= 96000 &&
1300 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1301 substream->runtime->channels == 2);
1302 if (do_spdif && cm->can_ac3_hw)
1303 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1304 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1305 return err;
1306 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1307}
1308
1309/* playback (via device #2) - enable spdif always */
1310static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1311{
1312 struct cmipci *cm = snd_pcm_substream_chip(substream);
1313 int err, do_ac3;
1314
1315 if (cm->can_ac3_hw)
1316 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1317 else
1318 do_ac3 = 1; /* doesn't matter */
1319 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1320 return err;
1321 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1322}
1323
1324/*
1325 * Apparently, the samples last played on channel A stay in some buffer, even
1326 * after the channel is reset, and get added to the data for the rear DACs when
1327 * playing a multichannel stream on channel B. This is likely to generate
1328 * wraparounds and thus distortions.
1329 * To avoid this, we play at least one zero sample after the actual stream has
1330 * stopped.
1331 */
1332static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1333{
1334 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1335 unsigned int reg, val;
1336
1337 if (rec->needs_silencing && runtime && runtime->dma_area) {
1338 /* set up a small silence buffer */
1339 memset(runtime->dma_area, 0, PAGE_SIZE);
1340 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1341 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1342 snd_cmipci_write(cm, reg, val);
1343
1344 /* configure for 16 bits, 2 channels, 8 kHz */
1345 if (runtime->channels > 2)
1346 set_dac_channels(cm, rec, 2);
1347 spin_lock_irq(&cm->reg_lock);
1348 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1349 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1350 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1351 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1352 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1353 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1354 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1355 if (cm->can_96k)
1356 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1357 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1358
1359 /* start stream (we don't need interrupts) */
1360 cm->ctrl |= CM_CHEN0 << rec->ch;
1361 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1362 spin_unlock_irq(&cm->reg_lock);
1363
1364 msleep(1);
1365
1366 /* stop and reset stream */
1367 spin_lock_irq(&cm->reg_lock);
1368 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1369 val = CM_RST_CH0 << rec->ch;
1370 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1371 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1372 spin_unlock_irq(&cm->reg_lock);
1373
1374 rec->needs_silencing = 0;
1375 }
1376}
1377
1378static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1379{
1380 struct cmipci *cm = snd_pcm_substream_chip(substream);
1381 setup_spdif_playback(cm, substream, 0, 0);
1382 restore_mixer_state(cm);
1383 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1384 return snd_cmipci_hw_free(substream);
1385}
1386
1387static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1388{
1389 struct cmipci *cm = snd_pcm_substream_chip(substream);
1390 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1391 return snd_cmipci_hw_free(substream);
1392}
1393
1394/* capture */
1395static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1396{
1397 struct cmipci *cm = snd_pcm_substream_chip(substream);
1398 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1399}
1400
1401/* capture with spdif (via device #2) */
1402static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1403{
1404 struct cmipci *cm = snd_pcm_substream_chip(substream);
1405
1406 spin_lock_irq(&cm->reg_lock);
1407 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1408 if (cm->can_96k) {
1409 if (substream->runtime->rate > 48000)
1410 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1411 else
1412 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1413 }
1414 if (snd_pcm_format_width(substream->runtime->format) > 16)
1415 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1416 else
1417 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1418
1419 spin_unlock_irq(&cm->reg_lock);
1420
1421 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1422}
1423
1424static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1425{
1426 struct cmipci *cm = snd_pcm_substream_chip(subs);
1427
1428 spin_lock_irq(&cm->reg_lock);
1429 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1430 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1431 spin_unlock_irq(&cm->reg_lock);
1432
1433 return snd_cmipci_hw_free(subs);
1434}
1435
1436
1437/*
1438 * interrupt handler
1439 */
1440static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1441{
1442 struct cmipci *cm = dev_id;
1443 unsigned int status, mask = 0;
1444
1445 /* fastpath out, to ease interrupt sharing */
1446 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1447 if (!(status & CM_INTR))
1448 return IRQ_NONE;
1449
1450 /* acknowledge interrupt */
1451 spin_lock(&cm->reg_lock);
1452 if (status & CM_CHINT0)
1453 mask |= CM_CH0_INT_EN;
1454 if (status & CM_CHINT1)
1455 mask |= CM_CH1_INT_EN;
1456 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1457 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1458 spin_unlock(&cm->reg_lock);
1459
1460 if (cm->rmidi && (status & CM_UARTINT))
1461 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1462
1463 if (cm->pcm) {
1464 if ((status & CM_CHINT0) && cm->channel[0].running)
1465 snd_pcm_period_elapsed(cm->channel[0].substream);
1466 if ((status & CM_CHINT1) && cm->channel[1].running)
1467 snd_pcm_period_elapsed(cm->channel[1].substream);
1468 }
1469 return IRQ_HANDLED;
1470}
1471
1472/*
1473 * h/w infos
1474 */
1475
1476/* playback on channel A */
1477static struct snd_pcm_hardware snd_cmipci_playback =
1478{
1479 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1480 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1481 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1482 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1483 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1484 .rate_min = 5512,
1485 .rate_max = 48000,
1486 .channels_min = 1,
1487 .channels_max = 2,
1488 .buffer_bytes_max = (128*1024),
1489 .period_bytes_min = 64,
1490 .period_bytes_max = (128*1024),
1491 .periods_min = 2,
1492 .periods_max = 1024,
1493 .fifo_size = 0,
1494};
1495
1496/* capture on channel B */
1497static struct snd_pcm_hardware snd_cmipci_capture =
1498{
1499 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1500 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1501 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1502 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1503 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1504 .rate_min = 5512,
1505 .rate_max = 48000,
1506 .channels_min = 1,
1507 .channels_max = 2,
1508 .buffer_bytes_max = (128*1024),
1509 .period_bytes_min = 64,
1510 .period_bytes_max = (128*1024),
1511 .periods_min = 2,
1512 .periods_max = 1024,
1513 .fifo_size = 0,
1514};
1515
1516/* playback on channel B - stereo 16bit only? */
1517static struct snd_pcm_hardware snd_cmipci_playback2 =
1518{
1519 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1520 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1521 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1522 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1523 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1524 .rate_min = 5512,
1525 .rate_max = 48000,
1526 .channels_min = 2,
1527 .channels_max = 2,
1528 .buffer_bytes_max = (128*1024),
1529 .period_bytes_min = 64,
1530 .period_bytes_max = (128*1024),
1531 .periods_min = 2,
1532 .periods_max = 1024,
1533 .fifo_size = 0,
1534};
1535
1536/* spdif playback on channel A */
1537static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1538{
1539 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1540 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1541 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1542 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1543 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1544 .rate_min = 44100,
1545 .rate_max = 48000,
1546 .channels_min = 2,
1547 .channels_max = 2,
1548 .buffer_bytes_max = (128*1024),
1549 .period_bytes_min = 64,
1550 .period_bytes_max = (128*1024),
1551 .periods_min = 2,
1552 .periods_max = 1024,
1553 .fifo_size = 0,
1554};
1555
1556/* spdif playback on channel A (32bit, IEC958 subframes) */
1557static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1558{
1559 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1560 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1561 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1562 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1563 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1564 .rate_min = 44100,
1565 .rate_max = 48000,
1566 .channels_min = 2,
1567 .channels_max = 2,
1568 .buffer_bytes_max = (128*1024),
1569 .period_bytes_min = 64,
1570 .period_bytes_max = (128*1024),
1571 .periods_min = 2,
1572 .periods_max = 1024,
1573 .fifo_size = 0,
1574};
1575
1576/* spdif capture on channel B */
1577static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1578{
1579 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1580 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1581 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1582 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1583 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1584 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1585 .rate_min = 44100,
1586 .rate_max = 48000,
1587 .channels_min = 2,
1588 .channels_max = 2,
1589 .buffer_bytes_max = (128*1024),
1590 .period_bytes_min = 64,
1591 .period_bytes_max = (128*1024),
1592 .periods_min = 2,
1593 .periods_max = 1024,
1594 .fifo_size = 0,
1595};
1596
1597static unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1598 32000, 44100, 48000, 88200, 96000, 128000 };
1599static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1600 .count = ARRAY_SIZE(rate_constraints),
1601 .list = rate_constraints,
1602 .mask = 0,
1603};
1604
1605/*
1606 * check device open/close
1607 */
1608static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1609{
1610 int ch = mode & CM_OPEN_CH_MASK;
1611
1612 /* FIXME: a file should wait until the device becomes free
1613 * when it's opened on blocking mode. however, since the current
1614 * pcm framework doesn't pass file pointer before actually opened,
1615 * we can't know whether blocking mode or not in open callback..
1616 */
1617 mutex_lock(&cm->open_mutex);
1618 if (cm->opened[ch]) {
1619 mutex_unlock(&cm->open_mutex);
1620 return -EBUSY;
1621 }
1622 cm->opened[ch] = mode;
1623 cm->channel[ch].substream = subs;
1624 if (! (mode & CM_OPEN_DAC)) {
1625 /* disable dual DAC mode */
1626 cm->channel[ch].is_dac = 0;
1627 spin_lock_irq(&cm->reg_lock);
1628 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1629 spin_unlock_irq(&cm->reg_lock);
1630 }
1631 mutex_unlock(&cm->open_mutex);
1632 return 0;
1633}
1634
1635static void close_device_check(struct cmipci *cm, int mode)
1636{
1637 int ch = mode & CM_OPEN_CH_MASK;
1638
1639 mutex_lock(&cm->open_mutex);
1640 if (cm->opened[ch] == mode) {
1641 if (cm->channel[ch].substream) {
1642 snd_cmipci_ch_reset(cm, ch);
1643 cm->channel[ch].running = 0;
1644 cm->channel[ch].substream = NULL;
1645 }
1646 cm->opened[ch] = 0;
1647 if (! cm->channel[ch].is_dac) {
1648 /* enable dual DAC mode again */
1649 cm->channel[ch].is_dac = 1;
1650 spin_lock_irq(&cm->reg_lock);
1651 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1652 spin_unlock_irq(&cm->reg_lock);
1653 }
1654 }
1655 mutex_unlock(&cm->open_mutex);
1656}
1657
1658/*
1659 */
1660
1661static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1662{
1663 struct cmipci *cm = snd_pcm_substream_chip(substream);
1664 struct snd_pcm_runtime *runtime = substream->runtime;
1665 int err;
1666
1667 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1668 return err;
1669 runtime->hw = snd_cmipci_playback;
1670 if (cm->chip_version == 68) {
1671 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1672 SNDRV_PCM_RATE_96000;
1673 runtime->hw.rate_max = 96000;
1674 } else if (cm->chip_version == 55) {
1675 err = snd_pcm_hw_constraint_list(runtime, 0,
1676 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1677 if (err < 0)
1678 return err;
1679 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1680 runtime->hw.rate_max = 128000;
1681 }
1682 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1683 cm->dig_pcm_status = cm->dig_status;
1684 return 0;
1685}
1686
1687static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1688{
1689 struct cmipci *cm = snd_pcm_substream_chip(substream);
1690 struct snd_pcm_runtime *runtime = substream->runtime;
1691 int err;
1692
1693 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1694 return err;
1695 runtime->hw = snd_cmipci_capture;
1696 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1697 runtime->hw.rate_min = 41000;
1698 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1699 } else if (cm->chip_version == 55) {
1700 err = snd_pcm_hw_constraint_list(runtime, 0,
1701 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1702 if (err < 0)
1703 return err;
1704 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1705 runtime->hw.rate_max = 128000;
1706 }
1707 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1708 return 0;
1709}
1710
1711static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1712{
1713 struct cmipci *cm = snd_pcm_substream_chip(substream);
1714 struct snd_pcm_runtime *runtime = substream->runtime;
1715 int err;
1716
1717 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1718 return err;
1719 runtime->hw = snd_cmipci_playback2;
1720 mutex_lock(&cm->open_mutex);
1721 if (! cm->opened[CM_CH_PLAY]) {
1722 if (cm->can_multi_ch) {
1723 runtime->hw.channels_max = cm->max_channels;
1724 if (cm->max_channels == 4)
1725 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1726 else if (cm->max_channels == 6)
1727 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1728 else if (cm->max_channels == 8)
1729 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1730 }
1731 }
1732 mutex_unlock(&cm->open_mutex);
1733 if (cm->chip_version == 68) {
1734 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1735 SNDRV_PCM_RATE_96000;
1736 runtime->hw.rate_max = 96000;
1737 } else if (cm->chip_version == 55) {
1738 err = snd_pcm_hw_constraint_list(runtime, 0,
1739 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1740 if (err < 0)
1741 return err;
1742 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1743 runtime->hw.rate_max = 128000;
1744 }
1745 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1746 return 0;
1747}
1748
1749static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1750{
1751 struct cmipci *cm = snd_pcm_substream_chip(substream);
1752 struct snd_pcm_runtime *runtime = substream->runtime;
1753 int err;
1754
1755 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1756 return err;
1757 if (cm->can_ac3_hw) {
1758 runtime->hw = snd_cmipci_playback_spdif;
1759 if (cm->chip_version >= 37) {
1760 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1761 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1762 }
1763 if (cm->can_96k) {
1764 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1765 SNDRV_PCM_RATE_96000;
1766 runtime->hw.rate_max = 96000;
1767 }
1768 } else {
1769 runtime->hw = snd_cmipci_playback_iec958_subframe;
1770 }
1771 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1772 cm->dig_pcm_status = cm->dig_status;
1773 return 0;
1774}
1775
1776static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1777{
1778 struct cmipci *cm = snd_pcm_substream_chip(substream);
1779 struct snd_pcm_runtime *runtime = substream->runtime;
1780 int err;
1781
1782 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1783 return err;
1784 runtime->hw = snd_cmipci_capture_spdif;
1785 if (cm->can_96k && !(cm->chip_version == 68)) {
1786 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1787 SNDRV_PCM_RATE_96000;
1788 runtime->hw.rate_max = 96000;
1789 }
1790 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1791 return 0;
1792}
1793
1794
1795/*
1796 */
1797
1798static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1799{
1800 struct cmipci *cm = snd_pcm_substream_chip(substream);
1801 close_device_check(cm, CM_OPEN_PLAYBACK);
1802 return 0;
1803}
1804
1805static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1806{
1807 struct cmipci *cm = snd_pcm_substream_chip(substream);
1808 close_device_check(cm, CM_OPEN_CAPTURE);
1809 return 0;
1810}
1811
1812static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1813{
1814 struct cmipci *cm = snd_pcm_substream_chip(substream);
1815 close_device_check(cm, CM_OPEN_PLAYBACK2);
1816 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1817 return 0;
1818}
1819
1820static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1821{
1822 struct cmipci *cm = snd_pcm_substream_chip(substream);
1823 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1824 return 0;
1825}
1826
1827static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1828{
1829 struct cmipci *cm = snd_pcm_substream_chip(substream);
1830 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1831 return 0;
1832}
1833
1834
1835/*
1836 */
1837
1838static struct snd_pcm_ops snd_cmipci_playback_ops = {
1839 .open = snd_cmipci_playback_open,
1840 .close = snd_cmipci_playback_close,
1841 .ioctl = snd_pcm_lib_ioctl,
1842 .hw_params = snd_cmipci_hw_params,
1843 .hw_free = snd_cmipci_playback_hw_free,
1844 .prepare = snd_cmipci_playback_prepare,
1845 .trigger = snd_cmipci_playback_trigger,
1846 .pointer = snd_cmipci_playback_pointer,
1847};
1848
1849static struct snd_pcm_ops snd_cmipci_capture_ops = {
1850 .open = snd_cmipci_capture_open,
1851 .close = snd_cmipci_capture_close,
1852 .ioctl = snd_pcm_lib_ioctl,
1853 .hw_params = snd_cmipci_hw_params,
1854 .hw_free = snd_cmipci_hw_free,
1855 .prepare = snd_cmipci_capture_prepare,
1856 .trigger = snd_cmipci_capture_trigger,
1857 .pointer = snd_cmipci_capture_pointer,
1858};
1859
1860static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1861 .open = snd_cmipci_playback2_open,
1862 .close = snd_cmipci_playback2_close,
1863 .ioctl = snd_pcm_lib_ioctl,
1864 .hw_params = snd_cmipci_playback2_hw_params,
1865 .hw_free = snd_cmipci_playback2_hw_free,
1866 .prepare = snd_cmipci_capture_prepare, /* channel B */
1867 .trigger = snd_cmipci_capture_trigger, /* channel B */
1868 .pointer = snd_cmipci_capture_pointer, /* channel B */
1869};
1870
1871static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1872 .open = snd_cmipci_playback_spdif_open,
1873 .close = snd_cmipci_playback_spdif_close,
1874 .ioctl = snd_pcm_lib_ioctl,
1875 .hw_params = snd_cmipci_hw_params,
1876 .hw_free = snd_cmipci_playback_hw_free,
1877 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1878 .trigger = snd_cmipci_playback_trigger,
1879 .pointer = snd_cmipci_playback_pointer,
1880};
1881
1882static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1883 .open = snd_cmipci_capture_spdif_open,
1884 .close = snd_cmipci_capture_spdif_close,
1885 .ioctl = snd_pcm_lib_ioctl,
1886 .hw_params = snd_cmipci_hw_params,
1887 .hw_free = snd_cmipci_capture_spdif_hw_free,
1888 .prepare = snd_cmipci_capture_spdif_prepare,
1889 .trigger = snd_cmipci_capture_trigger,
1890 .pointer = snd_cmipci_capture_pointer,
1891};
1892
1893
1894/*
1895 */
1896
1897static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1898{
1899 struct snd_pcm *pcm;
1900 int err;
1901
1902 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1903 if (err < 0)
1904 return err;
1905
1906 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1907 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1908
1909 pcm->private_data = cm;
1910 pcm->info_flags = 0;
1911 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1912 cm->pcm = pcm;
1913
1914 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1915 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1916
1917 return 0;
1918}
1919
1920static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1921{
1922 struct snd_pcm *pcm;
1923 int err;
1924
1925 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1926 if (err < 0)
1927 return err;
1928
1929 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1930
1931 pcm->private_data = cm;
1932 pcm->info_flags = 0;
1933 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1934 cm->pcm2 = pcm;
1935
1936 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1937 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1938
1939 return 0;
1940}
1941
1942static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1943{
1944 struct snd_pcm *pcm;
1945 int err;
1946
1947 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1948 if (err < 0)
1949 return err;
1950
1951 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1952 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1953
1954 pcm->private_data = cm;
1955 pcm->info_flags = 0;
1956 strcpy(pcm->name, "C-Media PCI IEC958");
1957 cm->pcm_spdif = pcm;
1958
1959 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1960 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1961
1962 return 0;
1963}
1964
1965/*
1966 * mixer interface:
1967 * - CM8338/8738 has a compatible mixer interface with SB16, but
1968 * lack of some elements like tone control, i/o gain and AGC.
1969 * - Access to native registers:
1970 * - A 3D switch
1971 * - Output mute switches
1972 */
1973
1974static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1975{
1976 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1977 outb(data, s->iobase + CM_REG_SB16_DATA);
1978}
1979
1980static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1981{
1982 unsigned char v;
1983
1984 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1985 v = inb(s->iobase + CM_REG_SB16_DATA);
1986 return v;
1987}
1988
1989/*
1990 * general mixer element
1991 */
1992struct cmipci_sb_reg {
1993 unsigned int left_reg, right_reg;
1994 unsigned int left_shift, right_shift;
1995 unsigned int mask;
1996 unsigned int invert: 1;
1997 unsigned int stereo: 1;
1998};
1999
2000#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
2001 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
2002
2003#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
2004{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2005 .info = snd_cmipci_info_volume, \
2006 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2007 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2008}
2009
2010#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2011#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2012#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2013#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2014
2015static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2016{
2017 r->left_reg = val & 0xff;
2018 r->right_reg = (val >> 8) & 0xff;
2019 r->left_shift = (val >> 16) & 0x07;
2020 r->right_shift = (val >> 19) & 0x07;
2021 r->invert = (val >> 22) & 1;
2022 r->stereo = (val >> 23) & 1;
2023 r->mask = (val >> 24) & 0xff;
2024}
2025
2026static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2027 struct snd_ctl_elem_info *uinfo)
2028{
2029 struct cmipci_sb_reg reg;
2030
2031 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2032 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2033 uinfo->count = reg.stereo + 1;
2034 uinfo->value.integer.min = 0;
2035 uinfo->value.integer.max = reg.mask;
2036 return 0;
2037}
2038
2039static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2040 struct snd_ctl_elem_value *ucontrol)
2041{
2042 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2043 struct cmipci_sb_reg reg;
2044 int val;
2045
2046 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2047 spin_lock_irq(&cm->reg_lock);
2048 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2049 if (reg.invert)
2050 val = reg.mask - val;
2051 ucontrol->value.integer.value[0] = val;
2052 if (reg.stereo) {
2053 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2054 if (reg.invert)
2055 val = reg.mask - val;
2056 ucontrol->value.integer.value[1] = val;
2057 }
2058 spin_unlock_irq(&cm->reg_lock);
2059 return 0;
2060}
2061
2062static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2063 struct snd_ctl_elem_value *ucontrol)
2064{
2065 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2066 struct cmipci_sb_reg reg;
2067 int change;
2068 int left, right, oleft, oright;
2069
2070 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2071 left = ucontrol->value.integer.value[0] & reg.mask;
2072 if (reg.invert)
2073 left = reg.mask - left;
2074 left <<= reg.left_shift;
2075 if (reg.stereo) {
2076 right = ucontrol->value.integer.value[1] & reg.mask;
2077 if (reg.invert)
2078 right = reg.mask - right;
2079 right <<= reg.right_shift;
2080 } else
2081 right = 0;
2082 spin_lock_irq(&cm->reg_lock);
2083 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2084 left |= oleft & ~(reg.mask << reg.left_shift);
2085 change = left != oleft;
2086 if (reg.stereo) {
2087 if (reg.left_reg != reg.right_reg) {
2088 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2089 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2090 } else
2091 oright = left;
2092 right |= oright & ~(reg.mask << reg.right_shift);
2093 change |= right != oright;
2094 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2095 } else
2096 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2097 spin_unlock_irq(&cm->reg_lock);
2098 return change;
2099}
2100
2101/*
2102 * input route (left,right) -> (left,right)
2103 */
2104#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2105{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2106 .info = snd_cmipci_info_input_sw, \
2107 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2108 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2109}
2110
2111static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2112 struct snd_ctl_elem_info *uinfo)
2113{
2114 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2115 uinfo->count = 4;
2116 uinfo->value.integer.min = 0;
2117 uinfo->value.integer.max = 1;
2118 return 0;
2119}
2120
2121static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2122 struct snd_ctl_elem_value *ucontrol)
2123{
2124 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2125 struct cmipci_sb_reg reg;
2126 int val1, val2;
2127
2128 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2129 spin_lock_irq(&cm->reg_lock);
2130 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2131 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2132 spin_unlock_irq(&cm->reg_lock);
2133 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2134 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2135 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2136 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2137 return 0;
2138}
2139
2140static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2141 struct snd_ctl_elem_value *ucontrol)
2142{
2143 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2144 struct cmipci_sb_reg reg;
2145 int change;
2146 int val1, val2, oval1, oval2;
2147
2148 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2149 spin_lock_irq(&cm->reg_lock);
2150 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2151 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2152 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2153 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2154 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2155 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2156 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2157 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2158 change = val1 != oval1 || val2 != oval2;
2159 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2160 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2161 spin_unlock_irq(&cm->reg_lock);
2162 return change;
2163}
2164
2165/*
2166 * native mixer switches/volumes
2167 */
2168
2169#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2170{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2171 .info = snd_cmipci_info_native_mixer, \
2172 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2173 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2174}
2175
2176#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2177{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2178 .info = snd_cmipci_info_native_mixer, \
2179 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2180 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2181}
2182
2183#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2184{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2185 .info = snd_cmipci_info_native_mixer, \
2186 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2187 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2188}
2189
2190#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2191{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2192 .info = snd_cmipci_info_native_mixer, \
2193 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2194 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2195}
2196
2197static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2198 struct snd_ctl_elem_info *uinfo)
2199{
2200 struct cmipci_sb_reg reg;
2201
2202 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2203 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2204 uinfo->count = reg.stereo + 1;
2205 uinfo->value.integer.min = 0;
2206 uinfo->value.integer.max = reg.mask;
2207 return 0;
2208
2209}
2210
2211static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2212 struct snd_ctl_elem_value *ucontrol)
2213{
2214 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2215 struct cmipci_sb_reg reg;
2216 unsigned char oreg, val;
2217
2218 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2219 spin_lock_irq(&cm->reg_lock);
2220 oreg = inb(cm->iobase + reg.left_reg);
2221 val = (oreg >> reg.left_shift) & reg.mask;
2222 if (reg.invert)
2223 val = reg.mask - val;
2224 ucontrol->value.integer.value[0] = val;
2225 if (reg.stereo) {
2226 val = (oreg >> reg.right_shift) & reg.mask;
2227 if (reg.invert)
2228 val = reg.mask - val;
2229 ucontrol->value.integer.value[1] = val;
2230 }
2231 spin_unlock_irq(&cm->reg_lock);
2232 return 0;
2233}
2234
2235static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2236 struct snd_ctl_elem_value *ucontrol)
2237{
2238 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2239 struct cmipci_sb_reg reg;
2240 unsigned char oreg, nreg, val;
2241
2242 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2243 spin_lock_irq(&cm->reg_lock);
2244 oreg = inb(cm->iobase + reg.left_reg);
2245 val = ucontrol->value.integer.value[0] & reg.mask;
2246 if (reg.invert)
2247 val = reg.mask - val;
2248 nreg = oreg & ~(reg.mask << reg.left_shift);
2249 nreg |= (val << reg.left_shift);
2250 if (reg.stereo) {
2251 val = ucontrol->value.integer.value[1] & reg.mask;
2252 if (reg.invert)
2253 val = reg.mask - val;
2254 nreg &= ~(reg.mask << reg.right_shift);
2255 nreg |= (val << reg.right_shift);
2256 }
2257 outb(nreg, cm->iobase + reg.left_reg);
2258 spin_unlock_irq(&cm->reg_lock);
2259 return (nreg != oreg);
2260}
2261
2262/*
2263 * special case - check mixer sensitivity
2264 */
2265static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2266 struct snd_ctl_elem_value *ucontrol)
2267{
2268 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2269 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2270}
2271
2272static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2273 struct snd_ctl_elem_value *ucontrol)
2274{
2275 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2276 if (cm->mixer_insensitive) {
2277 /* ignored */
2278 return 0;
2279 }
2280 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2281}
2282
2283
2284static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2285 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2286 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2287 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2288 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2289 { /* switch with sensitivity */
2290 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2291 .name = "PCM Playback Switch",
2292 .info = snd_cmipci_info_native_mixer,
2293 .get = snd_cmipci_get_native_mixer_sensitive,
2294 .put = snd_cmipci_put_native_mixer_sensitive,
2295 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2296 },
2297 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2298 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2299 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2300 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2301 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2302 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2303 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2304 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2305 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2306 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2307 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2308 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2309 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2310 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2311 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2312 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2313 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2314 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2315 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2316 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2317 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2318 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2319 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2320};
2321
2322/*
2323 * other switches
2324 */
2325
2326struct cmipci_switch_args {
2327 int reg; /* register index */
2328 unsigned int mask; /* mask bits */
2329 unsigned int mask_on; /* mask bits to turn on */
2330 unsigned int is_byte: 1; /* byte access? */
2331 unsigned int ac3_sensitive: 1; /* access forbidden during
2332 * non-audio operation?
2333 */
2334};
2335
2336#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2337
2338static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2339 struct snd_ctl_elem_value *ucontrol,
2340 struct cmipci_switch_args *args)
2341{
2342 unsigned int val;
2343 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2344
2345 spin_lock_irq(&cm->reg_lock);
2346 if (args->ac3_sensitive && cm->mixer_insensitive) {
2347 ucontrol->value.integer.value[0] = 0;
2348 spin_unlock_irq(&cm->reg_lock);
2349 return 0;
2350 }
2351 if (args->is_byte)
2352 val = inb(cm->iobase + args->reg);
2353 else
2354 val = snd_cmipci_read(cm, args->reg);
2355 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2356 spin_unlock_irq(&cm->reg_lock);
2357 return 0;
2358}
2359
2360static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2361 struct snd_ctl_elem_value *ucontrol)
2362{
2363 struct cmipci_switch_args *args;
2364 args = (struct cmipci_switch_args *)kcontrol->private_value;
2365 if (snd_BUG_ON(!args))
2366 return -EINVAL;
2367 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2368}
2369
2370static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2371 struct snd_ctl_elem_value *ucontrol,
2372 struct cmipci_switch_args *args)
2373{
2374 unsigned int val;
2375 int change;
2376 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2377
2378 spin_lock_irq(&cm->reg_lock);
2379 if (args->ac3_sensitive && cm->mixer_insensitive) {
2380 /* ignored */
2381 spin_unlock_irq(&cm->reg_lock);
2382 return 0;
2383 }
2384 if (args->is_byte)
2385 val = inb(cm->iobase + args->reg);
2386 else
2387 val = snd_cmipci_read(cm, args->reg);
2388 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2389 args->mask_on : (args->mask & ~args->mask_on));
2390 if (change) {
2391 val &= ~args->mask;
2392 if (ucontrol->value.integer.value[0])
2393 val |= args->mask_on;
2394 else
2395 val |= (args->mask & ~args->mask_on);
2396 if (args->is_byte)
2397 outb((unsigned char)val, cm->iobase + args->reg);
2398 else
2399 snd_cmipci_write(cm, args->reg, val);
2400 }
2401 spin_unlock_irq(&cm->reg_lock);
2402 return change;
2403}
2404
2405static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2406 struct snd_ctl_elem_value *ucontrol)
2407{
2408 struct cmipci_switch_args *args;
2409 args = (struct cmipci_switch_args *)kcontrol->private_value;
2410 if (snd_BUG_ON(!args))
2411 return -EINVAL;
2412 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2413}
2414
2415#ifndef TARGET_OS2
2416#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2417static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2418 .reg = xreg, \
2419 .mask = xmask, \
2420 .mask_on = xmask_on, \
2421 .is_byte = xis_byte, \
2422 .ac3_sensitive = xac3, \
2423}
2424#else
2425#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2426 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2427 xreg, \
2428 xmask, \
2429 xmask_on, \
2430 xis_byte, \
2431 xac3, \
2432 }
2433#endif
2434
2435#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2436 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2437
2438#if 0 /* these will be controlled in pcm device */
2439DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2440DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2441#endif
2442DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2443DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2444DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2445DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2446DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2447DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2448DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2449DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2450// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2451DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2452DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2453/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2454DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2455DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2456#if CM_CH_PLAY == 1
2457DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2458#else
2459DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2460#endif
2461DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2462// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2463// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2464// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2465DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2466
2467#define DEFINE_SWITCH(sname, stype, sarg) \
2468{ .name = sname, \
2469 .iface = stype, \
2470 .info = snd_cmipci_uswitch_info, \
2471 .get = snd_cmipci_uswitch_get, \
2472 .put = snd_cmipci_uswitch_put, \
2473 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2474}
2475
2476#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2477#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2478
2479
2480/*
2481 * callbacks for spdif output switch
2482 * needs toggle two registers..
2483 */
2484static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2485 struct snd_ctl_elem_value *ucontrol)
2486{
2487 int changed;
2488 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2489 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2490 return changed;
2491}
2492
2493static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2494 struct snd_ctl_elem_value *ucontrol)
2495{
2496 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2497 int changed;
2498 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2499 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2500 if (changed) {
2501 if (ucontrol->value.integer.value[0]) {
2502 if (chip->spdif_playback_avail)
2503 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2504 } else {
2505 if (chip->spdif_playback_avail)
2506 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2507 }
2508 }
2509 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2510 return changed;
2511}
2512
2513
2514static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2515 struct snd_ctl_elem_info *uinfo)
2516{
2517 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2518 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2519 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2520 uinfo->count = 1;
2521 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2522 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2523 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2524 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2525 return 0;
2526}
2527
2528static inline unsigned int get_line_in_mode(struct cmipci *cm)
2529{
2530 unsigned int val;
2531 if (cm->chip_version >= 39) {
2532 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2533 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2534 return 2;
2535 }
2536 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2537 if (val & CM_REAR2LIN)
2538 return 1;
2539 return 0;
2540}
2541
2542static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2543 struct snd_ctl_elem_value *ucontrol)
2544{
2545 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2546
2547 spin_lock_irq(&cm->reg_lock);
2548 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2549 spin_unlock_irq(&cm->reg_lock);
2550 return 0;
2551}
2552
2553static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2554 struct snd_ctl_elem_value *ucontrol)
2555{
2556 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2557 int change;
2558
2559 spin_lock_irq(&cm->reg_lock);
2560 if (ucontrol->value.enumerated.item[0] == 2)
2561 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2562 else
2563 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2564 if (ucontrol->value.enumerated.item[0] == 1)
2565 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2566 else
2567 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2568 spin_unlock_irq(&cm->reg_lock);
2569 return change;
2570}
2571
2572static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2573 struct snd_ctl_elem_info *uinfo)
2574{
2575 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2576 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2577 uinfo->count = 1;
2578 uinfo->value.enumerated.items = 2;
2579 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2580 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2581 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2582 return 0;
2583}
2584
2585static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2586 struct snd_ctl_elem_value *ucontrol)
2587{
2588 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2589 /* same bit as spdi_phase */
2590 spin_lock_irq(&cm->reg_lock);
2591 ucontrol->value.enumerated.item[0] =
2592 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2593 spin_unlock_irq(&cm->reg_lock);
2594 return 0;
2595}
2596
2597static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2598 struct snd_ctl_elem_value *ucontrol)
2599{
2600 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2601 int change;
2602
2603 spin_lock_irq(&cm->reg_lock);
2604 if (ucontrol->value.enumerated.item[0])
2605 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2606 else
2607 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2608 spin_unlock_irq(&cm->reg_lock);
2609 return change;
2610}
2611
2612/* both for CM8338/8738 */
2613static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2614 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2615 {
2616 .name = "Line-In Mode",
2617 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2618 .info = snd_cmipci_line_in_mode_info,
2619 .get = snd_cmipci_line_in_mode_get,
2620 .put = snd_cmipci_line_in_mode_put,
2621 },
2622};
2623
2624/* for non-multichannel chips */
2625static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2626DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2627
2628/* only for CM8738 */
2629static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2630#if 0 /* controlled in pcm device */
2631 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2632 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2633 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2634#endif
2635 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2636 { .name = "IEC958 Output Switch",
2637 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2638 .info = snd_cmipci_uswitch_info,
2639 .get = snd_cmipci_spdout_enable_get,
2640 .put = snd_cmipci_spdout_enable_put,
2641 },
2642 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2643 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2644 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2645// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2646 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2647 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2648};
2649
2650/* only for model 033/037 */
2651static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2652 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2653 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2654 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2655};
2656
2657/* only for model 039 or later */
2658static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2659 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2660 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2661 {
2662 .name = "Mic-In Mode",
2663 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2664 .info = snd_cmipci_mic_in_mode_info,
2665 .get = snd_cmipci_mic_in_mode_get,
2666 .put = snd_cmipci_mic_in_mode_put,
2667 }
2668};
2669
2670/* card control switches */
2671static struct snd_kcontrol_new snd_cmipci_modem_switch __devinitdata =
2672DEFINE_CARD_SWITCH("Modem", modem);
2673
2674
2675static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2676{
2677 struct snd_card *card;
2678 struct snd_kcontrol_new *sw;
2679 struct snd_kcontrol *kctl;
2680 unsigned int idx;
2681 int err;
2682
2683 if (snd_BUG_ON(!cm || !cm->card))
2684 return -EINVAL;
2685
2686 card = cm->card;
2687
2688 strcpy(card->mixername, "CMedia PCI");
2689
2690 spin_lock_irq(&cm->reg_lock);
2691 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2692 spin_unlock_irq(&cm->reg_lock);
2693
2694 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2695 if (cm->chip_version == 68) { // 8768 has no PCM volume
2696 if (!strcmp(snd_cmipci_mixers[idx].name,
2697 "PCM Playback Volume"))
2698 continue;
2699 }
2700 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2701 return err;
2702 }
2703
2704 /* mixer switches */
2705 sw = snd_cmipci_mixer_switches;
2706 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2707 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2708 if (err < 0)
2709 return err;
2710 }
2711 if (! cm->can_multi_ch) {
2712 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2713 if (err < 0)
2714 return err;
2715 }
2716 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2717 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2718 sw = snd_cmipci_8738_mixer_switches;
2719 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2720 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2721 if (err < 0)
2722 return err;
2723 }
2724 if (cm->can_ac3_hw) {
2725 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2726 return err;
2727 kctl->id.device = pcm_spdif_device;
2728 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2729 return err;
2730 kctl->id.device = pcm_spdif_device;
2731 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2732 return err;
2733 kctl->id.device = pcm_spdif_device;
2734 }
2735 if (cm->chip_version <= 37) {
2736 sw = snd_cmipci_old_mixer_switches;
2737 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2738 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2739 if (err < 0)
2740 return err;
2741 }
2742 }
2743 }
2744 if (cm->chip_version >= 39) {
2745 sw = snd_cmipci_extra_mixer_switches;
2746 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2747 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2748 if (err < 0)
2749 return err;
2750 }
2751 }
2752
2753 /* card switches */
2754 /*
2755 * newer chips don't have the register bits to force modem link
2756 * detection; the bit that was FLINKON now mutes CH1
2757 */
2758 if (cm->chip_version < 39) {
2759 err = snd_ctl_add(cm->card,
2760 snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2761 if (err < 0)
2762 return err;
2763 }
2764
2765 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2766 struct snd_ctl_elem_id elem_id;
2767 struct snd_kcontrol *ctl;
2768 memset(&elem_id, 0, sizeof(elem_id));
2769 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2770 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2771 ctl = snd_ctl_find_id(cm->card, &elem_id);
2772 if (ctl)
2773 cm->mixer_res_ctl[idx] = ctl;
2774 }
2775
2776 return 0;
2777}
2778
2779
2780/*
2781 * proc interface
2782 */
2783
2784#ifdef CONFIG_PROC_FS
2785static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2786 struct snd_info_buffer *buffer)
2787{
2788 struct cmipci *cm = entry->private_data;
2789 int i, v;
2790
2791 snd_iprintf(buffer, "%s\n", cm->card->longname);
2792 for (i = 0; i < 0x94; i++) {
2793 if (i == 0x28)
2794 i = 0x90;
2795 v = inb(cm->iobase + i);
2796 if (i % 4 == 0)
2797 snd_iprintf(buffer, "\n%02x:", i);
2798 snd_iprintf(buffer, " %02x", v);
2799 }
2800 snd_iprintf(buffer, "\n");
2801}
2802
2803static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2804{
2805 struct snd_info_entry *entry;
2806
2807 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2808 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2809}
2810#else /* !CONFIG_PROC_FS */
2811static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2812#endif
2813
2814
2815static struct pci_device_id snd_cmipci_ids[] = {
2816 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2817 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2818 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2819 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2820 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2821 {0,},
2822};
2823
2824
2825/*
2826 * check chip version and capabilities
2827 * driver name is modified according to the chip model
2828 */
2829static void __devinit query_chip(struct cmipci *cm)
2830{
2831 unsigned int detect;
2832
2833 /* check reg 0Ch, bit 24-31 */
2834 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2835 if (! detect) {
2836 /* check reg 08h, bit 24-28 */
2837 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2838 switch (detect) {
2839 case 0:
2840 cm->chip_version = 33;
2841 if (cm->do_soft_ac3)
2842 cm->can_ac3_sw = 1;
2843 else
2844 cm->can_ac3_hw = 1;
2845 break;
2846 case CM_CHIP_037:
2847 cm->chip_version = 37;
2848 cm->can_ac3_hw = 1;
2849 break;
2850 default:
2851 cm->chip_version = 39;
2852 cm->can_ac3_hw = 1;
2853 break;
2854 }
2855 cm->max_channels = 2;
2856 } else {
2857 if (detect & CM_CHIP_039) {
2858 cm->chip_version = 39;
2859 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2860 cm->max_channels = 6;
2861 else
2862 cm->max_channels = 4;
2863 } else if (detect & CM_CHIP_8768) {
2864 cm->chip_version = 68;
2865 cm->max_channels = 8;
2866 cm->can_96k = 1;
2867 } else {
2868 cm->chip_version = 55;
2869 cm->max_channels = 6;
2870 cm->can_96k = 1;
2871 }
2872 cm->can_ac3_hw = 1;
2873 cm->can_multi_ch = 1;
2874 }
2875}
2876
2877#ifdef SUPPORT_JOYSTICK
2878static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2879{
2880 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2881 struct gameport *gp;
2882 struct resource *r = NULL;
2883 int i, io_port = 0;
2884
2885 if (joystick_port[dev] == 0)
2886 return -ENODEV;
2887
2888 if (joystick_port[dev] == 1) { /* auto-detect */
2889 for (i = 0; ports[i]; i++) {
2890 io_port = ports[i];
2891 r = request_region(io_port, 1, "CMIPCI gameport");
2892 if (r)
2893 break;
2894 }
2895 } else {
2896 io_port = joystick_port[dev];
2897 r = request_region(io_port, 1, "CMIPCI gameport");
2898 }
2899
2900 if (!r) {
2901 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2902 return -EBUSY;
2903 }
2904
2905 cm->gameport = gp = gameport_allocate_port();
2906 if (!gp) {
2907 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2908 release_and_free_resource(r);
2909 return -ENOMEM;
2910 }
2911 gameport_set_name(gp, "C-Media Gameport");
2912 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2913 gameport_set_dev_parent(gp, &cm->pci->dev);
2914 gp->io = io_port;
2915 gameport_set_port_data(gp, r);
2916
2917 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2918
2919 gameport_register_port(cm->gameport);
2920
2921 return 0;
2922}
2923
2924static void snd_cmipci_free_gameport(struct cmipci *cm)
2925{
2926 if (cm->gameport) {
2927 struct resource *r = gameport_get_port_data(cm->gameport);
2928
2929 gameport_unregister_port(cm->gameport);
2930 cm->gameport = NULL;
2931
2932 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2933 release_and_free_resource(r);
2934 }
2935}
2936#else
2937static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2938static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2939#endif
2940
2941static int snd_cmipci_free(struct cmipci *cm)
2942{
2943 if (cm->irq >= 0) {
2944 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2945 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2946 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2947 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2948 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2949 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2950 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2951
2952 /* reset mixer */
2953 snd_cmipci_mixer_write(cm, 0, 0);
2954
2955 free_irq(cm->irq, cm);
2956 }
2957
2958 snd_cmipci_free_gameport(cm);
2959 pci_release_regions(cm->pci);
2960 pci_disable_device(cm->pci);
2961 kfree(cm);
2962 return 0;
2963}
2964
2965static int snd_cmipci_dev_free(struct snd_device *device)
2966{
2967 struct cmipci *cm = device->device_data;
2968 return snd_cmipci_free(cm);
2969}
2970
2971static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2972{
2973 long iosynth;
2974 unsigned int val;
2975 struct snd_opl3 *opl3;
2976 int err;
2977
2978 if (!fm_port)
2979 goto disable_fm;
2980
2981 if (cm->chip_version >= 39) {
2982 /* first try FM regs in PCI port range */
2983 iosynth = cm->iobase + CM_REG_FM_PCI;
2984 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2985 OPL3_HW_OPL3, 1, &opl3);
2986 } else {
2987 err = -EIO;
2988 }
2989 if (err < 0) {
2990 /* then try legacy ports */
2991 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2992 iosynth = fm_port;
2993 switch (iosynth) {
2994 case 0x3E8: val |= CM_FMSEL_3E8; break;
2995 case 0x3E0: val |= CM_FMSEL_3E0; break;
2996 case 0x3C8: val |= CM_FMSEL_3C8; break;
2997 case 0x388: val |= CM_FMSEL_388; break;
2998 default:
2999 goto disable_fm;
3000 }
3001 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3002 /* enable FM */
3003 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3004
3005 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
3006 OPL3_HW_OPL3, 0, &opl3) < 0) {
3007 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
3008 "skipping...\n", iosynth);
3009 goto disable_fm;
3010 }
3011 }
3012 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
3013 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
3014 return err;
3015 }
3016 return 0;
3017
3018 disable_fm:
3019 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
3020 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
3021 return 0;
3022}
3023
3024static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
3025 int dev, struct cmipci **rcmipci)
3026{
3027 struct cmipci *cm;
3028 int err;
3029 static struct snd_device_ops ops = {
3030 .dev_free = snd_cmipci_dev_free,
3031 };
3032 unsigned int val;
3033 long iomidi;
3034 int integrated_midi = 0;
3035 char modelstr[16];
3036 int pcm_index, pcm_spdif_index;
3037 static struct pci_device_id intel_82437vx[] = {
3038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3039 {0},
3040 };
3041
3042 *rcmipci = NULL;
3043
3044 if ((err = pci_enable_device(pci)) < 0)
3045 return err;
3046
3047 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3048 if (cm == NULL) {
3049 pci_disable_device(pci);
3050 return -ENOMEM;
3051 }
3052
3053 spin_lock_init(&cm->reg_lock);
3054 mutex_init(&cm->open_mutex);
3055 cm->device = pci->device;
3056 cm->card = card;
3057 cm->pci = pci;
3058 cm->irq = -1;
3059 cm->channel[0].ch = 0;
3060 cm->channel[1].ch = 1;
3061 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3062
3063 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3064 kfree(cm);
3065 pci_disable_device(pci);
3066 return err;
3067 }
3068 cm->iobase = pci_resource_start(pci, 0);
3069
3070 if (request_irq(pci->irq, snd_cmipci_interrupt,
3071 IRQF_SHARED, card->driver, cm)) {
3072 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3073 snd_cmipci_free(cm);
3074 return -EBUSY;
3075 }
3076 cm->irq = pci->irq;
3077
3078 pci_set_master(cm->pci);
3079
3080 /*
3081 * check chip version, max channels and capabilities
3082 */
3083
3084 cm->chip_version = 0;
3085 cm->max_channels = 2;
3086 cm->do_soft_ac3 = soft_ac3[dev];
3087
3088 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3089 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3090 query_chip(cm);
3091 /* added -MCx suffix for chip supporting multi-channels */
3092 if (cm->can_multi_ch)
3093 sprintf(cm->card->driver + strlen(cm->card->driver),
3094 "-MC%d", cm->max_channels);
3095 else if (cm->can_ac3_sw)
3096 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3097
3098 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3099 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3100
3101#if CM_CH_PLAY == 1
3102 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3103#else
3104 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3105#endif
3106
3107 /* initialize codec registers */
3108 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3109 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3110 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3111 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3112 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3113 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3114 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3115
3116 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3117 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3118#if CM_CH_PLAY == 1
3119 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3120#else
3121 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3122#endif
3123 if (cm->chip_version) {
3124 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3125 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3126 }
3127 /* Set Bus Master Request */
3128 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3129
3130 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3131 switch (pci->device) {
3132 case PCI_DEVICE_ID_CMEDIA_CM8738:
3133 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3134 if (!pci_dev_present(intel_82437vx))
3135 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3136 break;
3137 default:
3138 break;
3139 }
3140
3141 if (cm->chip_version < 68) {
3142 val = pci->device < 0x110 ? 8338 : 8738;
3143 } else {
3144 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3145 case 0:
3146 val = 8769;
3147 break;
3148 case 2:
3149 val = 8762;
3150 break;
3151 default:
3152 switch ((pci->subsystem_vendor << 16) |
3153 pci->subsystem_device) {
3154 case 0x13f69761:
3155 case 0x584d3741:
3156 case 0x584d3751:
3157 case 0x584d3761:
3158 case 0x584d3771:
3159 case 0x72848384:
3160 val = 8770;
3161 break;
3162 default:
3163 val = 8768;
3164 break;
3165 }
3166 }
3167 }
3168 sprintf(card->shortname, "C-Media CMI%d", val);
3169 if (cm->chip_version < 68)
3170 sprintf(modelstr, " (model %d)", cm->chip_version);
3171 else
3172 modelstr[0] = '\0';
3173 sprintf(card->longname, "%s%s at %#lx, irq %i",
3174 card->shortname, modelstr, cm->iobase, cm->irq);
3175
3176 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3177 snd_cmipci_free(cm);
3178 return err;
3179 }
3180
3181 if (cm->chip_version >= 39) {
3182 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3183 if (val != 0x00 && val != 0xff) {
3184 iomidi = cm->iobase + CM_REG_MPU_PCI;
3185 integrated_midi = 1;
3186 }
3187 }
3188 if (!integrated_midi) {
3189 val = 0;
3190 iomidi = mpu_port[dev];
3191 switch (iomidi) {
3192 case 0x320: val = CM_VMPU_320; break;
3193 case 0x310: val = CM_VMPU_310; break;
3194 case 0x300: val = CM_VMPU_300; break;
3195 case 0x330: val = CM_VMPU_330; break;
3196 default:
3197 iomidi = 0; break;
3198 }
3199 if (iomidi > 0) {
3200 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3201 /* enable UART */
3202 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3203 if (inb(iomidi + 1) == 0xff) {
3204 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3205 " at %#lx\n", iomidi);
3206 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3207 CM_UART_EN);
3208 iomidi = 0;
3209 }
3210 }
3211 }
3212
3213 if (cm->chip_version < 68) {
3214 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3215 if (err < 0)
3216 return err;
3217 }
3218
3219 /* reset mixer */
3220 snd_cmipci_mixer_write(cm, 0, 0);
3221
3222 snd_cmipci_proc_init(cm);
3223
3224 /* create pcm devices */
3225 pcm_index = pcm_spdif_index = 0;
3226 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3227 return err;
3228 pcm_index++;
3229 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3230 return err;
3231 pcm_index++;
3232 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3233 pcm_spdif_index = pcm_index;
3234 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3235 return err;
3236 }
3237
3238 /* create mixer interface & switches */
3239 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3240 return err;
3241
3242 if (iomidi > 0) {
3243 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3244 iomidi,
3245 (integrated_midi ?
3246 MPU401_INFO_INTEGRATED : 0),
3247 cm->irq, 0, &cm->rmidi)) < 0) {
3248 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3249 }
3250 }
3251
3252#ifdef USE_VAR48KRATE
3253 for (val = 0; val < ARRAY_SIZE(rates); val++)
3254 snd_cmipci_set_pll(cm, rates[val], val);
3255
3256 /*
3257 * (Re-)Enable external switch spdo_48k
3258 */
3259 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3260#endif /* USE_VAR48KRATE */
3261
3262 if (snd_cmipci_create_gameport(cm, dev) < 0)
3263 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3264
3265 snd_card_set_dev(card, &pci->dev);
3266
3267 *rcmipci = cm;
3268 return 0;
3269}
3270
3271/*
3272 */
3273
3274MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3275
3276static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3277 const struct pci_device_id *pci_id)
3278{
3279 static int dev;
3280 struct snd_card *card;
3281 struct cmipci *cm;
3282 int err;
3283
3284 if (dev >= SNDRV_CARDS)
3285 return -ENODEV;
3286 if (! enable[dev]) {
3287 dev++;
3288 return -ENOENT;
3289 }
3290
3291 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3292 if (err < 0)
3293 return err;
3294
3295 switch (pci->device) {
3296 case PCI_DEVICE_ID_CMEDIA_CM8738:
3297 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3298 strcpy(card->driver, "CMI8738");
3299 break;
3300 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3301 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3302 strcpy(card->driver, "CMI8338");
3303 break;
3304 default:
3305 strcpy(card->driver, "CMIPCI");
3306 break;
3307 }
3308
3309 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3310 snd_card_free(card);
3311 return err;
3312 }
3313 card->private_data = cm;
3314
3315 if ((err = snd_card_register(card)) < 0) {
3316 snd_card_free(card);
3317 return err;
3318 }
3319 pci_set_drvdata(pci, card);
3320 dev++;
3321 return 0;
3322
3323}
3324
3325static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3326{
3327 snd_card_free(pci_get_drvdata(pci));
3328 pci_set_drvdata(pci, NULL);
3329}
3330
3331
3332#ifdef CONFIG_PM
3333/*
3334 * power management
3335 */
3336static unsigned char saved_regs[] = {
3337 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3338 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3339 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3340 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3341 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3342};
3343
3344static unsigned char saved_mixers[] = {
3345 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3346 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3347 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3348 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3349 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3350 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3351 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3352 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3353};
3354
3355static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3356{
3357 struct snd_card *card = pci_get_drvdata(pci);
3358 struct cmipci *cm = card->private_data;
3359 int i;
3360
3361 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3362
3363 snd_pcm_suspend_all(cm->pcm);
3364 snd_pcm_suspend_all(cm->pcm2);
3365 snd_pcm_suspend_all(cm->pcm_spdif);
3366
3367 /* save registers */
3368 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3369 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3370 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3371 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3372
3373 /* disable ints */
3374 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3375
3376 pci_disable_device(pci);
3377 pci_save_state(pci);
3378 pci_set_power_state(pci, pci_choose_state(pci, state));
3379 return 0;
3380}
3381
3382static int snd_cmipci_resume(struct pci_dev *pci)
3383{
3384 struct snd_card *card = pci_get_drvdata(pci);
3385 struct cmipci *cm = card->private_data;
3386 int i;
3387
3388 pci_set_power_state(pci, PCI_D0);
3389 pci_restore_state(pci);
3390 if (pci_enable_device(pci) < 0) {
3391 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3392 "disabling device\n");
3393 snd_card_disconnect(card);
3394 return -EIO;
3395 }
3396 pci_set_master(pci);
3397
3398 /* reset / initialize to a sane state */
3399 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3400 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3401 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3402 snd_cmipci_mixer_write(cm, 0, 0);
3403
3404 /* restore registers */
3405 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3406 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3407 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3408 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3409
3410 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3411 return 0;
3412}
3413#endif /* CONFIG_PM */
3414
3415static struct pci_driver driver = {
3416 .name = "C-Media PCI",
3417 .id_table = snd_cmipci_ids,
3418 .probe = snd_cmipci_probe,
3419 .remove = __devexit_p(snd_cmipci_remove),
3420#ifdef CONFIG_PM
3421 .suspend = snd_cmipci_suspend,
3422 .resume = snd_cmipci_resume,
3423#endif
3424};
3425
3426static int __init alsa_card_cmipci_init(void)
3427{
3428 return pci_register_driver(&driver);
3429}
3430
3431static void __exit alsa_card_cmipci_exit(void)
3432{
3433 pci_unregister_driver(&driver);
3434}
3435
3436module_init(alsa_card_cmipci_init)
3437module_exit(alsa_card_cmipci_exit)
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