| 1 | /* SPDX-License-Identifier: GPL-2.0 */
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| 2 | #ifndef __SOUND_AZT3328_H
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| 3 | #define __SOUND_AZT3328_H
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| 4 |
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| 5 | /* "PU" == "power-up value", as tested on PCI168 PCI rev. 10
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| 6 | * "WRITE_ONLY" == register does not indicate actual bit values */
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| 7 |
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| 8 | /*** main I/O area port indices ***/
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| 9 | /* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
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| 10 | #define AZF_IO_SIZE_CTRL 0x80
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| 11 | #define AZF_IO_SIZE_CTRL_PM 0x70
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| 12 |
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| 13 | /* the driver initialisation suggests a layout of 4 areas
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| 14 | * within the main card control I/O:
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| 15 | * from 0x00 (playback codec), from 0x20 (recording codec)
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| 16 | * and from 0x40 (most certainly I2S out codec).
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| 17 | * And another area from 0x60 to 0x6f (DirectX timer, IRQ management,
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| 18 | * power management etc.???). */
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| 19 |
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| 20 | #define AZF_IO_OFFS_CODEC_PLAYBACK 0x00
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| 21 | #define AZF_IO_OFFS_CODEC_CAPTURE 0x20
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| 22 | #define AZF_IO_OFFS_CODEC_I2S_OUT 0x40
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| 23 |
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| 24 | #define IDX_IO_CODEC_DMA_FLAGS 0x00 /* PU:0x0000 */
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| 25 | /* able to reactivate output after output muting due to 8/16bit
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| 26 | * output change, just like 0x0002.
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| 27 | * 0x0001 is the only bit that's able to start the DMA counter */
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| 28 | #define DMA_RESUME 0x0001 /* paused if cleared? */
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| 29 | /* 0x0002 *temporarily* set during DMA stopping. hmm
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| 30 | * both 0x0002 and 0x0004 set in playback setup. */
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| 31 | /* able to reactivate output after output muting due to 8/16bit
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| 32 | * output change, just like 0x0001. */
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| 33 | #define DMA_RUN_SOMETHING1 0x0002 /* \ alternated (toggled) */
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| 34 | /* 0x0004: NOT able to reactivate output */
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| 35 | #define DMA_RUN_SOMETHING2 0x0004 /* / bits */
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| 36 | #define SOMETHING_ALMOST_ALWAYS_SET 0x0008 /* ???; can be modified */
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| 37 | #define DMA_EPILOGUE_SOMETHING 0x0010
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| 38 | #define DMA_SOMETHING_ELSE 0x0020 /* ??? */
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| 39 | #define SOMETHING_UNMODIFIABLE 0xffc0 /* unused? not modifiable */
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| 40 | #define IDX_IO_CODEC_IRQTYPE 0x02 /* PU:0x0001 */
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| 41 | /* write back to flags in case flags are set, in order to ACK IRQ in handler
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| 42 | * (bit 1 of port 0x64 indicates interrupt for one of these three types)
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| 43 | * sometimes in this case it just writes 0xffff to globally ACK all IRQs
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| 44 | * settings written are not reflected when reading back, though.
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| 45 | * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows? */
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| 46 | #define IRQ_SOMETHING 0x0001 /* something & ACK */
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| 47 | #define IRQ_FINISHED_DMABUF_1 0x0002 /* 1st dmabuf finished & ACK */
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| 48 | #define IRQ_FINISHED_DMABUF_2 0x0004 /* 2nd dmabuf finished & ACK */
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| 49 | #define IRQMASK_SOME_STATUS_1 0x0008 /* \ related bits */
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| 50 | #define IRQMASK_SOME_STATUS_2 0x0010 /* / (checked together in loop) */
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| 51 | #define IRQMASK_UNMODIFIABLE 0xffe0 /* unused? not modifiable */
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| 52 | /* start address of 1st DMA transfer area, PU:0x00000000 */
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| 53 | #define IDX_IO_CODEC_DMA_START_1 0x04
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| 54 | /* start address of 2nd DMA transfer area, PU:0x00000000 */
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| 55 | #define IDX_IO_CODEC_DMA_START_2 0x08
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| 56 | /* both lengths of DMA transfer areas, PU:0x00000000
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| 57 | length1: offset 0x0c, length2: offset 0x0e */
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| 58 | #define IDX_IO_CODEC_DMA_LENGTHS 0x0c
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| 59 | #define IDX_IO_CODEC_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
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| 60 | /* offset within current DMA transfer area, PU:0x0000 */
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| 61 | #define IDX_IO_CODEC_DMA_CURROFS 0x14
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| 62 | #define IDX_IO_CODEC_SOUNDFORMAT 0x16 /* PU:0x0010 */
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| 63 | /* all unspecified bits can't be modified */
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| 64 | #define SOUNDFORMAT_FREQUENCY_MASK 0x000f
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| 65 | #define SOUNDFORMAT_XTAL1 0x00
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| 66 | #define SOUNDFORMAT_XTAL2 0x01
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| 67 | /* all _SUSPECTED_ values are not used by Windows drivers, so we don't
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| 68 | * have any hard facts, only rough measurements.
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| 69 | * All we know is that the crystal used on the board has 24.576MHz,
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| 70 | * like many soundcards (which results in the frequencies below when
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| 71 | * using certain divider values selected by the values below) */
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| 72 | #define SOUNDFORMAT_FREQ_SUSPECTED_4000 0x0c | SOUNDFORMAT_XTAL1
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| 73 | #define SOUNDFORMAT_FREQ_SUSPECTED_4800 0x0a | SOUNDFORMAT_XTAL1
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| 74 | #define SOUNDFORMAT_FREQ_5510 0x0c | SOUNDFORMAT_XTAL2
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| 75 | #define SOUNDFORMAT_FREQ_6620 0x0a | SOUNDFORMAT_XTAL2
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| 76 | #define SOUNDFORMAT_FREQ_8000 0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */
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| 77 | #define SOUNDFORMAT_FREQ_9600 0x08 | SOUNDFORMAT_XTAL1
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| 78 | #define SOUNDFORMAT_FREQ_11025 0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */
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| 79 | #define SOUNDFORMAT_FREQ_SUSPECTED_13240 0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */
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| 80 | #define SOUNDFORMAT_FREQ_16000 0x02 | SOUNDFORMAT_XTAL1
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| 81 | #define SOUNDFORMAT_FREQ_22050 0x02 | SOUNDFORMAT_XTAL2
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| 82 | #define SOUNDFORMAT_FREQ_32000 0x04 | SOUNDFORMAT_XTAL1
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| 83 | #define SOUNDFORMAT_FREQ_44100 0x04 | SOUNDFORMAT_XTAL2
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| 84 | #define SOUNDFORMAT_FREQ_48000 0x06 | SOUNDFORMAT_XTAL1
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| 85 | #define SOUNDFORMAT_FREQ_SUSPECTED_66200 0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */
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| 86 | #define SOUNDFORMAT_FLAG_16BIT 0x0010
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| 87 | #define SOUNDFORMAT_FLAG_2CHANNELS 0x0020
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| 88 |
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| 89 |
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| 90 | /* define frequency helpers, for maximum value safety */
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| 91 | enum azf_freq_t {
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| 92 | #define AZF_FREQ(rate) AZF_FREQ_##rate = rate
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| 93 | AZF_FREQ(4000),
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| 94 | AZF_FREQ(4800),
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| 95 | AZF_FREQ(5512),
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| 96 | AZF_FREQ(6620),
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| 97 | AZF_FREQ(8000),
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| 98 | AZF_FREQ(9600),
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| 99 | AZF_FREQ(11025),
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| 100 | AZF_FREQ(13240),
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| 101 | AZF_FREQ(16000),
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| 102 | AZF_FREQ(22050),
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| 103 | AZF_FREQ(32000),
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| 104 | AZF_FREQ(44100),
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| 105 | AZF_FREQ(48000),
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| 106 | AZF_FREQ(66200),
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| 107 | #undef AZF_FREQ
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| 108 | };
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| 109 |
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| 110 | /** DirectX timer, main interrupt area (FIXME: and something else?) **/
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| 111 | #define IDX_IO_TIMER_VALUE 0x60 /* found this timer area by pure luck :-) */
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| 112 | /* timer countdown value; triggers IRQ when timer is finished */
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| 113 | #define TIMER_VALUE_MASK 0x000fffffUL
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| 114 | /* activate timer countdown */
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| 115 | #define TIMER_COUNTDOWN_ENABLE 0x01000000UL
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| 116 | /* trigger timer IRQ on zero transition */
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| 117 | #define TIMER_IRQ_ENABLE 0x02000000UL
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| 118 | /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?)
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| 119 | * had 0x0020 set upon IRQ handler */
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| 120 | #define TIMER_IRQ_ACK 0x04000000UL
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| 121 | #define IDX_IO_IRQSTATUS 0x64
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| 122 | /* some IRQ bit in here might also be used to signal a power-management timer
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| 123 | * timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing).
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| 124 | * OPL3 hardware contains several timers which confusingly in most cases
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| 125 | * are NOT routed to an IRQ, but some designs (e.g. LM4560) DO support that,
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| 126 | * so I wouldn't be surprised at all to discover that AZF3328
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| 127 | * supports that thing as well... */
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| 128 |
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| 129 | #define IRQ_PLAYBACK 0x0001
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| 130 | #define IRQ_RECORDING 0x0002
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| 131 | #define IRQ_I2S_OUT 0x0004 /* this IS I2S, right!? (untested) */
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| 132 | #define IRQ_GAMEPORT 0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */
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| 133 | #define IRQ_MPU401 0x0010
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| 134 | #define IRQ_TIMER 0x0020 /* DirectX timer */
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| 135 | #define IRQ_UNKNOWN2 0x0040 /* probably unused, or possibly OPL3 timer? */
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| 136 | #define IRQ_UNKNOWN3 0x0080 /* probably unused, or possibly OPL3 timer? */
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| 137 | #define IDX_IO_66H 0x66 /* writing 0xffff returns 0x0000 */
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| 138 | /* this is set to e.g. 0x3ff or 0x300, and writable;
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| 139 | * maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */
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| 140 | #define IDX_IO_SOME_VALUE 0x68
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| 141 | #define IO_68_RANDOM_TOGGLE1 0x0100 /* toggles randomly */
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| 142 | #define IO_68_RANDOM_TOGGLE2 0x0200 /* toggles randomly */
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| 143 | /* umm, nope, behaviour of these bits changes depending on what we wrote
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| 144 | * to 0x6b!!
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| 145 | * And they change upon playback/stop, too:
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| 146 | * Writing a value to 0x68 will display this exact value during playback,
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| 147 | * too but when stopped it can fall back to a rather different
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| 148 | * seemingly random value). Hmm, possibly this is a register which
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| 149 | * has a remote shadow which needs proper device supply which only exists
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| 150 | * in case playback is active? Or is this driver-induced?
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| 151 | */
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| 152 |
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| 153 | /* this WORD can be set to have bits 0x0028 activated (FIXME: correct??);
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| 154 | * actually inhibits PCM playback!!! maybe power management??: */
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| 155 | #define IDX_IO_6AH 0x6A /* WRITE_ONLY! */
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| 156 | /* bit 5: enabling this will activate permanent counting of bytes 2/3
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| 157 | * at gameport I/O (0xb402/3) (equal values each) and cause
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| 158 | * gameport legacy I/O at 0x0200 to be _DISABLED_!
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| 159 | * Is this Digital Enhanced Game Port Enable??? Or maybe it's Testmode
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| 160 | * for Enhanced Digital Gameport (see 4D Wave DX card): */
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| 161 | #define IO_6A_SOMETHING1_GAMEPORT 0x0020
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| 162 | /* bit 8; sure, this _pauses_ playback (later resumes at same spot!),
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| 163 | * but what the heck is this really about??: */
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| 164 | #define IO_6A_PAUSE_PLAYBACK_BIT8 0x0100
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| 165 | /* bit 9; sure, this _pauses_ playback (later resumes at same spot!),
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| 166 | * but what the heck is this really about??: */
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| 167 | #define IO_6A_PAUSE_PLAYBACK_BIT9 0x0200
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| 168 | /* BIT8 and BIT9 are _NOT_ able to affect OPL3 MIDI playback,
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| 169 | * thus it suggests influence on PCM only!!
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| 170 | * However OTOH there seems to be no bit anywhere around here
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| 171 | * which is able to disable OPL3... */
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| 172 | /* bit 10: enabling this actually changes values at legacy gameport
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| 173 | * I/O address (0x200); is this enabling of the Digital Enhanced Game Port???
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| 174 | * Or maybe this simply switches off the NE558 circuit, since enabling this
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| 175 | * still lets us evaluate button states, but not axis states */
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| 176 | #define IO_6A_SOMETHING2_GAMEPORT 0x0400
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| 177 | /* writing 0x0300: causes quite some crackling during
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| 178 | * PC activity such as switching windows (PCI traffic??
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| 179 | * --> FIFO/timing settings???) */
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| 180 | /* writing 0x0100 plus/or 0x0200 inhibits playback */
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| 181 | /* since the Windows .INF file has Flag_Enable_JoyStick and
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| 182 | * Flag_Enable_SB_DOS_Emulation directly together, it stands to reason
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| 183 | * that some other bit in this same register might be responsible
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| 184 | * for SB DOS Emulation activation (note that the file did NOT define
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| 185 | * a switch for OPL3!) */
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| 186 | #define IDX_IO_6CH 0x6C /* unknown; fully read-writable */
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| 187 | #define IDX_IO_6EH 0x6E
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| 188 | /* writing 0xffff returns 0x83fe (or 0x03fe only).
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| 189 | * writing 0x83 (and only 0x83!!) to 0x6f will cause 0x6c to switch
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| 190 | * from 0000 to ffff. */
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| 191 |
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| 192 | /* further I/O indices not saved/restored and not readable after writing,
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| 193 | * so probably not used */
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| 194 |
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| 195 |
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| 196 | /*** Gameport area port indices ***/
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| 197 | /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
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| 198 | #define AZF_IO_SIZE_GAME 0x08
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| 199 | #define AZF_IO_SIZE_GAME_PM 0x06
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| 200 |
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| 201 | enum {
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| 202 | AZF_GAME_LEGACY_IO_PORT = 0x200
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| 203 | };
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| 204 |
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| 205 | #define IDX_GAME_LEGACY_COMPATIBLE 0x00
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| 206 | /* in some operation mode, writing anything to this port
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| 207 | * triggers an interrupt:
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| 208 | * yup, that's in case IDX_GAME_01H has one of the
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| 209 | * axis measurement bits enabled
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| 210 | * (and of course one needs to have GAME_HWCFG_IRQ_ENABLE, too) */
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| 211 |
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| 212 | #define IDX_GAME_AXES_CONFIG 0x01
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| 213 | /* NOTE: layout of this register awfully similar (read: "identical??")
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| 214 | * to AD1815JS.pdf (p.29) */
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| 215 |
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| 216 | /* enables axis 1 (X axis) measurement: */
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| 217 | #define GAME_AXES_ENABLE_1 0x01
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| 218 | /* enables axis 2 (Y axis) measurement: */
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| 219 | #define GAME_AXES_ENABLE_2 0x02
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| 220 | /* enables axis 3 (X axis) measurement: */
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| 221 | #define GAME_AXES_ENABLE_3 0x04
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| 222 | /* enables axis 4 (Y axis) measurement: */
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| 223 | #define GAME_AXES_ENABLE_4 0x08
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| 224 | /* selects the current axis to read the measured value of
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| 225 | * (at IDX_GAME_AXIS_VALUE):
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| 226 | * 00 = axis 1, 01 = axis 2, 10 = axis 3, 11 = axis 4: */
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| 227 | #define GAME_AXES_READ_MASK 0x30
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| 228 | /* enable to have the latch continuously accept ADC values
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| 229 | * (and continuously cause interrupts in case interrupts are enabled);
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| 230 | * AD1815JS.pdf says it's ~16ms interval there: */
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| 231 | #define GAME_AXES_LATCH_ENABLE 0x40
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| 232 | /* joystick data (measured axes) ready for reading: */
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| 233 | #define GAME_AXES_SAMPLING_READY 0x80
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| 234 |
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| 235 | /* NOTE: other card specs (SiS960 and others!) state that the
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| 236 | * game position latches should be frozen when reading and be freed
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| 237 | * (== reset?) after reading!!!
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| 238 | * Freezing most likely means disabling 0x40 (GAME_AXES_LATCH_ENABLE),
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| 239 | * but how to free the value? */
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| 240 | /* An internet search for "gameport latch ADC" should provide some insight
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| 241 | * into how to program such a gameport system. */
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| 242 |
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| 243 | /* writing 0xf0 to 01H once reset both counters to 0, in some special mode!?
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| 244 | * yup, in case 6AH 0x20 is not enabled
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| 245 | * (and 0x40 is sufficient, 0xf0 is not needed) */
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| 246 |
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| 247 | #define IDX_GAME_AXIS_VALUE 0x02
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| 248 | /* R: value of currently configured axis (word value!);
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| 249 | * W: trigger axis measurement */
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| 250 |
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| 251 | #define IDX_GAME_HWCONFIG 0x04
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| 252 | /* note: bits 4 to 7 are never set (== 0) when reading!
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| 253 | * --> reserved bits? */
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| 254 | /* enables IRQ notification upon axes measurement ready: */
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| 255 | #define GAME_HWCFG_IRQ_ENABLE 0x01
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| 256 | /* these bits choose a different frequency for the
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| 257 | * internal ADC counter increment.
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| 258 | * hmm, seems to be a combo of bits:
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| 259 | * 00 --> standard frequency
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| 260 | * 10 --> 1/2
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| 261 | * 01 --> 1/20
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| 262 | * 11 --> 1/200: */
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| 263 | #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK 0x06
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| 264 |
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| 265 | /* FIXME: these values might be reversed... */
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| 266 | #define GAME_HWCFG_ADC_COUNTER_FREQ_STD 0
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| 267 | #define GAME_HWCFG_ADC_COUNTER_FREQ_1_2 1
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| 268 | #define GAME_HWCFG_ADC_COUNTER_FREQ_1_20 2
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| 269 | #define GAME_HWCFG_ADC_COUNTER_FREQ_1_200 3
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| 270 |
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| 271 | /* enable gameport legacy I/O address (0x200)
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| 272 | * I was unable to locate any configurability for a different address: */
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| 273 | #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE 0x08
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| 274 |
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| 275 | /*** MPU401 ***/
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| 276 | #define AZF_IO_SIZE_MPU 0x04
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| 277 | #define AZF_IO_SIZE_MPU_PM 0x04
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| 278 |
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| 279 | /*** OPL3 synth ***/
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| 280 | /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
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| 281 | #define AZF_IO_SIZE_OPL3 0x08
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| 282 | #define AZF_IO_SIZE_OPL3_PM 0x06
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| 283 | /* hmm, given that a standard OPL3 has 4 registers only,
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| 284 | * there might be some enhanced functionality lurking at the end
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| 285 | * (especially since register 0x04 has a "non-empty" value 0xfe) */
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| 286 |
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| 287 | /*** mixer I/O area port indices ***/
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| 288 | /* (only 0x22 of 0x40 bytes saved/restored by Windows driver)
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| 289 | * UNFORTUNATELY azf3328 is NOT truly AC97 compliant: see main file intro */
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| 290 | #define AZF_IO_SIZE_MIXER 0x40
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| 291 | #define AZF_IO_SIZE_MIXER_PM 0x22
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| 292 |
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| 293 | #define MIXER_VOLUME_RIGHT_MASK 0x001f
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| 294 | #define MIXER_VOLUME_LEFT_MASK 0x1f00
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| 295 | #define MIXER_MUTE_MASK 0x8000
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| 296 | #define IDX_MIXER_RESET 0x00 /* does NOT seem to have AC97 ID bits */
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| 297 | #define IDX_MIXER_PLAY_MASTER 0x02
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| 298 | #define IDX_MIXER_MODEMOUT 0x04
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| 299 | #define IDX_MIXER_BASSTREBLE 0x06
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| 300 | #define MIXER_BASSTREBLE_TREBLE_VOLUME_MASK 0x000e
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| 301 | #define MIXER_BASSTREBLE_BASS_VOLUME_MASK 0x0e00
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| 302 | #define IDX_MIXER_PCBEEP 0x08
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| 303 | #define IDX_MIXER_MODEMIN 0x0a
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| 304 | #define IDX_MIXER_MIC 0x0c
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| 305 | #define MIXER_MIC_MICGAIN_20DB_ENHANCEMENT_MASK 0x0040
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| 306 | #define IDX_MIXER_LINEIN 0x0e
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| 307 | #define IDX_MIXER_CDAUDIO 0x10
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| 308 | #define IDX_MIXER_VIDEO 0x12
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| 309 | #define IDX_MIXER_AUX 0x14
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| 310 | #define IDX_MIXER_WAVEOUT 0x16
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| 311 | #define IDX_MIXER_FMSYNTH 0x18
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| 312 | #define IDX_MIXER_REC_SELECT 0x1a
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| 313 | #define MIXER_REC_SELECT_MIC 0x00
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| 314 | #define MIXER_REC_SELECT_CD 0x01
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| 315 | #define MIXER_REC_SELECT_VIDEO 0x02
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| 316 | #define MIXER_REC_SELECT_AUX 0x03
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| 317 | #define MIXER_REC_SELECT_LINEIN 0x04
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| 318 | #define MIXER_REC_SELECT_MIXSTEREO 0x05
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| 319 | #define MIXER_REC_SELECT_MIXMONO 0x06
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| 320 | #define MIXER_REC_SELECT_MONOIN 0x07
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| 321 | #define IDX_MIXER_REC_VOLUME 0x1c
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| 322 | #define IDX_MIXER_ADVCTL1 0x1e
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| 323 | /* unlisted bits are unmodifiable */
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| 324 | #define MIXER_ADVCTL1_3DWIDTH_MASK 0x000e
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| 325 | #define MIXER_ADVCTL1_HIFI3D_MASK 0x0300 /* yup, this is missing the high bit that official AC97 contains, plus it doesn't have linear bit value range behaviour but instead acts weirdly (possibly we're dealing with two *different* 3D settings here??) */
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| 326 | #define IDX_MIXER_ADVCTL2 0x20 /* subset of AC97_GENERAL_PURPOSE reg! */
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| 327 | /* unlisted bits are unmodifiable */
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| 328 | #define MIXER_ADVCTL2_LPBK 0x0080 /* Loopback mode -- Win driver: "WaveOut3DBypass"? mutes WaveOut at LineOut */
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| 329 | #define MIXER_ADVCTL2_MS 0x0100 /* Mic Select 0=Mic1, 1=Mic2 -- Win driver: "ModemOutSelect"?? */
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| 330 | #define MIXER_ADVCTL2_MIX 0x0200 /* Mono output select 0=Mix, 1=Mic; Win driver: "MonoSelectSource"?? */
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| 331 | #define MIXER_ADVCTL2_3D 0x2000 /* 3D Enhancement 1=on */
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| 332 | #define MIXER_ADVCTL2_POP 0x8000 /* Pcm Out Path, 0=pre 3D, 1=post 3D */
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| 333 |
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| 334 | #define IDX_MIXER_SOMETHING30H 0x30 /* used, but unknown??? */
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| 335 |
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| 336 | /* driver internal flags */
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| 337 | #define SET_CHAN_LEFT 1
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| 338 | #define SET_CHAN_RIGHT 2
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| 339 |
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| 340 | /* helper macro to align I/O port ranges to 32bit I/O width */
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| 341 | #define AZF_ALIGN(x) (((x) + 3) & (~3))
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| 342 |
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| 343 | #endif /* __SOUND_AZT3328_H */
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