source: GPL/trunk/alsa-kernel/pci/atiixp.c@ 679

Last change on this file since 679 was 679, checked in by David Azarewicz, 4 years ago

Merge changes from Paul's uniaud32next branch.
File size: 45.9 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers
4 *
5 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
6 */
7
8#include <linux/io.h>
9#include <linux/delay.h>
10#include <linux/interrupt.h>
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <sound/core.h>
17#include <sound/pcm.h>
18#include <sound/pcm_params.h>
19#include <sound/info.h>
20#include <sound/ac97_codec.h>
21#include <sound/initval.h>
22
23#ifdef TARGET_OS2
24#define KBUILD_MODNAME "atiixp"
25#endif
26
27MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
28MODULE_DESCRIPTION("ATI IXP AC97 controller");
29MODULE_LICENSE("GPL");
30MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400/600}}");
31
32static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
33static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
34static int ac97_clock = 48000;
35static char *ac97_quirk;
36static bool spdif_aclink = 1;
37static int ac97_codec = -1;
38
39module_param(index, int, 0444);
40MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
41module_param(id, charp, 0444);
42MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
43module_param(ac97_clock, int, 0444);
44MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
45module_param(ac97_quirk, charp, 0444);
46MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
47module_param(ac97_codec, int, 0444);
48MODULE_PARM_DESC(ac97_codec, "Specify codec instead of probing.");
49module_param(spdif_aclink, bool, 0444);
50MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
51
52/* just for backward compatibility */
53//static bool enable;
54module_param(enable, bool, 0444);
55
56
57/*
58 */
59
60#define ATI_REG_ISR 0x00 /* interrupt source */
61#define ATI_REG_ISR_IN_XRUN (1U<<0)
62#define ATI_REG_ISR_IN_STATUS (1U<<1)
63#define ATI_REG_ISR_OUT_XRUN (1U<<2)
64#define ATI_REG_ISR_OUT_STATUS (1U<<3)
65#define ATI_REG_ISR_SPDF_XRUN (1U<<4)
66#define ATI_REG_ISR_SPDF_STATUS (1U<<5)
67#define ATI_REG_ISR_PHYS_INTR (1U<<8)
68#define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
69#define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
70#define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
71#define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
72#define ATI_REG_ISR_NEW_FRAME (1U<<13)
73
74#define ATI_REG_IER 0x04 /* interrupt enable */
75#define ATI_REG_IER_IN_XRUN_EN (1U<<0)
76#define ATI_REG_IER_IO_STATUS_EN (1U<<1)
77#define ATI_REG_IER_OUT_XRUN_EN (1U<<2)
78#define ATI_REG_IER_OUT_XRUN_COND (1U<<3)
79#define ATI_REG_IER_SPDF_XRUN_EN (1U<<4)
80#define ATI_REG_IER_SPDF_STATUS_EN (1U<<5)
81#define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
82#define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
83#define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
84#define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
85#define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
86#define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
87#define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */
88
89#define ATI_REG_CMD 0x08 /* command */
90#define ATI_REG_CMD_POWERDOWN (1U<<0)
91#define ATI_REG_CMD_RECEIVE_EN (1U<<1)
92#define ATI_REG_CMD_SEND_EN (1U<<2)
93#define ATI_REG_CMD_STATUS_MEM (1U<<3)
94#define ATI_REG_CMD_SPDF_OUT_EN (1U<<4)
95#define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5)
96#define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6)
97#define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6
98#define ATI_REG_CMD_IN_DMA_EN (1U<<8)
99#define ATI_REG_CMD_OUT_DMA_EN (1U<<9)
100#define ATI_REG_CMD_SPDF_DMA_EN (1U<<10)
101#define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11)
102#define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12)
103#define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12)
104#define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12)
105#define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12)
106#define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12)
107#define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16)
108#define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
109#define ATI_REG_CMD_INTERLEAVE_IN (1U<<21)
110#define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22)
111#define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
112#define ATI_REG_CMD_PACKED_DIS (1U<<24)
113#define ATI_REG_CMD_BURST_EN (1U<<25)
114#define ATI_REG_CMD_PANIC_EN (1U<<26)
115#define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
116#define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
117#define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
118#define ATI_REG_CMD_AC_SYNC (1U<<30)
119#define ATI_REG_CMD_AC_RESET (1U<<31)
120
121#define ATI_REG_PHYS_OUT_ADDR 0x0c
122#define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
123#define ATI_REG_PHYS_OUT_RW (1U<<2)
124#define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
125#define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
126#define ATI_REG_PHYS_OUT_DATA_SHIFT 16
127
128#define ATI_REG_PHYS_IN_ADDR 0x10
129#define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
130#define ATI_REG_PHYS_IN_ADDR_SHIFT 9
131#define ATI_REG_PHYS_IN_DATA_SHIFT 16
132
133#define ATI_REG_SLOTREQ 0x14
134
135#define ATI_REG_COUNTER 0x18
136#define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
137#define ATI_REG_COUNTER_BITCLOCK (31U<<8)
138
139#define ATI_REG_IN_FIFO_THRESHOLD 0x1c
140
141#define ATI_REG_IN_DMA_LINKPTR 0x20
142#define ATI_REG_IN_DMA_DT_START 0x24 /* RO */
143#define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */
144#define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */
145#define ATI_REG_IN_DMA_DT_SIZE 0x30
146
147#define ATI_REG_OUT_DMA_SLOT 0x34
148#define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3))
149#define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff
150#define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800
151#define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11
152
153#define ATI_REG_OUT_DMA_LINKPTR 0x38
154#define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */
155#define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */
156#define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */
157#define ATI_REG_OUT_DMA_DT_SIZE 0x48
158
159#define ATI_REG_SPDF_CMD 0x4c
160#define ATI_REG_SPDF_CMD_LFSR (1U<<4)
161#define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5)
162#define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */
163
164#define ATI_REG_SPDF_DMA_LINKPTR 0x50
165#define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */
166#define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */
167#define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */
168#define ATI_REG_SPDF_DMA_DT_SIZE 0x60
169
170#define ATI_REG_MODEM_MIRROR 0x7c
171#define ATI_REG_AUDIO_MIRROR 0x80
172
173#define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */
174#define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */
175
176#define ATI_REG_FIFO_FLUSH 0x88
177#define ATI_REG_FIFO_OUT_FLUSH (1U<<0)
178#define ATI_REG_FIFO_IN_FLUSH (1U<<1)
179
180/* LINKPTR */
181#define ATI_REG_LINKPTR_EN (1U<<0)
182
183/* [INT|OUT|SPDIF]_DMA_DT_SIZE */
184#define ATI_REG_DMA_DT_SIZE (0xffffU<<0)
185#define ATI_REG_DMA_FIFO_USED (0x1fU<<16)
186#define ATI_REG_DMA_FIFO_FREE (0x1fU<<21)
187#define ATI_REG_DMA_STATE (7U<<26)
188
189
190#define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
191
192
193struct atiixp;
194
195/*
196 * DMA packate descriptor
197 */
198
199struct atiixp_dma_desc {
200 __le32 addr; /* DMA buffer address */
201 u16 status; /* status bits */
202 u16 size; /* size of the packet in dwords */
203 __le32 next; /* address of the next packet descriptor */
204};
205
206/*
207 * stream enum
208 */
209enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */
210enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */
211enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */
212
213#define NUM_ATI_CODECS 3
214
215
216/*
217 * constants and callbacks for each DMA type
218 */
219struct atiixp_dma_ops {
220 int type; /* ATI_DMA_XXX */
221 unsigned int llp_offset; /* LINKPTR offset */
222 unsigned int dt_cur; /* DT_CUR offset */
223 /* called from open callback */
224 void (*enable_dma)(struct atiixp *chip, int on);
225 /* called from trigger (START/STOP) */
226 void (*enable_transfer)(struct atiixp *chip, int on);
227 /* called from trigger (STOP only) */
228 void (*flush_dma)(struct atiixp *chip);
229};
230
231/*
232 * DMA stream
233 */
234struct atiixp_dma {
235 const struct atiixp_dma_ops *ops;
236 struct snd_dma_buffer desc_buf;
237 struct snd_pcm_substream *substream; /* assigned PCM substream */
238 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
239 unsigned int period_bytes, periods;
240 int opened;
241 int running;
242 int suspended;
243 int pcm_open_flag;
244 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
245 unsigned int saved_curptr;
246};
247
248/*
249 * ATI IXP chip
250 */
251struct atiixp {
252 struct snd_card *card;
253 struct pci_dev *pci;
254
255 unsigned long addr;
256 void __iomem *remap_addr;
257 int irq;
258
259 struct snd_ac97_bus *ac97_bus;
260 struct snd_ac97 *ac97[NUM_ATI_CODECS];
261
262 spinlock_t reg_lock;
263
264 struct atiixp_dma dmas[NUM_ATI_DMAS];
265 struct ac97_pcm *pcms[NUM_ATI_PCMS];
266 struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS];
267
268 int max_channels; /* max. channels for PCM out */
269
270 unsigned int codec_not_ready_bits; /* for codec detection */
271
272 int spdif_over_aclink; /* passed from the module option */
273 struct mutex open_mutex; /* playback open mutex */
274};
275
276
277/*
278 */
279static const struct pci_device_id snd_atiixp_ids[] = {
280 { PCI_VDEVICE(ATI, 0x4341), 0 }, /* SB200 */
281 { PCI_VDEVICE(ATI, 0x4361), 0 }, /* SB300 */
282 { PCI_VDEVICE(ATI, 0x4370), 0 }, /* SB400 */
283 { PCI_VDEVICE(ATI, 0x4382), 0 }, /* SB600 */
284 { 0, }
285};
286
287MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
288
289static const struct snd_pci_quirk atiixp_quirks[] = {
290 SND_PCI_QUIRK(0x105b, 0x0c81, "Foxconn RC4107MA-RS2", 0),
291 SND_PCI_QUIRK(0x15bd, 0x3100, "DFI RS482", 0),
292 {0} /* terminator */
293};
294
295/*
296 * lowlevel functions
297 */
298
299/*
300 * update the bits of the given register.
301 * return 1 if the bits changed.
302 */
303static int snd_atiixp_update_bits(struct atiixp *chip, unsigned int reg,
304 unsigned int mask, unsigned int value)
305{
306 void __iomem *addr = chip->remap_addr + reg;
307 unsigned int data, old_data;
308 old_data = data = readl(addr);
309 data &= ~mask;
310 data |= value;
311 if (old_data == data)
312 return 0;
313 writel(data, addr);
314 return 1;
315}
316
317/*
318 * macros for easy use
319 */
320#define atiixp_write(chip,reg,value) \
321 writel(value, chip->remap_addr + ATI_REG_##reg)
322#define atiixp_read(chip,reg) \
323 readl(chip->remap_addr + ATI_REG_##reg)
324#define atiixp_update(chip,reg,mask,val) \
325 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
326
327/*
328 * handling DMA packets
329 *
330 * we allocate a linear buffer for the DMA, and split it to each packet.
331 * in a future version, a scatter-gather buffer should be implemented.
332 */
333
334#define ATI_DESC_LIST_SIZE \
335 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc))
336
337/*
338 * build packets ring for the given buffer size.
339 *
340 * IXP handles the buffer descriptors, which are connected as a linked
341 * list. although we can change the list dynamically, in this version,
342 * a static RING of buffer descriptors is used.
343 *
344 * the ring is built in this function, and is set up to the hardware.
345 */
346static int atiixp_build_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
347 struct snd_pcm_substream *substream,
348 unsigned int periods,
349 unsigned int period_bytes)
350{
351 unsigned int i;
352 u32 addr, desc_addr;
353 unsigned long flags;
354
355 if (periods > ATI_MAX_DESCRIPTORS)
356 return -ENOMEM;
357
358 if (dma->desc_buf.area == NULL) {
359 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
360 &chip->pci->dev,
361 ATI_DESC_LIST_SIZE,
362 &dma->desc_buf) < 0)
363 return -ENOMEM;
364 dma->period_bytes = dma->periods = 0; /* clear */
365 }
366
367 if (dma->periods == periods && dma->period_bytes == period_bytes) {
368 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
369 (char*)chip->remap_addr + dma->ops->llp_offset);
370 return 0;
371 }
372
373 /* reset DMA before changing the descriptor table */
374 spin_lock_irqsave(&chip->reg_lock, flags);
375 writel(0, chip->remap_addr + dma->ops->llp_offset);
376 dma->ops->enable_dma(chip, 0);
377 dma->ops->enable_dma(chip, 1);
378 spin_unlock_irqrestore(&chip->reg_lock, flags);
379
380 /* fill the entries */
381 addr = (u32)substream->runtime->dma_addr;
382 desc_addr = (u32)dma->desc_buf.addr;
383 for (i = 0; i < periods; i++) {
384 struct atiixp_dma_desc *desc;
385 desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i];
386 desc->addr = cpu_to_le32(addr);
387 desc->status = 0;
388 desc->size = period_bytes >> 2; /* in dwords */
389 desc_addr += sizeof(struct atiixp_dma_desc);
390 if (i == periods - 1)
391 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
392 else
393 desc->next = cpu_to_le32(desc_addr);
394 addr += period_bytes;
395 }
396
397 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
398 chip->remap_addr + dma->ops->llp_offset);
399
400 dma->period_bytes = period_bytes;
401 dma->periods = periods;
402
403 return 0;
404}
405
406/*
407 * remove the ring buffer and release it if assigned
408 */
409static void atiixp_clear_dma_packets(struct atiixp *chip, struct atiixp_dma *dma,
410 struct snd_pcm_substream *substream)
411{
412 if (dma->desc_buf.area) {
413 writel(0, chip->remap_addr + dma->ops->llp_offset);
414 snd_dma_free_pages(&dma->desc_buf);
415 dma->desc_buf.area = NULL;
416 }
417}
418
419/*
420 * AC97 interface
421 */
422static int snd_atiixp_acquire_codec(struct atiixp *chip)
423{
424 int timeout = 1000;
425
426 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
427 if (! timeout--) {
428 dev_warn(chip->card->dev, "codec acquire timeout\n");
429 return -EBUSY;
430 }
431 udelay(1);
432 }
433 return 0;
434}
435
436static unsigned short snd_atiixp_codec_read(struct atiixp *chip, unsigned short codec, unsigned short reg)
437{
438 unsigned int data;
439 int timeout;
440
441 if (snd_atiixp_acquire_codec(chip) < 0)
442 return 0xffff;
443 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
444 ATI_REG_PHYS_OUT_ADDR_EN |
445 ATI_REG_PHYS_OUT_RW |
446 codec;
447 atiixp_write(chip, PHYS_OUT_ADDR, data);
448 if (snd_atiixp_acquire_codec(chip) < 0)
449 return 0xffff;
450 timeout = 1000;
451 do {
452 data = atiixp_read(chip, PHYS_IN_ADDR);
453 if (data & ATI_REG_PHYS_IN_READ_FLAG)
454 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
455 udelay(1);
456 } while (--timeout);
457 /* time out may happen during reset */
458 if (reg < 0x7c)
459 dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg);
460 return 0xffff;
461}
462
463
464static void snd_atiixp_codec_write(struct atiixp *chip, unsigned short codec,
465 unsigned short reg, unsigned short val)
466{
467 unsigned int data;
468
469 if (snd_atiixp_acquire_codec(chip) < 0)
470 return;
471 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
472 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
473 ATI_REG_PHYS_OUT_ADDR_EN | codec;
474 atiixp_write(chip, PHYS_OUT_ADDR, data);
475}
476
477
478static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97,
479 unsigned short reg)
480{
481 struct atiixp *chip = ac97->private_data;
482 return snd_atiixp_codec_read(chip, ac97->num, reg);
483
484}
485
486static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
487 unsigned short val)
488{
489 struct atiixp *chip = ac97->private_data;
490 snd_atiixp_codec_write(chip, ac97->num, reg, val);
491}
492
493/*
494 * reset AC link
495 */
496static int snd_atiixp_aclink_reset(struct atiixp *chip)
497{
498 int timeout;
499
500 /* reset powerdoewn */
501 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
502 udelay(10);
503
504 /* perform a software reset */
505 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
506#pragma disable_message (302)
507 atiixp_read(chip, CMD);
508 udelay(10);
509 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
510
511 timeout = 10;
512 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
513 /* do a hard reset */
514 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
515 ATI_REG_CMD_AC_SYNC);
516 atiixp_read(chip, CMD);
517 mdelay(1);
518 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
519 if (!--timeout) {
520 dev_err(chip->card->dev, "codec reset timeout\n");
521 break;
522 }
523 }
524#pragma enable_message (302)
525
526 /* deassert RESET and assert SYNC to make sure */
527 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
528 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
529
530 return 0;
531}
532
533#ifdef CONFIG_PM_SLEEP
534static int snd_atiixp_aclink_down(struct atiixp *chip)
535{
536 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
537 // return -EBUSY;
538 atiixp_update(chip, CMD,
539 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
540 ATI_REG_CMD_POWERDOWN);
541 return 0;
542}
543#endif
544
545/*
546 * auto-detection of codecs
547 *
548 * the IXP chip can generate interrupts for the non-existing codecs.
549 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
550 * even if all three codecs are connected.
551 */
552
553#define ALL_CODEC_NOT_READY \
554 (ATI_REG_ISR_CODEC0_NOT_READY |\
555 ATI_REG_ISR_CODEC1_NOT_READY |\
556 ATI_REG_ISR_CODEC2_NOT_READY)
557#define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
558
559static int ac97_probing_bugs(struct pci_dev *pci)
560{
561 const struct snd_pci_quirk *q;
562
563 q = snd_pci_quirk_lookup(pci, atiixp_quirks);
564 if (q) {
565 dev_dbg(&pci->dev, "atiixp quirk for %s. Forcing codec %d\n",
566 snd_pci_quirk_name(q), q->value);
567
568 return q->value;
569 }
570 /* this hardware doesn't need workarounds. Probe for codec */
571 return -1;
572}
573
574static int snd_atiixp_codec_detect(struct atiixp *chip)
575{
576 int timeout;
577
578 chip->codec_not_ready_bits = 0;
579 if (ac97_codec == -1)
580 ac97_codec = ac97_probing_bugs(chip->pci);
581 if (ac97_codec >= 0) {
582 chip->codec_not_ready_bits |=
583 CODEC_CHECK_BITS ^ (1 << (ac97_codec + 10));
584 return 0;
585 }
586
587 atiixp_write(chip, IER, CODEC_CHECK_BITS);
588 /* wait for the interrupts */
589 timeout = 50;
590 while (timeout-- > 0) {
591 mdelay(1);
592 if (chip->codec_not_ready_bits)
593 break;
594 }
595 atiixp_write(chip, IER, 0); /* disable irqs */
596
597 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
598 dev_err(chip->card->dev, "no codec detected!\n");
599 return -ENXIO;
600 }
601 return 0;
602}
603
604
605/*
606 * enable DMA and irqs
607 */
608static int snd_atiixp_chip_start(struct atiixp *chip)
609{
610 unsigned int reg;
611
612 /* set up spdif, enable burst mode */
613 reg = atiixp_read(chip, CMD);
614 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT;
615 reg |= ATI_REG_CMD_BURST_EN;
616 atiixp_write(chip, CMD, reg);
617
618 reg = atiixp_read(chip, SPDF_CMD);
619 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH);
620 atiixp_write(chip, SPDF_CMD, reg);
621
622 /* clear all interrupt source */
623 atiixp_write(chip, ISR, 0xffffffff);
624 /* enable irqs */
625 atiixp_write(chip, IER,
626 ATI_REG_IER_IO_STATUS_EN |
627 ATI_REG_IER_IN_XRUN_EN |
628 ATI_REG_IER_OUT_XRUN_EN |
629 ATI_REG_IER_SPDF_XRUN_EN |
630 ATI_REG_IER_SPDF_STATUS_EN);
631 return 0;
632}
633
634
635/*
636 * disable DMA and IRQs
637 */
638static int snd_atiixp_chip_stop(struct atiixp *chip)
639{
640 /* clear interrupt source */
641 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
642 /* disable irqs */
643 atiixp_write(chip, IER, 0);
644 return 0;
645}
646
647
648/*
649 * PCM section
650 */
651
652/*
653 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
654 * position. when SG-buffer is implemented, the offset must be calculated
655 * correctly...
656 */
657static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream)
658{
659 struct atiixp *chip = snd_pcm_substream_chip(substream);
660 struct snd_pcm_runtime *runtime = substream->runtime;
661 struct atiixp_dma *dma = runtime->private_data;
662 unsigned int curptr;
663 int timeout = 1000;
664
665 while (timeout--) {
666 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
667 if (curptr < dma->buf_addr)
668 continue;
669 curptr -= dma->buf_addr;
670 if (curptr >= dma->buf_bytes)
671 continue;
672 return bytes_to_frames(runtime, curptr);
673 }
674 dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n",
675 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr);
676 return 0;
677}
678
679/*
680 * XRUN detected, and stop the PCM substream
681 */
682static void snd_atiixp_xrun_dma(struct atiixp *chip, struct atiixp_dma *dma)
683{
684 if (! dma->substream || ! dma->running)
685 return;
686 dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type);
687 snd_pcm_stop_xrun(dma->substream);
688}
689
690/*
691 * the period ack. update the substream.
692 */
693static void snd_atiixp_update_dma(struct atiixp *chip, struct atiixp_dma *dma)
694{
695 if (! dma->substream || ! dma->running)
696 return;
697 snd_pcm_period_elapsed(dma->substream);
698}
699
700/* set BUS_BUSY interrupt bit if any DMA is running */
701/* call with spinlock held */
702static void snd_atiixp_check_bus_busy(struct atiixp *chip)
703{
704 unsigned int bus_busy;
705 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN |
706 ATI_REG_CMD_RECEIVE_EN |
707 ATI_REG_CMD_SPDF_OUT_EN))
708 bus_busy = ATI_REG_IER_SET_BUS_BUSY;
709 else
710 bus_busy = 0;
711 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy);
712}
713
714/* common trigger callback
715 * calling the lowlevel callbacks in it
716 */
717static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
718{
719 struct atiixp *chip = snd_pcm_substream_chip(substream);
720 struct atiixp_dma *dma = substream->runtime->private_data;
721 int err = 0;
722
723 if (snd_BUG_ON(!dma->ops->enable_transfer ||
724 !dma->ops->flush_dma))
725 return -EINVAL;
726
727 spin_lock(&chip->reg_lock);
728 switch (cmd) {
729 case SNDRV_PCM_TRIGGER_START:
730 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
731 case SNDRV_PCM_TRIGGER_RESUME:
732 if (dma->running && dma->suspended &&
733 cmd == SNDRV_PCM_TRIGGER_RESUME)
734 writel(dma->saved_curptr, chip->remap_addr +
735 dma->ops->dt_cur);
736 dma->ops->enable_transfer(chip, 1);
737 dma->running = 1;
738 dma->suspended = 0;
739 break;
740 case SNDRV_PCM_TRIGGER_STOP:
741 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
742 case SNDRV_PCM_TRIGGER_SUSPEND:
743 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND;
744 if (dma->running && dma->suspended)
745 dma->saved_curptr = readl(chip->remap_addr +
746 dma->ops->dt_cur);
747 dma->ops->enable_transfer(chip, 0);
748 dma->running = 0;
749 break;
750 default:
751 err = -EINVAL;
752 break;
753 }
754 if (! err) {
755 snd_atiixp_check_bus_busy(chip);
756 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
757 dma->ops->flush_dma(chip);
758 snd_atiixp_check_bus_busy(chip);
759 }
760 }
761 spin_unlock(&chip->reg_lock);
762 return err;
763}
764
765
766/*
767 * lowlevel callbacks for each DMA type
768 *
769 * every callback is supposed to be called in chip->reg_lock spinlock
770 */
771
772/* flush FIFO of analog OUT DMA */
773static void atiixp_out_flush_dma(struct atiixp *chip)
774{
775 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH);
776}
777
778/* enable/disable analog OUT DMA */
779static void atiixp_out_enable_dma(struct atiixp *chip, int on)
780{
781 unsigned int data;
782 data = atiixp_read(chip, CMD);
783 if (on) {
784 if (data & ATI_REG_CMD_OUT_DMA_EN)
785 return;
786 atiixp_out_flush_dma(chip);
787 data |= ATI_REG_CMD_OUT_DMA_EN;
788 } else
789 data &= ~ATI_REG_CMD_OUT_DMA_EN;
790 atiixp_write(chip, CMD, data);
791}
792
793/* start/stop transfer over OUT DMA */
794static void atiixp_out_enable_transfer(struct atiixp *chip, int on)
795{
796 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN,
797 on ? ATI_REG_CMD_SEND_EN : 0);
798}
799
800/* enable/disable analog IN DMA */
801static void atiixp_in_enable_dma(struct atiixp *chip, int on)
802{
803 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN,
804 on ? ATI_REG_CMD_IN_DMA_EN : 0);
805}
806
807/* start/stop analog IN DMA */
808static void atiixp_in_enable_transfer(struct atiixp *chip, int on)
809{
810 if (on) {
811 unsigned int data = atiixp_read(chip, CMD);
812 if (! (data & ATI_REG_CMD_RECEIVE_EN)) {
813 data |= ATI_REG_CMD_RECEIVE_EN;
814#if 0 /* FIXME: this causes the endless loop */
815 /* wait until slot 3/4 are finished */
816 while ((atiixp_read(chip, COUNTER) &
817 ATI_REG_COUNTER_SLOT) != 5)
818 ;
819#endif
820 atiixp_write(chip, CMD, data);
821 }
822 } else
823 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0);
824}
825
826/* flush FIFO of analog IN DMA */
827static void atiixp_in_flush_dma(struct atiixp *chip)
828{
829 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH);
830}
831
832/* enable/disable SPDIF OUT DMA */
833static void atiixp_spdif_enable_dma(struct atiixp *chip, int on)
834{
835 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN,
836 on ? ATI_REG_CMD_SPDF_DMA_EN : 0);
837}
838
839/* start/stop SPDIF OUT DMA */
840static void atiixp_spdif_enable_transfer(struct atiixp *chip, int on)
841{
842 unsigned int data;
843 data = atiixp_read(chip, CMD);
844 if (on)
845 data |= ATI_REG_CMD_SPDF_OUT_EN;
846 else
847 data &= ~ATI_REG_CMD_SPDF_OUT_EN;
848 atiixp_write(chip, CMD, data);
849}
850
851/* flush FIFO of SPDIF OUT DMA */
852static void atiixp_spdif_flush_dma(struct atiixp *chip)
853{
854 int timeout;
855
856 /* DMA off, transfer on */
857 atiixp_spdif_enable_dma(chip, 0);
858 atiixp_spdif_enable_transfer(chip, 1);
859
860 timeout = 100;
861 do {
862 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED))
863 break;
864 udelay(1);
865 } while (timeout-- > 0);
866
867 atiixp_spdif_enable_transfer(chip, 0);
868}
869
870/* set up slots and formats for SPDIF OUT */
871static int snd_atiixp_spdif_prepare(struct snd_pcm_substream *substream)
872{
873 struct atiixp *chip = snd_pcm_substream_chip(substream);
874
875 spin_lock_irq(&chip->reg_lock);
876 if (chip->spdif_over_aclink) {
877 unsigned int data;
878 /* enable slots 10/11 */
879 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK,
880 ATI_REG_CMD_SPDF_CONFIG_01);
881 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
882 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
883 ATI_REG_OUT_DMA_SLOT_BIT(11);
884 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
885 atiixp_write(chip, OUT_DMA_SLOT, data);
886 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
887 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
888 ATI_REG_CMD_INTERLEAVE_OUT : 0);
889 } else {
890 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0);
891 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0);
892 }
893 spin_unlock_irq(&chip->reg_lock);
894 return 0;
895}
896
897/* set up slots and formats for analog OUT */
898static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream)
899{
900 struct atiixp *chip = snd_pcm_substream_chip(substream);
901 unsigned int data;
902
903 spin_lock_irq(&chip->reg_lock);
904 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK;
905 switch (substream->runtime->channels) {
906 case 8:
907 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) |
908 ATI_REG_OUT_DMA_SLOT_BIT(11);
909 fallthrough;
910 case 6:
911 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) |
912 ATI_REG_OUT_DMA_SLOT_BIT(8);
913 fallthrough;
914 case 4:
915 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) |
916 ATI_REG_OUT_DMA_SLOT_BIT(9);
917 fallthrough;
918 default:
919 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) |
920 ATI_REG_OUT_DMA_SLOT_BIT(4);
921 break;
922 }
923
924 /* set output threshold */
925 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT;
926 atiixp_write(chip, OUT_DMA_SLOT, data);
927
928 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT,
929 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
930 ATI_REG_CMD_INTERLEAVE_OUT : 0);
931
932 /*
933 * enable 6 channel re-ordering bit if needed
934 */
935 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN,
936 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0);
937
938 spin_unlock_irq(&chip->reg_lock);
939 return 0;
940}
941
942/* set up slots and formats for analog IN */
943static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream)
944{
945 struct atiixp *chip = snd_pcm_substream_chip(substream);
946
947 spin_lock_irq(&chip->reg_lock);
948 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN,
949 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ?
950 ATI_REG_CMD_INTERLEAVE_IN : 0);
951 spin_unlock_irq(&chip->reg_lock);
952 return 0;
953}
954
955/*
956 * hw_params - allocate the buffer and set up buffer descriptors
957 */
958static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream,
959 struct snd_pcm_hw_params *hw_params)
960{
961 struct atiixp *chip = snd_pcm_substream_chip(substream);
962 struct atiixp_dma *dma = substream->runtime->private_data;
963 int err;
964
965 dma->buf_addr = substream->runtime->dma_addr;
966 dma->buf_bytes = params_buffer_bytes(hw_params);
967
968 err = atiixp_build_dma_packets(chip, dma, substream,
969 params_periods(hw_params),
970 params_period_bytes(hw_params));
971 if (err < 0)
972 return err;
973
974 if (dma->ac97_pcm_type >= 0) {
975 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
976 /* PCM is bound to AC97 codec(s)
977 * set up the AC97 codecs
978 */
979 if (dma->pcm_open_flag) {
980 snd_ac97_pcm_close(pcm);
981 dma->pcm_open_flag = 0;
982 }
983 err = snd_ac97_pcm_open(pcm, params_rate(hw_params),
984 params_channels(hw_params),
985 pcm->r[0].slots);
986 if (err >= 0)
987 dma->pcm_open_flag = 1;
988 }
989
990 return err;
991}
992
993static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream)
994{
995 struct atiixp *chip = snd_pcm_substream_chip(substream);
996 struct atiixp_dma *dma = substream->runtime->private_data;
997
998 if (dma->pcm_open_flag) {
999 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type];
1000 snd_ac97_pcm_close(pcm);
1001 dma->pcm_open_flag = 0;
1002 }
1003 atiixp_clear_dma_packets(chip, dma, substream);
1004 return 0;
1005}
1006
1007
1008/*
1009 * pcm hardware definition, identical for all DMA types
1010 */
1011static const struct snd_pcm_hardware snd_atiixp_pcm_hw =
1012{
1013 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1014 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1015 SNDRV_PCM_INFO_PAUSE |
1016 SNDRV_PCM_INFO_RESUME |
1017 SNDRV_PCM_INFO_MMAP_VALID),
1018 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
1019 .rates = SNDRV_PCM_RATE_48000,
1020 .rate_min = 48000,
1021 .rate_max = 48000,
1022 .channels_min = 2,
1023 .channels_max = 2,
1024 .buffer_bytes_max = 256 * 1024,
1025 .period_bytes_min = 32,
1026 .period_bytes_max = 128 * 1024,
1027 .periods_min = 2,
1028 .periods_max = ATI_MAX_DESCRIPTORS,
1029};
1030
1031static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream,
1032 struct atiixp_dma *dma, int pcm_type)
1033{
1034 struct atiixp *chip = snd_pcm_substream_chip(substream);
1035 struct snd_pcm_runtime *runtime = substream->runtime;
1036 int err;
1037
1038 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1039 return -EINVAL;
1040
1041 if (dma->opened)
1042 return -EBUSY;
1043 dma->substream = substream;
1044 runtime->hw = snd_atiixp_pcm_hw;
1045 dma->ac97_pcm_type = pcm_type;
1046 if (pcm_type >= 0) {
1047 runtime->hw.rates = chip->pcms[pcm_type]->rates;
1048 snd_pcm_limit_hw_rates(runtime);
1049 } else {
1050 /* direct SPDIF */
1051 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
1052 }
1053 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1054 return err;
1055 runtime->private_data = dma;
1056
1057 /* enable DMA bits */
1058 spin_lock_irq(&chip->reg_lock);
1059 dma->ops->enable_dma(chip, 1);
1060 spin_unlock_irq(&chip->reg_lock);
1061 dma->opened = 1;
1062
1063 return 0;
1064}
1065
1066static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream,
1067 struct atiixp_dma *dma)
1068{
1069 struct atiixp *chip = snd_pcm_substream_chip(substream);
1070 /* disable DMA bits */
1071 if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma))
1072 return -EINVAL;
1073 spin_lock_irq(&chip->reg_lock);
1074 dma->ops->enable_dma(chip, 0);
1075 spin_unlock_irq(&chip->reg_lock);
1076 dma->substream = NULL;
1077 dma->opened = 0;
1078 return 0;
1079}
1080
1081/*
1082 */
1083static int snd_atiixp_playback_open(struct snd_pcm_substream *substream)
1084{
1085 struct atiixp *chip = snd_pcm_substream_chip(substream);
1086 int err;
1087
1088 mutex_lock(&chip->open_mutex);
1089 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
1090 mutex_unlock(&chip->open_mutex);
1091 if (err < 0)
1092 return err;
1093 substream->runtime->hw.channels_max = chip->max_channels;
1094 if (chip->max_channels > 2)
1095 /* channels must be even */
1096 snd_pcm_hw_constraint_step(substream->runtime, 0,
1097 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1098 return 0;
1099}
1100
1101static int snd_atiixp_playback_close(struct snd_pcm_substream *substream)
1102{
1103 struct atiixp *chip = snd_pcm_substream_chip(substream);
1104 int err;
1105 mutex_lock(&chip->open_mutex);
1106 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1107 mutex_unlock(&chip->open_mutex);
1108 return err;
1109}
1110
1111static int snd_atiixp_capture_open(struct snd_pcm_substream *substream)
1112{
1113 struct atiixp *chip = snd_pcm_substream_chip(substream);
1114 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
1115}
1116
1117static int snd_atiixp_capture_close(struct snd_pcm_substream *substream)
1118{
1119 struct atiixp *chip = snd_pcm_substream_chip(substream);
1120 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
1121}
1122
1123static int snd_atiixp_spdif_open(struct snd_pcm_substream *substream)
1124{
1125 struct atiixp *chip = snd_pcm_substream_chip(substream);
1126 int err;
1127 mutex_lock(&chip->open_mutex);
1128 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */
1129 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2);
1130 else
1131 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1);
1132 mutex_unlock(&chip->open_mutex);
1133 return err;
1134}
1135
1136static int snd_atiixp_spdif_close(struct snd_pcm_substream *substream)
1137{
1138 struct atiixp *chip = snd_pcm_substream_chip(substream);
1139 int err;
1140 mutex_lock(&chip->open_mutex);
1141 if (chip->spdif_over_aclink)
1142 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
1143 else
1144 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]);
1145 mutex_unlock(&chip->open_mutex);
1146 return err;
1147}
1148
1149/* AC97 playback */
1150static const struct snd_pcm_ops snd_atiixp_playback_ops = {
1151 .open = snd_atiixp_playback_open,
1152 .close = snd_atiixp_playback_close,
1153 .hw_params = snd_atiixp_pcm_hw_params,
1154 .hw_free = snd_atiixp_pcm_hw_free,
1155 .prepare = snd_atiixp_playback_prepare,
1156 .trigger = snd_atiixp_pcm_trigger,
1157 .pointer = snd_atiixp_pcm_pointer,
1158};
1159
1160/* AC97 capture */
1161static const struct snd_pcm_ops snd_atiixp_capture_ops = {
1162 .open = snd_atiixp_capture_open,
1163 .close = snd_atiixp_capture_close,
1164 .hw_params = snd_atiixp_pcm_hw_params,
1165 .hw_free = snd_atiixp_pcm_hw_free,
1166 .prepare = snd_atiixp_capture_prepare,
1167 .trigger = snd_atiixp_pcm_trigger,
1168 .pointer = snd_atiixp_pcm_pointer,
1169};
1170
1171/* SPDIF playback */
1172static const struct snd_pcm_ops snd_atiixp_spdif_ops = {
1173 .open = snd_atiixp_spdif_open,
1174 .close = snd_atiixp_spdif_close,
1175 .hw_params = snd_atiixp_pcm_hw_params,
1176 .hw_free = snd_atiixp_pcm_hw_free,
1177 .prepare = snd_atiixp_spdif_prepare,
1178 .trigger = snd_atiixp_pcm_trigger,
1179 .pointer = snd_atiixp_pcm_pointer,
1180};
1181
1182static const struct ac97_pcm atiixp_pcm_defs[] = {
1183 /* front PCM */
1184 {
1185 .exclusive = 1,
1186 .r = { {
1187 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1188 (1 << AC97_SLOT_PCM_RIGHT) |
1189 (1 << AC97_SLOT_PCM_CENTER) |
1190 (1 << AC97_SLOT_PCM_SLEFT) |
1191 (1 << AC97_SLOT_PCM_SRIGHT) |
1192 (1 << AC97_SLOT_LFE)
1193 }
1194 }
1195 },
1196 /* PCM IN #1 */
1197 {
1198 .stream = 1,
1199 .exclusive = 1,
1200 .r = { {
1201 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1202 (1 << AC97_SLOT_PCM_RIGHT)
1203 }
1204 }
1205 },
1206 /* S/PDIF OUT (optional) */
1207 {
1208 .exclusive = 1,
1209 .spdif = 1,
1210 .r = { {
1211 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1212 (1 << AC97_SLOT_SPDIF_RIGHT2)
1213 }
1214 }
1215 },
1216};
1217
1218static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = {
1219 .type = ATI_DMA_PLAYBACK,
1220 .llp_offset = ATI_REG_OUT_DMA_LINKPTR,
1221 .dt_cur = ATI_REG_OUT_DMA_DT_CUR,
1222 .enable_dma = atiixp_out_enable_dma,
1223 .enable_transfer = atiixp_out_enable_transfer,
1224 .flush_dma = atiixp_out_flush_dma,
1225};
1226
1227static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = {
1228 .type = ATI_DMA_CAPTURE,
1229 .llp_offset = ATI_REG_IN_DMA_LINKPTR,
1230 .dt_cur = ATI_REG_IN_DMA_DT_CUR,
1231 .enable_dma = atiixp_in_enable_dma,
1232 .enable_transfer = atiixp_in_enable_transfer,
1233 .flush_dma = atiixp_in_flush_dma,
1234};
1235
1236static const struct atiixp_dma_ops snd_atiixp_spdif_dma_ops = {
1237 .type = ATI_DMA_SPDIF,
1238 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR,
1239 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR,
1240 .enable_dma = atiixp_spdif_enable_dma,
1241 .enable_transfer = atiixp_spdif_enable_transfer,
1242 .flush_dma = atiixp_spdif_flush_dma,
1243};
1244
1245
1246static int snd_atiixp_pcm_new(struct atiixp *chip)
1247{
1248 struct snd_pcm *pcm;
1249 struct snd_pcm_chmap *chmap;
1250 struct snd_ac97_bus *pbus = chip->ac97_bus;
1251 int err, i, num_pcms;
1252
1253 /* initialize constants */
1254 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
1255 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
1256 if (! chip->spdif_over_aclink)
1257 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops;
1258
1259 /* assign AC97 pcm */
1260 if (chip->spdif_over_aclink)
1261 num_pcms = 3;
1262 else
1263 num_pcms = 2;
1264 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs);
1265 if (err < 0)
1266 return err;
1267 for (i = 0; i < num_pcms; i++)
1268 chip->pcms[i] = &pbus->pcms[i];
1269
1270 chip->max_channels = 2;
1271 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
1272 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE))
1273 chip->max_channels = 6;
1274 else
1275 chip->max_channels = 4;
1276 }
1277
1278 /* PCM #0: analog I/O */
1279 err = snd_pcm_new(chip->card, "ATI IXP AC97",
1280 ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1281 if (err < 0)
1282 return err;
1283 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1284 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1285 pcm->private_data = chip;
1286 strcpy(pcm->name, "ATI IXP AC97");
1287 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1288
1289 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1290 &chip->pci->dev, 64*1024, 128*1024);
1291
1292 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1293 snd_pcm_alt_chmaps, chip->max_channels, 0,
1294 &chmap);
1295 if (err < 0)
1296 return err;
1297 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
1298 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
1299
1300 /* no SPDIF support on codec? */
1301 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates)
1302 return 0;
1303
1304 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */
1305 if (chip->pcms[ATI_PCM_SPDIF])
1306 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000;
1307
1308 /* PCM #1: spdif playback */
1309 err = snd_pcm_new(chip->card, "ATI IXP IEC958",
1310 ATI_PCMDEV_DIGITAL, 1, 0, &pcm);
1311 if (err < 0)
1312 return err;
1313 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops);
1314 pcm->private_data = chip;
1315 if (chip->spdif_over_aclink)
1316 strcpy(pcm->name, "ATI IXP IEC958 (AC97)");
1317 else
1318 strcpy(pcm->name, "ATI IXP IEC958 (Direct)");
1319 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm;
1320
1321 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1322 &chip->pci->dev, 64*1024, 128*1024);
1323
1324 /* pre-select AC97 SPDIF slots 10/11 */
1325 for (i = 0; i < NUM_ATI_CODECS; i++) {
1326 if (chip->ac97[i])
1327 snd_ac97_update_bits(chip->ac97[i],
1328 AC97_EXTENDED_STATUS,
1329 0x03 << 4, 0x03 << 4);
1330 }
1331
1332 return 0;
1333}
1334
1335
1336
1337/*
1338 * interrupt handler
1339 */
1340static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id)
1341{
1342 struct atiixp *chip = dev_id;
1343 unsigned int status;
1344
1345 status = atiixp_read(chip, ISR);
1346
1347 if (! status)
1348 return IRQ_NONE;
1349
1350 /* process audio DMA */
1351 if (status & ATI_REG_ISR_OUT_XRUN)
1352 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1353 else if (status & ATI_REG_ISR_OUT_STATUS)
1354 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1355 if (status & ATI_REG_ISR_IN_XRUN)
1356 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1357 else if (status & ATI_REG_ISR_IN_STATUS)
1358 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1359 if (! chip->spdif_over_aclink) {
1360 if (status & ATI_REG_ISR_SPDF_XRUN)
1361 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1362 else if (status & ATI_REG_ISR_SPDF_STATUS)
1363 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]);
1364 }
1365
1366 /* for codec detection */
1367 if (status & CODEC_CHECK_BITS) {
1368 unsigned int detected;
1369 detected = status & CODEC_CHECK_BITS;
1370 spin_lock(&chip->reg_lock);
1371 chip->codec_not_ready_bits |= detected;
1372 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1373 spin_unlock(&chip->reg_lock);
1374 }
1375
1376 /* ack */
1377 atiixp_write(chip, ISR, status);
1378
1379 return IRQ_HANDLED;
1380}
1381
1382
1383/*
1384 * ac97 mixer section
1385 */
1386
1387static const struct ac97_quirk ac97_quirks[] = {
1388 {
1389 .subvendor = 0x103c,
1390 .subdevice = 0x006b,
1391 .name = "HP Pavilion ZV5030US",
1392 .type = AC97_TUNE_MUTE_LED
1393 },
1394 {
1395 .subvendor = 0x103c,
1396 .subdevice = 0x308b,
1397 .name = "HP nx6125",
1398 .type = AC97_TUNE_MUTE_LED
1399 },
1400 {
1401 .subvendor = 0x103c,
1402 .subdevice = 0x3091,
1403 .name = "unknown HP",
1404 .type = AC97_TUNE_MUTE_LED
1405 },
1406 {0} /* terminator */
1407};
1408
1409static int snd_atiixp_mixer_new(struct atiixp *chip, int clock,
1410 const char *quirk_override)
1411{
1412 struct snd_ac97_bus *pbus;
1413 struct snd_ac97_template ac97;
1414 int i, err;
1415 int codec_count;
1416 static const struct snd_ac97_bus_ops ops = {
1417 .write = snd_atiixp_ac97_write,
1418 .read = snd_atiixp_ac97_read,
1419 };
1420 static const unsigned int codec_skip[NUM_ATI_CODECS] = {
1421 ATI_REG_ISR_CODEC0_NOT_READY,
1422 ATI_REG_ISR_CODEC1_NOT_READY,
1423 ATI_REG_ISR_CODEC2_NOT_READY,
1424 };
1425
1426 if (snd_atiixp_codec_detect(chip) < 0)
1427 return -ENXIO;
1428
1429 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
1430 return err;
1431 pbus->clock = clock;
1432 chip->ac97_bus = pbus;
1433
1434 codec_count = 0;
1435 for (i = 0; i < NUM_ATI_CODECS; i++) {
1436 if (chip->codec_not_ready_bits & codec_skip[i])
1437 continue;
1438 memset(&ac97, 0, sizeof(ac97));
1439 ac97.private_data = chip;
1440 ac97.pci = chip->pci;
1441 ac97.num = i;
1442 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
1443 if (! chip->spdif_over_aclink)
1444 ac97.scaps |= AC97_SCAP_NO_SPDIF;
1445 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1446 chip->ac97[i] = NULL; /* to be sure */
1447 dev_dbg(chip->card->dev,
1448 "codec %d not available for audio\n", i);
1449 continue;
1450 }
1451 codec_count++;
1452 }
1453
1454 if (! codec_count) {
1455 dev_err(chip->card->dev, "no codec available\n");
1456 return -ENODEV;
1457 }
1458
1459 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
1460
1461 return 0;
1462}
1463
1464
1465#ifdef CONFIG_PM_SLEEP
1466/*
1467 * power management
1468 */
1469static int snd_atiixp_suspend(struct device *dev)
1470{
1471 struct snd_card *card = dev_get_drvdata(dev);
1472 struct atiixp *chip = card->private_data;
1473 int i;
1474
1475 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1476 for (i = 0; i < NUM_ATI_CODECS; i++)
1477 snd_ac97_suspend(chip->ac97[i]);
1478 snd_atiixp_aclink_down(chip);
1479 snd_atiixp_chip_stop(chip);
1480 return 0;
1481}
1482
1483static int snd_atiixp_resume(struct device *dev)
1484{
1485 struct snd_card *card = dev_get_drvdata(dev);
1486 struct atiixp *chip = card->private_data;
1487 int i;
1488
1489 snd_atiixp_aclink_reset(chip);
1490 snd_atiixp_chip_start(chip);
1491
1492 for (i = 0; i < NUM_ATI_CODECS; i++)
1493 snd_ac97_resume(chip->ac97[i]);
1494
1495 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1496 if (chip->pcmdevs[i]) {
1497 struct atiixp_dma *dma = &chip->dmas[i];
1498 if (dma->substream && dma->suspended) {
1499 dma->ops->enable_dma(chip, 1);
1500 dma->substream->ops->prepare(dma->substream);
1501 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
1502 chip->remap_addr + dma->ops->llp_offset);
1503 }
1504 }
1505
1506 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1507 return 0;
1508}
1509
1510static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume);
1511#define SND_ATIIXP_PM_OPS &snd_atiixp_pm
1512#else
1513#define SND_ATIIXP_PM_OPS NULL
1514#endif /* CONFIG_PM_SLEEP */
1515
1516
1517/*
1518 * proc interface for register dump
1519 */
1520
1521static void snd_atiixp_proc_read(struct snd_info_entry *entry,
1522 struct snd_info_buffer *buffer)
1523{
1524 struct atiixp *chip = entry->private_data;
1525 int i;
1526
1527 for (i = 0; i < 256; i += 4)
1528 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1529}
1530
1531static void snd_atiixp_proc_init(struct atiixp *chip)
1532{
1533 snd_card_ro_proc_new(chip->card, "atiixp", chip, snd_atiixp_proc_read);
1534}
1535
1536
1537/*
1538 * destructor
1539 */
1540
1541static int snd_atiixp_free(struct atiixp *chip)
1542{
1543 if (chip->irq < 0)
1544 goto __hw_end;
1545 snd_atiixp_chip_stop(chip);
1546
1547 __hw_end:
1548 if (chip->irq >= 0)
1549 free_irq(chip->irq, chip);
1550 iounmap(chip->remap_addr);
1551 pci_release_regions(chip->pci);
1552 pci_disable_device(chip->pci);
1553 kfree(chip);
1554 return 0;
1555}
1556
1557static int snd_atiixp_dev_free(struct snd_device *device)
1558{
1559 struct atiixp *chip = device->device_data;
1560 return snd_atiixp_free(chip);
1561}
1562
1563/*
1564 * constructor for chip instance
1565 */
1566static int snd_atiixp_create(struct snd_card *card,
1567 struct pci_dev *pci,
1568 struct atiixp **r_chip)
1569{
1570 static const struct snd_device_ops ops = {
1571 .dev_free = snd_atiixp_dev_free,
1572 };
1573 struct atiixp *chip;
1574 int err;
1575
1576 if ((err = pci_enable_device(pci)) < 0)
1577 return err;
1578
1579 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1580 if (chip == NULL) {
1581 pci_disable_device(pci);
1582 return -ENOMEM;
1583 }
1584
1585 spin_lock_init(&chip->reg_lock);
1586 mutex_init(&chip->open_mutex);
1587 chip->card = card;
1588 chip->pci = pci;
1589 chip->irq = -1;
1590 if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) {
1591 pci_disable_device(pci);
1592 kfree(chip);
1593 return err;
1594 }
1595 chip->addr = pci_resource_start(pci, 0);
1596 chip->remap_addr = pci_ioremap_bar(pci, 0);
1597 if (chip->remap_addr == NULL) {
1598 dev_err(card->dev, "AC'97 space ioremap problem\n");
1599 snd_atiixp_free(chip);
1600 return -EIO;
1601 }
1602
1603 if (request_irq(pci->irq, snd_atiixp_interrupt, IRQF_SHARED,
1604 KBUILD_MODNAME, chip)) {
1605 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1606 snd_atiixp_free(chip);
1607 return -EBUSY;
1608 }
1609 chip->irq = pci->irq;
1610 card->sync_irq = chip->irq;
1611 pci_set_master(pci);
1612
1613 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1614 snd_atiixp_free(chip);
1615 return err;
1616 }
1617
1618 *r_chip = chip;
1619 return 0;
1620}
1621
1622
1623static int snd_atiixp_probe(struct pci_dev *pci,
1624 const struct pci_device_id *pci_id)
1625{
1626 struct snd_card *card;
1627 struct atiixp *chip;
1628 int err;
1629
1630 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
1631 if (err < 0)
1632 return err;
1633
1634 strcpy(card->driver, spdif_aclink ? "ATIIXP" : "ATIIXP-SPDMA");
1635 strcpy(card->shortname, "ATI IXP");
1636 if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
1637 goto __error;
1638 card->private_data = chip;
1639
1640 if ((err = snd_atiixp_aclink_reset(chip)) < 0)
1641 goto __error;
1642
1643 chip->spdif_over_aclink = spdif_aclink;
1644
1645 if ((err = snd_atiixp_mixer_new(chip, ac97_clock, ac97_quirk)) < 0)
1646 goto __error;
1647
1648 if ((err = snd_atiixp_pcm_new(chip)) < 0)
1649 goto __error;
1650
1651 snd_atiixp_proc_init(chip);
1652
1653 snd_atiixp_chip_start(chip);
1654
1655 snprintf(card->longname, sizeof(card->longname),
1656 "%s rev %x with %s at %#lx, irq %i", card->shortname,
1657#ifndef TARGET_OS2
1658 pci->revision,
1659#else
1660 snd_pci_revision(pci),
1661#endif
1662 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?",
1663 chip->addr, chip->irq);
1664
1665 if ((err = snd_card_register(card)) < 0)
1666 goto __error;
1667
1668 pci_set_drvdata(pci, card);
1669 return 0;
1670
1671 __error:
1672 snd_card_free(card);
1673 return err;
1674}
1675
1676static void snd_atiixp_remove(struct pci_dev *pci)
1677{
1678 snd_card_free(pci_get_drvdata(pci));
1679}
1680
1681static struct pci_driver atiixp_driver = {
1682 .name = KBUILD_MODNAME,
1683 .id_table = snd_atiixp_ids,
1684 .probe = snd_atiixp_probe,
1685 .remove = snd_atiixp_remove,
1686 .driver = {
1687 .pm = SND_ATIIXP_PM_OPS,
1688 },
1689};
1690
1691module_pci_driver(atiixp_driver);
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