| 1 | /* SPDX-License-Identifier: GPL-2.0 */
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| 2 | /* Analog Devices 1889 audio driver
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| 3 | * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
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| 4 | */
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| 5 |
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| 6 | #ifndef __AD1889_H__
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| 7 | #define __AD1889_H__
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| 8 |
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| 9 | #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
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| 10 | #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
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| 11 | #define AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */
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| 12 | #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
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| 13 | #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
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| 14 | #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
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| 15 | #define AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */
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| 16 |
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| 17 | #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
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| 18 | #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
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| 19 | #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
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| 20 | #define AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */
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| 21 | #define AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo request point */
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| 22 | #define AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */
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| 23 | #define AD_DS_RAMC_RERQ 0x3000 /* res. fifo request point */
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| 24 |
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| 25 | #define AD_DS_WADA 0x04 /* wave channel mix attenuation */
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| 26 | #define AD_DS_WADA_RWAM 0x0080 /* right wave mute */
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| 27 | #define AD_DS_WADA_RWAA 0x001f /* right wave attenuation */
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| 28 | #define AD_DS_WADA_LWAM 0x8000 /* left wave mute */
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| 29 | #define AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */
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| 30 |
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| 31 | #define AD_DS_SYDA 0x06 /* synthesis channel mix attenuation */
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| 32 | #define AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */
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| 33 | #define AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */
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| 34 | #define AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */
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| 35 | #define AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */
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| 36 |
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| 37 | #define AD_DS_WAS 0x08 /* wave channel sample rate */
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| 38 | #define AD_DS_WAS_WAS 0xffff /* sample rate mask */
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| 39 |
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| 40 | #define AD_DS_RES 0x0a /* resampler channel sample rate */
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| 41 | #define AD_DS_RES_RES 0xffff /* sample rate mask */
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| 42 |
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| 43 | #define AD_DS_CCS 0x0c /* chip control/status */
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| 44 | #define AD_DS_CCS_ADO 0x0001 /* ADC channel overflow */
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| 45 | #define AD_DS_CCS_REO 0x0002 /* resampler channel overflow */
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| 46 | #define AD_DS_CCS_SYU 0x0004 /* synthesis channel underflow */
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| 47 | #define AD_DS_CCS_WAU 0x0008 /* wave channel underflow */
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| 48 | /* bits 4 -> 7, 9, 11 -> 14 reserved */
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| 49 | #define AD_DS_CCS_XTD 0x0100 /* xtd delay control (4096 clock cycles) */
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| 50 | #define AD_DS_CCS_PDALL 0x0400 /* power */
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| 51 | #define AD_DS_CCS_CLKEN 0x8000 /* clock */
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| 52 |
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| 53 | #define AD_DMA_RESBA 0x40 /* RES base address */
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| 54 | #define AD_DMA_RESCA 0x44 /* RES current address */
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| 55 | #define AD_DMA_RESBC 0x48 /* RES base count */
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| 56 | #define AD_DMA_RESCC 0x4c /* RES current count */
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| 57 |
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| 58 | #define AD_DMA_ADCBA 0x50 /* ADC base address */
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| 59 | #define AD_DMA_ADCCA 0x54 /* ADC current address */
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| 60 | #define AD_DMA_ADCBC 0x58 /* ADC base count */
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| 61 | #define AD_DMA_ADCCC 0x5c /* ADC current count */
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| 62 |
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| 63 | #define AD_DMA_SYNBA 0x60 /* synth base address */
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| 64 | #define AD_DMA_SYNCA 0x64 /* synth current address */
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| 65 | #define AD_DMA_SYNBC 0x68 /* synth base count */
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| 66 | #define AD_DMA_SYNCC 0x6c /* synth current count */
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| 67 |
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| 68 | #define AD_DMA_WAVBA 0x70 /* wave base address */
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| 69 | #define AD_DMA_WAVCA 0x74 /* wave current address */
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| 70 | #define AD_DMA_WAVBC 0x78 /* wave base count */
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| 71 | #define AD_DMA_WAVCC 0x7c /* wave current count */
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| 72 |
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| 73 | #define AD_DMA_RESIC 0x80 /* RES dma interrupt current byte count */
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| 74 | #define AD_DMA_RESIB 0x84 /* RES dma interrupt base byte count */
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| 75 |
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| 76 | #define AD_DMA_ADCIC 0x88 /* ADC dma interrupt current byte count */
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| 77 | #define AD_DMA_ADCIB 0x8c /* ADC dma interrupt base byte count */
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| 78 |
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| 79 | #define AD_DMA_SYNIC 0x90 /* synth dma interrupt current byte count */
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| 80 | #define AD_DMA_SYNIB 0x94 /* synth dma interrupt base byte count */
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| 81 |
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| 82 | #define AD_DMA_WAVIC 0x98 /* wave dma interrupt current byte count */
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| 83 | #define AD_DMA_WAVIB 0x9c /* wave dma interrupt base byte count */
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| 84 |
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| 85 | #define AD_DMA_ICC 0xffffff /* current byte count mask */
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| 86 | #define AD_DMA_IBC 0xffffff /* base byte count mask */
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| 87 | /* bits 24 -> 31 reserved */
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| 88 |
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| 89 | /* 4 bytes pad */
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| 90 | #define AD_DMA_ADC 0xa8 /* ADC dma control and status */
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| 91 | #define AD_DMA_SYNTH 0xb0 /* Synth dma control and status */
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| 92 | #define AD_DMA_WAV 0xb8 /* wave dma control and status */
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| 93 | #define AD_DMA_RES 0xa0 /* Resample dma control and status */
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| 94 |
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| 95 | #define AD_DMA_SGDE 0x0001 /* SGD mode enable */
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| 96 | #define AD_DMA_LOOP 0x0002 /* loop enable */
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| 97 | #define AD_DMA_IM 0x000c /* interrupt mode mask */
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| 98 | #define AD_DMA_IM_DIS (~AD_DMA_IM) /* disable */
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| 99 | #define AD_DMA_IM_CNT 0x0004 /* interrupt on count */
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| 100 | #define AD_DMA_IM_SGD 0x0008 /* interrupt on SGD flag */
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| 101 | #define AD_DMA_IM_EOL 0x000c /* interrupt on End of Linked List */
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| 102 | #define AD_DMA_SGDS 0x0030 /* SGD status */
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| 103 | #define AD_DMA_SFLG 0x0040 /* SGD flag */
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| 104 | #define AD_DMA_EOL 0x0080 /* SGD end of list */
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| 105 | /* bits 8 -> 15 reserved */
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| 106 |
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| 107 | #define AD_DMA_DISR 0xc0 /* dma interrupt status */
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| 108 | #define AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */
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| 109 | #define AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */
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| 110 | #define AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */
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| 111 | #define AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */
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| 112 | /* bits 4, 5 reserved */
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| 113 | #define AD_DMA_DISR_SEPS 0x000040 /* serial eeprom status */
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| 114 | /* bits 7 -> 13 reserved */
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| 115 | #define AD_DMA_DISR_PMAI 0x004000 /* pci master abort interrupt */
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| 116 | #define AD_DMA_DISR_PTAI 0x008000 /* pci target abort interrupt */
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| 117 | #define AD_DMA_DISR_PTAE 0x010000 /* pci target abort interrupt enable */
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| 118 | #define AD_DMA_DISR_PMAE 0x020000 /* pci master abort interrupt enable */
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| 119 | /* bits 19 -> 31 reserved */
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| 120 |
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| 121 | /* interrupt mask */
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| 122 | #define AD_INTR_MASK (AD_DMA_DISR_RESI|AD_DMA_DISR_ADCI| \
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| 123 | AD_DMA_DISR_WAVI|AD_DMA_DISR_SYNI| \
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| 124 | AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI)
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| 125 |
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| 126 | #define AD_DMA_CHSS 0xc4 /* dma channel stop status */
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| 127 | #define AD_DMA_CHSS_RESS 0x000001 /* resampler channel stopped */
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| 128 | #define AD_DMA_CHSS_ADCS 0x000002 /* ADC channel stopped */
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| 129 | #define AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */
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| 130 | #define AD_DMA_CHSS_WAVS 0x000008 /* wave channel stopped */
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| 131 |
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| 132 | #define AD_GPIO_IPC 0xc8 /* gpio port control */
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| 133 | #define AD_GPIO_OP 0xca /* gpio output port status */
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| 134 | #define AD_GPIO_IP 0xcc /* gpio input port status */
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| 135 |
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| 136 | #define AD_AC97_BASE 0x100 /* ac97 base register */
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| 137 |
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| 138 | #define AD_AC97_RESET 0x100 /* reset */
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| 139 |
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| 140 | #define AD_AC97_PWR_CTL 0x126 /* == AC97_POWERDOWN */
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| 141 | #define AD_AC97_PWR_ADC 0x0001 /* ADC ready status */
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| 142 | #define AD_AC97_PWR_DAC 0x0002 /* DAC ready status */
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| 143 | #define AD_AC97_PWR_PR0 0x0100 /* PR0 (ADC) powerdown */
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| 144 | #define AD_AC97_PWR_PR1 0x0200 /* PR1 (DAC) powerdown */
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| 145 |
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| 146 | #define AD_MISC_CTL 0x176 /* misc control */
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| 147 | #define AD_MISC_CTL_DACZ 0x8000 /* set for zero fill, unset for repeat */
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| 148 | #define AD_MISC_CTL_ARSR 0x0001 /* set for SR1, unset for SR0 */
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| 149 | #define AD_MISC_CTL_ALSR 0x0100
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| 150 | #define AD_MISC_CTL_DLSR 0x0400
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| 151 | #define AD_MISC_CTL_DRSR 0x0004
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| 152 |
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| 153 | #define AD_AC97_SR0 0x178 /* sample rate 0, 0xbb80 == 48K */
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| 154 | #define AD_AC97_SR0_48K 0xbb80 /* 48KHz */
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| 155 | #define AD_AC97_SR1 0x17a /* sample rate 1 */
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| 156 |
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| 157 | #define AD_AC97_ACIC 0x180 /* ac97 codec interface control */
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| 158 | #define AD_AC97_ACIC_ACIE 0x0001 /* analog codec interface enable */
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| 159 | #define AD_AC97_ACIC_ACRD 0x0002 /* analog codec reset disable */
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| 160 | #define AD_AC97_ACIC_ASOE 0x0004 /* audio stream output enable */
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| 161 | #define AD_AC97_ACIC_VSRM 0x0008 /* variable sample rate mode */
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| 162 | #define AD_AC97_ACIC_FSDH 0x0100 /* force SDATA_OUT high */
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| 163 | #define AD_AC97_ACIC_FSYH 0x0200 /* force sync high */
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| 164 | #define AD_AC97_ACIC_ACRDY 0x8000 /* analog codec ready status */
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| 165 | /* bits 10 -> 14 reserved */
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| 166 |
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| 167 |
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| 168 | #define AD_DS_MEMSIZE 512
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| 169 | #define AD_OPL_MEMSIZE 16
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| 170 | #define AD_MIDI_MEMSIZE 16
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| 171 |
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| 172 | #define AD_WAV_STATE 0
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| 173 | #define AD_ADC_STATE 1
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| 174 | #define AD_MAX_STATES 2
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| 175 |
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| 176 | #define AD_CHAN_WAV 0x0001
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| 177 | #define AD_CHAN_ADC 0x0002
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| 178 | #define AD_CHAN_RES 0x0004
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| 179 | #define AD_CHAN_SYN 0x0008
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| 180 |
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| 181 |
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| 182 | /* The chip would support 4 GB buffers and 16 MB periods,
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| 183 | * but let's not overdo it ... */
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| 184 | #define BUFFER_BYTES_MAX (256 * 1024)
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| 185 | #define PERIOD_BYTES_MIN 32
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| 186 | #define PERIOD_BYTES_MAX (BUFFER_BYTES_MAX / 2)
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| 187 | #define PERIODS_MIN 2
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| 188 | #define PERIODS_MAX (BUFFER_BYTES_MAX / PERIOD_BYTES_MIN)
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| 189 |
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| 190 | #endif /* __AD1889_H__ */
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