source: GPL/trunk/alsa-kernel/include/sound/emu10k1.h

Last change on this file was 777, checked in by David Azarewicz, 6 months ago

Merge from uniaud32-exp branch
File size: 102.8 KB
Line 
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4 * Creative Labs, Inc.
5 * Definitions for EMU10K1 (SB Live!) chips
6 */
7#ifndef __SOUND_EMU10K1_H
8#define __SOUND_EMU10K1_H
9
10
11#include <sound/pcm.h>
12#include <sound/rawmidi.h>
13#include <sound/hwdep.h>
14#include <sound/ac97_codec.h>
15#include <sound/util_mem.h>
16#include <sound/pcm-indirect.h>
17#include <sound/timer.h>
18#include <linux/interrupt.h>
19#include <linux/mutex.h>
20#include <linux/firmware.h>
21#include <linux/io.h>
22
23#include <uapi/sound/emu10k1.h>
24
25/* ------------------- DEFINES -------------------- */
26
27#define EMUPAGESIZE 4096
28#define MAXPAGES0 4096 /* 32 bit mode */
29#define MAXPAGES1 8192 /* 31 bit mode */
30#define NUM_G 64 /* use all channels */
31#define NUM_EFX_PLAYBACK 16
32
33/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
34#define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
35#define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
36
37#define TMEMSIZE 256*1024
38
39#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
40
41// This is used to define hardware bit-fields (sub-registers) by combining
42// the bit shift and count with the actual register address. The passed
43// mask must represent a single run of adjacent bits.
44// The non-concatenating (_NC) variant should be used directly only for
45// sub-registers that do not follow the <register>_<field> naming pattern.
46#define SUB_REG_NC(reg, field, mask) \
47 enum { \
48 field ## _MASK = mask, \
49 field = reg | \
50 (__builtin_ctz(mask) << 16) | \
51 (__builtin_popcount(mask) << 24), \
52 };
53#define SUB_REG(reg, field, mask) SUB_REG_NC(reg, reg ## _ ## field, mask)
54
55// Macros for manipulating values of bit-fields declared using the above macros.
56// Best used with constant register addresses, as otherwise quite some code is
57// generated. The actual register read/write functions handle combined addresses
58// automatically, so use of these macros conveys no advantage when accessing a
59// single sub-register at a time.
60#define REG_SHIFT(r) (((r) >> 16) & 0x1f)
61#define REG_SIZE(r) (((r) >> 24) & 0x1f)
62#define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)
63#define REG_MASK(r) (REG_MASK0(r) << REG_SHIFT(r))
64#define REG_VAL_GET(r, v) ((v & REG_MASK(r)) >> REG_SHIFT(r))
65#define REG_VAL_PUT(r, v) ((v) << REG_SHIFT(r))
66
67// List terminator for snd_emu10k1_ptr_write_multiple()
68#define REGLIST_END ~0
69
70// Audigy specify registers are prefixed with 'A_'
71
72/************************************************************************************************/
73/* PCI function 0 registers, address = <val> + PCIBASE0 */
74/************************************************************************************************/
75
76#define PTR 0x00 /* Indexed register set pointer register */
77 /* NOTE: The CHANNELNUM and ADDRESS words can */
78 /* be modified independently of each other. */
79#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
80 /* channel number of the register to be */
81 /* accessed. For non per-channel registers the */
82 /* value should be set to zero. */
83#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
84#define A_PTR_ADDRESS_MASK 0x0fff0000
85
86#define DATA 0x04 /* Indexed register set data register */
87
88#define IPR 0x08 /* Global interrupt pending register */
89 /* Clear pending interrupts by writing a 1 to */
90 /* the relevant bits and zero to the other bits */
91#define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
92 to interrupt */
93#define IPR_WATERMARK_REACHED 0x40000000
94#define IPR_A_GPIO 0x20000000 /* GPIO input pin change */
95
96/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
97#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
98#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
99
100#define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
101#define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
102
103#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
104#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
105#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
106#define IPR_PCIERROR 0x00200000 /* PCI bus error */
107#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
108#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
109#define IPR_MUTE 0x00040000 /* Mute button pressed */
110#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
111#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
112#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
113#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
114#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
115#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
116#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
117#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
118#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
119#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
120#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
121#define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
122 /* The interrupt is triggered shortly after */
123 /* CCR_READADDRESS has crossed the boundary; */
124 /* due to the cache, this runs ahead of the */
125 /* actual playback position. */
126#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
127 /* highest set channel in CLIPL, CLIPH, HLIPL, */
128 /* or HLIPH. When IPR is written with CL set, */
129 /* the bit in H/CLIPL or H/CLIPH corresponding */
130 /* to the CN value written will be cleared. */
131
132#define INTE 0x0c /* Interrupt enable register */
133#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
134#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
135#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
136#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
137#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
138#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
139#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
140#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
141#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
142#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
143#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
144#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
145#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
146#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
147#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
148#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
149#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
150#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
151
152#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
153 /* NOTE: There is no reason to use this under */
154 /* Linux, and it will cause odd hardware */
155 /* behavior and possibly random segfaults and */
156 /* lockups if enabled. */
157
158#define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */
159
160/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
161#define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
162#define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
163
164#define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000
165#define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000
166
167#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
168 /* NOTE: This bit must always be enabled */
169#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
170#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
171#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
172#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
173#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
174#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
175#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
176#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
177#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
178#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
179#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
180#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
181#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
182
183#define WC 0x10 /* Wall Clock register */
184#ifndef TARGET_OS2
185SUB_REG(WC, SAMPLECOUNTER, 0x03FFFFC0) /* Sample periods elapsed since reset */
186SUB_REG(WC, CURRENTCHANNEL, 0x0000003F) /* Channel [0..63] currently being serviced */
187 /* NOTE: Each channel takes 1/64th of a sample */
188 /* period to be serviced. */
189
190#else
191#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
192#define WC_SAMPLECOUNTER 0x14060010
193#define WC_CURRENTCHANNEL 0x0700003F /* Channel [0..63] currently being serviced */
194 /* NOTE: Each channel takes 1/64th of a sample */
195 /* period to be serviced. */
196#endif
197#define HCFG 0x14 /* Hardware config register */
198 /* NOTE: There is no reason to use the legacy */
199 /* SoundBlaster emulation stuff described below */
200 /* under Linux, and all kinds of weird hardware */
201 /* behavior can result if you try. Don't. */
202#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
203#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
204#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
205#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
206#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
207#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
208#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
209#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
210#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
211#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
212#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
213#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
214 /* NOTE: The rest of the bits in this register */
215 /* _are_ relevant under Linux. */
216#define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
217#define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
218#define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
219#define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
220
221/* Specific to Alice2, CA0102 */
222
223#define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
224#define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
225#define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
226 /* will automatically mute their output when */
227 /* they are not rate-locked to the external */
228 /* async audio source */
229#define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
230 /* will automatically mute their output when */
231 /* the SPDIF V-bit indicates invalid audio */
232#define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
233#define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
234/* 0x00000800 not used on Alice2 */
235#define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
236 /* phase track the previous input. */
237 /* I2S0 can phase track the last S/PDIF input */
238#define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
239 /* conversion for the corresponding */
240 /* I2S format input */
241/* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
242
243/* Older chips */
244
245#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
246#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
247#define HCFG_GPINPUT0 0x00004000 /* External pin112 */
248#define HCFG_GPINPUT1 0x00002000 /* External pin110 */
249#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
250#define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
251#define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
252#define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
253#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
254#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
255 /* 1 = Force all 3 async digital inputs to use */
256 /* the same async sample rate tracker (ZVIDEO) */
257#define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
258#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
259#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
260#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
261#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
262 /* will automatically mute their output when */
263 /* they are not rate-locked to the external */
264 /* async audio source */
265#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
266 /* NOTE: This should generally never be used. */
267#ifndef TARGET_OS2
268SUB_REG(HCFG, LOCKTANKCACHE, 0x00000004) /* 1 = Cancel bustmaster accesses to tankcache */
269 /* NOTE: This should generally never be used. */
270#else
271#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
272 /* NOTE: This should generally never be used. */
273#define HCFG_LOCKTANKCACHE 0x01020014
274#endif
275#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
276 /* NOTE: This is a 'cheap' way to implement a */
277 /* master mute function on the mute button, and */
278 /* in general should not be used unless a more */
279 /* sophisticated master mute function has not */
280 /* been written. */
281#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
282 /* Should be set to 1 when the EMU10K1 is */
283 /* completely initialized. */
284
285// On Audigy, the MPU port moved to the 0x70-0x74 ptr registers
286
287#define MUDATA 0x18 /* MPU401 data register (8 bits) */
288
289#define MUCMD 0x19 /* MPU401 command register (8 bits) */
290#define MUCMD_RESET 0xff /* RESET command */
291#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
292 /* NOTE: All other commands are ignored */
293
294#define MUSTAT MUCMD /* MPU401 status register (8 bits) */
295#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
296#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
297
298#define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */
299#define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */
300#define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */
301#define A_GPOUTPUT_MASK 0x00ff
302
303// The GPIO port is used for I/O config on Sound Blasters;
304// card-specific info can be found in the emu_chip_details table.
305// On E-MU cards the port is used as the interface to the FPGA.
306
307// Audigy output/GPIO stuff taken from the kX drivers
308#define A_IOCFG A_GPIO
309#define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
310#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
311#define A_IOCFG_ENABLE_DIGITAL 0x0004
312#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
313#define A_IOCFG_UNKNOWN_20 0x0020
314#define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
315#define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
316#define A_IOCFG_GPOUT2 0x0001 /* IR */
317#define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
318 /* + digital for generic 10k2 */
319#define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
320#define A_IOCFG_FRONT_JACK 0x4000
321#define A_IOCFG_REAR_JACK 0x8000
322#define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
323
324#define TIMER 0x1a /* Timer terminal count register */
325 /* NOTE: After the rate is changed, a maximum */
326 /* of 1024 sample periods should be allowed */
327 /* before the new rate is guaranteed accurate. */
328#define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */
329 /* 0 == 1024 periods, [1..4] are not useful */
330
331#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
332
333#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
334#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
335#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
336
337/* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
338#define PTR2 0x20 /* Indexed register set pointer register */
339#define DATA2 0x24 /* Indexed register set data register */
340#define IPR2 0x28 /* P16V interrupt pending register */
341#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
342#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
343#define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
344#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
345 /* 0x00000100 Playback. Only in once per period.
346 * 0x00110000 Capture. Int on half buffer.
347 */
348#define INTE2 0x2c /* P16V Interrupt enable register. */
349#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
350#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
351#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
352#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
353#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
354#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
355#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
356#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
357#define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
358#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
359#define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
360 /* 0x00000000 2-channel output. */
361 /* 0x00000200 8-channel output. */
362 /* 0x00000004 pauses stream/irq fail. */
363 /* Rest of bits do nothing to sound output */
364 /* bit 0: Enable P16V audio.
365 * bit 1: Lock P16V record memory cache.
366 * bit 2: Lock P16V playback memory cache.
367 * bit 3: Dummy record insert zero samples.
368 * bit 8: Record 8-channel in phase.
369 * bit 9: Playback 8-channel in phase.
370 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
371 * bit 13: Playback mixer enable.
372 * bit 14: Route SRC48 mixer output to fx engine.
373 * bit 15: Enable IEEE 1394 chip.
374 */
375#define IPR3 0x38 /* Cdif interrupt pending register */
376#define INTE3 0x3c /* Cdif interrupt enable register. */
377
378/************************************************************************************************/
379/* PCI function 1 registers, address = <val> + PCIBASE1 */
380/************************************************************************************************/
381
382#define JOYSTICK1 0x00 /* Analog joystick port register */
383#define JOYSTICK2 0x01 /* Analog joystick port register */
384#define JOYSTICK3 0x02 /* Analog joystick port register */
385#define JOYSTICK4 0x03 /* Analog joystick port register */
386#define JOYSTICK5 0x04 /* Analog joystick port register */
387#define JOYSTICK6 0x05 /* Analog joystick port register */
388#define JOYSTICK7 0x06 /* Analog joystick port register */
389#define JOYSTICK8 0x07 /* Analog joystick port register */
390
391/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
392/* When reading, use these bitfields: */
393#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
394#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
395
396/********************************************************************************************************/
397/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
398/********************************************************************************************************/
399
400// No official documentation was released for EMU10K1, but some info
401// about playback can be extrapolated from the EMU8K documents:
402// "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers
403// "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view
404
405// The short version:
406// - The engine has 64 playback channels, also called voices. The channels
407// operate independently, except when paired for stereo (see below).
408// - PCM samples are fetched into the cache; see description of CD0 below.
409// - Samples are consumed at the rate CPF_CURRENTPITCH.
410// - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8
411// - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated
412// according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero
413// CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim.
414// - The value is multiplied by CVCF_CURRENTVOL.
415// - The value goes through a filter with cutoff CVCF_CURRENTFILTER;
416// delay stages Z1 and Z2.
417// - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2)
418// of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*,
419// multiplied by a per-send amount (*_FXSENDAMOUNT_*).
420// The scaling of the send amounts is exponential-ish.
421// - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*.
422// - The pitch, volume, and filter cutoff can be modulated by two envelope
423// engines and two low frequency oscillators.
424// - To avoid abrupt changes to the parameters (which may cause audible
425// distortion), the modulation engine sets the target registers, towards
426// which the current registers "swerve" gradually.
427
428// For the odd channel in a stereo pair, these registers are meaningless:
429// CPF_STEREO, CPF_CURRENTPITCH, PTRX_PITCHTARGET, CCR_CACHEINVALIDSIZE,
430// PSST_LOOPSTARTADDR, DSL_LOOPENDADDR, CCCA_CURRADDR
431// The somewhat non-obviously still meaningful ones are:
432// CPF_STOP, CPF_FRACADDRESS, CCR_READADDRESS (!),
433// CCCA_INTERPROM, CCCA_8BITSELECT (!)
434// (The envelope engine is ignored here, as stereo matters only for verbatim playback.)
435
436#define CPF 0x00 /* Current pitch and fraction register */
437#ifndef TARGET_OS2
438SUB_REG(CPF, CURRENTPITCH, 0xffff0000) /* Current pitch (linear, 0x4000 == unity pitch shift) */
439#else
440#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
441#define CPF_CURRENTPITCH 0x10100000
442#endif
443#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
444#ifndef TARGET_OS2
445SUB_REG(CPF, STOP, 0x00004000) /* 1 = Current pitch forced to 0 */
446 /* Can be set only while matching bit in SOLEx is 1 */
447#else
448#define CPF_STOP 0x00004000 /* 1 = Current pitch forced to 0 */
449#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
450#endif
451#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
452
453#define PTRX 0x01 /* Pitch target and send A/B amounts register */
454#ifndef TARGET_OS2
455SUB_REG(PTRX, PITCHTARGET, 0xffff0000) /* Pitch target of specified channel */
456SUB_REG(PTRX, FXSENDAMOUNT_A, 0x0000ff00) /* Linear level of channel output sent to FX send bus A */
457SUB_REG(PTRX, FXSENDAMOUNT_B, 0x000000ff) /* Linear level of channel output sent to FX send bus B */
458#else
459#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
460#define PTRX_PITCHTARGET 0x10100001
461#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
462#define PTRX_FXSENDAMOUNT_A 0x08080001
463#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
464#define PTRX_FXSENDAMOUNT_B 0x08000001
465#endif
466
467// Note: the volumes are raw multpliers, so real 100% is impossible.
468#define CVCF 0x02 /* Current volume and filter cutoff register */
469#ifndef TARGET_OS2
470SUB_REG(CVCF, CURRENTVOL, 0xffff0000) /* Current linear volume of specified channel */
471SUB_REG(CVCF, CURRENTFILTER, 0x0000ffff) /* Current filter cutoff frequency of specified channel */
472#else
473#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
474#define CVCF_CURRENTVOL 0x10100002
475#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
476#define CVCF_CURRENTFILTER 0x10000002
477#endif
478
479#define VTFT 0x03 /* Volume target and filter cutoff target register */
480#ifndef TARGET_OS2
481SUB_REG(VTFT, VOLUMETARGET, 0xffff0000) /* Volume target of specified channel */
482SUB_REG(VTFT, FILTERTARGET, 0x0000ffff) /* Filter cutoff target of specified channel */
483#else
484#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
485#define VTFT_VOLUMETARGET 0x10100003
486#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
487#define VTFT_FILTERTARGET 0x10000003
488#endif
489
490#define Z1 0x05 /* Filter delay memory 1 register */
491
492#define Z2 0x04 /* Filter delay memory 2 register */
493
494#define PSST 0x06 /* Send C amount and loop start address register */
495#ifndef TARGET_OS2
496SUB_REG(PSST, FXSENDAMOUNT_C, 0xff000000) /* Linear level of channel output sent to FX send bus C */
497SUB_REG(PSST, LOOPSTARTADDR, 0x00ffffff) /* Loop start address of the specified channel */
498#else
499#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
500
501#define PSST_FXSENDAMOUNT_C 0x08180006
502
503#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
504#define PSST_LOOPSTARTADDR 0x18000006
505#endif
506
507#define DSL 0x07 /* Send D amount and loop end address register */
508#ifndef TARGET_OS2
509SUB_REG(DSL, FXSENDAMOUNT_D, 0xff000000) /* Linear level of channel output sent to FX send bus D */
510SUB_REG(DSL, LOOPENDADDR, 0x00ffffff) /* Loop end address of the specified channel */
511#else
512#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
513
514#define DSL_FXSENDAMOUNT_D 0x08180007
515
516#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
517#define DSL_LOOPENDADDR 0x18000007
518#endif
519
520#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
521#ifndef TARGET_OS2
522SUB_REG(CCCA, RESONANCE, 0xf0000000) /* Lowpass filter resonance (Q) height */
523#else
524#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
525#endif
526#define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */
527 /* 1 == full band, 7 == lowpass */
528 /* ROM 0 is used when pitch shifting downward or less */
529 /* then 3 semitones upward. Increasingly higher ROM */
530 /* numbers are used, typically in steps of 3 semitones, */
531 /* as upward pitch shifting is performed. */
532#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
533#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
534#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
535#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
536#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
537#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
538#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
539#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
540#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
541 /* 8-bit samples are unsigned, 16-bit ones signed */
542#ifndef TARGET_OS2
543SUB_REG(CCCA, CURRADDR, 0x00ffffff) /* Current address of the selected channel */
544#else
545#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
546#define CCCA_CURRADDR 0x18000008
547#endif
548
549#define CCR 0x09 /* Cache control register */
550#ifndef TARGET_OS2
551SUB_REG(CCR, CACHEINVALIDSIZE, 0xfe000000) /* Number of invalid samples before the read address */
552#else
553#define CCR_CACHEINVALIDSIZE 0x07190009
554#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
555#endif
556#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
557#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
558 /* Auto-set from CPF_STEREO_MASK */
559#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
560 /* Auto-set from CCCA_8BITSELECT */
561#ifndef TARGET_OS2
562SUB_REG(CCR, READADDRESS, 0x003f0000) /* Next cached sample to play */
563SUB_REG(CCR, LOOPINVALSIZE, 0x0000fe00) /* Number of invalid samples in cache prior to loop */
564#else
565#define CCR_READADDRESS 0x06100009
566#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
567#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
568 /* NOTE: This is valid only if CACHELOOPFLAG is set */
569#endif
570 /* NOTE: This is valid only if CACHELOOPFLAG is set */
571#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
572#ifndef TARGET_OS2
573SUB_REG(CCR, CACHELOOPADDRHI, 0x000000ff) /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
574#else
575#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
576#endif
577
578#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
579 /* NOTE: This register is normally not used */
580#ifndef TARGET_OS2
581SUB_REG(CLP, CACHELOOPADDR, 0x0000ffff) /* Cache loop address low word */
582#else
583#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
584#endif
585
586#define FXRT 0x0b /* Effects send routing register */
587 /* NOTE: It is illegal to assign the same routing to */
588 /* two effects sends. */
589#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
590#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
591#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
592#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
593
594#define MAPA 0x0c /* Cache map A */
595#define MAPB 0x0d /* Cache map B */
596
597#define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */
598#define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */
599
600#define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
601#define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
602
603/* 0x0e, 0x0f: Internal state, at least on Audigy */
604
605#define ENVVOL 0x10 /* Volume envelope register */
606#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
607 /* 0x8000-n == 666*n usec delay */
608
609#define ATKHLDV 0x11 /* Volume envelope hold and attack register */
610#define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */
611#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
612#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
613 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
614
615#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
616#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */
617#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
618#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */
619 /* this channel and from writing to pitch, filter and */
620 /* volume targets. */
621#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
622 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
623
624#define LFOVAL1 0x13 /* Modulation LFO value */
625#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
626 /* 0x8000-n == 666*n usec delay */
627
628#define ENVVAL 0x14 /* Modulation envelope register */
629#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
630 /* 0x8000-n == 666*n usec delay */
631
632#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
633#define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */
634#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
635#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
636 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
637
638#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
639#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */
640#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
641#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
642 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
643
644#define LFOVAL2 0x17 /* Vibrato LFO register */
645#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
646 /* 0x8000-n == 666*n usec delay */
647
648#define IP 0x18 /* Initial pitch register */
649#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
650 /* 4 bits of octave, 12 bits of fractional octave */
651#define IP_UNITY 0x0000e000 /* Unity pitch shift */
652
653#define IFATN 0x19 /* Initial filter cutoff and attenuation register */
654#ifndef TARGET_OS2
655SUB_REG(IFATN, FILTERCUTOFF, 0x0000ff00) /* Initial filter cutoff frequency in exponential units */
656 /* 6 most significant bits are semitones */
657 /* 2 least significant bits are fractions */
658SUB_REG(IFATN, ATTENUATION, 0x000000ff) /* Initial attenuation in 0.375dB steps */
659
660#else
661#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
662 /* 6 most significant bits are semitones */
663 /* 2 least significant bits are fractions */
664#define IFATN_FILTERCUTOFF 0x08080019
665#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
666#define IFATN_ATTENUATION 0x08000019
667#endif
668#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
669#ifndef TARGET_OS2
670SUB_REG(PEFE, PITCHAMOUNT, 0x0000ff00) /* Pitch envlope amount */
671 /* Signed 2's complement, +/- one octave peak extremes */
672SUB_REG(PEFE, FILTERAMOUNT, 0x000000ff) /* Filter envlope amount */
673 /* Signed 2's complement, +/- six octaves peak extremes */
674#else
675#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
676 /* Signed 2's complement, +/- one octave peak extremes */
677#define PEFE_PITCHAMOUNT 0x0808001a
678#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
679 /* Signed 2's complement, +/- six octaves peak extremes */
680#define PEFE_FILTERAMOUNT 0x0800001a
681#endif
682
683
684#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
685#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
686 /* Signed 2's complement, +/- one octave extremes */
687#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
688 /* Signed 2's complement, +/- three octave extremes */
689
690#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
691#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
692 /* Signed 2's complement, with +/- 12dB extremes */
693#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
694 /* ??Hz steps, maximum of ?? Hz. */
695
696#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
697#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
698 /* Signed 2's complement, +/- one octave extremes */
699#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
700 /* 0.039Hz steps, maximum of 9.85 Hz. */
701
702#define TEMPENV 0x1e /* Tempory envelope register */
703#define TEMPENV_MASK 0x0000ffff /* 16-bit value */
704 /* NOTE: All channels contain internal variables; do */
705 /* not write to these locations. */
706
707/* 0x1f: not used */
708
709// 32 cache registers (== 128 bytes) per channel follow.
710// In stereo mode, the two channels' caches are concatenated into one,
711// and hold the interleaved frames.
712// The cache holds 64 frames, so the upper half is not used in 8-bit mode.
713// All registers mentioned below count in frames. Shortcuts:
714// CA = CCCA_CURRADDR, CRA = CCR_READADDRESS,
715// CLA = CCR_CACHELOOPADDRHI:CLP_CACHELOOPADDR,
716// CIS = CCR_CACHEINVALIDSIZE, LIS = CCR_LOOPINVALSIZE,
717// CLF = CCR_CACHELOOPFLAG, LF = CCR_LOOPFLAG
718// The cache is a ring buffer; CRA operates modulo 64.
719// The cache is filled from (CA - CIS) into (CRA - CIS).
720// The engine has a fetch threshold of 32 bytes, so it tries to keep
721// CIS below 8 (16-bit stereo), 16 (16-bit mono, 8-bit stereo), or
722// 32 (8-bit mono). The actual transfers are pretty unpredictable,
723// especially if several voices are running.
724// Frames are consumed at CRA, which is incremented afterwards,
725// along with CA and CIS. This implies that the actual playback
726// position always lags CA by exactly 64 frames.
727// When CA reaches DSL_LOOPENDADDR, LF is set for one frame's time.
728// LF's rising edge causes the current values of CA and CIS to be
729// copied into CLA and LIS, resp., and CLF to be set.
730// If CLF is set, the first LIS of the CIS frames are instead
731// filled from (CLA - LIS), and CLF is subsequently reset.
732#define CD0 0x20 /* Cache data registers 0 .. 0x1f */
733
734#define PTB 0x40 /* Page table base register */
735#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
736
737#define TCB 0x41 /* Tank cache base register */
738#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
739
740#define ADCCR 0x42 /* ADC sample rate/stereo control register */
741#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
742#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
743 /* NOTE: To guarantee phase coherency, both channels */
744 /* must be disabled prior to enabling both channels. */
745#define A_ADCCR_RCHANENABLE 0x00000020
746#define A_ADCCR_LCHANENABLE 0x00000010
747
748#define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
749#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
750#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
751#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
752#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
753#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
754#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
755#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
756#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
757#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
758#define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
759#define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
760#define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
761
762#define FXWC 0x43 /* FX output write channels register */
763 /* When set, each bit enables the writing of the */
764 /* corresponding FX output channel (internal registers */
765 /* 0x20-0x3f) to host memory. This mode of recording */
766 /* is 16bit, 48KHz only. All 32 channels can be enabled */
767 /* simultaneously. */
768
769#define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
770
771#define TCBS 0x44 /* Tank cache buffer size register */
772#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
773#define TCBS_BUFFSIZE_16K 0x00000000
774#define TCBS_BUFFSIZE_32K 0x00000001
775#define TCBS_BUFFSIZE_64K 0x00000002
776#define TCBS_BUFFSIZE_128K 0x00000003
777#define TCBS_BUFFSIZE_256K 0x00000004
778#define TCBS_BUFFSIZE_512K 0x00000005
779#define TCBS_BUFFSIZE_1024K 0x00000006
780#define TCBS_BUFFSIZE_2048K 0x00000007
781
782#define MICBA 0x45 /* AC97 microphone buffer address register */
783#define MICBA_MASK 0xfffff000 /* 20 bit base address */
784
785#define ADCBA 0x46 /* ADC buffer address register */
786#define ADCBA_MASK 0xfffff000 /* 20 bit base address */
787
788#define FXBA 0x47 /* FX Buffer Address */
789#define FXBA_MASK 0xfffff000 /* 20 bit base address */
790
791#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
792
793#define MICBS 0x49 /* Microphone buffer size register */
794
795#define ADCBS 0x4a /* ADC buffer size register */
796
797#define FXBS 0x4b /* FX buffer size register */
798
799/* The following mask values define the size of the ADC, MIC and FX buffers in bytes */
800#define ADCBS_BUFSIZE_NONE 0x00000000
801#define ADCBS_BUFSIZE_384 0x00000001
802#define ADCBS_BUFSIZE_448 0x00000002
803#define ADCBS_BUFSIZE_512 0x00000003
804#define ADCBS_BUFSIZE_640 0x00000004
805#define ADCBS_BUFSIZE_768 0x00000005
806#define ADCBS_BUFSIZE_896 0x00000006
807#define ADCBS_BUFSIZE_1024 0x00000007
808#define ADCBS_BUFSIZE_1280 0x00000008
809#define ADCBS_BUFSIZE_1536 0x00000009
810#define ADCBS_BUFSIZE_1792 0x0000000a
811#define ADCBS_BUFSIZE_2048 0x0000000b
812#define ADCBS_BUFSIZE_2560 0x0000000c
813#define ADCBS_BUFSIZE_3072 0x0000000d
814#define ADCBS_BUFSIZE_3584 0x0000000e
815#define ADCBS_BUFSIZE_4096 0x0000000f
816#define ADCBS_BUFSIZE_5120 0x00000010
817#define ADCBS_BUFSIZE_6144 0x00000011
818#define ADCBS_BUFSIZE_7168 0x00000012
819#define ADCBS_BUFSIZE_8192 0x00000013
820#define ADCBS_BUFSIZE_10240 0x00000014
821#define ADCBS_BUFSIZE_12288 0x00000015
822#define ADCBS_BUFSIZE_14366 0x00000016
823#define ADCBS_BUFSIZE_16384 0x00000017
824#define ADCBS_BUFSIZE_20480 0x00000018
825#define ADCBS_BUFSIZE_24576 0x00000019
826#define ADCBS_BUFSIZE_28672 0x0000001a
827#define ADCBS_BUFSIZE_32768 0x0000001b
828#define ADCBS_BUFSIZE_40960 0x0000001c
829#define ADCBS_BUFSIZE_49152 0x0000001d
830#define ADCBS_BUFSIZE_57344 0x0000001e
831#define ADCBS_BUFSIZE_65536 0x0000001f
832
833// On Audigy, the FX send amounts are not applied instantly, but determine
834// targets towards which the following registers swerve gradually.
835#define A_CSBA 0x4c /* FX send B & A current amounts */
836#define A_CSDC 0x4d /* FX send D & C current amounts */
837#define A_CSFE 0x4e /* FX send F & E current amounts */
838#define A_CSHG 0x4f /* FX send H & G current amounts */
839
840// NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1)
841#define CDCS 0x50 /* CD-ROM digital channel status register */
842
843#define GPSCS 0x51 /* General Purpose SPDIF channel status register */
844
845// Corresponding EMU10K1_DBG_* constants are in the public header
846#define DBG 0x52
847
848#define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
849
850#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
851
852// Corresponding A_DBG_* constants are in the public header
853#define A_DBG 0x53
854
855// NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
856#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
857
858#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
859
860#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
861
862#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
863#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
864#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
865#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
866#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
867#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
868#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
869#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
870#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
871#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
872#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
873#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
874#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
875#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
876#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
877#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
878#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
879#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
880#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
881#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
882#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
883#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
884#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
885
886/* 0x57: Not used */
887
888/* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */
889#define CLIEL 0x58 /* Channel loop interrupt enable low register */
890#define CLIEH 0x59 /* Channel loop interrupt enable high register */
891
892#define CLIPL 0x5a /* Channel loop interrupt pending low register */
893#define CLIPH 0x5b /* Channel loop interrupt pending high register */
894
895// These cause CPF_STOP_MASK to be set shortly after CCCA_CURRADDR passes DSL_LOOPENDADDR.
896// Subsequent changes to the address registers don't resume; clearing the bit here or in CPF does.
897// The registers are NOT synchronized; the next serviced channel picks up immediately.
898#define SOLEL 0x5c /* Stop on loop enable low register */
899#define SOLEH 0x5d /* Stop on loop enable high register */
900
901#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
902#define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
903#define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
904/* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
905#define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
906
907#define AC97SLOT 0x5f /* additional AC97 slots enable bits */
908#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
909#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
910#define AC97SLOT_CNTR 0x10 /* Center enable */
911#define AC97SLOT_LFE 0x20 /* LFE enable */
912
913#define A_PCB 0x5f /* PCB Revision */
914
915// NOTE: 0x60,61,62: 64-bit
916#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
917
918#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
919
920#define ZVSRCS 0x62 /* ZVideo sample rate converter status */
921 /* NOTE: This one has no SPDIFLOCKED field */
922 /* Assumes sample lock */
923
924/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
925#define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
926#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
927#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
928#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
929
930/* Note that these values can vary +/- by a small amount */
931#define SRCS_SPDIFRATE_44 0x0003acd9
932#define SRCS_SPDIFRATE_48 0x00040000
933#define SRCS_SPDIFRATE_96 0x00080000
934
935#define MICIDX 0x63 /* Microphone recording buffer index register */
936#ifndef TARGET_OS2
937SUB_REG(MICIDX, IDX, 0x0000ffff)
938#else
939#define MICIDX_MASK 0x0000ffff /* 16-bit value */
940#define MICIDX_IDX 0x10000063
941#endif
942
943#define ADCIDX 0x64 /* ADC recording buffer index register */
944#ifndef TARGET_OS2
945SUB_REG(ADCIDX, IDX, 0x0000ffff)
946#else
947#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
948#define ADCIDX_IDX 0x10000064
949#endif
950
951#define A_ADCIDX 0x63
952#ifndef TARGET_OS2
953SUB_REG(A_ADCIDX, IDX, 0x0000ffff)
954#else
955#define A_ADCIDX_IDX 0x10000063
956#endif
957
958#define A_MICIDX 0x64
959#ifndef TARGET_OS2
960SUB_REG(A_MICIDX, IDX, 0x0000ffff)
961#else
962#define A_MICIDX_IDX 0x10000064
963#endif
964
965#define FXIDX 0x65 /* FX recording buffer index register */
966#ifndef TARGET_OS2
967SUB_REG(FXIDX, IDX, 0x0000ffff)
968#else
969#define FXIDX_MASK 0x0000ffff /* 16-bit value */
970#define FXIDX_IDX 0x10000065
971#endif
972
973/* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */
974#define HLIEL 0x66 /* Channel half loop interrupt enable low register */
975#define HLIEH 0x67 /* Channel half loop interrupt enable high register */
976
977#define HLIPL 0x68 /* Channel half loop interrupt pending low register */
978#define HLIPH 0x69 /* Channel half loop interrupt pending high register */
979
980#define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */
981#define A_SPRA 0x6b /* S/PDIF Host Record Address */
982#define A_SPRC 0x6c /* S/PDIF Host Record Control */
983
984#define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */
985
986#define A_TTB 0x6e /* Tank Table Base */
987#define A_TDOF 0x6f /* Tank Delay Offset */
988
989/* This is the MPU port on the card (via the game port) */
990#define A_MUDATA1 0x70
991#define A_MUCMD1 0x71
992#define A_MUSTAT1 A_MUCMD1
993
994/* This is the MPU port on the Audigy Drive */
995#define A_MUDATA2 0x72
996#define A_MUCMD2 0x73
997#define A_MUSTAT2 A_MUCMD2
998
999/* The next two are the Audigy equivalent of FXWC */
1000/* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */
1001/* Each bit selects a channel for recording */
1002#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
1003#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
1004
1005#define A_EHC 0x76 /* Extended Hardware Control */
1006
1007#define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */
1008#define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
1009#define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */
1010#define A_SPDIF_192000 0x00000020
1011#define A_SPDIF_96000 0x00000040
1012#define A_SPDIF_44100 0x00000080
1013#define A_SPDIF_MUTED 0x000000c0
1014
1015#ifndef TARGET_OS2
1016SUB_REG_NC(A_EHC, A_I2S_CAPTURE_RATE, 0x00000e00) /* This sets the capture PCM rate, but it is */
1017 /* unclear if this sets the ADC rate as well. */
1018#else
1019#define A_I2S_CAPTURE_RATE 0x00000e00
1020#define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
1021 /* unclear if this sets the ADC rate as well. */
1022#endif
1023#define A_I2S_CAPTURE_48000 0x0
1024#define A_I2S_CAPTURE_192000 0x1
1025#define A_I2S_CAPTURE_96000 0x2
1026#define A_I2S_CAPTURE_44100 0x4
1027
1028#define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
1029#define A_EHC_SRC48_BYPASS 0x00000000
1030#define A_EHC_SRC48_192 0x00002000
1031#define A_EHC_SRC48_96 0x00004000
1032#define A_EHC_SRC48_44 0x00008000
1033#define A_EHC_SRC48_MUTED 0x0000c000
1034
1035#define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */
1036#define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */
1037#define A_EHC_P17V_SEL1_MASK 0x000c0000
1038#define A_EHC_P17V_SEL2_MASK 0x00300000
1039#define A_EHC_P17V_SEL3_MASK 0x00c00000
1040
1041#define A_EHC_ASYNC_BYPASS 0x80000000
1042
1043#define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */
1044#define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */
1045#define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */
1046/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
1047
1048#define A_SRT_ESTSAMPLERATE 0x001fffff
1049#define A_SRT_RATELOCKED 0x01000000
1050
1051#define A_TTDA 0x7a /* Tank Table DMA Address */
1052#define A_TTDD 0x7b /* Tank Table DMA Data */
1053
1054// In A_FXRT1 & A_FXRT2, the 0x80 bit of each byte completely disables the
1055// filter (CVCF_CURRENTFILTER) for the corresponding channel. There is no
1056// effect on the volume (CVCF_CURRENTVOLUME) or the interpolator's filter
1057// (CCCA_INTERPROM_MASK).
1058
1059#define A_FXRT2 0x7c
1060#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
1061#define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
1062#define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
1063#define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
1064
1065#define A_SENDAMOUNTS 0x7d
1066#define A_FXSENDAMOUNT_E_MASK 0xFF000000
1067#define A_FXSENDAMOUNT_F_MASK 0x00FF0000
1068#define A_FXSENDAMOUNT_G_MASK 0x0000FF00
1069#define A_FXSENDAMOUNT_H_MASK 0x000000FF
1070
1071/* The send amounts for this one are the same as used with the emu10k1 */
1072#define A_FXRT1 0x7e
1073#define A_FXRT_CHANNELA 0x0000003f
1074#define A_FXRT_CHANNELB 0x00003f00
1075#define A_FXRT_CHANNELC 0x003f0000
1076#define A_FXRT_CHANNELD 0x3f000000
1077
1078/* 0x7f: Not used */
1079
1080/* The public header defines the GPR and TRAM base addresses that
1081 * are valid for _both_ CPU and DSP addressing. */
1082
1083/* Each DSP microcode instruction is mapped into 2 doublewords */
1084/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
1085#define MICROCODEBASE 0x400 /* Microcode data base address */
1086#define A_MICROCODEBASE 0x600
1087
1088
1089/************************************************************************************************/
1090/* E-MU Digital Audio System overview */
1091/************************************************************************************************/
1092
1093// - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2);
1094// the PCIe variants simply put the Audigy chip behind a PCI bridge.
1095// - All physical PCM I/O is routed through an additional FPGA; the regular
1096// EXTIN/EXTOUT ports are unconnected.
1097// - The FPGA has a signal routing matrix, to connect each destination (output
1098// socket or capture channel) to a source (input socket or playback channel).
1099// - The FPGA is controlled via Audigy's GPIO port, while sample data is
1100// transmitted via proprietary EMU32 serial links. On first-generation
1101// E-MU 1010 cards, Audigy's I2S inputs are also used for sample data.
1102// - The Audio/Micro Dock is attached to Hana via EDI, a "network" link.
1103// - The Audigy chip operates in slave mode; the clock is supplied by the FPGA.
1104// Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples),
1105// while the later cards use a single crystal and a PLL chip.
1106// - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz
1107// sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels
1108// are bundled.
1109// - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total
1110// number of usable inputs/outputs is limited, esp. with ADAT in use.
1111// - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
1112// to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels
1113// can overlap with the Dock's ADC/DAC's high channels.
1114// - The code names are mentioned below and in the emu_chip_details table.
1115
1116/************************************************************************************************/
1117/* EMU1010 FPGA registers */
1118/************************************************************************************************/
1119
1120#define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
1121#define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
1122
1123#define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
1124#define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
1125
1126#define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
1127#define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
1128
1129#define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
1130 /* Must be written after power on to reset DLL */
1131 /* One is unable to detect the Audio dock without this */
1132#define EMU_HANA_WCLOCK_SRC_MASK 0x07
1133#define EMU_HANA_WCLOCK_INT_48K 0x00
1134#define EMU_HANA_WCLOCK_INT_44_1K 0x01
1135#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
1136#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
1137#define EMU_HANA_WCLOCK_SYNC_BNC 0x04
1138#define EMU_HANA_WCLOCK_2ND_HANA 0x05
1139#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
1140#define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
1141#define EMU_HANA_WCLOCK_MULT_MASK 0x18
1142#define EMU_HANA_WCLOCK_1X 0x00
1143#define EMU_HANA_WCLOCK_2X 0x08
1144#define EMU_HANA_WCLOCK_4X 0x10
1145#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
1146
1147// If the selected external clock source is/becomes invalid or incompatible
1148// with the clock multiplier, the clock source is reset to this value, and
1149// a WCLK_CHANGED interrupt is raised.
1150#define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
1151#define EMU_HANA_DEFCLOCK_48K 0x00
1152#define EMU_HANA_DEFCLOCK_44_1K 0x01
1153
1154#define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
1155#define EMU_MUTE 0x00
1156#define EMU_UNMUTE 0x01
1157
1158#define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
1159#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
1160#define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
1161
1162#define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
1163#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1164#define EMU_HANA_IRQ_ADAT 0x02
1165#define EMU_HANA_IRQ_DOCK 0x04
1166#define EMU_HANA_IRQ_DOCK_LOST 0x08
1167
1168#define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
1169#define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00
1170#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
1171#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1172#define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00
1173#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1174#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1175#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1176
1177#define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
1178#define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1179#define EMU_HANA_OPTICAL_IN_ADAT 0x01
1180#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1181#define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1182
1183#define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1184#define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */
1185#define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */
1186#define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */
1187#define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */
1188#define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */
1189#define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */
1190
1191#define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
1192#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
1193#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
1194#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
1195#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
1196
1197#define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
1198#define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
1199#define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1200#define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
1201#define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
1202#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
1203#define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
1204
1205#define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
1206#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
1207#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
1208#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
1209#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
1210#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
1211#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
1212
1213#define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1214#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1215#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
1216#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
1217#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1218
1219#define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1220#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1221#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
1222#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
1223#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
1224#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1225#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1226#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1227#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1228
1229#define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
1230#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
1231#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
1232#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
1233#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
1234#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
1235
1236#define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1237#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
1238#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
1239#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
1240#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
1241#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
1242
1243/* 0x14 - 0x1f Unused R/W registers */
1244
1245#define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */
1246 /* Same bits as for EMU_HANA_IRQ_ENABLE */
1247 /* Reading the register resets it. */
1248
1249#define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
1250#define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */
1251#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
1252#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */
1253#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */
1254
1255#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */
1256 /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */
1257
1258#define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1259#define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1260
1261#define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1262#define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1263
1264#define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
1265#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1266#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1267
1268// The actual code disagrees about the bit width of the registers -
1269// the formula used is freq = 0x1770000 / (((X_HI << 5) | X_LO) + 1)
1270
1271#define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1272#define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1273
1274#define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1275#define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1276
1277#define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1278#define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1279
1280#define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1281#define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1282
1283/* 0x30 - 0x3f Unused Read only registers */
1284
1285// The meaning of this is not clear; kX-project just calls it "lock" in some info-only code.
1286#define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */
1287#define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */
1288
1289/************************************************************************************************/
1290/* EMU1010 Audio Destinations */
1291/************************************************************************************************/
1292/* Hana, original 1010,1212m,1820[m] using Alice2
1293 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1294 * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock
1295 * 0x00: Dock DAC 1 Left
1296 * 0x04: Dock DAC 1 Right
1297 * 0x08: Dock DAC 2 Left
1298 * 0x0c: Dock DAC 2 Right
1299 * 0x10: Dock DAC 3 Left
1300 * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left)
1301 * 0x14: Dock DAC 3 Right
1302 * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right)
1303 * 0x18: Dock DAC 4 Left
1304 * 0x1a: S/PDIF Left
1305 * 0x1c: Dock DAC 4 Right
1306 * 0x1e: S/PDIF Right
1307 * 0x02, 0x00: Hana S/PDIF Left
1308 * 0x02, 0x01: Hana S/PDIF Right
1309 * 0x03, 0x00: Hamoa DAC Left
1310 * 0x03, 0x01: Hamoa DAC Right
1311 * 0x04, 0x00-0x07: Hana ADAT
1312 * 0x05, 0x00: I2S0 Left to Alice2
1313 * 0x05, 0x01: I2S0 Right to Alice2
1314 * 0x06, 0x00: I2S0 Left to Alice2
1315 * 0x06, 0x01: I2S0 Right to Alice2
1316 * 0x07, 0x00: I2S0 Left to Alice2
1317 * 0x07, 0x01: I2S0 Right to Alice2
1318 *
1319 * Hana2 never released, but used Tina
1320 * Not needed.
1321 *
1322 * Hana3, rev2 1010,1212m,1616[m] using Tina
1323 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1324 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1325 * 0x00: Dock DAC 1 Left
1326 * 0x04: Dock DAC 1 Right
1327 * 0x08: Dock DAC 2 Left
1328 * 0x0c: Dock DAC 2 Right
1329 * 0x10: Dock DAC 3 Left
1330 * 0x12: Dock S/PDIF Left
1331 * 0x14: Dock DAC 3 Right
1332 * 0x16: Dock S/PDIF Right
1333 * 0x18-0x1f: Dock ADAT 0-7
1334 * 0x02, 0x00: Hana3 S/PDIF Left
1335 * 0x02, 0x01: Hana3 S/PDIF Right
1336 * 0x03, 0x00: Hamoa DAC Left
1337 * 0x03, 0x01: Hamoa DAC Right
1338 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1339 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1340 * 0x06-0x07: Not used
1341 *
1342 * HanaLite, rev1 0404 using Alice2
1343 * HanaLiteLite, rev2 0404 using Tina
1344 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina
1345 * 0x01: Not used
1346 * 0x02, 0x00: S/PDIF Left
1347 * 0x02, 0x01: S/PDIF Right
1348 * 0x03, 0x00: DAC Left
1349 * 0x03, 0x01: DAC Right
1350 * 0x04-0x07: Not used
1351 *
1352 * Mana, Cardbus 1616 using Tina2
1353 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1354 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1355 * (same as rev2 1010)
1356 * 0x02: Not used
1357 * 0x03, 0x00: Mana DAC Left
1358 * 0x03, 0x01: Mana DAC Right
1359 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1360 * 0x05-0x07: Not used
1361 */
1362
1363/* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1364 * physical outputs of Hana, or outputs going to Alice2/Tina for capture -
1365 * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into
1366 * a channel depends on the mixer control setting for each destination - see
1367 * the register arrays in emumixer.c.
1368 */
1369#define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
1370 /* This channel is delayed by one sample. */
1371#define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1372#define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1373#define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1374#define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1375#define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1376#define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1377#define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1378#define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1379#define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1380#define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1381#define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
1382#define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
1383#define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
1384#define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
1385#define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
1386#define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1387#define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1388#define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1389#define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
1390#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1391#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1392#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1393#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
1394#define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1395#define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1396#define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1397#define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
1398#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1399#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1400#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1401#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
1402#define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1403#define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1404#define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1405#define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
1406#define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1407#define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
1408#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1409#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1410#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1411#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
1412#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1413#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
1414#define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1415#define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1416#define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1417#define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
1418#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1419#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
1420#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1421#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1422#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1423#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
1424#define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1425#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
1426#define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1427#define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
1428#define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */
1429#define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */
1430#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1431#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
1432#define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */
1433#define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */
1434#define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1435#define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1436#define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1437#define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1438#define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1439#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1440#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1441#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1442// In S/MUX mode, the samples of one channel are adjacent.
1443#define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
1444#define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
1445#define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
1446#define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
1447#define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
1448#define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
1449#define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
1450
1451/* Additional destinations for 1616(M)/Microdock */
1452
1453#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1454#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1455#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1456#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1457#define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */
1458
1459#define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1460#define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1461
1462/************************************************************************************************/
1463/* EMU1010 Audio Sources */
1464/************************************************************************************************/
1465/* Hana, original 1010,1212m,1820[m] using Alice2
1466 * 0x00, 0x00-0x1f: Silence
1467 * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock
1468 * 0x00: Dock Mic A
1469 * 0x04: Dock Mic B
1470 * 0x08: Dock ADC 1 Left
1471 * 0x0c: Dock ADC 1 Right
1472 * 0x10: Dock ADC 2 Left
1473 * 0x14: Dock ADC 2 Right
1474 * 0x18: Dock ADC 3 Left
1475 * 0x1c: Dock ADC 3 Right
1476 * 0x02, 0x00: Hamoa ADC Left
1477 * 0x02, 0x01: Hamoa ADC Right
1478 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1479 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1480 * 0x04, 0x00-0x07: Hana ADAT
1481 * 0x05, 0x00: Hana S/PDIF Left
1482 * 0x05, 0x01: Hana S/PDIF Right
1483 * 0x06-0x07: Not used
1484 *
1485 * Hana2 never released, but used Tina
1486 * Not needed.
1487 *
1488 * Hana3, rev2 1010,1212m,1616[m] using Tina
1489 * 0x00, 0x00-0x1f: Silence
1490 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1491 * 0x00: Dock Mic A
1492 * 0x04: Dock Mic B
1493 * 0x08: Dock ADC 1 Left
1494 * 0x0c: Dock ADC 1 Right
1495 * 0x10: Dock ADC 2 Left
1496 * 0x12: Dock S/PDIF Left
1497 * 0x14: Dock ADC 2 Right
1498 * 0x16: Dock S/PDIF Right
1499 * 0x18-0x1f: Dock ADAT 0-7
1500 * 0x02, 0x00: Hamoa ADC Left
1501 * 0x02, 0x01: Hamoa ADC Right
1502 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1503 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1504 * 0x04, 0x00-0x07: Hana3 ADAT
1505 * 0x05, 0x00: Hana3 S/PDIF Left
1506 * 0x05, 0x01: Hana3 S/PDIF Right
1507 * 0x06-0x07: Not used
1508 *
1509 * HanaLite, rev1 0404 using Alice2
1510 * HanaLiteLite, rev2 0404 using Tina
1511 * 0x00, 0x00-0x1f: Silence
1512 * 0x01: Not used
1513 * 0x02, 0x00: ADC Left
1514 * 0x02, 0x01: ADC Right
1515 * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output
1516 * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output
1517 * 0x04: Not used
1518 * 0x05, 0x00: S/PDIF Left
1519 * 0x05, 0x01: S/PDIF Right
1520 * 0x06-0x07: Not used
1521 *
1522 * Mana, Cardbus 1616 using Tina2
1523 * 0x00, 0x00-0x1f: Silence
1524 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1525 * (same as rev2 1010)
1526 * 0x02: Not used
1527 * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output
1528 * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output
1529 * 0x04-0x07: Not used
1530 */
1531
1532/* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1533 * destinations using a mixer control for each destination - see emumixer.c.
1534 * Sources are either physical inputs of Hana, or inputs from Alice2/Tina -
1535 * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B.
1536 */
1537#define EMU_SRC_SILENCE 0x0000 /* Silence */
1538#define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1539#define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
1540#define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
1541#define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
1542#define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1543#define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
1544#define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
1545#define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
1546#define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1547#define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
1548#define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
1549#define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
1550#define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1551#define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
1552#define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
1553#define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
1554#define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1555#define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
1556#define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
1557#define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
1558#define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1559#define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
1560#define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
1561#define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
1562#define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1563#define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
1564#define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
1565#define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
1566#define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1567#define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
1568#define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
1569#define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
1570#define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1571#define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1572#define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1573#define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1574#define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1575#define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1576#define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1577#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1578#define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
1579#define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
1580// In S/MUX mode, the samples of one channel are adjacent.
1581#define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
1582#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1583#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
1584#define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */
1585#define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */
1586#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1587#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
1588#define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */
1589#define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */
1590
1591/* Additional inputs for 1616(M)/Microdock */
1592
1593#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */
1594#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */
1595#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */
1596#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */
1597#define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */
1598
1599/* 0x600 and 0x700 no used */
1600
1601
1602/* ------------------- CONSTANTS -------------------- */
1603
1604extern const char * const snd_emu10k1_fxbus[32];
1605extern const char * const snd_emu10k1_sblive_ins[16];
1606extern const char * const snd_emu10k1_audigy_ins[16];
1607extern const char * const snd_emu10k1_sblive_outs[32];
1608extern const char * const snd_emu10k1_audigy_outs[32];
1609extern const s8 snd_emu10k1_sblive51_fxbus2_map[16];
1610
1611/* ------------------- STRUCTURES -------------------- */
1612
1613enum {
1614 EMU10K1_UNUSED, // This must be zero
1615 EMU10K1_EFX,
1616 EMU10K1_EFX_IRQ,
1617 EMU10K1_PCM,
1618 EMU10K1_PCM_IRQ,
1619 EMU10K1_SYNTH,
1620 EMU10K1_NUM_TYPES
1621};
1622
1623struct snd_emu10k1;
1624
1625struct snd_emu10k1_voice {
1626 unsigned char number;
1627 unsigned char use;
1628 unsigned char dirty;
1629 unsigned char last;
1630 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1631
1632 struct snd_emu10k1_pcm *epcm;
1633};
1634
1635enum {
1636 PLAYBACK_EMUVOICE,
1637 PLAYBACK_EFX,
1638 CAPTURE_AC97ADC,
1639 CAPTURE_AC97MIC,
1640 CAPTURE_EFX
1641};
1642
1643struct snd_emu10k1_pcm {
1644 struct snd_emu10k1 *emu;
1645 int type;
1646 struct snd_pcm_substream *substream;
1647 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1648 struct snd_emu10k1_voice *extra;
1649 unsigned short running;
1650 unsigned short first_ptr;
1651 snd_pcm_uframes_t resume_pos;
1652 struct snd_util_memblk *memblk;
1653 unsigned int pitch_target;
1654 unsigned int start_addr;
1655 unsigned int ccca_start_addr;
1656 unsigned int capture_ipr; /* interrupt acknowledge mask */
1657 unsigned int capture_inte; /* interrupt enable mask */
1658 unsigned int capture_ba_reg; /* buffer address register */
1659 unsigned int capture_bs_reg; /* buffer size register */
1660 unsigned int capture_idx_reg; /* buffer index register */
1661 unsigned int capture_cr_val; /* control value */
1662 unsigned int capture_cr_val2; /* control value2 (for audigy) */
1663 unsigned int capture_bs_val; /* buffer size value */
1664 unsigned int capture_bufsize; /* buffer size in bytes */
1665};
1666
1667struct snd_emu10k1_pcm_mixer {
1668 /* mono, left, right x 8 sends (4 on emu10k1) */
1669 unsigned char send_routing[3][8];
1670 unsigned char send_volume[3][8];
1671 // 0x8000 is neutral. The mixer code rescales it to 0xffff to maintain
1672 // backwards compatibility with user space.
1673 unsigned short attn[3];
1674 struct snd_emu10k1_pcm *epcm;
1675};
1676
1677#define snd_emu10k1_compose_send_routing(route) \
1678((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1679
1680#define snd_emu10k1_compose_audigy_fxrt1(route) \
1681((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24) | 0x80808080)
1682
1683#define snd_emu10k1_compose_audigy_fxrt2(route) \
1684((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24) | 0x80808080)
1685
1686#define snd_emu10k1_compose_audigy_sendamounts(vol) \
1687(((unsigned int)vol[4] << 24) | ((unsigned int)vol[5] << 16) | ((unsigned int)vol[6] << 8) | (unsigned int)vol[7])
1688
1689struct snd_emu10k1_memblk {
1690 struct snd_util_memblk mem;
1691 /* private part */
1692 int first_page, last_page, pages, mapped_page;
1693 unsigned int map_locked;
1694 struct list_head mapped_link;
1695 struct list_head mapped_order_link;
1696};
1697
1698#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1699
1700#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1701
1702struct snd_emu10k1_fx8010_ctl {
1703 struct list_head list; /* list link container */
1704 unsigned int vcount;
1705 unsigned int count; /* count of GPR (1..16) */
1706 unsigned short gpr[32]; /* GPR number(s) */
1707 int value[32];
1708 int min; /* minimum range */
1709 int max; /* maximum range */
1710 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1711 struct snd_kcontrol *kcontrol;
1712};
1713
1714typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1715
1716struct snd_emu10k1_fx8010_irq {
1717 struct snd_emu10k1_fx8010_irq *next;
1718 snd_fx8010_irq_handler_t *handler;
1719 unsigned short gpr_running;
1720 void *private_data;
1721};
1722
1723struct snd_emu10k1_fx8010_pcm {
1724 unsigned int valid: 1,
1725 opened: 1,
1726 active: 1;
1727 unsigned int channels; /* 16-bit channels count */
1728 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1729 unsigned int buffer_size; /* count of buffered samples */
1730 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1731 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1732 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1733 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1734 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1735 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1736 unsigned char etram[32]; /* external TRAM address & data */
1737 struct snd_pcm_indirect pcm_rec;
1738 unsigned int tram_pos;
1739 unsigned int tram_shift;
1740 struct snd_emu10k1_fx8010_irq irq;
1741};
1742
1743struct snd_emu10k1_fx8010 {
1744 unsigned short extin_mask; /* used external inputs (bitmask); not used for Audigy */
1745 unsigned short extout_mask; /* used external outputs (bitmask); not used for Audigy */
1746 unsigned int itram_size; /* internal TRAM size in samples */
1747 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1748 unsigned int dbg; /* FX debugger register */
1749 unsigned char name[128];
1750 int gpr_size; /* size of allocated GPR controls */
1751 int gpr_count; /* count of used kcontrols */
1752 struct list_head gpr_ctl; /* GPR controls */
1753 struct mutex lock;
1754 struct snd_emu10k1_fx8010_pcm pcm[8];
1755 spinlock_t irq_lock;
1756 struct snd_emu10k1_fx8010_irq *irq_handlers;
1757};
1758
1759struct snd_emu10k1_midi {
1760 struct snd_emu10k1 *emu;
1761 struct snd_rawmidi *rmidi;
1762 struct snd_rawmidi_substream *substream_input;
1763 struct snd_rawmidi_substream *substream_output;
1764 unsigned int midi_mode;
1765 spinlock_t input_lock;
1766 spinlock_t output_lock;
1767 spinlock_t open_lock;
1768 int tx_enable, rx_enable;
1769 int port;
1770 int ipr_tx, ipr_rx;
1771 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1772};
1773
1774enum {
1775 EMU_MODEL_SB,
1776 EMU_MODEL_EMU1010,
1777 EMU_MODEL_EMU1010B,
1778 EMU_MODEL_EMU1616,
1779 EMU_MODEL_EMU0404,
1780};
1781
1782// Chip-o-logy:
1783// - All SB Live! cards use EMU10K1 chips
1784// - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver
1785// - Original Audigy uses CA0100 "Alice"
1786// - Audigy 2 uses CA0102/CA10200 "Alice2"
1787// - Has an interface for CA0151 (P16V) "Alice3"
1788// - Audigy 2 Value uses CA0108/CA10300 "Tina"
1789// - Approximately a CA0102 with an on-chip CA0151 (P17V)
1790// - Audigy 2 ZS NB uses CA0109 "Tina2"
1791// - Cardbus version of CA0108
1792struct snd_emu_chip_details {
1793 u32 vendor;
1794 u32 device;
1795 u32 subsystem;
1796 unsigned char revision;
1797 unsigned char emu_model; /* EMU model type */
1798#ifndef TARGET_OS2
1799 unsigned int emu10k1_chip:1; /* Original SB Live. Not SB Live 24bit. */
1800 /* Redundant with emu10k2_chip being unset. */
1801 unsigned int emu10k2_chip:1; /* Audigy 1 or Audigy 2. */
1802 unsigned int ca0102_chip:1; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1803 /* Redundant with ca0108_chip being unset. */
1804 unsigned int ca0108_chip:1; /* Audigy 2 Value */
1805 unsigned int ca_cardbus_chip:1; /* Audigy 2 ZS Notebook */
1806 unsigned int ca0151_chip:1; /* P16V */
1807 unsigned int spk20:1; /* Stereo only */
1808 unsigned int spk71:1; /* Has 7.1 speakers */
1809 unsigned int no_adat:1; /* Has no ADAT, only SPDIF */
1810 unsigned int sblive51:1; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1811 unsigned int spdif_bug:1; /* Has Spdif phasing bug */
1812 unsigned int ac97_chip:2; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1813 unsigned int ecard:1; /* APS EEPROM */
1814 unsigned int spi_dac:1; /* SPI interface for DAC; requires ca0108_chip */
1815 unsigned int i2c_adc:1; /* I2C interface for ADC; requires ca0108_chip */
1816 unsigned int adc_1361t:1; /* Use Philips 1361T ADC */
1817 unsigned int invert_shared_spdif:1; /* analog/digital switch inverted */
1818#else
1819 unsigned int emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1820 /* Redundant with emu10k2_chip being unset. */
1821 unsigned int emu10k2_chip; /* Audigy 1 or Audigy 2. */
1822 unsigned int ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1823 /* Redundant with ca0108_chip being unset. */
1824 unsigned int ca0108_chip; /* Audigy 2 Value */
1825 unsigned int ca_cardbus_chip; /* Audigy 2 ZS Notebook */
1826 unsigned int ca0151_chip; /* P16V */
1827 unsigned int spk20; /* Stereo only */
1828 unsigned int spk71; /* Has 7.1 speakers */
1829 unsigned int no_adat; /* Has no ADAT, only SPDIF */
1830 unsigned int sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1831 unsigned int spdif_bug; /* Has Spdif phasing bug */
1832 unsigned int ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1833 unsigned int ecard; /* APS EEPROM */
1834 unsigned int spi_dac; /* SPI interface for DAC; requires ca0108_chip */
1835 unsigned int i2c_adc; /* I2C interface for ADC; requires ca0108_chip */
1836 unsigned int adc_1361t; /* Use Philips 1361T ADC */
1837 unsigned int invert_shared_spdif; /* analog/digital switch inverted */
1838#endif
1839 const char *driver;
1840 const char *name;
1841 const char *id; /* for backward compatibility - can be NULL if not needed */
1842};
1843
1844#define NUM_OUTPUT_DESTS 28
1845#define NUM_INPUT_DESTS 22
1846
1847struct snd_emu1010 {
1848 unsigned char output_source[NUM_OUTPUT_DESTS];
1849 unsigned char input_source[NUM_INPUT_DESTS];
1850 unsigned int adc_pads; /* bit mask */
1851 unsigned int dac_pads; /* bit mask */
1852 unsigned int wclock; /* Cached register value */
1853 unsigned int word_clock; /* Cached effective value */
1854 unsigned int clock_source;
1855 unsigned int clock_fallback;
1856 unsigned int optical_in; /* 0:SPDIF, 1:ADAT */
1857 unsigned int optical_out; /* 0:SPDIF, 1:ADAT */
1858 struct work_struct work;
1859 struct mutex lock;
1860};
1861
1862struct snd_emu10k1 {
1863 int irq;
1864
1865 unsigned long port; /* I/O port number */
1866 unsigned int tos_link: 1, /* tos link detected */
1867 rear_ac97: 1, /* rear channels are on AC'97 */
1868 enable_ir: 1;
1869 unsigned int support_tlv :1;
1870 /* Contains profile of card capabilities */
1871 const struct snd_emu_chip_details *card_capabilities;
1872 unsigned int audigy; /* is Audigy? */
1873 unsigned int revision; /* chip revision */
1874 unsigned int serial; /* serial number */
1875 unsigned short model; /* subsystem id */
1876 unsigned int ecard_ctrl; /* ecard control bits */
1877 unsigned int address_mode; /* address mode */
1878 unsigned long dma_mask; /* PCI DMA mask */
1879 bool iommu_workaround; /* IOMMU workaround needed */
1880 int max_cache_pages; /* max memory size / PAGE_SIZE */
1881 struct snd_dma_buffer silent_page; /* silent page */
1882 struct snd_dma_buffer ptb_pages; /* page table pages */
1883 struct snd_dma_device p16v_dma_dev;
1884 struct snd_dma_buffer *p16v_buffer;
1885
1886 struct snd_util_memhdr *memhdr; /* page allocation list */
1887
1888 struct list_head mapped_link_head;
1889 struct list_head mapped_order_link_head;
1890 void **page_ptr_table;
1891 unsigned long *page_addr_table;
1892 spinlock_t memblk_lock;
1893
1894 unsigned int spdif_bits[3]; /* s/pdif out setup */
1895 unsigned int i2c_capture_source;
1896 u8 i2c_capture_volume[4][2];
1897
1898 struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */
1899 int gpr_base;
1900
1901 struct snd_ac97 *ac97;
1902
1903 struct pci_dev *pci;
1904 struct snd_card *card;
1905 struct snd_pcm *pcm;
1906 struct snd_pcm *pcm_mic;
1907 struct snd_pcm *pcm_efx;
1908 struct snd_pcm *pcm_multi;
1909 struct snd_pcm *pcm_p16v;
1910
1911 spinlock_t synth_lock;
1912 void *synth;
1913 int (*get_synth_voice)(struct snd_emu10k1 *emu);
1914
1915 spinlock_t reg_lock; // high-level driver lock
1916 spinlock_t emu_lock; // low-level i/o lock
1917 spinlock_t voice_lock; // voice allocator lock
1918 spinlock_t spi_lock; /* serialises access to spi port */
1919 spinlock_t i2c_lock; /* serialises access to i2c port */
1920
1921 struct snd_emu10k1_voice voices[NUM_G];
1922 int p16v_device_offset;
1923 u32 p16v_capture_source;
1924 u32 p16v_capture_channel;
1925 struct snd_emu1010 emu1010;
1926 struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1927 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1928 struct snd_kcontrol *ctl_send_routing;
1929 struct snd_kcontrol *ctl_send_volume;
1930 struct snd_kcontrol *ctl_attn;
1931 struct snd_kcontrol *ctl_efx_send_routing;
1932 struct snd_kcontrol *ctl_efx_send_volume;
1933 struct snd_kcontrol *ctl_efx_attn;
1934 struct snd_kcontrol *ctl_clock_source;
1935
1936 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1937 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1938 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1939 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1940 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1941 void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1942 void (*gpio_interrupt)(struct snd_emu10k1 *emu);
1943 void (*p16v_interrupt)(struct snd_emu10k1 *emu);
1944
1945 struct snd_pcm_substream *pcm_capture_substream;
1946 struct snd_pcm_substream *pcm_capture_mic_substream;
1947 struct snd_pcm_substream *pcm_capture_efx_substream;
1948
1949 struct snd_timer *timer;
1950
1951 struct snd_emu10k1_midi midi;
1952 struct snd_emu10k1_midi midi2; /* for audigy */
1953
1954 unsigned int efx_voices_mask[2];
1955 unsigned int next_free_voice;
1956
1957 const struct firmware *firmware;
1958 const struct firmware *dock_fw;
1959
1960#ifdef CONFIG_PM_SLEEP
1961 unsigned int *saved_ptr;
1962 unsigned int *saved_gpr;
1963 unsigned int *tram_val_saved;
1964 unsigned int *tram_addr_saved;
1965 unsigned int *saved_icode;
1966 unsigned int *p16v_saved;
1967 unsigned int saved_a_iocfg, saved_hcfg;
1968 bool suspend;
1969#endif
1970
1971};
1972
1973int snd_emu10k1_create(struct snd_card *card,
1974 struct pci_dev *pci,
1975 unsigned short extin_mask,
1976 unsigned short extout_mask,
1977 long max_cache_bytes,
1978 int enable_ir,
1979 uint subsystem);
1980
1981int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device);
1982int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device);
1983int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device);
1984int snd_p16v_pcm(struct snd_emu10k1 *emu, int device);
1985int snd_p16v_mixer(struct snd_emu10k1 * emu);
1986int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device);
1987int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device);
1988int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1989int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1990int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device);
1991
1992irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1993
1994void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1995int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1996void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1997int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1998int snd_emu10k1_done(struct snd_emu10k1 * emu);
1999
2000/* I/O functions */
2001unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
2002void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
2003void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...);
2004unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
2005void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
2006int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
2007int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
2008static inline void snd_emu1010_fpga_lock(struct snd_emu10k1 *emu) { mutex_lock(&emu->emu1010.lock); };
2009static inline void snd_emu1010_fpga_unlock(struct snd_emu10k1 *emu) { mutex_unlock(&emu->emu1010.lock); };
2010void snd_emu1010_fpga_write_lock(struct snd_emu10k1 *emu, u32 reg, u32 value);
2011void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
2012void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value);
2013void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src);
2014u32 snd_emu1010_fpga_link_dst_src_read(struct snd_emu10k1 *emu, u32 dst);
2015int snd_emu1010_get_raw_rate(struct snd_emu10k1 *emu, u8 src);
2016void snd_emu1010_update_clock(struct snd_emu10k1 *emu);
2017void snd_emu1010_load_firmware_entry(struct snd_emu10k1 *emu, int dock, const struct firmware *fw_entry);
2018unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
2019void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
2020void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
2021void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
2022void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
2023void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
2024void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
2025void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
2026void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
2027#if 0
2028void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
2029void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
2030#endif
2031void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices);
2032void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices);
2033int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices);
2034void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
2035static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
2036unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
2037void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
2038
2039#ifdef CONFIG_PM_SLEEP
2040void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
2041void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
2042void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
2043int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
2044void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
2045void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
2046void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
2047int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
2048void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
2049void snd_p16v_suspend(struct snd_emu10k1 *emu);
2050void snd_p16v_resume(struct snd_emu10k1 *emu);
2051#endif
2052
2053/* memory allocation */
2054struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
2055int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
2056int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size,
2057 struct snd_dma_buffer *dmab);
2058struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
2059int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
2060int snd_emu10k1_synth_memset(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size, u8 value);
2061int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size, u32 xor);
2062int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
2063
2064/* voice allocation */
2065int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int count, int channels,
2066 struct snd_emu10k1_pcm *epcm, struct snd_emu10k1_voice **rvoice);
2067int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
2068
2069/* MIDI uart */
2070int snd_emu10k1_midi(struct snd_emu10k1 * emu);
2071int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
2072
2073/* proc interface */
2074int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
2075
2076/* fx8010 irq handler */
2077int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
2078 snd_fx8010_irq_handler_t *handler,
2079 unsigned char gpr_running,
2080 void *private_data,
2081 struct snd_emu10k1_fx8010_irq *irq);
2082int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
2083 struct snd_emu10k1_fx8010_irq *irq);
2084
2085#endif /* __SOUND_EMU10K1_H */
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