source: GPL/trunk/alsa-kernel/hda/hdac_controller.c

Last change on this file was 777, checked in by David Azarewicz, 7 months ago

Merge from uniaud32-exp branch
File size: 20.8 KB
Line 
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * HD-audio controller helpers
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/export.h>
9#include <sound/core.h>
10#include <sound/hdaudio.h>
11#include <sound/hda_register.h>
12#include "local.h"
13
14/* clear CORB read pointer properly */
15static void azx_clear_corbrp(struct hdac_bus *bus)
16{
17 int timeout;
18
19 for (timeout = 1000; timeout > 0; timeout--) {
20 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
21 break;
22 udelay(1);
23 }
24 if (timeout <= 0)
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
26 snd_hdac_chip_readw(bus, CORBRP));
27
28 snd_hdac_chip_writew(bus, CORBRP, 0);
29 for (timeout = 1000; timeout > 0; timeout--) {
30 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
31 break;
32 udelay(1);
33 }
34 if (timeout <= 0)
35 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
36 snd_hdac_chip_readw(bus, CORBRP));
37}
38
39/**
40 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
41 * @bus: HD-audio core bus
42 */
43void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
44{
45 WARN_ON_ONCE(!bus->rb.area);
46
47 spin_lock_irq(&bus->reg_lock);
48 /* CORB set up */
49 bus->corb.addr = bus->rb.addr;
50 bus->corb.buf = (__le32 *)bus->rb.area;
51 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
52 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
53
54 /* set the corb size to 256 entries (ULI requires explicitly) */
55 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
56 /* set the corb write pointer to 0 */
57 snd_hdac_chip_writew(bus, CORBWP, 0);
58
59 /* reset the corb hw read pointer */
60 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
61 if (!bus->corbrp_self_clear)
62 azx_clear_corbrp(bus);
63
64 /* enable corb dma */
65 if (!bus->use_pio_for_commands)
66 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
67
68 /* RIRB set up */
69 bus->rirb.addr = bus->rb.addr + 2048;
70 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
71 bus->rirb.wp = bus->rirb.rp = 0;
72 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
73 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
74 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
75
76 /* set the rirb size to 256 entries (ULI requires explicitly) */
77 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
78 /* reset the rirb hw write pointer */
79 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
80 /* set N=1, get RIRB response interrupt for new entry */
81 snd_hdac_chip_writew(bus, RINTCNT, 1);
82 /* enable rirb dma and response irq */
83 if (bus->not_use_interrupts)
84 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN);
85 else
86 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
87 /* Accept unsolicited responses */
88 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
89 spin_unlock_irq(&bus->reg_lock);
90}
91EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
92
93/* wait for cmd dmas till they are stopped */
94static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
95{
96 unsigned long timeout;
97
98 timeout = jiffies + msecs_to_jiffies(100);
99 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
100 && time_before(jiffies, timeout))
101 udelay(10);
102
103 timeout = jiffies + msecs_to_jiffies(100);
104 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
105 && time_before(jiffies, timeout))
106 udelay(10);
107}
108
109/**
110 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
111 * @bus: HD-audio core bus
112 */
113void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
114{
115 spin_lock_irq(&bus->reg_lock);
116 /* disable ringbuffer DMAs */
117 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
118 snd_hdac_chip_writeb(bus, CORBCTL, 0);
119 spin_unlock_irq(&bus->reg_lock);
120
121 hdac_wait_for_cmd_dmas(bus);
122
123 spin_lock_irq(&bus->reg_lock);
124 /* disable unsolicited responses */
125 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
126 spin_unlock_irq(&bus->reg_lock);
127}
128EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
129
130static unsigned int azx_command_addr(u32 cmd)
131{
132 unsigned int addr = cmd >> 28;
133
134 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
135 addr = 0;
136 return addr;
137}
138
139/* receive an Immediate Response with PIO */
140static int snd_hdac_bus_wait_for_pio_response(struct hdac_bus *bus,
141 unsigned int addr)
142{
143 int timeout = 50;
144
145 while (timeout--) {
146 /* check IRV bit */
147 if (snd_hdac_chip_readw(bus, IRS) & AZX_IRS_VALID) {
148 /* reuse rirb.res as the response return value */
149 bus->rirb.res[addr] = snd_hdac_chip_readl(bus, IR);
150 return 0;
151 }
152 udelay(1);
153 }
154
155 dev_dbg_ratelimited(bus->dev, "get_response_pio timeout: IRS=%#x\n",
156 snd_hdac_chip_readw(bus, IRS));
157
158 bus->rirb.res[addr] = -1;
159
160 return -EIO;
161}
162
163/**
164 * snd_hdac_bus_send_cmd_pio - send a command verb via Immediate Command
165 * @bus: HD-audio core bus
166 * @val: encoded verb value to send
167 *
168 * Returns zero for success or a negative error code.
169 */
170static int snd_hdac_bus_send_cmd_pio(struct hdac_bus *bus, unsigned int val)
171{
172 unsigned int addr = azx_command_addr(val);
173 int timeout = 50;
174 int ret = -EIO;
175
176 spin_lock_irq(&bus->reg_lock);
177
178 while (timeout--) {
179 /* check ICB bit */
180 if (!((snd_hdac_chip_readw(bus, IRS) & AZX_IRS_BUSY))) {
181 /* Clear IRV bit */
182 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_VALID, AZX_IRS_VALID);
183 snd_hdac_chip_writel(bus, IC, val);
184 /* Set ICB bit */
185 snd_hdac_chip_updatew(bus, IRS, AZX_IRS_BUSY, AZX_IRS_BUSY);
186
187 ret = snd_hdac_bus_wait_for_pio_response(bus, addr);
188 goto out;
189 }
190 udelay(1);
191 }
192
193 dev_dbg_ratelimited(bus->dev, "send_cmd_pio timeout: IRS=%#x, val=%#x\n",
194 snd_hdac_chip_readw(bus, IRS), val);
195
196out:
197 spin_unlock_irq(&bus->reg_lock);
198
199 return ret;
200}
201
202/**
203 * snd_hdac_bus_get_response_pio - receive a response via Immediate Response
204 * @bus: HD-audio core bus
205 * @addr: codec address
206 * @res: pointer to store the value, NULL when not needed
207 *
208 * Returns zero if a value is read, or a negative error code.
209 */
210static int snd_hdac_bus_get_response_pio(struct hdac_bus *bus,
211 unsigned int addr, unsigned int *res)
212{
213 if (res)
214 *res = bus->rirb.res[addr];
215
216 return 0;
217}
218
219/**
220 * snd_hdac_bus_send_cmd_corb - send a command verb via CORB
221 * @bus: HD-audio core bus
222 * @val: encoded verb value to send
223 *
224 * Returns zero for success or a negative error code.
225 */
226static int snd_hdac_bus_send_cmd_corb(struct hdac_bus *bus, unsigned int val)
227{
228 unsigned int addr = azx_command_addr(val);
229 unsigned int wp, rp;
230
231 spin_lock_irq(&bus->reg_lock);
232
233 bus->last_cmd[azx_command_addr(val)] = val;
234
235 /* add command to corb */
236 wp = snd_hdac_chip_readw(bus, CORBWP);
237 if (wp == 0xffff) {
238 /* something wrong, controller likely turned to D3 */
239 spin_unlock_irq(&bus->reg_lock);
240 return -EIO;
241 }
242 wp++;
243 wp %= AZX_MAX_CORB_ENTRIES;
244
245 rp = snd_hdac_chip_readw(bus, CORBRP);
246 if (wp == rp) {
247 /* oops, it's full */
248 spin_unlock_irq(&bus->reg_lock);
249 return -EAGAIN;
250 }
251
252 bus->rirb.cmds[addr]++;
253 bus->corb.buf[wp] = cpu_to_le32(val);
254 snd_hdac_chip_writew(bus, CORBWP, wp);
255
256 spin_unlock_irq(&bus->reg_lock);
257
258 return 0;
259}
260
261#define AZX_RIRB_EX_UNSOL_EV (1<<4)
262
263/**
264 * snd_hdac_bus_update_rirb - retrieve RIRB entries
265 * @bus: HD-audio core bus
266 *
267 * Usually called from interrupt handler.
268 * The caller needs bus->reg_lock spinlock before calling this.
269 */
270void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
271{
272 unsigned int rp, wp;
273 unsigned int addr;
274 u32 res, res_ex;
275
276 wp = snd_hdac_chip_readw(bus, RIRBWP);
277 if (wp == 0xffff) {
278 /* something wrong, controller likely turned to D3 */
279 return;
280 }
281
282 if (wp == bus->rirb.wp)
283 return;
284 bus->rirb.wp = wp;
285
286 while (bus->rirb.rp != wp) {
287 bus->rirb.rp++;
288 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
289
290 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
291 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
292 res = le32_to_cpu(bus->rirb.buf[rp]);
293 addr = res_ex & 0xf;
294 if (addr >= HDA_MAX_CODECS) {
295 dev_err(bus->dev,
296 "spurious response %#x:%#x, rp = %d, wp = %d",
297 res, res_ex, bus->rirb.rp, wp);
298 snd_BUG();
299 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
300 snd_hdac_bus_queue_event(bus, res, res_ex);
301 else if (bus->rirb.cmds[addr]) {
302 bus->rirb.res[addr] = res;
303 bus->rirb.cmds[addr]--;
304 if (!bus->rirb.cmds[addr] &&
305 waitqueue_active(&bus->rirb_wq))
306 wake_up(&bus->rirb_wq);
307 } else {
308 dev_err_ratelimited(bus->dev,
309 "spurious response %#x:%#x, last cmd=%#08x\n",
310 res, res_ex, bus->last_cmd[addr]);
311 }
312 }
313}
314EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
315
316/**
317 * snd_hdac_bus_get_response_rirb - receive a response via RIRB
318 * @bus: HD-audio core bus
319 * @addr: codec address
320 * @res: pointer to store the value, NULL when not needed
321 *
322 * Returns zero if a value is read, or a negative error code.
323 */
324static int snd_hdac_bus_get_response_rirb(struct hdac_bus *bus,
325 unsigned int addr, unsigned int *res)
326{
327 unsigned long timeout;
328 unsigned long loopcounter;
329 //NOT_USED wait_queue_entry_t wait;
330 bool warned = false;
331
332#ifndef TARGET_OS2
333 init_wait_entry(&wait, 0);
334#endif
335 timeout = jiffies + msecs_to_jiffies(1000);
336
337 for (loopcounter = 0;; loopcounter++) {
338 spin_lock_irq(&bus->reg_lock);
339#ifndef TARGET_OS2
340 if (!bus->polling_mode)
341 prepare_to_wait(&bus->rirb_wq, &wait,
342 TASK_UNINTERRUPTIBLE);
343#endif
344 if (bus->polling_mode)
345 snd_hdac_bus_update_rirb(bus);
346 if (!bus->rirb.cmds[addr]) {
347 if (res)
348 *res = bus->rirb.res[addr]; /* the last value */
349#ifndef TARGET_OS2
350 if (!bus->polling_mode)
351 finish_wait(&bus->rirb_wq, &wait);
352#endif
353 spin_unlock_irq(&bus->reg_lock);
354 return 0;
355 }
356 spin_unlock_irq(&bus->reg_lock);
357 if (time_after(jiffies, timeout))
358 break;
359#define LOOP_COUNT_MAX 3000
360 if (!bus->polling_mode) {
361 schedule_timeout(msecs_to_jiffies(2));
362 } else if (bus->needs_damn_long_delay ||
363 loopcounter > LOOP_COUNT_MAX) {
364 if (loopcounter > LOOP_COUNT_MAX && !warned) {
365 dev_dbg_ratelimited(bus->dev,
366 "too slow response, last cmd=%#08x\n",
367 bus->last_cmd[addr]);
368 warned = true;
369 }
370 msleep(2); /* temporary workaround */
371 } else {
372 udelay(10);
373 cond_resched();
374 }
375 }
376#ifndef TARGET_OS2
377 if (!bus->polling_mode)
378 finish_wait(&bus->rirb_wq, &wait);
379#endif
380 return -EIO;
381}
382
383/**
384 * snd_hdac_bus_send_cmd - send a command verb via CORB or PIO
385 * @bus: HD-audio core bus
386 * @val: encoded verb value to send
387 *
388 * Returns zero for success or a negative error code.
389 */
390int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
391{
392 if (bus->use_pio_for_commands)
393 return snd_hdac_bus_send_cmd_pio(bus, val);
394
395 return snd_hdac_bus_send_cmd_corb(bus, val);
396}
397EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
398
399/**
400 * snd_hdac_bus_get_response - receive a response via RIRB or PIO
401 * @bus: HD-audio core bus
402 * @addr: codec address
403 * @res: pointer to store the value, NULL when not needed
404 *
405 * Returns zero if a value is read, or a negative error code.
406 */
407int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
408 unsigned int *res)
409{
410 if (bus->use_pio_for_commands)
411 return snd_hdac_bus_get_response_pio(bus, addr, res);
412
413 return snd_hdac_bus_get_response_rirb(bus, addr, res);
414}
415EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
416
417#define HDAC_MAX_CAPS 10
418/**
419 * snd_hdac_bus_parse_capabilities - parse capability structure
420 * @bus: the pointer to bus object
421 *
422 * Returns 0 if successful, or a negative error code.
423 */
424int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
425{
426 unsigned int cur_cap;
427 unsigned int offset;
428 unsigned int counter = 0;
429
430 offset = snd_hdac_chip_readw(bus, LLCH);
431
432 /* Lets walk the linked capabilities list */
433 do {
434 cur_cap = _snd_hdac_chip_readl(bus, offset);
435
436 dev_dbg(bus->dev, "Capability version: 0x%x\n",
437 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
438
439 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
440 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
441
442 if (cur_cap == -1) {
443 dev_dbg(bus->dev, "Invalid capability reg read\n");
444 break;
445 }
446
447 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
448 case AZX_ML_CAP_ID:
449 dev_dbg(bus->dev, "Found ML capability\n");
450 bus->mlcap = bus->remap_addr + offset;
451 break;
452
453 case AZX_GTS_CAP_ID:
454 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
455 bus->gtscap = bus->remap_addr + offset;
456 break;
457
458 case AZX_PP_CAP_ID:
459 /* PP capability found, the Audio DSP is present */
460 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
461 bus->ppcap = bus->remap_addr + offset;
462 break;
463
464 case AZX_SPB_CAP_ID:
465 /* SPIB capability found, handler function */
466 dev_dbg(bus->dev, "Found SPB capability\n");
467 bus->spbcap = bus->remap_addr + offset;
468 break;
469
470 case AZX_DRSM_CAP_ID:
471 /* DMA resume capability found, handler function */
472 dev_dbg(bus->dev, "Found DRSM capability\n");
473 bus->drsmcap = bus->remap_addr + offset;
474 break;
475
476 default:
477 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
478 cur_cap = 0;
479 break;
480 }
481
482 counter++;
483
484 if (counter > HDAC_MAX_CAPS) {
485 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
486 break;
487 }
488
489 /* read the offset of next capability */
490 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
491
492 } while (offset);
493
494 return 0;
495}
496EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
497
498/*
499 * Lowlevel interface
500 */
501
502/**
503 * snd_hdac_bus_enter_link_reset - enter link reset
504 * @bus: HD-audio core bus
505 *
506 * Enter to the link reset state.
507 */
508void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
509{
510 unsigned long timeout;
511
512 /* reset controller */
513 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
514
515 timeout = jiffies + msecs_to_jiffies(100);
516 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
517 time_before(jiffies, timeout))
518 usleep_range(500, 1000);
519}
520EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
521
522/**
523 * snd_hdac_bus_exit_link_reset - exit link reset
524 * @bus: HD-audio core bus
525 *
526 * Exit from the link reset state.
527 */
528void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
529{
530 unsigned long timeout;
531
532 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET);
533
534 timeout = jiffies + msecs_to_jiffies(100);
535 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
536 usleep_range(500, 1000);
537}
538EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
539
540/* reset codec link */
541int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
542{
543 if (!full_reset)
544 goto skip_reset;
545
546 /* clear STATESTS if not in reset */
547 if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
548 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
549
550 /* reset controller */
551 snd_hdac_bus_enter_link_reset(bus);
552
553 /* delay for >= 100us for codec PLL to settle per spec
554 * Rev 0.9 section 5.5.1
555 */
556 usleep_range(500, 1000);
557
558 /* Bring controller out of reset */
559 snd_hdac_bus_exit_link_reset(bus);
560
561 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
562 usleep_range(1000, 1200);
563
564 skip_reset:
565 /* check to see if controller is ready */
566 if (!snd_hdac_chip_readb(bus, GCTL)) {
567 dev_dbg(bus->dev, "controller not ready!\n");
568 return -EBUSY;
569 }
570
571 /* detect codecs */
572 if (!bus->codec_mask) {
573 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
574 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
575 }
576
577 return 0;
578}
579EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
580
581/* enable interrupts */
582static void azx_int_enable(struct hdac_bus *bus)
583{
584 /* enable controller CIE and GIE */
585 snd_hdac_chip_updatel(bus, INTCTL,
586 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN,
587 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
588}
589
590/* disable interrupts */
591static void azx_int_disable(struct hdac_bus *bus)
592{
593 struct hdac_stream *azx_dev;
594
595 /* disable interrupts in stream descriptor */
596 list_for_each_entry(azx_dev, &bus->stream_list, list, struct hdac_stream)
597 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
598
599 /* disable SIE for all streams & disable controller CIE and GIE */
600 snd_hdac_chip_writel(bus, INTCTL, 0);
601}
602
603/* clear interrupts */
604static void azx_int_clear(struct hdac_bus *bus)
605{
606 struct hdac_stream *azx_dev;
607
608 /* clear stream status */
609 list_for_each_entry(azx_dev, &bus->stream_list, list, struct hdac_stream)
610 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
611
612 /* clear STATESTS */
613 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
614
615 /* clear rirb status */
616 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
617
618 /* clear int status */
619 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
620}
621
622/**
623 * snd_hdac_bus_init_chip - reset and start the controller registers
624 * @bus: HD-audio core bus
625 * @full_reset: Do full reset
626 */
627bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
628{
629 if (bus->chip_init)
630 return false;
631
632 /* reset controller */
633 snd_hdac_bus_reset_link(bus, full_reset);
634
635 /* clear interrupts */
636 azx_int_clear(bus);
637
638 /* initialize the codec command I/O */
639 snd_hdac_bus_init_cmd_io(bus);
640
641 /* enable interrupts after CORB/RIRB buffers are initialized above */
642 azx_int_enable(bus);
643
644 /* program the position buffer */
645 if (bus->use_posbuf && bus->posbuf.addr) {
646 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
647 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
648 }
649
650 bus->chip_init = true;
651
652 return true;
653}
654EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
655
656/**
657 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
658 * @bus: HD-audio core bus
659 */
660void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
661{
662 if (!bus->chip_init)
663 return;
664
665 /* disable interrupts */
666 azx_int_disable(bus);
667 azx_int_clear(bus);
668
669 /* disable CORB/RIRB */
670 snd_hdac_bus_stop_cmd_io(bus);
671
672 /* disable position buffer */
673 if (bus->posbuf.addr) {
674 snd_hdac_chip_writel(bus, DPLBASE, 0);
675 snd_hdac_chip_writel(bus, DPUBASE, 0);
676 }
677
678 bus->chip_init = false;
679}
680EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
681
682/**
683 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
684 * @bus: HD-audio core bus
685 * @status: INTSTS register value
686 * @ack: callback to be called for woken streams
687 *
688 * Returns the bits of handled streams, or zero if no stream is handled.
689 */
690int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
691 void (*ack)(struct hdac_bus *,
692 struct hdac_stream *))
693{
694 struct hdac_stream *azx_dev;
695 u8 sd_status;
696 int handled = 0;
697
698 list_for_each_entry(azx_dev, &bus->stream_list, list, struct hdac_stream) {
699 if (status & azx_dev->sd_int_sta_mask) {
700 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
701 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
702 handled |= 1 << azx_dev->index;
703 if ((!azx_dev->substream && !azx_dev->cstream) ||
704 !azx_dev->running || !(sd_status & SD_INT_COMPLETE))
705 continue;
706 if (ack)
707 ack(bus, azx_dev);
708 }
709 }
710 return handled;
711}
712EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
713
714/**
715 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
716 * @bus: HD-audio core bus
717 *
718 * Call this after assigning the all streams.
719 * Returns zero for success, or a negative error code.
720 */
721int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
722{
723 struct hdac_stream *s;
724 int num_streams = 0;
725 int dma_type = bus->dma_type ? bus->dma_type : SNDRV_DMA_TYPE_DEV;
726 int err;
727
728 list_for_each_entry(s, &bus->stream_list, list, struct hdac_stream) {
729 /* allocate memory for the BDL for each stream */
730 err = snd_dma_alloc_pages(dma_type, bus->dev,
731 BDL_SIZE, &s->bdl);
732 num_streams++;
733 if (err < 0)
734 return -ENOMEM;
735 }
736
737 if (WARN_ON(!num_streams))
738 return -EINVAL;
739 /* allocate memory for the position buffer */
740 err = snd_dma_alloc_pages(dma_type, bus->dev,
741 num_streams * 8, &bus->posbuf);
742 if (err < 0)
743 return -ENOMEM;
744 list_for_each_entry(s, &bus->stream_list, list, struct hdac_stream)
745 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
746
747 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
748 return snd_dma_alloc_pages(dma_type, bus->dev, PAGE_SIZE, &bus->rb);
749}
750EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
751
752/**
753 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
754 * @bus: HD-audio core bus
755 */
756void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
757{
758 struct hdac_stream *s;
759
760 list_for_each_entry(s, &bus->stream_list, list, struct hdac_stream) {
761 if (s->bdl.area)
762 snd_dma_free_pages(&s->bdl);
763 }
764
765 if (bus->rb.area)
766 snd_dma_free_pages(&bus->rb);
767 if (bus->posbuf.area)
768 snd_dma_free_pages(&bus->posbuf);
769}
770EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);
771
772/**
773 * snd_hdac_bus_link_power - power up/down codec link
774 * @codec: HD-audio device
775 * @enable: whether to power-up the link
776 */
777void snd_hdac_bus_link_power(struct hdac_device *codec, bool enable)
778{
779 if (enable)
780 set_bit(codec->addr, &codec->bus->codec_powered);
781 else
782 clear_bit(codec->addr, &codec->bus->codec_powered);
783}
784EXPORT_SYMBOL_GPL(snd_hdac_bus_link_power);
Note: See TracBrowser for help on using the repository browser.