| 1 | /*
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| 2 | * include/linux/serial_reg.h
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| 3 | *
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| 4 | * Copyright (C) 1992, 1994 by Theodore Ts'o.
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| 5 | *
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| 6 | * Redistribution of this file is permitted under the terms of the GNU
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| 7 | * Public License (GPL)
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| 8 | *
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| 9 | * These are the UART port assignments, expressed as offsets from the base
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| 10 | * register. These assignments should hold for any serial port based on
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| 11 | * a 8250, 16450, or 16550(A).
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| 12 | */
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| 13 |
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| 14 | #ifndef _LINUX_SERIAL_REG_H
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| 15 | #define _LINUX_SERIAL_REG_H
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| 16 |
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| 17 | #define UART_RX 0 /* In: Receive buffer (DLAB=0) */
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| 18 | #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
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| 19 | #define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
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| 20 | #define UART_TRG 0 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
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| 21 | * In: Fifo count
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| 22 | * Out: Fifo custom trigger levels
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| 23 | * XR16C85x only */
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| 24 |
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| 25 | #define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
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| 26 | #define UART_IER 1 /* Out: Interrupt Enable Register */
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| 27 | #define UART_FCTR 1 /* (LCR=BF) Feature Control Register
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| 28 | * XR16C85x only */
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| 29 |
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| 30 | #define UART_IIR 2 /* In: Interrupt ID Register */
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| 31 | #define UART_FCR 2 /* Out: FIFO Control Register */
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| 32 | #define UART_EFR 2 /* I/O: Extended Features Register */
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| 33 | /* (DLAB=1, 16C660 only) */
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| 34 |
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| 35 | #define UART_LCR 3 /* Out: Line Control Register */
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| 36 | #define UART_MCR 4 /* Out: Modem Control Register */
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| 37 | #define UART_LSR 5 /* In: Line Status Register */
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| 38 | #define UART_MSR 6 /* In: Modem Status Register */
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| 39 | #define UART_SCR 7 /* I/O: Scratch Register */
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| 40 | #define UART_EMSR 7 /* (LCR=BF) Extended Mode Select Register
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| 41 | * FCTR bit 6 selects SCR or EMSR
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| 42 | * XR16c85x only */
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| 43 |
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| 44 | /*
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| 45 | * These are the definitions for the FIFO Control Register
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| 46 | * (16650 only)
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| 47 | */
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| 48 | #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
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| 49 | #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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| 50 | #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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| 51 | #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
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| 52 | #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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| 53 | #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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| 54 | #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
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| 55 | #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
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| 56 | #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
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| 57 | /* 16650 redefinitions */
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| 58 | #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
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| 59 | #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
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| 60 | #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
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| 61 | #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
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| 62 | #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
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| 63 | #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
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| 64 | #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
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| 65 | #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
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| 66 | /* TI 16750 definitions */
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| 67 | #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode */
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| 68 |
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| 69 | /*
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| 70 | * These are the definitions for the Line Control Register
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| 71 | *
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| 72 | * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
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| 73 | * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
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| 74 | */
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| 75 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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| 76 | #define UART_LCR_SBC 0x40 /* Set break control */
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| 77 | #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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| 78 | #define UART_LCR_EPAR 0x10 /* Even parity select */
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| 79 | #define UART_LCR_PARITY 0x08 /* Parity Enable */
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| 80 | #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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| 81 | #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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| 82 | #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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| 83 | #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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| 84 | #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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| 85 |
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| 86 | /*
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| 87 | * These are the definitions for the Line Status Register
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| 88 | */
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| 89 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */
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| 90 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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| 91 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */
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| 92 | #define UART_LSR_FE 0x08 /* Frame error indicator */
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| 93 | #define UART_LSR_PE 0x04 /* Parity error indicator */
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| 94 | #define UART_LSR_OE 0x02 /* Overrun error indicator */
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| 95 | #define UART_LSR_DR 0x01 /* Receiver data ready */
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| 96 |
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| 97 | /*
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| 98 | * These are the definitions for the Interrupt Identification Register
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| 99 | */
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| 100 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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| 101 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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| 102 |
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| 103 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */
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| 104 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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| 105 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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| 106 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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| 107 |
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| 108 | /*
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| 109 | * These are the definitions for the Interrupt Enable Register
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| 110 | */
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| 111 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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| 112 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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| 113 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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| 114 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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| 115 | /*
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| 116 | * Sleep mode for ST16650 and TI16750.
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| 117 | * Note that for 16650, EFR-bit 4 must be selected as well.
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| 118 | */
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| 119 | #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
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| 120 |
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| 121 | /*
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| 122 | * These are the definitions for the Modem Control Register
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| 123 | */
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| 124 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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| 125 | #define UART_MCR_OUT2 0x08 /* Out2 complement */
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| 126 | #define UART_MCR_OUT1 0x04 /* Out1 complement */
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| 127 | #define UART_MCR_RTS 0x02 /* RTS complement */
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| 128 | #define UART_MCR_DTR 0x01 /* DTR complement */
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| 129 |
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| 130 | /*
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| 131 | * These are the definitions for the Modem Status Register
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| 132 | */
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| 133 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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| 134 | #define UART_MSR_RI 0x40 /* Ring Indicator */
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| 135 | #define UART_MSR_DSR 0x20 /* Data Set Ready */
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| 136 | #define UART_MSR_CTS 0x10 /* Clear to Send */
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| 137 | #define UART_MSR_DDCD 0x08 /* Delta DCD */
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| 138 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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| 139 | #define UART_MSR_DDSR 0x02 /* Delta DSR */
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| 140 | #define UART_MSR_DCTS 0x01 /* Delta CTS */
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| 141 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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| 142 |
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| 143 | /*
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| 144 | * These are the definitions for the Extended Features Register
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| 145 | * (StarTech 16C660 only, when DLAB=1)
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| 146 | */
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| 147 | #define UART_EFR_CTS 0x80 /* CTS flow control */
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| 148 | #define UART_EFR_RTS 0x40 /* RTS flow control */
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| 149 | #define UART_EFR_SCD 0x20 /* Special character detect */
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| 150 | #define UART_EFR_ECB 0x10 /* Enhanced control bit */
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| 151 | /*
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| 152 | * the low four bits control software flow control
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| 153 | */
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| 154 |
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| 155 | /*
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| 156 | * These register definitions are for the 16C950
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| 157 | */
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| 158 | #define UART_ASR 0x01 /* Additional Status Register */
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| 159 | #define UART_RFL 0x03 /* Transmitter FIFO level */
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| 160 | #define UART_TFL 0x04 /* Receiver FIFO level */
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| 161 | #define UART_ICR 0x05 /* Index Control Register */
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| 162 |
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| 163 | /* The 16950 ICR registers */
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| 164 | #define UART_ACR 0x00 /* Additional Control Register */
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| 165 | #define UART_CPR 0x01 /* Clock Prescalar Register */
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| 166 | #define UART_TCR 0x02 /* Times Clock Register */
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| 167 | #define UART_CKS 0x03 /* Clock Select Register */
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| 168 | #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
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| 169 | #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
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| 170 | #define UART_FCL 0x06 /* Flow Control Level Lower */
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| 171 | #define UART_FCH 0x07 /* Flow Control Level Higher */
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| 172 | #define UART_ID1 0x08 /* ID #1 */
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| 173 | #define UART_ID2 0x09 /* ID #2 */
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| 174 | #define UART_ID3 0x0A /* ID #3 */
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| 175 | #define UART_REV 0x0B /* Revision */
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| 176 | #define UART_CSR 0x0C /* Channel Software Reset */
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| 177 | #define UART_NMR 0x0D /* Nine-bit Mode Register */
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| 178 | #define UART_CTR 0xFF
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| 179 |
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| 180 | /*
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| 181 | * The 16C950 Additional Control Reigster
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| 182 | */
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| 183 | #define UART_ACR_RXDIS 0x01 /* Receiver disable */
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| 184 | #define UART_ACR_TXDIS 0x02 /* Receiver disable */
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| 185 | #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
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| 186 | #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
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| 187 | #define UART_ACR_ICRRD 0x40 /* ICR Read enable */
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| 188 | #define UART_ACR_ASREN 0x80 /* Additional status enable */
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| 189 |
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| 190 | /*
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| 191 | * These are the definitions for the Feature Control Register
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| 192 | * (XR16C85x only, when LCR=bf; doubles with the Interrupt Enable
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| 193 | * Register, UART register #1)
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| 194 | */
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| 195 | #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
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| 196 | #define UART_FCTR_RTS_4DELAY 0x01
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| 197 | #define UART_FCTR_RTS_6DELAY 0x02
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| 198 | #define UART_FCTR_RTS_8DELAY 0x03
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| 199 | #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
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| 200 | #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
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| 201 | #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
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| 202 | #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
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| 203 | #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
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| 204 | #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
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| 205 | #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
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| 206 | #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
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| 207 | #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
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| 208 |
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| 209 | /*
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| 210 | * These are the definitions for the Enhanced Mode Select Register
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| 211 | * (XR16C85x only, when LCR=bf and FCTR bit 6=1; doubles with the
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| 212 | * Scratch register, UART register #7)
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| 213 | */
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| 214 | #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
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| 215 | #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
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| 216 |
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| 217 | /*
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| 218 | * These are the definitions for the Programmable Trigger
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| 219 | * Register (XR16C85x only, when LCR=bf; doubles with the UART RX/TX
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| 220 | * register, UART register #0)
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| 221 | */
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| 222 | #define UART_TRG_1 0x01
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| 223 | #define UART_TRG_4 0x04
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| 224 | #define UART_TRG_8 0x08
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| 225 | #define UART_TRG_16 0x10
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| 226 | #define UART_TRG_32 0x20
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| 227 | #define UART_TRG_64 0x40
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| 228 | #define UART_TRG_96 0x60
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| 229 | #define UART_TRG_120 0x78
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| 230 | #define UART_TRG_128 0x80
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| 231 |
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| 232 | #endif /* _LINUX_SERIAL_REG_H */
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| 233 |
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