source: GPL/include/asm/processor.h@ 1

Last change on this file since 1 was 1, checked in by vladest, 20 years ago

initial import
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1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <linux/threads.h>
16
17/*
18 * Default implementation of macro that returns current
19 * instruction pointer ("program counter").
20 */
21#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
22
23/*
24 * CPU type and hardware bug flags. Kept separately for each CPU.
25 * Members of this structure are referenced in head.S, so think twice
26 * before touching them. [mj]
27 */
28
29struct cpuinfo_x86 {
30 __u8 x86; /* CPU family */
31 __u8 x86_vendor; /* CPU vendor */
32 __u8 x86_model;
33 __u8 x86_mask;
34 char wp_works_ok; /* It doesn't on 386's */
35 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
36 char hard_math;
37 char rfu;
38 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
39 __u32 x86_capability;
40 char x86_vendor_id[16];
41 char x86_model_id[64];
42 int x86_cache_size; /* in KB - valid for CPUS which support this
43 call */
44 int fdiv_bug;
45 int f00f_bug;
46 int coma_bug;
47 unsigned long loops_per_sec;
48 unsigned long *pgd_quick;
49 unsigned long *pmd_quick;
50 unsigned long *pte_quick;
51 unsigned long pgtable_cache_sz;
52};
53
54#define X86_VENDOR_INTEL 0
55#define X86_VENDOR_CYRIX 1
56#define X86_VENDOR_AMD 2
57#define X86_VENDOR_UMC 3
58#define X86_VENDOR_NEXGEN 4
59#define X86_VENDOR_CENTAUR 5
60#define X86_VENDOR_UNKNOWN 0xff
61
62/*
63 * capabilities of CPUs
64 */
65
66#define X86_FEATURE_FPU 0x00000001 /* onboard FPU */
67#define X86_FEATURE_VME 0x00000002 /* Virtual Mode Extensions */
68#define X86_FEATURE_DE 0x00000004 /* Debugging Extensions */
69#define X86_FEATURE_PSE 0x00000008 /* Page Size Extensions */
70#define X86_FEATURE_TSC 0x00000010 /* Time Stamp Counter */
71#define X86_FEATURE_MSR 0x00000020 /* Model-Specific Registers, RDMSR, WRMSR */
72#define X86_FEATURE_PAE 0x00000040 /* Physical Address Extensions */
73#define X86_FEATURE_MCE 0x00000080 /* Machine Check Exceptions */
74#define X86_FEATURE_CX8 0x00000100 /* CMPXCHG8 instruction */
75#define X86_FEATURE_APIC 0x00000200 /* onboard APIC */
76#define X86_FEATURE_10 0x00000400
77#define X86_FEATURE_SEP 0x00000800 /* Fast System Call */
78#define X86_FEATURE_MTRR 0x00001000 /* Memory Type Range Registers */
79#define X86_FEATURE_PGE 0x00002000 /* Page Global Enable */
80#define X86_FEATURE_MCA 0x00004000 /* Machine Check Architecture */
81#define X86_FEATURE_CMOV 0x00008000 /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
82#define X86_FEATURE_PAT 0x00010000 /* Page Attribute Table */
83#define X86_FEATURE_PSE36 0x00020000 /* 36-bit PSEs */
84#define X86_FEATURE_18 0x00040000
85#define X86_FEATURE_19 0x00080000
86#define X86_FEATURE_20 0x00100000
87#define X86_FEATURE_21 0x00200000
88#define X86_FEATURE_22 0x00400000
89#define X86_FEATURE_MMX 0x00800000 /* multimedia extensions */
90#define X86_FEATURE_FXSR 0x01000000 /* FXSAVE and FXRSTOR instructions (fast save and restore of FPU context), and CR4.OSFXSR (OS uses these instructions) available */
91#define X86_FEATURE_25 0x02000000
92#define X86_FEATURE_26 0x04000000
93#define X86_FEATURE_27 0x08000000
94#define X86_FEATURE_28 0x10000000
95#define X86_FEATURE_29 0x20000000
96#define X86_FEATURE_30 0x40000000
97#define X86_FEATURE_AMD3D 0x80000000
98
99extern struct cpuinfo_x86 boot_cpu_data;
100extern struct tss_struct init_tss[NR_CPUS];
101
102#ifdef __SMP__
103extern struct cpuinfo_x86 cpu_data[];
104#define current_cpu_data cpu_data[smp_processor_id()]
105#else
106#define cpu_data &boot_cpu_data
107#define current_cpu_data boot_cpu_data
108#endif
109
110#define cpu_has_pge \
111 (boot_cpu_data.x86_capability & X86_FEATURE_PGE)
112#define cpu_has_pse \
113 (boot_cpu_data.x86_capability & X86_FEATURE_PSE)
114#define cpu_has_pae \
115 (boot_cpu_data.x86_capability & X86_FEATURE_PAE)
116#define cpu_has_tsc \
117 (cpu_data[smp_processor_id()].x86_capability & X86_FEATURE_TSC)
118
119extern char ignore_irq13;
120
121extern void identify_cpu(struct cpuinfo_x86 *);
122extern void print_cpu_info(struct cpuinfo_x86 *);
123extern void dodgy_tsc(void);
124
125
126/*
127 * Intel CPU features in CR4
128 */
129#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
130#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
131#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
132#define X86_CR4_DE 0x0008 /* enable debugging extensions */
133#define X86_CR4_PSE 0x0010 /* enable page size extensions */
134#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
135#define X86_CR4_MCE 0x0040 /* Machine check enable */
136#define X86_CR4_PGE 0x0080 /* enable global pages */
137#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
138
139/*
140 * Save the cr4 feature set we're using (ie
141 * Pentium 4MB enable and PPro Global page
142 * enable), so that any CPU's that boot up
143 * after us can get the correct flags.
144 */
145extern unsigned long mmu_cr4_features;
146
147
148/*
149 * Cyrix CPU configuration register indexes
150 */
151#define CX86_CCR0 0xc0
152#define CX86_CCR1 0xc1
153#define CX86_CCR2 0xc2
154#define CX86_CCR3 0xc3
155#define CX86_CCR4 0xe8
156#define CX86_CCR5 0xe9
157#define CX86_CCR6 0xea
158#define CX86_DIR0 0xfe
159#define CX86_DIR1 0xff
160#define CX86_ARR_BASE 0xc4
161#define CX86_RCR_BASE 0xdc
162
163/*
164 * Cyrix CPU indexed register access macros
165 */
166
167#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
168
169#define setCx86(reg, data) do { \
170 outb((reg), 0x22); \
171 outb((data), 0x23); \
172} while (0)
173
174/*
175 * Bus types (default is ISA, but people can check others with these..)
176 */
177extern int EISA_bus;
178extern int MCA_bus;
179
180/* from system description table in BIOS. Mostly for MCA use, but
181others may find it useful. */
182extern unsigned int machine_id;
183extern unsigned int machine_submodel_id;
184extern unsigned int BIOS_revision;
185extern unsigned int mca_pentium_flag;
186
187/*
188 * User space process size: 3GB (default).
189 */
190#define TASK_SIZE (PAGE_OFFSET)
191
192/* This decides where the kernel will search for a free chunk of vm
193 * space during mmap's.
194 */
195#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
196
197/*
198 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
199 */
200#define IO_BITMAP_SIZE 32
201#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
202#define INVALID_IO_BITMAP_OFFSET 0x8000
203
204struct i387_hard_struct {
205 long cwd;
206 long swd;
207 long twd;
208 long fip;
209 long fcs;
210 long foo;
211 long fos;
212 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
213 long status; /* software status information */
214};
215
216struct i387_soft_struct {
217 long cwd;
218 long swd;
219 long twd;
220 long fip;
221 long fcs;
222 long foo;
223 long fos;
224 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
225 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
226 struct info *info;
227 unsigned long entry_eip;
228};
229
230union i387_union {
231 struct i387_hard_struct hard;
232 struct i387_soft_struct soft;
233};
234
235typedef unsigned long mm_segment_t;
236
237
238struct tss_struct {
239 unsigned short back_link,__blh;
240 unsigned long esp0;
241 unsigned short ss0,__ss0h;
242 unsigned long esp1;
243 unsigned short ss1,__ss1h;
244 unsigned long esp2;
245 unsigned short ss2,__ss2h;
246 unsigned long __cr3;
247 unsigned long eip;
248 unsigned long eflags;
249 unsigned long eax,ecx,edx,ebx;
250 unsigned long esp;
251 unsigned long ebp;
252 unsigned long esi;
253 unsigned long edi;
254 unsigned short es, __esh;
255 unsigned short cs, __csh;
256 unsigned short ss, __ssh;
257 unsigned short ds, __dsh;
258 unsigned short fs, __fsh;
259 unsigned short gs, __gsh;
260 unsigned short ldt, __ldth;
261 unsigned short trace, bitmap;
262 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
263 /*
264 * pads the TSS to be cacheline-aligned (size is 0x100)
265 */
266 unsigned long __cacheline_filler[5];
267};
268
269struct thread_struct {
270 unsigned long esp0;
271 unsigned long eip;
272 unsigned long esp;
273 unsigned long fs;
274 unsigned long gs;
275/* Hardware debugging registers */
276 unsigned long debugreg[8]; /* %%db0-7 debug registers */
277/* fault info */
278 unsigned long cr2, trap_no, error_code;
279/* floating point info */
280 union i387_union i387;
281/* virtual 86 mode info */
282 struct vm86_struct * vm86_info;
283 unsigned long screen_bitmap;
284 unsigned long v86flags, v86mask, v86mode, saved_esp0;
285/* IO permissions */
286 int ioperm;
287 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
288};
289
290/* Forward declaration, a strange C thing */
291struct task_struct;
292struct mm_struct;
293
294/* Free all resources held by a thread. */
295extern void release_thread(struct task_struct *);
296/*
297 * create a kernel thread without removing it from tasklists
298 */
299extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
300
301/* Copy and release all segment info associated with a VM */
302extern void copy_segments(struct task_struct *p, struct mm_struct * mm);
303extern void release_segments(struct mm_struct * mm);
304extern void forget_segments(void);
305
306/*
307 * FPU lazy state save handling..
308 */
309#define save_fpu(tsk) do { \
310 asm volatile("fnsave %0\n\tfwait":"=m" (tsk->thread.i387)); \
311 tsk->flags &= ~PF_USEDFPU; \
312 stts(); \
313} while (0)
314
315#define unlazy_fpu(tsk) do { \
316 if (tsk->flags & PF_USEDFPU) \
317 save_fpu(tsk); \
318} while (0)
319
320#define clear_fpu(tsk) do { \
321 if (tsk->flags & PF_USEDFPU) { \
322 tsk->flags &= ~PF_USEDFPU; \
323 stts(); \
324 } \
325} while (0)
326
327/*
328 * Return saved PC of a blocked thread.
329 */
330//extern inline unsigned long thread_saved_pc(struct thread_struct *t)
331//{
332// return ((unsigned long *)t->esp)[3];
333//}
334
335unsigned long get_wchan(struct task_struct *p);
336#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
337#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
338
339#define THREAD_SIZE (2*PAGE_SIZE)
340#define alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
341#define free_task_struct(p) free_pages((unsigned long) (p), 1)
342
343#define init_task (init_task_union.task)
344#define init_stack (init_task_union.stack)
345
346#endif /* __ASM_I386_PROCESSOR_H */
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