source: GPL/alsa-kernel/pci/rme9652/rme9652.c@ 18

Last change on this file since 18 was 18, checked in by vladest, 20 years ago

initial import
File size: 84.7 KB
Line 
1/*
2 * ALSA driver for RME Digi9652 audio interfaces
3 *
4 * Copyright (c) 1999 IEM - Winfried Ritsch
5 * Copyright (c) 1999-2001 Paul Davis
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23#define SNDRV_MAIN_OBJECT_FILE
24#include <sound/driver.h>
25#include <sound/control.h>
26#include <sound/pcm.h>
27#include <sound/info.h>
28#define SNDRV_GET_ID
29#include <sound/initval.h>
30
31static int snd_index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
32static char *snd_id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
33static int snd_enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE; /* Enable this card */
34
35EXPORT_NO_SYMBOLS;
36MODULE_PARM(snd_index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
37MODULE_PARM_DESC(snd_index, "Index value for RME Digi9652 (Hammerfall) soundcard.");
38MODULE_PARM_SYNTAX(snd_index, SNDRV_INDEX_DESC);
39MODULE_PARM(snd_id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
40MODULE_PARM_DESC(snd_id, "ID string for RME Digi9652 (Hammerfall) soundcard.");
41MODULE_PARM_SYNTAX(snd_id, SNDRV_ID_DESC);
42MODULE_PARM(snd_enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
43MODULE_PARM_DESC(snd_enable, "Enable/disable specific RME96{52,36} soundcards.");
44MODULE_PARM_SYNTAX(snd_enable, SNDRV_ENABLE_DESC);
45MODULE_AUTHOR("Paul Davis <pbd@op.net>, Winfried Ritsch");
46MODULE_DESCRIPTION("RME Digi9652/Digi9636");
47MODULE_CLASSES("{sound}");
48MODULE_DEVICES("{{RME,Hammerfall},"
49 "{RME,Hammerfall-Light}}");
50
51/* The Hammerfall has two sets of 24 ADAT + 2 S/PDIF channels, one for
52 capture, one for playback. Both the ADAT and S/PDIF channels appear
53 to the host CPU in the same block of memory. There is no functional
54 difference between them in terms of access.
55
56 The Hammerfall Light is identical to the Hammerfall, except that it
57 has 2 sets 18 channels (16 ADAT + 2 S/PDIF) for capture and playback.
58*/
59
60#define RME9652_NCHANNELS 26
61#define RME9636_NCHANNELS 18
62
63/* Preferred sync source choices - used by "sync_pref" control switch */
64
65#define RME9652_SYNC_FROM_SPDIF 0
66#define RME9652_SYNC_FROM_ADAT1 1
67#define RME9652_SYNC_FROM_ADAT2 2
68#define RME9652_SYNC_FROM_ADAT3 3
69
70/* Possible sources of S/PDIF input */
71
72#define RME9652_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
73#define RME9652_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
74#define RME9652_SPDIFIN_INTERN 2 /* internal (CDROM) */
75
76/* ------------- Status-Register bits --------------------- */
77
78#define RME9652_IRQ (1<<0) /* IRQ is High if not reset by irq_clear */
79#define RME9652_lock_2 (1<<1) /* ADAT 3-PLL: 1=locked, 0=unlocked */
80#define RME9652_lock_1 (1<<2) /* ADAT 2-PLL: 1=locked, 0=unlocked */
81#define RME9652_lock_0 (1<<3) /* ADAT 1-PLL: 1=locked, 0=unlocked */
82#define RME9652_fs48 (1<<4) /* sample rate is 0=44.1/88.2,1=48/96 Khz */
83#define RME9652_wsel_rd (1<<5) /* if Word-Clock is used and valid then 1 */
84 /* bits 6-15 encode h/w buffer pointer position */
85#define RME9652_sync_2 (1<<16) /* if ADAT-IN 3 in sync to system clock */
86#define RME9652_sync_1 (1<<17) /* if ADAT-IN 2 in sync to system clock */
87#define RME9652_sync_0 (1<<18) /* if ADAT-IN 1 in sync to system clock */
88#define RME9652_DS_rd (1<<19) /* 1=Double Speed Mode, 0=Normal Speed */
89#define RME9652_tc_busy (1<<20) /* 1=time-code copy in progress (960ms) */
90#define RME9652_tc_out (1<<21) /* time-code out bit */
91#define RME9652_F_0 (1<<22) /* 000=64kHz, 100=88.2kHz, 011=96kHz */
92#define RME9652_F_1 (1<<23) /* 111=32kHz, 110=44.1kHz, 101=48kHz, */
93#define RME9652_F_2 (1<<24) /* external Crystal Chip if ERF=1 */
94#define RME9652_ERF (1<<25) /* Error-Flag of SDPIF Receiver (1=No Lock) */
95#define RME9652_buffer_id (1<<26) /* toggles by each interrupt on rec/play */
96#define RME9652_tc_valid (1<<27) /* 1 = a signal is detected on time-code input */
97#define RME9652_SPDIF_READ (1<<28) /* byte available from Rev 1.5+ S/PDIF interface */
98
99#define RME9652_sync (RME9652_sync_0|RME9652_sync_1|RME9652_sync_2)
100#define RME9652_lock (RME9652_lock_0|RME9652_lock_1|RME9652_lock_2)
101#define RME9652_F (RME9652_F_0|RME9652_F_1|RME9652_F_2)
102#define rme9652_decode_spdif_rate(x) ((x)>>22)
103
104/* Bit 6..15 : h/w buffer pointer */
105
106#define RME9652_buf_pos 0x000FFC0
107
108/* Bits 31,30,29 are bits 5,4,3 of h/w pointer position on later
109 Rev G EEPROMS and Rev 1.5 cards or later.
110*/
111
112#define RME9652_REV15_buf_pos(x) ((((x)&0xE0000000)>>26)|((x)&RME9652_buf_pos))
113
114#ifndef PCI_VENDOR_ID_XILINX
115#define PCI_VENDOR_ID_XILINX 0x10ee
116#endif
117#ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL
118#define PCI_DEVICE_ID_XILINX_HAMMERFALL 0x3fc4
119#endif
120
121/* amount of io space we remap for register access. i'm not sure we
122 even need this much, but 1K is nice round number :)
123*/
124
125#define RME9652_IO_EXTENT 1024
126
127#define RME9652_init_buffer 0
128#define RME9652_play_buffer 32 /* holds ptr to 26x64kBit host RAM */
129#define RME9652_rec_buffer 36 /* holds ptr to 26x64kBit host RAM */
130#define RME9652_control_register 64
131#define RME9652_irq_clear 96
132#define RME9652_time_code 100 /* useful if used with alesis adat */
133#define RME9652_thru_base 128 /* 132...228 Thru for 26 channels */
134
135/* Read-only registers */
136
137/* Writing to any of the register locations writes to the status
138 register. We'll use the first location as our point of access.
139*/
140
141#define RME9652_status_register 0
142
143/* --------- Control-Register Bits ---------------- */
144
145
146#define RME9652_start_bit (1<<0) /* start record/play */
147 /* bits 1-3 encode buffersize/latency */
148#define RME9652_Master (1<<4) /* Clock Mode Master=1,Slave/Auto=0 */
149#define RME9652_IE (1<<5) /* Interupt Enable */
150#define RME9652_freq (1<<6) /* samplerate 0=44.1/88.2, 1=48/96 kHz */
151#define RME9652_freq1 (1<<7) /* if 0, 32kHz, else always 1 */
152#define RME9652_DS (1<<8) /* Doule Speed 0=44.1/48, 1=88.2/96 Khz */
153#define RME9652_PRO (1<<9) /* S/PDIF out: 0=consumer, 1=professional */
154#define RME9652_EMP (1<<10) /* Emphasis 0=None, 1=ON */
155#define RME9652_Dolby (1<<11) /* Non-audio bit 1=set, 0=unset */
156#define RME9652_opt_out (1<<12) /* Use 1st optical OUT as SPDIF: 1=yes,0=no */
157#define RME9652_wsel (1<<13) /* use Wordclock as sync (overwrites master) */
158#define RME9652_inp_0 (1<<14) /* SPDIF-IN: 00=optical (ADAT1), */
159#define RME9652_inp_1 (1<<15) /* 01=koaxial (Cinch), 10=Internal CDROM */
160#define RME9652_SyncPref_ADAT2 (1<<16)
161#define RME9652_SyncPref_ADAT3 (1<<17)
162#define RME9652_SPDIF_RESET (1<<18) /* Rev 1.5+: h/w S/PDIF receiver */
163#define RME9652_SPDIF_SELECT (1<<19)
164#define RME9652_SPDIF_CLOCK (1<<20)
165#define RME9652_SPDIF_WRITE (1<<21)
166#define RME9652_ADAT1_INTERNAL (1<<22) /* Rev 1.5+: if set, internal CD connector carries ADAT */
167
168/* buffersize = 512Bytes * 2^n, where n is made from Bit2 ... Bit0 */
169
170#define RME9652_latency 0x0e
171#define rme9652_encode_latency(x) (((x)&0x7)<<1)
172#define rme9652_decode_latency(x) (((x)>>1)&0x7)
173#define rme9652_running_double_speed(s) ((s)->control_register & RME9652_DS)
174#define RME9652_inp (RME9652_inp_0|RME9652_inp_1)
175#define rme9652_encode_spdif_in(x) (((x)&0x3)<<14)
176#define rme9652_decode_spdif_in(x) (((x)>>14)&0x3)
177
178#define RME9652_SyncPref_Mask (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
179#define RME9652_SyncPref_ADAT1 0
180#define RME9652_SyncPref_SPDIF (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
181
182/* the size of a substream (1 mono data stream) */
183
184#define RME9652_CHANNEL_BUFFER_SAMPLES (16*1024)
185#define RME9652_CHANNEL_BUFFER_BYTES (4*RME9652_CHANNEL_BUFFER_SAMPLES)
186
187/* the size of the area we need to allocate for DMA transfers. the
188 size is the same regardless of the number of channels - the
189 9636 still uses the same memory area.
190
191 Note that we allocate 1 more channel than is apparently needed
192 because the h/w seems to write 1 byte beyond the end of the last
193 page. Sigh.
194*/
195
196#define RME9652_DMA_AREA_BYTES ((RME9652_NCHANNELS+1) * RME9652_CHANNEL_BUFFER_BYTES)
197#define RME9652_DMA_AREA_KILOBYTES (RME9652_DMA_AREA_BYTES/1024)
198
199typedef struct snd_rme9652 {
200 int dev;
201
202 spinlock_t lock;
203 int irq;
204 unsigned long port;
205 struct resource *res_port;
206 unsigned long iobase;
207
208 u32 control_register; /* cached value */
209 u32 thru_bits; /* thru 1=on, 0=off channel 1=Bit1... channel 26= Bit26 */
210
211 u32 creg_spdif;
212 u32 creg_spdif_stream;
213
214 char *card_name; /* hammerfall or hammerfall light names */
215
216 size_t hw_offsetmask; /* &-with status register to get real hw_offset */
217 size_t prev_hw_offset; /* previous hw offset */
218 size_t max_jitter; /* maximum jitter in frames for
219 hw pointer */
220 size_t period_bytes; /* guess what this is */
221
222 unsigned char ds_channels;
223 unsigned char ss_channels; /* different for hammerfall/hammerfall-light */
224
225 void *capture_buffer_unaligned; /* original buffer addresses */
226 void *playback_buffer_unaligned; /* original buffer addresses */
227 unsigned char *capture_buffer; /* suitably aligned address */
228 unsigned char *playback_buffer; /* suitably aligned address */
229 dma_addr_t capture_buffer_addr;
230 dma_addr_t playback_buffer_addr;
231
232 pid_t capture_pid;
233 pid_t playback_pid;
234
235 snd_pcm_substream_t *capture_substream;
236 snd_pcm_substream_t *playback_substream;
237 int running;
238
239 int passthru; /* non-zero if doing pass-thru */
240 int hw_rev; /* h/w rev * 10 (i.e. 1.5 has hw_rev = 15) */
241
242 int last_spdif_sample_rate; /* so that we can catch externally ... */
243 int last_adat_sample_rate; /* ... induced rate changes */
244
245 char *channel_map;
246
247 snd_card_t *card;
248 snd_pcm_t *pcm;
249 struct pci_dev *pci;
250 snd_info_entry_t *proc_entry;
251 snd_kcontrol_t *spdif_ctl;
252
253} rme9652_t;
254
255/* These tables map the ALSA channels 1..N to the channels that we
256 need to use in order to find the relevant channel buffer. RME
257 refer to this kind of mapping as between "the ADAT channel and
258 the DMA channel." We index it using the logical audio channel,
259 and the value is the DMA channel (i.e. channel buffer number)
260 where the data for that channel can be read/written from/to.
261*/
262
263static char channel_map_9652_ss[26] = {
264 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
265 18, 19, 20, 21, 22, 23, 24, 25
266};
267
268static char channel_map_9636_ss[26] = {
269 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
270 /* channels 16 and 17 are S/PDIF */
271 24, 25,
272 /* channels 18-25 don't exist */
273 -1, -1, -1, -1, -1, -1, -1, -1
274};
275
276static char channel_map_9652_ds[26] = {
277 /* ADAT channels are remapped */
278 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
279 /* channels 12 and 13 are S/PDIF */
280 24, 25,
281 /* others don't exist */
282 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
283};
284
285static char channel_map_9636_ds[26] = {
286 /* ADAT channels are remapped */
287 1, 3, 5, 7, 9, 11, 13, 15,
288 /* channels 8 and 9 are S/PDIF */
289 24, 25
290 /* others don't exist */
291 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
292};
293
294#define RME9652_PREALLOCATE_MEMORY /* via module snd-rme9652_mem */
295
296#ifdef RME9652_PREALLOCATE_MEMORY
297extern void *snd_rme9652_get_buffer(int card, dma_addr_t *dmaaddr);
298extern void snd_rme9652_free_buffer(int card, void *ptr);
299#endif
300
301static struct pci_device_id snd_rme9652_ids[] __devinitdata = {
302 {0x10ee, 0x3fc4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,}, /* RME Digi9652 */
303 {0,}
304};
305
306MODULE_DEVICE_TABLE(pci, snd_rme9652_ids);
307
308static inline void rme9652_write(rme9652_t *rme9652, int reg, int val)
309{
310 writel(val, rme9652->iobase + reg);
311}
312
313static inline unsigned int rme9652_read(rme9652_t *rme9652, int reg)
314{
315 return readl(rme9652->iobase + reg);
316}
317
318static inline int snd_rme9652_use_is_exclusive(rme9652_t *rme9652)
319{
320 unsigned long flags;
321 int ret = 1;
322
323 spin_lock_irqsave(&rme9652->lock, flags);
324 if ((rme9652->playback_pid != rme9652->capture_pid) &&
325 (rme9652->playback_pid >= 0) && (rme9652->capture_pid >= 0)) {
326 ret = 0;
327 }
328 spin_unlock_irqrestore(&rme9652->lock, flags);
329 return ret;
330}
331
332static inline int rme9652_adat_sample_rate(rme9652_t *rme9652)
333{
334 if (rme9652_running_double_speed(rme9652)) {
335 return (rme9652_read(rme9652, RME9652_status_register) &
336 RME9652_fs48) ? 96000 : 88200;
337 } else {
338 return (rme9652_read(rme9652, RME9652_status_register) &
339 RME9652_fs48) ? 48000 : 44100;
340 }
341}
342
343static inline void rme9652_compute_period_size(rme9652_t *rme9652)
344{
345 unsigned int i;
346
347 i = rme9652->control_register & RME9652_latency;
348 rme9652->period_bytes = 1 << ((rme9652_decode_latency(i) + 8));
349 rme9652->hw_offsetmask =
350 (rme9652->period_bytes * 2 - 1) & RME9652_buf_pos;
351 rme9652->max_jitter = 16 + (rme9652->period_bytes <= 1024 ? 32 : 64);
352}
353
354static inline snd_pcm_uframes_t rme9652_hw_pointer(rme9652_t *rme9652)
355{
356 int status;
357 int offset, frag;
358 snd_pcm_uframes_t period_size = rme9652->period_bytes / 4;
359 snd_pcm_sframes_t delta;
360
361 status = rme9652_read(rme9652, RME9652_status_register);
362 offset = status & RME9652_buf_pos;
363
364 /* The hardware may give a backward movement for up to 80 frames
365 Martin Kirst <martin.kirst@freenet.de> knows the details.
366 */
367
368 delta = rme9652->prev_hw_offset - offset;
369 delta &= 0xffff;
370 if (delta <= rme9652->max_jitter * 4)
371 offset = rme9652->prev_hw_offset;
372 else
373 rme9652->prev_hw_offset = offset;
374 offset &= rme9652->hw_offsetmask;
375 offset /= 4;
376 frag = status & RME9652_buffer_id;
377
378 if (offset < period_size) {
379 if (offset > rme9652->max_jitter) {
380 if (frag)
381 printk("Unexpected hw_pointer position (bufid == 0): status: %x offset: %d\n", status, offset);
382 } else if (!frag)
383 return 0;
384 offset -= rme9652->max_jitter;
385 if (offset < 0)
386 offset += period_size * 2;
387 } else {
388 if (offset > period_size + rme9652->max_jitter) {
389 if (!frag)
390 printk("Unexpected hw_pointer position (bufid == 1): status: %x offset: %d\n", status, offset);
391 } else if (frag)
392 return period_size;
393 offset -= rme9652->max_jitter;
394 }
395
396 return offset;
397}
398
399static inline void rme9652_reset_hw_pointer(rme9652_t *rme9652)
400{
401 int i;
402
403 /* reset the FIFO pointer to zero. We do this by writing to 8
404 registers, each of which is a 32bit wide register, and set
405 them all to zero. Note that s->iobase is a pointer to
406 int32, not pointer to char.
407 */
408
409 for (i = 0; i < 8; i++) {
410 rme9652_write(rme9652, i * 4, 0);
411 udelay(10);
412 }
413 rme9652->prev_hw_offset = 0;
414}
415
416static inline void rme9652_start(rme9652_t *s)
417{
418 s->control_register |= (RME9652_IE | RME9652_start_bit);
419 rme9652_write(s, RME9652_control_register, s->control_register);
420}
421
422static inline void rme9652_stop(rme9652_t *s)
423{
424 s->control_register &= ~(RME9652_start_bit | RME9652_IE);
425 rme9652_write(s, RME9652_control_register, s->control_register);
426}
427
428static int rme9652_set_interrupt_interval(rme9652_t *s,
429 unsigned int frames)
430{
431 int restart = 0;
432 int n;
433
434 spin_lock_irq(&s->lock);
435
436 if ((restart = s->running)) {
437 rme9652_stop(s);
438 }
439
440 frames >>= 7;
441 n = 0;
442 while (frames) {
443 n++;
444 frames >>= 1;
445 }
446
447 s->control_register &= ~RME9652_latency;
448 s->control_register |= rme9652_encode_latency(n);
449
450 rme9652_write(s, RME9652_control_register, s->control_register);
451
452 rme9652_compute_period_size(s);
453
454 if (restart)
455 rme9652_start(s);
456
457 spin_unlock_irq(&s->lock);
458
459 return 0;
460}
461
462static int rme9652_set_rate(rme9652_t *rme9652, int rate)
463{
464 int restart;
465 int reject_if_open = 0;
466 int xrate;
467
468 /* Changing from a "single speed" to a "double speed" rate is
469 not allowed if any substreams are open. This is because
470 such a change causes a shift in the location of
471 the DMA buffers and a reduction in the number of available
472 buffers.
473
474 Note that a similar but essentially insoluble problem
475 exists for externally-driven rate changes. All we can do
476 is to flag rate changes in the read/write routines.
477 */
478
479 spin_lock_irq(&rme9652->lock);
480 xrate = rme9652_adat_sample_rate(rme9652);
481
482 switch (rate) {
483 case 44100:
484 if (xrate > 48000) {
485 reject_if_open = 1;
486 }
487 rate = 0;
488 break;
489 case 48000:
490 if (xrate > 48000) {
491 reject_if_open = 1;
492 }
493 rate = RME9652_freq;
494 break;
495 case 88200:
496 if (xrate < 48000) {
497 reject_if_open = 1;
498 }
499 rate = RME9652_DS;
500 break;
501 case 96000:
502 if (xrate < 48000) {
503 reject_if_open = 1;
504 }
505 rate = RME9652_DS | RME9652_freq;
506 break;
507 default:
508 return -EINVAL;
509 }
510
511 if (reject_if_open &&
512 (rme9652->capture_pid >= 0 || rme9652->playback_pid >= 0)) {
513 spin_unlock_irq(&rme9652->lock);
514 return -EBUSY;
515 }
516
517 if ((restart = rme9652->running)) {
518 rme9652_stop(rme9652);
519 }
520
521 rme9652->control_register &= ~(RME9652_freq | RME9652_DS);
522 rme9652->control_register |= rate;
523 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
524
525 if (restart) {
526 rme9652_start(rme9652);
527 }
528
529 if (rate & RME9652_DS) {
530 if (rme9652->ss_channels == RME9652_NCHANNELS) {
531 rme9652->channel_map = channel_map_9652_ds;
532 } else {
533 rme9652->channel_map = channel_map_9636_ds;
534 }
535 } else {
536 if (rme9652->ss_channels == RME9652_NCHANNELS) {
537 rme9652->channel_map = channel_map_9652_ss;
538 } else {
539 rme9652->channel_map = channel_map_9636_ss;
540 }
541 }
542
543 spin_unlock_irq(&rme9652->lock);
544 return 0;
545}
546
547static void rme9652_set_thru(rme9652_t *rme9652, int channel, int enable)
548{
549 int i;
550
551 rme9652->passthru = 0;
552
553 if (channel < 0) {
554
555 /* set thru for all channels */
556
557 if (enable) {
558 for (i = 0; i < RME9652_NCHANNELS; i++) {
559 rme9652->thru_bits |= (1 << i);
560 rme9652_write(rme9652, RME9652_thru_base + i * 4, 1);
561 }
562 } else {
563 for (i = 0; i < RME9652_NCHANNELS; i++) {
564 rme9652->thru_bits &= ~(1 << i);
565 rme9652_write(rme9652, RME9652_thru_base + i * 4, 0);
566 }
567 }
568
569 } else {
570 int mapped_channel;
571
572 snd_assert(channel == RME9652_NCHANNELS, return);
573 mapped_channel = rme9652->channel_map[channel];
574
575 if (enable) {
576 rme9652->thru_bits |= (1 << mapped_channel);
577 } else {
578 rme9652->thru_bits &= ~(1 << mapped_channel);
579 }
580
581 rme9652_write(rme9652,
582 RME9652_thru_base + mapped_channel * 4,
583 enable ? 1 : 0);
584 }
585}
586
587static int rme9652_set_passthru(rme9652_t *rme9652, int onoff)
588{
589 if (onoff) {
590 rme9652_set_thru(rme9652, -1, 1);
591
592 /* we don't want interrupts, so do a
593 custom version of rme9652_start().
594 */
595
596 rme9652->control_register =
597 RME9652_inp_0 |
598 rme9652_encode_latency(7) |
599 RME9652_start_bit;
600
601 rme9652_reset_hw_pointer(rme9652);
602
603 rme9652_write(rme9652, RME9652_control_register,
604 rme9652->control_register);
605 rme9652->passthru = 1;
606 } else {
607 rme9652_set_thru(rme9652, -1, 0);
608 rme9652_stop(rme9652);
609 rme9652->passthru = 0;
610 }
611
612 return 0;
613}
614
615static void rme9652_spdif_set_bit (rme9652_t *rme9652, int mask, int onoff)
616{
617 if (onoff)
618 rme9652->control_register |= mask;
619 else
620 rme9652->control_register &= ~mask;
621
622 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
623}
624
625static void rme9652_spdif_write_byte (rme9652_t *rme9652, const int val)
626{
627 long mask;
628 long i;
629
630 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
631 if (val & mask)
632 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 1);
633 else
634 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 0);
635
636 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
637 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
638 }
639}
640
641static int rme9652_spdif_read_byte (rme9652_t *rme9652)
642{
643 long mask;
644 long val;
645 long i;
646
647 val = 0;
648
649 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
650 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);
651 if (rme9652_read (rme9652, RME9652_status_register) & RME9652_SPDIF_READ)
652 val |= mask;
653 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);
654 }
655
656 return val;
657}
658
659static void rme9652_write_spdif_codec (rme9652_t *rme9652, const int address, const int data)
660{
661 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
662 rme9652_spdif_write_byte (rme9652, 0x20);
663 rme9652_spdif_write_byte (rme9652, address);
664 rme9652_spdif_write_byte (rme9652, data);
665 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
666}
667
668
669static int rme9652_spdif_read_codec (rme9652_t *rme9652, const int address)
670{
671 int ret;
672
673 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
674 rme9652_spdif_write_byte (rme9652, 0x20);
675 rme9652_spdif_write_byte (rme9652, address);
676 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
677 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);
678
679 rme9652_spdif_write_byte (rme9652, 0x21);
680 ret = rme9652_spdif_read_byte (rme9652);
681 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);
682
683 return ret;
684}
685
686static void rme9652_initialize_spdif_receiver (rme9652_t *rme9652)
687{
688 /* XXX what unsets this ? */
689
690 rme9652->control_register |= RME9652_SPDIF_RESET;
691
692 rme9652_write_spdif_codec (rme9652, 4, 0x40);
693 rme9652_write_spdif_codec (rme9652, 17, 0x13);
694 rme9652_write_spdif_codec (rme9652, 6, 0x02);
695}
696
697static inline int rme9652_spdif_sample_rate(rme9652_t *s)
698{
699 unsigned int rate_bits;
700
701 if (rme9652_read(s, RME9652_status_register) & RME9652_ERF) {
702 return -1; /* error condition */
703 }
704
705 if (s->hw_rev == 15) {
706
707 int x, y, ret;
708
709 x = rme9652_spdif_read_codec (s, 30);
710
711 if (x != 0)
712 y = 48000 * 64 / x;
713 else
714 y = 0;
715
716 if (y > 30400 && y < 33600) ret = 32000;
717 else if (y > 41900 && y < 46000) ret = 44100;
718 else if (y > 46000 && y < 50400) ret = 48000;
719 else if (y > 60800 && y < 67200) ret = 64000;
720 else if (y > 83700 && y < 92000) ret = 88200;
721 else if (y > 92000 && y < 100000) ret = 96000;
722 else ret = 0;
723 return ret;
724 }
725
726 rate_bits = rme9652_read(s, RME9652_status_register) & RME9652_F;
727
728 switch (rme9652_decode_spdif_rate(rate_bits)) {
729 case 0x7:
730 return 32000;
731 break;
732
733 case 0x6:
734 return 44100;
735 break;
736
737 case 0x5:
738 return 48000;
739 break;
740
741 case 0x4:
742 return 88200;
743 break;
744
745 case 0x3:
746 return 96000;
747 break;
748
749 case 0x0:
750 return 64000;
751 break;
752
753 default:
754 snd_printk("%s: unknown S/PDIF input rate (bits = 0x%x)\n",
755 s->card_name, rate_bits);
756 return 0;
757 break;
758 }
759}
760
761/*-----------------------------------------------------------------------------
762 Control Interface
763 ----------------------------------------------------------------------------*/
764
765static u32 snd_rme9652_convert_from_aes(snd_aes_iec958_t *aes)
766{
767 u32 val = 0;
768 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME9652_PRO : 0;
769 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME9652_Dolby : 0;
770 if (val & RME9652_PRO)
771 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME9652_EMP : 0;
772 else
773 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME9652_EMP : 0;
774 return val;
775}
776
777static void snd_rme9652_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
778{
779 aes->status[0] = ((val & RME9652_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
780 ((val & RME9652_Dolby) ? IEC958_AES0_NONAUDIO : 0);
781 if (val & RME9652_PRO)
782 aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
783 else
784 aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
785}
786
787static int snd_rme9652_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
788{
789 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
790 uinfo->count = 1;
791 return 0;
792}
793
794static int snd_rme9652_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
795{
796 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
797
798 snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif);
799 return 0;
800}
801
802static int snd_rme9652_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
803{
804 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
805 unsigned long flags;
806 int change;
807 u32 val;
808
809 val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
810 spin_lock_irqsave(&rme9652->lock, flags);
811 change = val != rme9652->creg_spdif;
812 rme9652->creg_spdif = val;
813 spin_unlock_irqrestore(&rme9652->lock, flags);
814 return change;
815}
816
817static int snd_rme9652_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
818{
819 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
820 uinfo->count = 1;
821 return 0;
822}
823
824static int snd_rme9652_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
825{
826 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
827
828 snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif_stream);
829 return 0;
830}
831
832static int snd_rme9652_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
833{
834 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
835 unsigned long flags;
836 int change;
837 u32 val;
838
839 val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);
840 spin_lock_irqsave(&rme9652->lock, flags);
841 change = val != rme9652->creg_spdif_stream;
842 rme9652->creg_spdif_stream = val;
843 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
844 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= val);
845 spin_unlock_irqrestore(&rme9652->lock, flags);
846 return change;
847}
848
849static int snd_rme9652_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
850{
851 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
852 uinfo->count = 1;
853 return 0;
854}
855
856static int snd_rme9652_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
857{
858 ucontrol->value.iec958.status[0] = kcontrol->private_value;
859 return 0;
860}
861
862#ifdef TARGET_OS2
863#define RME9652_ADAT1_IN(xname, xindex) \
864{ SNDRV_CTL_ELEM_IFACE_PCM, 0, 0, xname, xindex, \
865 0, 0, snd_rme9652_info_adat1_in, \
866 snd_rme9652_get_adat1_in, \
867 snd_rme9652_put_adat1_in,0 }
868#else
869#define RME9652_ADAT1_IN(xname, xindex) \
870{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
871 info: snd_rme9652_info_adat1_in, \
872 get: snd_rme9652_get_adat1_in, \
873 put: snd_rme9652_put_adat1_in }
874#endif
875
876static unsigned int rme9652_adat1_in(rme9652_t *rme9652)
877{
878 if (rme9652->control_register & RME9652_ADAT1_INTERNAL)
879 return 1;
880 return 0;
881}
882
883static int rme9652_set_adat1_input(rme9652_t *rme9652, int internal)
884{
885 int restart = 0;
886
887 if (internal) {
888 rme9652->control_register |= RME9652_ADAT1_INTERNAL;
889 } else {
890 rme9652->control_register &= ~RME9652_ADAT1_INTERNAL;
891 }
892
893 /* XXX do we actually need to stop the card when we do this ? */
894
895 if ((restart = rme9652->running)) {
896 rme9652_stop(rme9652);
897 }
898
899 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
900
901 if (restart) {
902 rme9652_start(rme9652);
903 }
904
905 return 0;
906}
907
908static int snd_rme9652_info_adat1_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
909{
910 static char *texts[2] = {"ADAT1", "Internal"};
911
912 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
913 uinfo->count = 1;
914 uinfo->value.enumerated.items = 2;
915 if (uinfo->value.enumerated.item > 1)
916 uinfo->value.enumerated.item = 1;
917 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
918 return 0;
919}
920
921static int snd_rme9652_get_adat1_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
922{
923 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
924 unsigned long flags;
925
926 spin_lock_irqsave(&rme9652->lock, flags);
927 ucontrol->value.enumerated.item[0] = rme9652_adat1_in(rme9652);
928 spin_unlock_irqrestore(&rme9652->lock, flags);
929 return 0;
930}
931
932static int snd_rme9652_put_adat1_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
933{
934 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
935 unsigned long flags;
936 int change;
937 unsigned int val;
938
939 if (!snd_rme9652_use_is_exclusive(rme9652))
940 return -EBUSY;
941 val = ucontrol->value.enumerated.item[0] % 2;
942 spin_lock_irqsave(&rme9652->lock, flags);
943 change = val != rme9652_adat1_in(rme9652);
944 if (change)
945 rme9652_set_adat1_input(rme9652, val);
946 spin_unlock_irqrestore(&rme9652->lock, flags);
947 return change;
948}
949
950#ifdef TARGET_OS2
951#define RME9652_SPDIF_IN(xname, xindex) \
952{ SNDRV_CTL_ELEM_IFACE_PCM, 0, 0, xname, xindex, \
953 0, 0, snd_rme9652_info_spdif_in, \
954 snd_rme9652_get_spdif_in, snd_rme9652_put_spdif_in,0 }
955#else
956#define RME9652_SPDIF_IN(xname, xindex) \
957{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
958 info: snd_rme9652_info_spdif_in, \
959 get: snd_rme9652_get_spdif_in, put: snd_rme9652_put_spdif_in }
960#endif
961
962static unsigned int rme9652_spdif_in(rme9652_t *rme9652)
963{
964 return rme9652_decode_spdif_in(rme9652->control_register &
965 RME9652_inp);
966}
967
968static int rme9652_set_spdif_input(rme9652_t *rme9652, int in)
969{
970 int restart = 0;
971
972 rme9652->control_register &= ~RME9652_inp;
973 rme9652->control_register |= rme9652_encode_spdif_in(in);
974
975 if ((restart = rme9652->running)) {
976 rme9652_stop(rme9652);
977 }
978
979 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
980
981 if (restart) {
982 rme9652_start(rme9652);
983 }
984
985 return 0;
986}
987
988static int snd_rme9652_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
989{
990 static char *texts[3] = {"ADAT1", "Coaxial", "Internal"};
991
992 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
993 uinfo->count = 1;
994 uinfo->value.enumerated.items = 3;
995 if (uinfo->value.enumerated.item > 2)
996 uinfo->value.enumerated.item = 2;
997 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
998 return 0;
999}
1000
1001static int snd_rme9652_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1002{
1003 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1004 unsigned long flags;
1005
1006 spin_lock_irqsave(&rme9652->lock, flags);
1007 ucontrol->value.enumerated.item[0] = rme9652_spdif_in(rme9652);
1008 spin_unlock_irqrestore(&rme9652->lock, flags);
1009 return 0;
1010}
1011
1012static int snd_rme9652_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1013{
1014 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1015 unsigned long flags;
1016 int change;
1017 unsigned int val;
1018
1019 if (!snd_rme9652_use_is_exclusive(rme9652))
1020 return -EBUSY;
1021 val = ucontrol->value.enumerated.item[0] % 3;
1022 spin_lock_irqsave(&rme9652->lock, flags);
1023 change = val != rme9652_spdif_in(rme9652);
1024 if (change)
1025 rme9652_set_spdif_input(rme9652, val);
1026 spin_unlock_irqrestore(&rme9652->lock, flags);
1027 return change;
1028}
1029
1030#ifdef TARGET_OS2
1031#define RME9652_SPDIF_OUT(xname, xindex) \
1032{ SNDRV_CTL_ELEM_IFACE_PCM, 0, 0, xname, xindex, \
1033 0, 0, snd_rme9652_info_spdif_out, \
1034 snd_rme9652_get_spdif_out, snd_rme9652_put_spdif_out, 0 }
1035#else
1036#define RME9652_SPDIF_OUT(xname, xindex) \
1037{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
1038 info: snd_rme9652_info_spdif_out, \
1039 get: snd_rme9652_get_spdif_out, put: snd_rme9652_put_spdif_out }
1040#endif
1041
1042static int rme9652_spdif_out(rme9652_t *rme9652)
1043{
1044 return (rme9652->control_register & RME9652_opt_out) ? 1 : 0;
1045}
1046
1047static int rme9652_set_spdif_output(rme9652_t *rme9652, int out)
1048{
1049 int restart = 0;
1050
1051 if (out) {
1052 rme9652->control_register |= RME9652_opt_out;
1053 } else {
1054 rme9652->control_register &= ~RME9652_opt_out;
1055 }
1056
1057 if ((restart = rme9652->running)) {
1058 rme9652_stop(rme9652);
1059 }
1060
1061 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1062
1063 if (restart) {
1064 rme9652_start(rme9652);
1065 }
1066
1067 return 0;
1068}
1069
1070static int snd_rme9652_info_spdif_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1071{
1072 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1073 uinfo->count = 1;
1074 uinfo->value.integer.min = 0;
1075 uinfo->value.integer.max = 1;
1076 return 0;
1077}
1078
1079static int snd_rme9652_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1080{
1081 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1082 unsigned long flags;
1083
1084 spin_lock_irqsave(&rme9652->lock, flags);
1085 ucontrol->value.integer.value[0] = rme9652_spdif_out(rme9652);
1086 spin_unlock_irqrestore(&rme9652->lock, flags);
1087 return 0;
1088}
1089
1090static int snd_rme9652_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1091{
1092 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1093 unsigned long flags;
1094 int change;
1095 unsigned int val;
1096
1097 if (!snd_rme9652_use_is_exclusive(rme9652))
1098 return -EBUSY;
1099 val = ucontrol->value.integer.value[0] & 1;
1100 spin_lock_irqsave(&rme9652->lock, flags);
1101 change = val != rme9652_spdif_out(rme9652);
1102 rme9652_set_spdif_output(rme9652, val);
1103 spin_unlock_irqrestore(&rme9652->lock, flags);
1104 return change;
1105}
1106
1107#ifdef TARGET_OS2
1108#define RME9652_SYNC_MODE(xname, xindex) \
1109{ SNDRV_CTL_ELEM_IFACE_PCM, 0, 0, xname, xindex, \
1110 0, 0, snd_rme9652_info_sync_mode, \
1111 snd_rme9652_get_sync_mode, snd_rme9652_put_sync_mode,0 }
1112#else
1113#define RME9652_SYNC_MODE(xname, xindex) \
1114{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
1115 info: snd_rme9652_info_sync_mode, \
1116 get: snd_rme9652_get_sync_mode, put: snd_rme9652_put_sync_mode }
1117#endif
1118
1119static int rme9652_sync_mode(rme9652_t *rme9652)
1120{
1121 if (rme9652->control_register & RME9652_wsel) {
1122 return 2;
1123 } else if (rme9652->control_register & RME9652_Master) {
1124 return 1;
1125 } else {
1126 return 0;
1127 }
1128}
1129
1130static int rme9652_set_sync_mode(rme9652_t *rme9652, int mode)
1131{
1132 int restart = 0;
1133
1134 switch (mode) {
1135 case 0:
1136 rme9652->control_register &=
1137 ~(RME9652_Master | RME9652_wsel);
1138 break;
1139 case 1:
1140 rme9652->control_register =
1141 (rme9652->control_register & ~RME9652_wsel) | RME9652_Master;
1142 break;
1143 case 2:
1144 rme9652->control_register |=
1145 (RME9652_Master | RME9652_wsel);
1146 break;
1147 }
1148
1149 if ((restart = rme9652->running)) {
1150 rme9652_stop(rme9652);
1151 }
1152
1153 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1154
1155 if (restart) {
1156 rme9652_start(rme9652);
1157 }
1158
1159 return 0;
1160}
1161
1162static int snd_rme9652_info_sync_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1163{
1164 static char *texts[3] = {"AutoSync", "Master", "Word Clock"};
1165
1166 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1167 uinfo->count = 1;
1168 uinfo->value.enumerated.items = 3;
1169 if (uinfo->value.enumerated.item > 2)
1170 uinfo->value.enumerated.item = 2;
1171 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1172 return 0;
1173}
1174
1175static int snd_rme9652_get_sync_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1176{
1177 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1178 unsigned long flags;
1179
1180 spin_lock_irqsave(&rme9652->lock, flags);
1181 ucontrol->value.enumerated.item[0] = rme9652_sync_mode(rme9652);
1182 spin_unlock_irqrestore(&rme9652->lock, flags);
1183 return 0;
1184}
1185
1186static int snd_rme9652_put_sync_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1187{
1188 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1189 unsigned long flags;
1190 int change;
1191 unsigned int val;
1192
1193 val = ucontrol->value.enumerated.item[0] % 3;
1194 spin_lock_irqsave(&rme9652->lock, flags);
1195 change = val != rme9652_sync_mode(rme9652);
1196 rme9652_set_sync_mode(rme9652, val);
1197 spin_unlock_irqrestore(&rme9652->lock, flags);
1198 return change;
1199}
1200
1201#ifdef TARGET_OS2
1202#define RME9652_SYNC_PREF(xname, xindex) \
1203{ SNDRV_CTL_ELEM_IFACE_PCM, 0, 0, xname, xindex, \
1204 0, 0, snd_rme9652_info_sync_pref, \
1205 snd_rme9652_get_sync_pref, snd_rme9652_put_sync_pref, 0 }
1206#else
1207#define RME9652_SYNC_PREF(xname, xindex) \
1208{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
1209 info: snd_rme9652_info_sync_pref, \
1210 get: snd_rme9652_get_sync_pref, put: snd_rme9652_put_sync_pref }
1211#endif
1212
1213static int rme9652_sync_pref(rme9652_t *rme9652)
1214{
1215 switch (rme9652->control_register & RME9652_SyncPref_Mask) {
1216 case RME9652_SyncPref_ADAT1:
1217 return RME9652_SYNC_FROM_ADAT1;
1218 case RME9652_SyncPref_ADAT2:
1219 return RME9652_SYNC_FROM_ADAT2;
1220 case RME9652_SyncPref_ADAT3:
1221 return RME9652_SYNC_FROM_ADAT3;
1222 case RME9652_SyncPref_SPDIF:
1223 return RME9652_SYNC_FROM_SPDIF;
1224 }
1225 /* Not reachable */
1226 return 0;
1227}
1228
1229static int rme9652_set_sync_pref(rme9652_t *rme9652, int pref)
1230{
1231 int restart;
1232
1233 rme9652->control_register &= ~RME9652_SyncPref_Mask;
1234 switch (pref) {
1235 case RME9652_SYNC_FROM_ADAT1:
1236 rme9652->control_register |= RME9652_SyncPref_ADAT1;
1237 break;
1238 case RME9652_SYNC_FROM_ADAT2:
1239 rme9652->control_register |= RME9652_SyncPref_ADAT2;
1240 break;
1241 case RME9652_SYNC_FROM_ADAT3:
1242 rme9652->control_register |= RME9652_SyncPref_ADAT3;
1243 break;
1244 case RME9652_SYNC_FROM_SPDIF:
1245 rme9652->control_register |= RME9652_SyncPref_SPDIF;
1246 break;
1247 }
1248
1249 if ((restart = rme9652->running)) {
1250 rme9652_stop(rme9652);
1251 }
1252
1253 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
1254
1255 if (restart) {
1256 rme9652_start(rme9652);
1257 }
1258
1259 return 0;
1260}
1261
1262static int snd_rme9652_info_sync_pref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1263{
1264 static char *texts[4] = {"IEC958 In", "ADAT1 In", "ADAT2 In", "ADAT3 In"};
1265 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1266
1267 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1268 uinfo->count = 1;
1269 uinfo->value.enumerated.items = rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3;
1270 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1271 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1272 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1273 return 0;
1274}
1275
1276static int snd_rme9652_get_sync_pref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1277{
1278 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1279 unsigned long flags;
1280
1281 spin_lock_irqsave(&rme9652->lock, flags);
1282 ucontrol->value.enumerated.item[0] = rme9652_sync_pref(rme9652);
1283 spin_unlock_irqrestore(&rme9652->lock, flags);
1284 return 0;
1285}
1286
1287static int snd_rme9652_put_sync_pref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1288{
1289 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1290 unsigned long flags;
1291 int change, max;
1292 unsigned int val;
1293
1294 if (!snd_rme9652_use_is_exclusive(rme9652))
1295 return -EBUSY;
1296 max = rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3;
1297 val = ucontrol->value.enumerated.item[0] % max;
1298 spin_lock_irqsave(&rme9652->lock, flags);
1299 change = val != rme9652_sync_pref(rme9652);
1300 rme9652_set_sync_pref(rme9652, val);
1301 spin_unlock_irqrestore(&rme9652->lock, flags);
1302 return change;
1303}
1304
1305static int snd_rme9652_info_thru(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1306{
1307 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1308 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1309 uinfo->count = rme9652->ss_channels;
1310 uinfo->value.integer.min = 0;
1311 uinfo->value.integer.max = 1;
1312 return 0;
1313}
1314
1315static int snd_rme9652_get_thru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1316{
1317 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1318 unsigned int k;
1319 u32 thru_bits = rme9652->thru_bits;
1320
1321 for (k = 0; k < rme9652->ss_channels; ++k) {
1322 ucontrol->value.integer.value[k] = !!(thru_bits & (1 << k));
1323 }
1324 return 0;
1325}
1326
1327static int snd_rme9652_put_thru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1328{
1329 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1330 unsigned long flags;
1331 int change;
1332 unsigned int chn;
1333 u32 thru_bits = 0;
1334
1335 if (!snd_rme9652_use_is_exclusive(rme9652))
1336 return -EBUSY;
1337
1338 for (chn = 0; chn < rme9652->ss_channels; ++chn) {
1339 if (ucontrol->value.integer.value[chn])
1340 thru_bits |= 1 << chn;
1341 }
1342
1343 spin_lock_irqsave(&rme9652->lock, flags);
1344 change = thru_bits ^ rme9652->thru_bits;
1345 if (change) {
1346 for (chn = 0; chn < rme9652->ss_channels; ++chn) {
1347 if (!(change & (1 << chn)))
1348 continue;
1349 rme9652_set_thru(rme9652,chn,thru_bits&(1<<chn));
1350 }
1351 }
1352 spin_unlock_irqrestore(&rme9652->lock, flags);
1353 return !!change;
1354}
1355
1356#ifdef TARGET_OS2
1357#define RME9652_PASSTHRU(xname, xindex) \
1358{ SNDRV_CTL_ELEM_IFACE_PCM, 0, 0, xname, xindex, \
1359 0, 0, snd_rme9652_info_passthru, \
1360 snd_rme9652_put_passthru, \
1361 snd_rme9652_get_passthru,0 }
1362#else
1363#define RME9652_PASSTHRU(xname, xindex) \
1364{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
1365 info: snd_rme9652_info_passthru, \
1366 put: snd_rme9652_put_passthru, \
1367 get: snd_rme9652_get_passthru }
1368#endif
1369
1370static int snd_rme9652_info_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo)
1371{
1372 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1373 uinfo->count = 1;
1374 uinfo->value.integer.min = 0;
1375 uinfo->value.integer.max = 1;
1376 return 0;
1377}
1378
1379static int snd_rme9652_get_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1380{
1381 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1382 unsigned long flags;
1383
1384 spin_lock_irqsave(&rme9652->lock, flags);
1385 ucontrol->value.integer.value[0] = rme9652->passthru;
1386 spin_unlock_irqrestore(&rme9652->lock, flags);
1387 return 0;
1388}
1389
1390static int snd_rme9652_put_passthru(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1391{
1392 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1393 unsigned long flags;
1394 int change;
1395 unsigned int val;
1396 int err = 0;
1397
1398 if (!snd_rme9652_use_is_exclusive(rme9652))
1399 return -EBUSY;
1400
1401 val = ucontrol->value.integer.value[0] & 1;
1402 spin_lock_irqsave(&rme9652->lock, flags);
1403 change = (ucontrol->value.integer.value[0] != rme9652->passthru);
1404 if (change)
1405 err = rme9652_set_passthru(rme9652, val);
1406 spin_unlock_irqrestore(&rme9652->lock, flags);
1407 return err ? err : change;
1408}
1409
1410/* Read-only switches */
1411
1412#ifdef TARGET_OS2
1413#define RME9652_SPDIF_RATE(xname, xindex) \
1414{ SNDRV_CTL_ELEM_IFACE_PCM, 0,0, xname, xindex, \
1415 SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1416 0, snd_rme9652_info_spdif_rate, \
1417 snd_rme9652_get_spdif_rate, 0,0 }
1418#else
1419#define RME9652_SPDIF_RATE(xname, xindex) \
1420{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
1421 access: SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1422 info: snd_rme9652_info_spdif_rate, \
1423 get: snd_rme9652_get_spdif_rate }
1424#endif
1425
1426static int snd_rme9652_info_spdif_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1427{
1428 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1429 uinfo->count = 1;
1430 uinfo->value.integer.min = 0;
1431 uinfo->value.integer.max = 96000;
1432 return 0;
1433}
1434
1435static int snd_rme9652_get_spdif_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1436{
1437 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1438 unsigned long flags;
1439
1440 spin_lock_irqsave(&rme9652->lock, flags);
1441 ucontrol->value.integer.value[0] = rme9652_spdif_sample_rate(rme9652);
1442 spin_unlock_irqrestore(&rme9652->lock, flags);
1443 return 0;
1444}
1445
1446#ifdef TARGET_OS2
1447#define RME9652_ADAT_SYNC(xname, xindex, xidx) \
1448{ SNDRV_CTL_ELEM_IFACE_PCM, 0, 0, xname, xindex, \
1449 SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1450 0, snd_rme9652_info_adat_sync, \
1451 snd_rme9652_get_adat_sync, 0, xidx }
1452#else
1453#define RME9652_ADAT_SYNC(xname, xindex, xidx) \
1454{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
1455 access: SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1456 info: snd_rme9652_info_adat_sync, \
1457 get: snd_rme9652_get_adat_sync, private_value: xidx }
1458#endif
1459
1460static int snd_rme9652_info_adat_sync(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1461{
1462 static char *texts[4] = {"No Lock", "Lock", "No Lock Sync", "Lock Sync"};
1463
1464 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1465 uinfo->count = 1;
1466 uinfo->value.enumerated.items = 4;
1467 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1468 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1469 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1470 return 0;
1471}
1472
1473static int snd_rme9652_get_adat_sync(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1474{
1475 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1476 unsigned int mask1, mask2, val;
1477
1478 switch (kcontrol->private_value) {
1479 case 0: mask1 = RME9652_lock_0; mask2 = RME9652_sync_0; break;
1480 case 1: mask1 = RME9652_lock_1; mask2 = RME9652_sync_1; break;
1481 case 2: mask1 = RME9652_lock_2; mask2 = RME9652_sync_2; break;
1482 default: return -EINVAL;
1483 }
1484 val = rme9652_read(rme9652, RME9652_status_register);
1485 ucontrol->value.enumerated.item[0] = (val & mask1) ? 1 : 0;
1486 ucontrol->value.enumerated.item[0] |= (val & mask2) ? 2 : 0;
1487 return 0;
1488}
1489
1490#ifdef TARGET_OS2
1491#define RME9652_TC_VALID(xname, xindex) \
1492{ SNDRV_CTL_ELEM_IFACE_PCM, 0,0, xname, xindex, \
1493 SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1494 0, snd_rme9652_info_tc_valid, \
1495 snd_rme9652_get_tc_valid,0,0 }
1496#else
1497#define RME9652_TC_VALID(xname, xindex) \
1498{ iface: SNDRV_CTL_ELEM_IFACE_PCM, name: xname, index: xindex, \
1499 access: SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1500 info: snd_rme9652_info_tc_valid, \
1501 get: snd_rme9652_get_tc_valid }
1502#endif
1503
1504static int snd_rme9652_info_tc_valid(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1505{
1506 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1507 uinfo->count = 1;
1508 uinfo->value.integer.min = 0;
1509 uinfo->value.integer.max = 1;
1510 return 0;
1511}
1512
1513static int snd_rme9652_get_tc_valid(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1514{
1515 rme9652_t *rme9652 = _snd_kcontrol_chip(kcontrol);
1516
1517 ucontrol->value.integer.value[0] =
1518 (rme9652_read(rme9652, RME9652_status_register) & RME9652_tc_valid) ? 1 : 0;
1519 return 0;
1520}
1521
1522#if ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE
1523
1524/* FIXME: this routine needs a port to the new control API --jk */
1525
1526static int snd_rme9652_get_tc_value(void *private_data,
1527 snd_kswitch_t *kswitch,
1528 snd_switch_t *uswitch)
1529{
1530 rme9652_t *s = (rme9652_t *) private_data;
1531 u32 value;
1532 int i;
1533
1534 uswitch->type = SNDRV_SW_TYPE_DWORD;
1535
1536 if ((rme9652_read(s, RME9652_status_register) &
1537 RME9652_tc_valid) == 0) {
1538 uswitch->value.data32[0] = 0;
1539 return 0;
1540 }
1541
1542 /* timecode request */
1543
1544 rme9652_write(s, RME9652_time_code, 0);
1545
1546 /* XXX bug alert: loop-based timing !!!! */
1547
1548 for (i = 0; i < 50; i++) {
1549 if (!(rme9652_read(s, i * 4) & RME9652_tc_busy))
1550 break;
1551 }
1552
1553 if (!(rme9652_read(s, i * 4) & RME9652_tc_busy)) {
1554 return -EIO;
1555 }
1556
1557 value = 0;
1558
1559 for (i = 0; i < 32; i++) {
1560 value >>= 1;
1561
1562 if (rme9652_read(s, i * 4) & RME9652_tc_out)
1563 value |= 0x80000000;
1564 }
1565
1566 if (value > 2 * 60 * 48000) {
1567 value -= 2 * 60 * 48000;
1568 } else {
1569 value = 0;
1570 }
1571
1572 uswitch->value.data32[0] = value;
1573
1574 return 0;
1575}
1576
1577#endif /* ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE */
1578
1579#define RME9652_CONTROLS (sizeof(snd_rme9652_controls)/sizeof(snd_kcontrol_new_t))
1580
1581static snd_kcontrol_new_t snd_rme9652_controls[] = {
1582#ifdef TARGET_OS2
1583{
1584 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
1585 SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),0,0,0,
1586 snd_rme9652_control_spdif_info,
1587 snd_rme9652_control_spdif_get,
1588 snd_rme9652_control_spdif_put,0
1589},
1590{
1591 SNDRV_CTL_ELEM_IFACE_PCM,0, 0,
1592 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),0,
1593 SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,0,
1594 snd_rme9652_control_spdif_stream_info,
1595 snd_rme9652_control_spdif_stream_get,
1596 snd_rme9652_control_spdif_stream_put,0
1597},
1598{
1599 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
1600 SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),0,
1601 SNDRV_CTL_ELEM_ACCESS_READ,0,
1602 snd_rme9652_control_spdif_mask_info,
1603 snd_rme9652_control_spdif_mask_get,0,
1604 IEC958_AES0_NONAUDIO |
1605 IEC958_AES0_PROFESSIONAL |
1606 IEC958_AES0_CON_EMPHASIS
1607},
1608{
1609 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
1610 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),0,
1611 SNDRV_CTL_ELEM_ACCESS_READ,0,
1612 snd_rme9652_control_spdif_mask_info,
1613 snd_rme9652_control_spdif_mask_get,0,
1614 IEC958_AES0_NONAUDIO |
1615 IEC958_AES0_PROFESSIONAL |
1616 IEC958_AES0_PRO_EMPHASIS
1617},
1618#else
1619{
1620 iface: SNDRV_CTL_ELEM_IFACE_PCM,
1621 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1622 info: snd_rme9652_control_spdif_info,
1623 get: snd_rme9652_control_spdif_get,
1624 put: snd_rme9652_control_spdif_put,
1625},
1626{
1627 access: SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1628 iface: SNDRV_CTL_ELEM_IFACE_PCM,
1629 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1630 info: snd_rme9652_control_spdif_stream_info,
1631 get: snd_rme9652_control_spdif_stream_get,
1632 put: snd_rme9652_control_spdif_stream_put,
1633},
1634{
1635 access: SNDRV_CTL_ELEM_ACCESS_READ,
1636 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
1637 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1638 info: snd_rme9652_control_spdif_mask_info,
1639 get: snd_rme9652_control_spdif_mask_get,
1640 private_value: IEC958_AES0_NONAUDIO |
1641 IEC958_AES0_PROFESSIONAL |
1642 IEC958_AES0_CON_EMPHASIS,
1643},
1644{
1645 access: SNDRV_CTL_ELEM_ACCESS_READ,
1646 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
1647 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
1648 info: snd_rme9652_control_spdif_mask_info,
1649 get: snd_rme9652_control_spdif_mask_get,
1650 private_value: IEC958_AES0_NONAUDIO |
1651 IEC958_AES0_PROFESSIONAL |
1652 IEC958_AES0_PRO_EMPHASIS,
1653},
1654#endif
1655RME9652_SPDIF_IN("IEC958 Input Connector", 0),
1656RME9652_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
1657RME9652_SYNC_MODE("Sync Mode", 0),
1658RME9652_SYNC_PREF("Preferred Sync Source", 0),
1659{
1660#ifdef TARGET_OS2
1661 SNDRV_CTL_ELEM_IFACE_PCM,0, 0,
1662 "Channels Thru",
1663 0,0,0,
1664 snd_rme9652_info_thru,
1665 snd_rme9652_get_thru,
1666 snd_rme9652_put_thru,0
1667#else
1668 iface: SNDRV_CTL_ELEM_IFACE_PCM,
1669 name: "Channels Thru",
1670 index: 0,
1671 info: snd_rme9652_info_thru,
1672 get: snd_rme9652_get_thru,
1673 put: snd_rme9652_put_thru,
1674#endif
1675},
1676RME9652_SPDIF_RATE("IEC958 Sample Rate", 0),
1677RME9652_ADAT_SYNC("ADAT1 Sync Check", 0, 0),
1678RME9652_ADAT_SYNC("ADAT2 Sync Check", 0, 1),
1679RME9652_ADAT_SYNC("ADAT3 Sync Check", 0, 2),
1680RME9652_TC_VALID("Timecode Valid", 0),
1681RME9652_PASSTHRU("Passthru", 0)
1682};
1683
1684static snd_kcontrol_new_t snd_rme9652_adat3_check =
1685RME9652_ADAT_SYNC("ADAT3 Sync Check", 0, 2);
1686
1687static snd_kcontrol_new_t snd_rme9652_adat1_input =
1688RME9652_ADAT1_IN("ADAT1 Input Source", 0);
1689
1690int snd_rme9652_create_controls(snd_card_t *card, rme9652_t *rme9652)
1691{
1692 int idx, err;
1693 snd_kcontrol_t *kctl;
1694
1695 for (idx = 0; idx < RME9652_CONTROLS; idx++) {
1696 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_controls[idx], rme9652))) < 0)
1697 return err;
1698 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1699 rme9652->spdif_ctl = kctl;
1700 }
1701
1702 if (rme9652->ss_channels == RME9652_NCHANNELS)
1703 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_adat3_check, rme9652))) < 0)
1704 return err;
1705
1706 if (rme9652->hw_rev >= 15)
1707 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme9652_adat1_input, rme9652))) < 0)
1708 return err;
1709
1710 return 0;
1711}
1712
1713/*------------------------------------------------------------
1714 /proc interface
1715 ------------------------------------------------------------*/
1716
1717static void
1718snd_rme9652_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1719{
1720 rme9652_t *rme9652 = (rme9652_t *) entry->private_data;
1721 u32 thru_bits = rme9652->thru_bits;
1722 int show_auto_sync_source = 0;
1723 int i;
1724 unsigned int status;
1725 int x;
1726
1727 status = rme9652_read(rme9652, RME9652_status_register);
1728
1729 snd_iprintf(buffer, "%s (Card #%d)\n", rme9652->card_name, rme9652->card->number + 1);
1730 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
1731 rme9652->capture_buffer, rme9652->playback_buffer);
1732 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
1733 rme9652->irq, rme9652->port, rme9652->iobase);
1734
1735 snd_iprintf(buffer, "\n");
1736
1737 x = 1 << (6 + rme9652_decode_latency(rme9652->control_register &
1738 RME9652_latency));
1739
1740 snd_iprintf(buffer, "Latency: %d samples (2 periods of %lu bytes)\n",
1741 x, (unsigned long) rme9652->period_bytes);
1742 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n",
1743 rme9652_hw_pointer(rme9652));
1744 snd_iprintf(buffer, "Passthru: %s\n",
1745 rme9652->passthru ? "yes" : "no");
1746
1747 if ((rme9652->control_register & (RME9652_Master | RME9652_wsel)) == 0) {
1748 snd_iprintf(buffer, "Clock mode: autosync\n");
1749 show_auto_sync_source = 1;
1750 } else if (rme9652->control_register & RME9652_wsel) {
1751 if (status & RME9652_wsel_rd) {
1752 snd_iprintf(buffer, "Clock mode: word clock\n");
1753 } else {
1754 snd_iprintf(buffer, "Clock mode: word clock (no signal)\n");
1755 }
1756 } else {
1757 snd_iprintf(buffer, "Clock mode: master\n");
1758 }
1759
1760 if (show_auto_sync_source) {
1761 switch (rme9652->control_register & RME9652_SyncPref_Mask) {
1762 case RME9652_SyncPref_ADAT1:
1763 snd_iprintf(buffer, "Pref. sync source: ADAT1\n");
1764 break;
1765 case RME9652_SyncPref_ADAT2:
1766 snd_iprintf(buffer, "Pref. sync source: ADAT2\n");
1767 break;
1768 case RME9652_SyncPref_ADAT3:
1769 snd_iprintf(buffer, "Pref. sync source: ADAT3\n");
1770 break;
1771 case RME9652_SyncPref_SPDIF:
1772 snd_iprintf(buffer, "Pref. sync source: IEC958\n");
1773 break;
1774 default:
1775 snd_iprintf(buffer, "Pref. sync source: ???\n");
1776 }
1777 }
1778
1779 if (rme9652->hw_rev >= 15)
1780 snd_iprintf(buffer, "\nADAT1 Input source: %s\n",
1781 (rme9652->control_register & RME9652_ADAT1_INTERNAL) ?
1782 "Internal" : "ADAT1 optical");
1783
1784 snd_iprintf(buffer, "\n");
1785
1786 switch (rme9652_decode_spdif_in(rme9652->control_register &
1787 RME9652_inp)) {
1788 case RME9652_SPDIFIN_OPTICAL:
1789 snd_iprintf(buffer, "IEC958 input: ADAT1\n");
1790 break;
1791 case RME9652_SPDIFIN_COAXIAL:
1792 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
1793 break;
1794 case RME9652_SPDIFIN_INTERN:
1795 snd_iprintf(buffer, "IEC958 input: Internal\n");
1796 break;
1797 default:
1798 snd_iprintf(buffer, "IEC958 input: ???\n");
1799 break;
1800 }
1801
1802 if (rme9652->control_register & RME9652_opt_out) {
1803 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
1804 } else {
1805 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
1806 }
1807
1808 if (rme9652->control_register & RME9652_PRO) {
1809 snd_iprintf(buffer, "IEC958 quality: Professional\n");
1810 } else {
1811 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
1812 }
1813
1814 if (rme9652->control_register & RME9652_EMP) {
1815 snd_iprintf(buffer, "IEC958 emphasis: on\n");
1816 } else {
1817 snd_iprintf(buffer, "IEC958 emphasis: off\n");
1818 }
1819
1820 if (rme9652->control_register & RME9652_Dolby) {
1821 snd_iprintf(buffer, "IEC958 Dolby: on\n");
1822 } else {
1823 snd_iprintf(buffer, "IEC958 Dolby: off\n");
1824 }
1825
1826 i = rme9652_spdif_sample_rate(rme9652);
1827
1828 if (i < 0) {
1829 snd_iprintf(buffer,
1830 "IEC958 sample rate: error flag set\n");
1831 } else if (i == 0) {
1832 snd_iprintf(buffer, "IEC958 sample rate: undetermined\n");
1833 } else {
1834 snd_iprintf(buffer, "IEC958 sample rate: %d\n", i);
1835 }
1836
1837 snd_iprintf(buffer, "\n");
1838
1839 snd_iprintf(buffer, "ADAT Sample rate: %dHz\n",
1840 rme9652_adat_sample_rate(rme9652));
1841
1842 /* Sync Check */
1843
1844 x = status & RME9652_sync_0;
1845 if (status & RME9652_lock_0) {
1846 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
1847 } else {
1848 snd_iprintf(buffer, "ADAT1: No Lock\n");
1849 }
1850
1851 x = status & RME9652_sync_1;
1852 if (status & RME9652_lock_1) {
1853 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
1854 } else {
1855 snd_iprintf(buffer, "ADAT2: No Lock\n");
1856 }
1857
1858 x = status & RME9652_sync_2;
1859 if (status & RME9652_lock_2) {
1860 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
1861 } else {
1862 snd_iprintf(buffer, "ADAT3: No Lock\n");
1863 }
1864
1865 snd_iprintf(buffer, "\n");
1866
1867 snd_iprintf(buffer, "Timecode signal: %s\n",
1868 (status & RME9652_tc_valid) ? "yes" : "no");
1869
1870 /* thru modes */
1871
1872 snd_iprintf(buffer, "Punch Status:\n\n");
1873
1874 for (i = 0; i < rme9652->ss_channels; i++) {
1875 if (thru_bits & (1 << i)) {
1876 snd_iprintf(buffer, "%2d: on ", i + 1);
1877 } else {
1878 snd_iprintf(buffer, "%2d: off ", i + 1);
1879 }
1880
1881 if (((i + 1) % 8) == 0) {
1882 snd_iprintf(buffer, "\n");
1883 }
1884 }
1885
1886 snd_iprintf(buffer, "\n");
1887}
1888
1889static void __init snd_rme9652_proc_init(rme9652_t *rme9652)
1890{
1891 snd_info_entry_t *entry;
1892
1893 if ((entry = snd_info_create_card_entry(rme9652->card, "rme9652", rme9652->card->proc_root)) !=
1894 NULL) {
1895 entry->content = SNDRV_INFO_CONTENT_TEXT;
1896 entry->private_data = rme9652;
1897 entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
1898 entry->c.text.read_size = 256;
1899 entry->c.text.read = snd_rme9652_proc_read;
1900 if (snd_info_register(entry) < 0) {
1901 snd_info_free_entry(entry);
1902 entry = NULL;
1903 }
1904 }
1905 rme9652->proc_entry = entry;
1906}
1907
1908static void snd_rme9652_proc_done(rme9652_t *rme9652)
1909{
1910 if (rme9652->proc_entry) {
1911 snd_info_unregister(rme9652->proc_entry);
1912 rme9652->proc_entry = NULL;
1913 }
1914}
1915
1916static void snd_rme9652_free_buffers(rme9652_t *rme9652)
1917{
1918 if (rme9652->capture_buffer_unaligned) {
1919#ifndef RME9652_PREALLOCATE_MEMORY
1920 snd_free_pci_pages(rme9652->pci,
1921 RME9652_DMA_AREA_BYTES,
1922 rme9652->capture_buffer_unaligned,
1923 rme9652->capture_buffer_addr);
1924#else
1925 snd_rme9652_free_buffer(rme9652->dev, rme9652->capture_buffer_unaligned);
1926#endif
1927 }
1928
1929 if (rme9652->playback_buffer_unaligned) {
1930#ifndef RME9652_PREALLOCATE_MEMORY
1931 snd_free_pci_pages(rme9652->pci,
1932 RME9652_DMA_AREA_BYTES,
1933 rme9652->playback_buffer_unaligned,
1934 rme9652->playback_buffer_addr);
1935#else
1936 snd_rme9652_free_buffer(rme9652->dev, rme9652->playback_buffer_unaligned);
1937#endif
1938 }
1939}
1940
1941static int snd_rme9652_free(rme9652_t *rme9652)
1942{
1943 if (rme9652->irq >= 0)
1944 rme9652_stop(rme9652);
1945 snd_rme9652_proc_done(rme9652);
1946 snd_rme9652_free_buffers(rme9652);
1947
1948 if (rme9652->iobase)
1949 iounmap((void *) rme9652->iobase);
1950 if (rme9652->res_port)
1951 release_resource(rme9652->res_port);
1952 if (rme9652->irq >= 0)
1953 free_irq(rme9652->irq, (void *)rme9652);
1954 return 0;
1955}
1956
1957static int __init snd_rme9652_initialize_memory(rme9652_t *rme9652)
1958{
1959 void *pb, *cb;
1960 dma_addr_t pb_addr, cb_addr;
1961 unsigned long pb_bus, cb_bus;
1962
1963#ifndef RME9652_PREALLOCATE_MEMORY
1964 cb = snd_malloc_pci_pages(rme9652->pci, RME9652_DMA_AREA_BYTES, &cb_addr);
1965 pb = snd_malloc_pci_pages(rme9652->pci, RME9652_DMA_AREA_BYTES, &pb_addr);
1966#else
1967 cb = snd_rme9652_get_buffer(rme9652->dev, &cb_addr);
1968 pb = snd_rme9652_get_buffer(rme9652->dev, &pb_addr);
1969#endif
1970
1971 if (cb == 0 || pb == 0) {
1972 if (cb) {
1973#ifdef RME9652_PREALLOCATE_MEMORY
1974 snd_rme9652_free_buffer(rme9652->dev, cb);
1975#else
1976 snd_free_pci_pages(rme9652->pci, RME9652_DMA_AREA_BYTES, cb, cb_addr);
1977#endif
1978 }
1979 if (pb) {
1980#ifdef RME9652_PREALLOCATE_MEMORY
1981 snd_rme9652_free_buffer(rme9652->dev, pb);
1982#else
1983 snd_free_pci_pages(rme9652->pci, RME9652_DMA_AREA_BYTES, pb, pb_addr);
1984#endif
1985 }
1986
1987 snd_printk("%s: no buffers available\n",
1988 rme9652->card_name);
1989 return -ENOMEM;
1990 }
1991
1992 /* save raw addresses for use when freeing memory later */
1993
1994 rme9652->capture_buffer_unaligned = cb;
1995 rme9652->playback_buffer_unaligned = pb;
1996 rme9652->capture_buffer_addr = cb_addr;
1997 rme9652->playback_buffer_addr = pb_addr;
1998
1999 /* Align to bus-space 64K boundary */
2000
2001 cb_bus = cb_addr;
2002 cb_bus = (cb_bus + 0xFFFF) & ~0xFFFFl;
2003
2004 pb_bus = pb_addr;
2005 pb_bus = (pb_bus + 0xFFFF) & ~0xFFFFl;
2006
2007 /* Tell the card where it is */
2008
2009 rme9652_write(rme9652, RME9652_rec_buffer, cb_bus);
2010 rme9652_write(rme9652, RME9652_play_buffer, pb_bus);
2011
2012 rme9652->capture_buffer = bus_to_virt(cb_bus);
2013 rme9652->playback_buffer = bus_to_virt(pb_bus);
2014
2015 return 0;
2016}
2017
2018static void snd_rme9652_set_defaults(rme9652_t *rme9652)
2019{
2020 unsigned int k;
2021
2022 /* ASSUMPTION: rme9652->lock is either held, or
2023 there is no need to hold it (e.g. during module
2024 initalization).
2025 */
2026
2027 /* set defaults:
2028
2029 SPDIF Input via Coax
2030 autosync clock mode
2031 maximum latency (7 = 8192 samples, 64Kbyte buffer,
2032 which implies 2 4096 sample, 32Kbyte periods).
2033
2034 if rev 1.5, initialize the S/PDIF receiver.
2035
2036 */
2037
2038 rme9652->control_register =
2039 RME9652_inp_0 | rme9652_encode_latency(7);
2040
2041 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);
2042
2043 rme9652_reset_hw_pointer(rme9652);
2044 rme9652_compute_period_size(rme9652);
2045
2046 /* default: thru off for all channels */
2047
2048 for (k = 0; k < RME9652_NCHANNELS; ++k)
2049 rme9652_write(rme9652, RME9652_thru_base + k * 4, 0);
2050
2051 rme9652->thru_bits = 0;
2052 rme9652->passthru = 0;
2053
2054 /* set a default rate so that the channel map is set up */
2055
2056 rme9652_set_rate(rme9652, 48000);
2057}
2058
2059void snd_rme9652_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2060{
2061 rme9652_t *rme9652 = (rme9652_t *) dev_id;
2062
2063 if (!(rme9652_read(rme9652, RME9652_status_register) & RME9652_IRQ)) {
2064 return;
2065 }
2066
2067 rme9652_write(rme9652, RME9652_irq_clear, 0);
2068
2069 if (rme9652->capture_substream) {
2070 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
2071 }
2072
2073 if (rme9652->playback_substream) {
2074 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
2075 }
2076}
2077
2078static snd_pcm_uframes_t snd_rme9652_hw_pointer(snd_pcm_substream_t *substream)
2079{
2080 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2081 return rme9652_hw_pointer(rme9652);
2082}
2083
2084static char *rme9652_channel_buffer_location(rme9652_t *rme9652,
2085 int stream,
2086 int channel)
2087
2088{
2089 int mapped_channel;
2090
2091 snd_assert(channel >= 0 || channel < RME9652_NCHANNELS, return NULL);
2092
2093 if ((mapped_channel = rme9652->channel_map[channel]) < 0) {
2094 return NULL;
2095 }
2096
2097 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
2098 return rme9652->capture_buffer +
2099 (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
2100 } else {
2101 return rme9652->playback_buffer +
2102 (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
2103 }
2104}
2105
2106static int snd_rme9652_playback_copy(snd_pcm_substream_t *substream, int channel,
2107 snd_pcm_uframes_t pos, void *src, snd_pcm_uframes_t count)
2108{
2109 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2110 char *channel_buf;
2111
2112 snd_assert(pos + count <= RME9652_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
2113 channel_buf = rme9652_channel_buffer_location (rme9652,
2114 substream->pstr->stream,
2115 channel);
2116 snd_assert(channel_buf != NULL, return -EIO);
2117 copy_from_user(channel_buf + pos * 4, src, count * 4);
2118 return count;
2119}
2120
2121static int snd_rme9652_capture_copy(snd_pcm_substream_t *substream, int channel,
2122 snd_pcm_uframes_t pos, void *dst, snd_pcm_uframes_t count)
2123{
2124 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2125 char *channel_buf;
2126
2127 snd_assert(pos + count <= RME9652_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
2128 channel_buf = rme9652_channel_buffer_location (rme9652,
2129 substream->pstr->stream,
2130 channel);
2131 snd_assert(channel_buf != NULL, return -EIO);
2132 copy_to_user(dst, channel_buf + pos * 4, count * 4);
2133 return count;
2134}
2135
2136static int snd_rme9652_hw_silence(snd_pcm_substream_t *substream, int channel,
2137 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
2138{
2139 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2140 char *channel_buf;
2141
2142 channel_buf = rme9652_channel_buffer_location (rme9652,
2143 substream->pstr->stream,
2144 channel);
2145 snd_assert(channel_buf != NULL, return -EIO);
2146 memset(channel_buf + pos * 4, 0, count * 4);
2147 return count;
2148}
2149
2150static int snd_rme9652_reset(snd_pcm_substream_t *substream)
2151{
2152 snd_pcm_runtime_t *runtime = substream->runtime;
2153 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2154 snd_pcm_substream_t *other;
2155 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2156 other = rme9652->capture_substream;
2157 else
2158 other = rme9652->playback_substream;
2159 if (rme9652->running)
2160 runtime->status->hw_ptr = rme9652_hw_pointer(rme9652);
2161 else
2162 runtime->status->hw_ptr = 0;
2163 if (other) {
2164 snd_pcm_substream_t *s = substream;
2165 snd_pcm_runtime_t *oruntime = other->runtime;
2166 do {
2167 s = s->link_next;
2168 if (s == other) {
2169 oruntime->status->hw_ptr = runtime->status->hw_ptr;
2170 break;
2171 }
2172 } while (s != substream);
2173 }
2174 return 0;
2175}
2176
2177static int snd_rme9652_hw_params(snd_pcm_substream_t *substream,
2178 snd_pcm_hw_params_t *params)
2179{
2180 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2181 int err;
2182 pid_t this_pid;
2183 pid_t other_pid;
2184
2185 spin_lock_irq(&rme9652->lock);
2186
2187 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2188 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
2189 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= rme9652->creg_spdif_stream);
2190 this_pid = rme9652->playback_pid;
2191 other_pid = rme9652->capture_pid;
2192 } else {
2193 this_pid = rme9652->capture_pid;
2194 other_pid = rme9652->playback_pid;
2195 }
2196
2197 if ((other_pid > 0) && (this_pid != other_pid)) {
2198
2199 /* The other stream is open, and not by the same
2200 task as this one. Make sure that the parameters
2201 that matter are the same.
2202 */
2203
2204 if (params_rate(params) !=
2205 rme9652_adat_sample_rate(rme9652)) {
2206 spin_unlock_irq(&rme9652->lock);
2207 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
2208 return -EBUSY;
2209 }
2210
2211 if (params_period_size(params) != rme9652->period_bytes / 4) {
2212 spin_unlock_irq(&rme9652->lock);
2213 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
2214 return -EBUSY;
2215 }
2216
2217 /* We're fine. */
2218
2219 spin_unlock_irq(&rme9652->lock);
2220 return 0;
2221
2222 } else {
2223 spin_unlock_irq(&rme9652->lock);
2224 }
2225
2226 /* how to make sure that the rate matches an externally-set one ?
2227 */
2228
2229 if ((err = rme9652_set_rate(rme9652, params_rate(params))) < 0) {
2230 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
2231 return err;
2232 }
2233
2234 if ((err = rme9652_set_interrupt_interval(rme9652, params_period_size(params))) < 0) {
2235 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
2236 return err;
2237 }
2238
2239 return 0;
2240}
2241
2242static int snd_rme9652_channel_info(snd_pcm_substream_t *substream,
2243 snd_pcm_channel_info_t *info)
2244{
2245 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2246 int chn;
2247
2248 snd_assert(info->channel < RME9652_NCHANNELS, return -EINVAL);
2249 if ((chn = rme9652->channel_map[info->channel]) < 0) {
2250 return -EINVAL;
2251 }
2252
2253 info->offset = chn * RME9652_CHANNEL_BUFFER_BYTES;
2254 info->first = 0;
2255 info->step = 32;
2256 return 0;
2257}
2258
2259static int snd_rme9652_ioctl(snd_pcm_substream_t *substream,
2260 unsigned int cmd, void *arg)
2261{
2262 switch (cmd) {
2263 case SNDRV_PCM_IOCTL1_RESET:
2264 {
2265 return snd_rme9652_reset(substream);
2266 }
2267 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
2268 {
2269 snd_pcm_channel_info_t *info = arg;
2270 return snd_rme9652_channel_info(substream, info);
2271 }
2272 default:
2273 break;
2274 }
2275
2276 return snd_pcm_lib_ioctl(substream, cmd, arg);
2277}
2278
2279static void rme9652_silence_playback(rme9652_t *rme9652)
2280{
2281 memset(rme9652->playback_buffer, 0, RME9652_DMA_AREA_BYTES);
2282}
2283
2284static int snd_rme9652_trigger(snd_pcm_substream_t *substream,
2285 int cmd)
2286{
2287 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2288 snd_pcm_substream_t *other;
2289 int running;
2290 spin_lock(&rme9652->lock);
2291 running = rme9652->running;
2292 switch (cmd) {
2293 case SNDRV_PCM_TRIGGER_START:
2294 running |= 1 << substream->stream;
2295 break;
2296 case SNDRV_PCM_TRIGGER_STOP:
2297 running &= ~(1 << substream->stream);
2298 break;
2299 default:
2300 snd_BUG();
2301 spin_unlock(&rme9652->lock);
2302 return -EINVAL;
2303 }
2304 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2305 other = rme9652->capture_substream;
2306 else
2307 other = rme9652->playback_substream;
2308
2309 if (other) {
2310 snd_pcm_substream_t *s = substream;
2311 do {
2312 s = s->link_next;
2313 if (s == other) {
2314 snd_pcm_trigger_done(s, substream);
2315 if (cmd == SNDRV_PCM_TRIGGER_START)
2316 running |= 1 << s->stream;
2317 else
2318 running &= ~(1 << s->stream);
2319 goto _ok;
2320 }
2321 } while (s != substream);
2322 if (cmd == SNDRV_PCM_TRIGGER_START) {
2323 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
2324 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2325 rme9652_silence_playback(rme9652);
2326 } else {
2327 if (running &&
2328 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2329 rme9652_silence_playback(rme9652);
2330 }
2331 }
2332 _ok:
2333 snd_pcm_trigger_done(substream, substream);
2334 if (!rme9652->running && running)
2335 rme9652_start(rme9652);
2336 else if (rme9652->running && !running)
2337 rme9652_stop(rme9652);
2338 rme9652->running = running;
2339 spin_unlock(&rme9652->lock);
2340
2341 return 0;
2342}
2343
2344static int snd_rme9652_prepare(snd_pcm_substream_t *substream)
2345{
2346 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2347 int result = 0;
2348
2349 spin_lock_irq(&rme9652->lock);
2350 if (!rme9652->running)
2351 rme9652_reset_hw_pointer(rme9652);
2352 spin_unlock_irq(&rme9652->lock);
2353 return result;
2354}
2355
2356#ifdef TARGET_OS2
2357static snd_pcm_hardware_t snd_rme9652_playback_subinfo =
2358{
2359/* info: */ (SNDRV_PCM_INFO_MMAP |
2360 SNDRV_PCM_INFO_MMAP_VALID |
2361 SNDRV_PCM_INFO_NONINTERLEAVED |
2362 SNDRV_PCM_INFO_SYNC_START |
2363 SNDRV_PCM_INFO_DOUBLE),
2364/* formats: */ SNDRV_PCM_FMTBIT_S32_LE,
2365/* rates: */ (SNDRV_PCM_RATE_44100 |
2366 SNDRV_PCM_RATE_48000 |
2367 SNDRV_PCM_RATE_88200 |
2368 SNDRV_PCM_RATE_96000),
2369/* rate_min: */ 44100,
2370/* rate_max: */ 96000,
2371/* channels_min: */ 10,
2372/* channels_max: */ 26,
2373/* buffer_bytes_max: */ 1024*1024,
2374/* period_bytes_min: */ 1,
2375/* period_bytes_max: */ 1024*1024,
2376/* periods_min: */ 2,
2377/* periods_max: */ 2,
2378/* fifo_size: */ 0,
2379};
2380
2381static snd_pcm_hardware_t snd_rme9652_capture_subinfo =
2382{
2383/* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |
2384 SNDRV_PCM_INFO_NONINTERLEAVED |
2385 SNDRV_PCM_INFO_SYNC_START),
2386/* formats: */ SNDRV_PCM_FMTBIT_S32_LE,
2387/* rates: */ (SNDRV_PCM_RATE_44100 |
2388 SNDRV_PCM_RATE_48000 |
2389 SNDRV_PCM_RATE_88200 |
2390 SNDRV_PCM_RATE_96000),
2391/* rate_min: */ 44100,
2392/* rate_max: */ 96000,
2393/* channels_min: */ 10,
2394/* channels_max: */ 26,
2395/* buffer_bytes_max: */ 1024*1024,
2396/* period_bytes_min: */ 1,
2397/* period_bytes_max: */ 1024*1024,
2398/* periods_min: */ 2,
2399/* periods_max: */ 2,
2400/* fifo_size: */ 0,
2401};
2402#else
2403static snd_pcm_hardware_t snd_rme9652_playback_subinfo =
2404{
2405 info: (SNDRV_PCM_INFO_MMAP |
2406 SNDRV_PCM_INFO_MMAP_VALID |
2407 SNDRV_PCM_INFO_NONINTERLEAVED |
2408 SNDRV_PCM_INFO_SYNC_START |
2409 SNDRV_PCM_INFO_DOUBLE),
2410 formats: SNDRV_PCM_FMTBIT_S32_LE,
2411 rates: (SNDRV_PCM_RATE_44100 |
2412 SNDRV_PCM_RATE_48000 |
2413 SNDRV_PCM_RATE_88200 |
2414 SNDRV_PCM_RATE_96000),
2415 rate_min: 44100,
2416 rate_max: 96000,
2417 channels_min: 10,
2418 channels_max: 26,
2419 buffer_bytes_max: 1024*1024,
2420 period_bytes_min: 1,
2421 period_bytes_max: 1024*1024,
2422 periods_min: 2,
2423 periods_max: 2,
2424 fifo_size: 0,
2425};
2426
2427static snd_pcm_hardware_t snd_rme9652_capture_subinfo =
2428{
2429 info: (SNDRV_PCM_INFO_MMAP |
2430 SNDRV_PCM_INFO_MMAP_VALID |
2431 SNDRV_PCM_INFO_NONINTERLEAVED |
2432 SNDRV_PCM_INFO_SYNC_START),
2433 formats: SNDRV_PCM_FMTBIT_S32_LE,
2434 rates: (SNDRV_PCM_RATE_44100 |
2435 SNDRV_PCM_RATE_48000 |
2436 SNDRV_PCM_RATE_88200 |
2437 SNDRV_PCM_RATE_96000),
2438 rate_min: 44100,
2439 rate_max: 96000,
2440 channels_min: 10,
2441 channels_max: 26,
2442 buffer_bytes_max: 1024*1024,
2443 period_bytes_min: 1,
2444 period_bytes_max: 1024*1024,
2445 periods_min: 2,
2446 periods_max: 2,
2447 fifo_size: 0,
2448};
2449#endif
2450
2451static unsigned int period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
2452
2453#define PERIOD_SIZES sizeof(period_sizes) / sizeof(period_sizes[0])
2454
2455#ifdef TARGET_OS2
2456static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
2457 PERIOD_SIZES,
2458 period_sizes,
2459 0
2460};
2461#else
2462static snd_pcm_hw_constraint_list_t hw_constraints_period_sizes = {
2463 count: PERIOD_SIZES,
2464 list: period_sizes,
2465 mask: 0
2466};
2467#endif
2468
2469static int snd_rme9652_hw_rule_channels(snd_pcm_hw_params_t *params,
2470 snd_pcm_hw_rule_t *rule)
2471{
2472 rme9652_t *rme9652 = rule->private;
2473 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2474#ifdef TARGET_OS2
2475 unsigned int list[2];
2476 list[0] = rme9652->ds_channels; list[1] = rme9652->ss_channels;
2477#else
2478 unsigned int list[2] = { rme9652->ds_channels, rme9652->ss_channels };
2479#endif
2480 return snd_interval_list(c, 2, list, 0);
2481}
2482
2483static int snd_rme9652_hw_rule_channels_rate(snd_pcm_hw_params_t *params,
2484 snd_pcm_hw_rule_t *rule)
2485{
2486 rme9652_t *rme9652 = rule->private;
2487 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2488 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2489 if (r->min > 48000) {
2490#ifdef TARGET_OS2
2491 snd_interval_t t = {0};
2492 t.min = rme9652->ds_channels;
2493 t.max = rme9652->ds_channels;
2494 t.integer = 1;
2495#else
2496 snd_interval_t t = {
2497 min: rme9652->ds_channels,
2498 max: rme9652->ds_channels,
2499 integer: 1,
2500 };
2501#endif
2502 return snd_interval_refine(c, &t);
2503 } else if (r->max < 88200) {
2504#ifdef TARGET_OS2
2505 snd_interval_t t = {0};
2506 t.min = rme9652->ss_channels;
2507 t.max = rme9652->ss_channels;
2508 t.integer = 1;
2509#else
2510 snd_interval_t t = {
2511 min: rme9652->ss_channels,
2512 max: rme9652->ss_channels,
2513 integer: 1,
2514 };
2515#endif
2516 return snd_interval_refine(c, &t);
2517 }
2518 return 0;
2519}
2520
2521static int snd_rme9652_hw_rule_rate_channels(snd_pcm_hw_params_t *params,
2522 snd_pcm_hw_rule_t *rule)
2523{
2524 rme9652_t *rme9652 = rule->private;
2525 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2526 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2527 if (c->min >= rme9652->ss_channels) {
2528 snd_interval_t t = {
2529#ifdef TARGET_OS2
2530 44100,
2531 48000,
2532 0, 0, 1, 0,
2533#else
2534 min: 44100,
2535 max: 48000,
2536 integer: 1,
2537#endif
2538 };
2539 return snd_interval_refine(r, &t);
2540 } else if (c->max <= rme9652->ds_channels) {
2541 snd_interval_t t = {
2542#ifdef TARGET_OS2
2543 88200,
2544 96000,
2545 0, 0, 1, 0,
2546#else
2547 min: 88200,
2548 max: 96000,
2549 integer: 1,
2550#endif
2551 };
2552 return snd_interval_refine(r, &t);
2553 }
2554 return 0;
2555}
2556
2557static int snd_rme9652_playback_open(snd_pcm_substream_t *substream)
2558{
2559 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2560 unsigned long flags;
2561 snd_pcm_runtime_t *runtime = substream->runtime;
2562
2563 spin_lock_irqsave(&rme9652->lock, flags);
2564
2565 snd_pcm_set_sync(substream);
2566
2567 runtime->hw = snd_rme9652_playback_subinfo;
2568 runtime->dma_area = rme9652->playback_buffer;
2569 runtime->dma_bytes = RME9652_DMA_AREA_BYTES;
2570
2571 if (rme9652->capture_substream == NULL) {
2572 rme9652_stop(rme9652);
2573 rme9652_set_thru(rme9652, -1, 0);
2574 }
2575
2576 rme9652->playback_pid = current->pid;
2577 rme9652->playback_substream = substream;
2578
2579 spin_unlock_irqrestore(&rme9652->lock, flags);
2580
2581 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2582 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
2583 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2584 snd_rme9652_hw_rule_channels, rme9652,
2585 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2586 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2587 snd_rme9652_hw_rule_channels_rate, rme9652,
2588 SNDRV_PCM_HW_PARAM_RATE, -1);
2589 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2590 snd_rme9652_hw_rule_rate_channels, rme9652,
2591 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2592
2593 rme9652->creg_spdif_stream = rme9652->creg_spdif;
2594 rme9652->spdif_ctl->access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2595 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
2596 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);
2597 return 0;
2598}
2599
2600static int snd_rme9652_playback_release(snd_pcm_substream_t *substream)
2601{
2602 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2603 unsigned long flags;
2604
2605 spin_lock_irqsave(&rme9652->lock, flags);
2606
2607 rme9652->playback_pid = -1;
2608 rme9652->playback_substream = NULL;
2609
2610 spin_unlock_irqrestore(&rme9652->lock, flags);
2611
2612 rme9652->spdif_ctl->access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2613 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
2614 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);
2615 return 0;
2616}
2617
2618
2619static int snd_rme9652_capture_open(snd_pcm_substream_t *substream)
2620{
2621 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2622 unsigned long flags;
2623 snd_pcm_runtime_t *runtime = substream->runtime;
2624
2625 spin_lock_irqsave(&rme9652->lock, flags);
2626
2627 snd_pcm_set_sync(substream);
2628
2629 runtime->hw = snd_rme9652_capture_subinfo;
2630 runtime->dma_area = rme9652->capture_buffer;
2631 runtime->dma_bytes = RME9652_DMA_AREA_BYTES;
2632
2633 if (rme9652->playback_substream == NULL) {
2634 rme9652_stop(rme9652);
2635 rme9652_set_thru(rme9652, -1, 0);
2636 }
2637
2638 rme9652->capture_pid = current->pid;
2639 rme9652->capture_substream = substream;
2640
2641 spin_unlock_irqrestore(&rme9652->lock, flags);
2642
2643 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2644 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);
2645 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2646 snd_rme9652_hw_rule_channels, rme9652,
2647 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2648 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2649 snd_rme9652_hw_rule_channels_rate, rme9652,
2650 SNDRV_PCM_HW_PARAM_RATE, -1);
2651 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2652 snd_rme9652_hw_rule_rate_channels, rme9652,
2653 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2654 return 0;
2655}
2656
2657static int snd_rme9652_capture_release(snd_pcm_substream_t *substream)
2658{
2659 rme9652_t *rme9652 = _snd_pcm_substream_chip(substream);
2660 unsigned long flags;
2661
2662 spin_lock_irqsave(&rme9652->lock, flags);
2663
2664 rme9652->capture_pid = -1;
2665 rme9652->capture_substream = NULL;
2666
2667 spin_unlock_irqrestore(&rme9652->lock, flags);
2668 return 0;
2669}
2670
2671#ifdef TARGET_OS2
2672static snd_pcm_ops_t snd_rme9652_playback_ops = {
2673/* open: */ snd_rme9652_playback_open,
2674/* close: */ snd_rme9652_playback_release,
2675/* ioctl: */ snd_rme9652_ioctl,
2676/* hw_params: */ snd_rme9652_hw_params,
2677 0,
2678/* prepare: */ snd_rme9652_prepare,
2679/* trigger: */ snd_rme9652_trigger,
2680/* pointer: */ snd_rme9652_hw_pointer,
2681/* copy: */ snd_rme9652_playback_copy,
2682/* silence: */ snd_rme9652_hw_silence,
2683};
2684
2685static snd_pcm_ops_t snd_rme9652_capture_ops = {
2686/* open: */ snd_rme9652_capture_open,
2687/* close: */ snd_rme9652_capture_release,
2688/* ioctl: */ snd_rme9652_ioctl,
2689/* hw_params: */ snd_rme9652_hw_params,
2690 0,
2691/* prepare: */ snd_rme9652_prepare,
2692/* trigger: */ snd_rme9652_trigger,
2693/* pointer: */ snd_rme9652_hw_pointer,
2694/* copy: */ snd_rme9652_capture_copy,
2695 0
2696};
2697#else
2698static snd_pcm_ops_t snd_rme9652_playback_ops = {
2699 open: snd_rme9652_playback_open,
2700 close: snd_rme9652_playback_release,
2701 ioctl: snd_rme9652_ioctl,
2702 hw_params: snd_rme9652_hw_params,
2703 prepare: snd_rme9652_prepare,
2704 trigger: snd_rme9652_trigger,
2705 pointer: snd_rme9652_hw_pointer,
2706 copy: snd_rme9652_playback_copy,
2707 silence: snd_rme9652_hw_silence,
2708};
2709
2710static snd_pcm_ops_t snd_rme9652_capture_ops = {
2711 open: snd_rme9652_capture_open,
2712 close: snd_rme9652_capture_release,
2713 ioctl: snd_rme9652_ioctl,
2714 hw_params: snd_rme9652_hw_params,
2715 prepare: snd_rme9652_prepare,
2716 trigger: snd_rme9652_trigger,
2717 pointer: snd_rme9652_hw_pointer,
2718 copy: snd_rme9652_capture_copy,
2719};
2720#endif
2721
2722static int __init snd_rme9652_create_pcm(snd_card_t *card,
2723 rme9652_t *rme9652)
2724{
2725 snd_pcm_t *pcm;
2726 int err;
2727
2728 if ((err = snd_pcm_new(card,
2729 rme9652->card_name,
2730 0, 1, 1, &pcm)) < 0) {
2731 return err;
2732 }
2733
2734 rme9652->pcm = pcm;
2735 pcm->private_data = rme9652;
2736 strcpy(pcm->name, rme9652->card_name);
2737
2738 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme9652_playback_ops);
2739 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme9652_capture_ops);
2740
2741 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
2742
2743 return 0;
2744}
2745
2746static int __init snd_rme9652_create(snd_card_t *card,
2747 rme9652_t *rme9652)
2748{
2749 struct pci_dev *pci = rme9652->pci;
2750 int err;
2751 int status;
2752 unsigned short rev;
2753
2754 rme9652->irq = -1;
2755 rme9652->card = card;
2756
2757 if ((err = pci_enable_device(pci)) < 0)
2758 return err;
2759
2760 spin_lock_init(&rme9652->lock);
2761
2762 rme9652->port = pci_resource_start(pci, 0);
2763 if ((rme9652->res_port = request_mem_region(rme9652->port, RME9652_IO_EXTENT, "rme9652")) == NULL) {
2764 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", rme9652->port, rme9652->port + RME9652_IO_EXTENT - 1);
2765 return -EBUSY;
2766 }
2767
2768 if (request_irq(pci->irq, snd_rme9652_interrupt, SA_INTERRUPT|SA_SHIRQ, "rme9652", (void *)rme9652)) {
2769 snd_printk("unable to grab IRQ %d\n", pci->irq);
2770 return -EBUSY;
2771 }
2772 rme9652->irq = pci->irq;
2773
2774 rme9652->iobase = (unsigned long) ioremap(rme9652->port, RME9652_IO_EXTENT);
2775 if (rme9652->iobase == 0) {
2776 snd_printk("unable to remap region 0x%lx-0x%lx\n", rme9652->port, rme9652->port + RME9652_IO_EXTENT - 1);
2777 return -EBUSY;
2778 }
2779
2780 /* Determine the h/w rev level of the card. This seems like
2781 a particularly kludgy way to encode it, but its what RME
2782 chose to do, so we follow them ...
2783 */
2784
2785 status = rme9652_read(rme9652, RME9652_status_register);
2786 if (rme9652_decode_spdif_rate(status&RME9652_F) == 1) {
2787 rme9652->hw_rev = 15;
2788 } else {
2789 rme9652->hw_rev = 11;
2790 }
2791
2792 /* Differentiate between the standard Hammerfall, and the
2793 "Light", which does not have the expansion board. This
2794 method comes from information received from Mathhias
2795 Clausen at RME. Display the EEPROM and h/w revID where
2796 relevant.
2797 */
2798
2799 pci_read_config_word(rme9652->pci, PCI_CLASS_REVISION, &rev);
2800 strcpy(card->driver, "RME9652");
2801 switch (rev & 0xff) {
2802 case 8: /* original eprom */
2803 strcpy(card->driver, "RME9636");
2804 if (rme9652->hw_rev == 15) {
2805 rme9652->card_name = "RME Digi9636 (Rev 1.5)";
2806 } else {
2807 rme9652->card_name = "RME Digi9636";
2808 }
2809 rme9652->ss_channels = RME9636_NCHANNELS;
2810 break;
2811 case 9: /* W36_G EPROM */
2812 strcpy(card->driver, "RME9636");
2813 rme9652->card_name = "RME Digi9636 (Rev G)";
2814 rme9652->ss_channels = RME9636_NCHANNELS;
2815 break;
2816 case 4: /* W52_G EPROM */
2817 rme9652->card_name = "RME Digi9652 (Rev G)";
2818 rme9652->ss_channels = RME9652_NCHANNELS;
2819 break;
2820 default:
2821 case 3: /* original eprom */
2822 if (rme9652->hw_rev == 15) {
2823 rme9652->card_name = "RME Digi9652 (Rev 1.5)";
2824 } else {
2825 rme9652->card_name = "RME Digi9652";
2826 }
2827 rme9652->ss_channels = RME9652_NCHANNELS;
2828 break;
2829 }
2830
2831 rme9652->ds_channels = (rme9652->ss_channels - 2) / 2 + 2;
2832
2833 pci_set_master(rme9652->pci);
2834
2835 if ((err = snd_rme9652_initialize_memory(rme9652)) < 0) {
2836 return err;
2837 }
2838
2839 if ((err = snd_rme9652_create_pcm(card, rme9652)) < 0) {
2840 return err;
2841 }
2842
2843 if ((err = snd_rme9652_create_controls(card, rme9652)) < 0) {
2844 return err;
2845 }
2846
2847 snd_rme9652_proc_init(rme9652);
2848
2849 rme9652->last_spdif_sample_rate = -1;
2850 rme9652->last_adat_sample_rate = -1;
2851 rme9652->playback_pid = -1;
2852 rme9652->capture_pid = -1;
2853 rme9652->capture_substream = NULL;
2854 rme9652->playback_substream = NULL;
2855
2856 snd_rme9652_set_defaults(rme9652);
2857
2858 if (rme9652->hw_rev == 15) {
2859 rme9652_initialize_spdif_receiver (rme9652);
2860 }
2861
2862 return 0;
2863}
2864
2865static void snd_rme9652_card_free(snd_card_t *card)
2866{
2867 rme9652_t *rme9652 = (rme9652_t *) card->private_data;
2868
2869 if (rme9652)
2870 snd_rme9652_free(rme9652);
2871}
2872
2873static int snd_rme9652_probe(struct pci_dev *pci,
2874 const struct pci_device_id *id)
2875{
2876 static int dev = 0;
2877 rme9652_t *rme9652;
2878 snd_card_t *card;
2879 int err;
2880
2881 for (; dev < SNDRV_CARDS; dev++) {
2882 if (!snd_enable[dev]) {
2883 dev++;
2884 return -ENOENT;
2885 }
2886 break;
2887 }
2888
2889 if (dev >= SNDRV_CARDS)
2890 return -ENODEV;
2891
2892 card = snd_card_new(snd_index[dev], snd_id[dev], THIS_MODULE,
2893 sizeof(rme9652_t));
2894
2895 if (!card)
2896 return -ENOMEM;
2897
2898 rme9652 = (rme9652_t *) card->private_data;
2899 card->private_free = snd_rme9652_card_free;
2900 rme9652->dev = dev;
2901 rme9652->pci = pci;
2902
2903 if ((err = snd_rme9652_create(card, rme9652)) < 0) {
2904 snd_card_free(card);
2905 return err;
2906 }
2907
2908 strcpy(card->shortname, rme9652->card_name);
2909
2910 sprintf(card->longname, "%s at 0x%lx, irq %d",
2911 card->shortname, rme9652->port, rme9652->irq);
2912
2913
2914 if ((err = snd_card_register(card)) < 0) {
2915 snd_card_free(card);
2916 return err;
2917 }
2918 PCI_SET_DRIVER_DATA(pci, card);
2919 dev++;
2920 return 0;
2921}
2922
2923static void __exit snd_rme9652_remove(struct pci_dev *pci)
2924{
2925 snd_card_free(PCI_GET_DRIVER_DATA(pci));
2926 PCI_SET_DRIVER_DATA(pci, NULL);
2927}
2928
2929#ifdef TARGET_OS2
2930static struct pci_driver driver = {
2931 0, 0,"RME Digi9652 (Hammerfall)",
2932 snd_rme9652_ids,
2933 snd_rme9652_probe,
2934 snd_rme9652_remove,0,0
2935};
2936#else
2937static struct pci_driver driver = {
2938 name:"RME Digi9652 (Hammerfall)",
2939 id_table:snd_rme9652_ids,
2940 probe:snd_rme9652_probe,
2941 remove:snd_rme9652_remove,
2942};
2943#endif
2944
2945static int __init alsa_card_hammerfall_init(void)
2946{
2947 if (pci_module_init(&driver) < 0) {
2948#ifdef MODULE
2949 snd_printk("RME Digi9652/Digi9636: no cards found\n");
2950#endif
2951 return -ENODEV;
2952 }
2953
2954 return 0;
2955}
2956
2957static void __exit alsa_card_hammerfall_exit(void)
2958{
2959 pci_unregister_driver(&driver);
2960}
2961
2962module_init(alsa_card_hammerfall_init)
2963module_exit(alsa_card_hammerfall_exit)
2964
2965#ifndef MODULE
2966
2967/* format is: snd-card-rme9652=snd_enable,snd_index,snd_id */
2968
2969static int __init alsa_card_rme9652_setup(char *str)
2970{
2971 static unsigned __initdata nr_dev = 0;
2972
2973 if (nr_dev >= SNDRV_CARDS)
2974 return 0;
2975 (void)(get_option(&str,&snd_enable[nr_dev]) == 2 &&
2976 get_option(&str,&snd_index[nr_dev]) == 2 &&
2977 get_id(&str,&snd_id[nr_dev]) == 2);
2978 nr_dev++;
2979 return 1;
2980}
2981
2982__setup("snd-card-rme9652=", alsa_card_rme9652_setup);
2983
2984#endif /* ifndef MODULE */
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