source: GPL/alsa-kernel/pci/rme96.c@ 1

Last change on this file since 1 was 1, checked in by vladest, 20 years ago

initial import
File size: 77.9 KB
Line 
1/*
2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces
4 *
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 *
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 */
25
26#define SNDRV_MAIN_OBJECT_FILE
27
28#include <sound/driver.h>
29#include <sound/info.h>
30#include <sound/control.h>
31#include <sound/pcm.h>
32#define SNDRV_GET_ID
33#include <sound/initval.h>
34
35/* note, two last pcis should be equal, it is not a bug */
36EXPORT_NO_SYMBOLS;
37MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
38 "Digi96/8 PAD");
39MODULE_CLASSES("{sound}");
40MODULE_DEVICES("{{RME,Digi96},"
41 "{RME,Digi96/8},"
42 "{RME,Digi96/8 PRO},"
43 "{RME,Digi96/8 PST},"
44 "{RME,Digi96/8 PAD}}");
45
46static int snd_index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
47static char *snd_id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
48static int snd_enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE; /* Enable this card */
49
50MODULE_PARM(snd_index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
51MODULE_PARM_DESC(snd_index, "Index value for RME Digi96 soundcard.");
52MODULE_PARM_SYNTAX(snd_index, SNDRV_INDEX_DESC);
53MODULE_PARM(snd_id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
54MODULE_PARM_DESC(snd_id, "ID string for RME Digi96 soundcard.");
55MODULE_PARM_SYNTAX(snd_id, SNDRV_ID_DESC);
56MODULE_PARM(snd_enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
57MODULE_PARM_DESC(snd_enable, "Enable RME Digi96 soundcard.");
58MODULE_PARM_SYNTAX(snd_enable, SNDRV_ENABLE_DESC);
59MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
60
61/*
62 * Defines for RME Digi96 series, from internal RME reference documents
63 * dated 12.01.00
64 */
65
66#define RME96_SPDIF_NCHANNELS 2
67
68/* Playback and capture buffer size */
69#define RME96_BUFFER_SIZE 0x10000
70
71/* IO area size */
72#define RME96_IO_SIZE 0x60000
73
74/* IO area offsets */
75#define RME96_IO_PLAY_BUFFER 0x0
76#define RME96_IO_REC_BUFFER 0x10000
77#define RME96_IO_CONTROL_REGISTER 0x20000
78#define RME96_IO_ADDITIONAL_REG 0x20004
79#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
80#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
81#define RME96_IO_SET_PLAY_POS 0x40000
82#define RME96_IO_RESET_PLAY_POS 0x4FFFC
83#define RME96_IO_SET_REC_POS 0x50000
84#define RME96_IO_RESET_REC_POS 0x5FFFC
85#define RME96_IO_GET_PLAY_POS 0x20000
86#define RME96_IO_GET_REC_POS 0x30000
87
88/* Write control register bits */
89#define RME96_WCR_START (1 << 0)
90#define RME96_WCR_START_2 (1 << 1)
91#define RME96_WCR_GAIN_0 (1 << 2)
92#define RME96_WCR_GAIN_1 (1 << 3)
93#define RME96_WCR_MODE24 (1 << 4)
94#define RME96_WCR_MODE24_2 (1 << 5)
95#define RME96_WCR_BM (1 << 6)
96#define RME96_WCR_BM_2 (1 << 7)
97#define RME96_WCR_ADAT (1 << 8)
98#define RME96_WCR_FREQ_0 (1 << 9)
99#define RME96_WCR_FREQ_1 (1 << 10)
100#define RME96_WCR_DS (1 << 11)
101#define RME96_WCR_PRO (1 << 12)
102#define RME96_WCR_EMP (1 << 13)
103#define RME96_WCR_SEL (1 << 14)
104#define RME96_WCR_MASTER (1 << 15)
105#define RME96_WCR_PD (1 << 16)
106#define RME96_WCR_INP_0 (1 << 17)
107#define RME96_WCR_INP_1 (1 << 18)
108#define RME96_WCR_THRU_0 (1 << 19)
109#define RME96_WCR_THRU_1 (1 << 20)
110#define RME96_WCR_THRU_2 (1 << 21)
111#define RME96_WCR_THRU_3 (1 << 22)
112#define RME96_WCR_THRU_4 (1 << 23)
113#define RME96_WCR_THRU_5 (1 << 24)
114#define RME96_WCR_THRU_6 (1 << 25)
115#define RME96_WCR_THRU_7 (1 << 26)
116#define RME96_WCR_DOLBY (1 << 27)
117#define RME96_WCR_MONITOR_0 (1 << 28)
118#define RME96_WCR_MONITOR_1 (1 << 29)
119#define RME96_WCR_ISEL (1 << 30)
120#define RME96_WCR_IDIS (1 << 31)
121
122#define RME96_WCR_BITPOS_GAIN_0 2
123#define RME96_WCR_BITPOS_GAIN_1 3
124#define RME96_WCR_BITPOS_FREQ_0 9
125#define RME96_WCR_BITPOS_FREQ_1 10
126#define RME96_WCR_BITPOS_INP_0 17
127#define RME96_WCR_BITPOS_INP_1 18
128#define RME96_WCR_BITPOS_MONITOR_0 28
129#define RME96_WCR_BITPOS_MONITOR_1 29
130
131/* Read control register bits */
132#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
133#define RME96_RCR_IRQ_2 (1 << 16)
134#define RME96_RCR_T_OUT (1 << 17)
135#define RME96_RCR_DEV_ID_0 (1 << 21)
136#define RME96_RCR_DEV_ID_1 (1 << 22)
137#define RME96_RCR_LOCK (1 << 23)
138#define RME96_RCR_VERF (1 << 26)
139#define RME96_RCR_F0 (1 << 27)
140#define RME96_RCR_F1 (1 << 28)
141#define RME96_RCR_F2 (1 << 29)
142#define RME96_RCR_AUTOSYNC (1 << 30)
143#define RME96_RCR_IRQ (1 << 31)
144
145#define RME96_RCR_BITPOS_F0 27
146#define RME96_RCR_BITPOS_F1 28
147#define RME96_RCR_BITPOS_F2 29
148
149/* Additonal register bits */
150#define RME96_AR_WSEL (1 << 0)
151#define RME96_AR_ANALOG (1 << 1)
152#define RME96_AR_FREQPAD_0 (1 << 2)
153#define RME96_AR_FREQPAD_1 (1 << 3)
154#define RME96_AR_FREQPAD_2 (1 << 4)
155#define RME96_AR_PD2 (1 << 5)
156#define RME96_AR_DAC_EN (1 << 6)
157#define RME96_AR_CLATCH (1 << 7)
158#define RME96_AR_CCLK (1 << 8)
159#define RME96_AR_CDATA (1 << 9)
160
161#define RME96_AR_BITPOS_F0 2
162#define RME96_AR_BITPOS_F1 3
163#define RME96_AR_BITPOS_F2 4
164
165/* Monitor tracks */
166#define RME96_MONITOR_TRACKS_1_2 0
167#define RME96_MONITOR_TRACKS_3_4 1
168#define RME96_MONITOR_TRACKS_5_6 2
169#define RME96_MONITOR_TRACKS_7_8 3
170
171/* Attenuation */
172#define RME96_ATTENUATION_0 0
173#define RME96_ATTENUATION_6 1
174#define RME96_ATTENUATION_12 2
175#define RME96_ATTENUATION_18 3
176
177/* Input types */
178#define RME96_INPUT_OPTICAL 0
179#define RME96_INPUT_COAXIAL 1
180#define RME96_INPUT_INTERNAL 2
181#define RME96_INPUT_XLR 3
182#define RME96_INPUT_ANALOG 4
183
184/* Clock modes */
185#define RME96_CLOCKMODE_SLAVE 0
186#define RME96_CLOCKMODE_MASTER 1
187#define RME96_CLOCKMODE_WORDCLOCK 2
188
189/* Block sizes in bytes */
190#define RME96_SMALL_BLOCK_SIZE 2048
191#define RME96_LARGE_BLOCK_SIZE 8192
192
193/* Volume control */
194#define RME96_AD1852_VOL_BITS 14
195#define RME96_AD1855_VOL_BITS 10
196
197/*
198 * PCI vendor/device ids, could in the future be defined in <linux/pci.h>,
199 * therefore #ifndef is used.
200 */
201#ifndef PCI_VENDOR_ID_XILINX
202#define PCI_VENDOR_ID_XILINX 0x10ee
203#endif
204#ifndef PCI_DEVICE_ID_DIGI96
205#define PCI_DEVICE_ID_DIGI96 0x3fc0
206#endif
207#ifndef PCI_DEVICE_ID_DIGI96_8
208#define PCI_DEVICE_ID_DIGI96_8 0x3fc1
209#endif
210#ifndef PCI_DEVICE_ID_DIGI96_8_PRO
211#define PCI_DEVICE_ID_DIGI96_8_PRO 0x3fc2
212#endif
213#ifndef PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST
214#define PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 0x3fc3
215#endif
216
217typedef struct snd_rme96 {
218 spinlock_t lock;
219 int irq;
220 unsigned long port;
221 struct resource *res_port;
222 unsigned long iobase;
223
224 u32 wcreg; /* cached write control register value */
225 u32 wcreg_spdif; /* S/PDIF setup */
226 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
227 u32 rcreg; /* cached read control register value */
228 u32 areg; /* cached additional register value */
229 u16 vol[2]; /* cached volume of analog output */
230
231 u8 rev; /* card revision number */
232
233 snd_pcm_substream_t *playback_substream;
234 snd_pcm_substream_t *capture_substream;
235
236 int playback_frlog; /* log2 of framesize */
237 int capture_frlog;
238
239 size_t playback_periodsize; /* in bytes, zero if not used */
240 size_t capture_periodsize; /* in bytes, zero if not used */
241
242 size_t playback_ptr;
243 size_t capture_ptr;
244
245 snd_card_t *card;
246 snd_pcm_t *spdif_pcm;
247 snd_pcm_t *adat_pcm;
248 struct pci_dev *pci;
249 snd_info_entry_t *proc_entry;
250 snd_kcontrol_t *spdif_ctl;
251} rme96_t;
252
253static struct pci_device_id snd_rme96_ids[] __devinitdata = {
254 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96,
255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
256 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8,
257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
258 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PRO,
259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
260 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST,
261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
262 { 0, }
263};
264
265MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
266
267#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
268#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
269#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
270#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO || \
271 (rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST)
272#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
273#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
274 ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO && (rme96)->rev == 2))
275#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
276
277static int
278snd_rme96_playback_prepare(snd_pcm_substream_t *substream);
279
280static int
281snd_rme96_capture_prepare(snd_pcm_substream_t *substream);
282
283static int
284snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
285 int cmd);
286
287static int
288snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
289 int cmd);
290
291static snd_pcm_uframes_t
292snd_rme96_playback_pointer(snd_pcm_substream_t *substream);
293
294static snd_pcm_uframes_t
295snd_rme96_capture_pointer(snd_pcm_substream_t *substream);
296
297static void __init
298snd_rme96_proc_init(rme96_t *rme96);
299
300static void
301snd_rme96_proc_done(rme96_t *rme96);
302
303static int
304snd_rme96_create_switches(snd_card_t *card,
305 rme96_t *rme96);
306
307static inline unsigned int
308snd_rme96_playback_ptr(rme96_t *rme96)
309{
310 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
311 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
312}
313
314static inline unsigned int
315snd_rme96_capture_ptr(rme96_t *rme96)
316{
317 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
318 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
319}
320
321static int
322snd_rme96_playback_silence(snd_pcm_substream_t *substream,
323 int channel, /* not used (interleaved data) */
324 snd_pcm_uframes_t pos,
325 snd_pcm_uframes_t count)
326{
327 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
328 count <<= rme96->playback_frlog;
329 pos <<= rme96->playback_frlog;
330 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
331 0, count);
332 return 0;
333}
334
335static int
336snd_rme96_playback_copy(snd_pcm_substream_t *substream,
337 int channel, /* not used (interleaved data) */
338 snd_pcm_uframes_t pos,
339 void *src,
340 snd_pcm_uframes_t count)
341{
342 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
343 count <<= rme96->playback_frlog;
344 pos <<= rme96->playback_frlog;
345 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
346 count);
347 return 0;
348}
349
350static int
351snd_rme96_capture_copy(snd_pcm_substream_t *substream,
352 int channel, /* not used (interleaved data) */
353 snd_pcm_uframes_t pos,
354 void *dst,
355 snd_pcm_uframes_t count)
356{
357 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
358 count <<= rme96->capture_frlog;
359 pos <<= rme96->capture_frlog;
360 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
361 count);
362 return 0;
363}
364
365/*
366 * Digital output capabilites (S/PDIF)
367 */
368#ifdef TARGET_OS2
369static snd_pcm_hardware_t snd_rme96_playback_spdif_info =
370{
371/* info: */ (SNDRV_PCM_INFO_MMAP |
372 SNDRV_PCM_INFO_MMAP_VALID |
373 SNDRV_PCM_INFO_INTERLEAVED |
374 SNDRV_PCM_INFO_PAUSE),
375/* formats: */ (SNDRV_PCM_FMTBIT_S16_LE |
376 SNDRV_PCM_FMTBIT_S32_LE),
377/* rates: */ (SNDRV_PCM_RATE_32000 |
378 SNDRV_PCM_RATE_44100 |
379 SNDRV_PCM_RATE_48000 |
380 SNDRV_PCM_RATE_64000 |
381 SNDRV_PCM_RATE_88200 |
382 SNDRV_PCM_RATE_96000),
383/* rate_min: */ 32000,
384/* rate_max: */ 96000,
385/* channels_min: */ 2,
386/* channels_max: */ 2,
387/* buffer_bytes_max: */ RME96_BUFFER_SIZE,
388/* period_bytes_min: */ RME96_SMALL_BLOCK_SIZE,
389/* period_bytes_max: */ RME96_LARGE_BLOCK_SIZE,
390/* periods_min: */ RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
391/* periods_max: */ RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
392/* fifo_size: */ 0,
393};
394
395/*
396 * Digital input capabilites (S/PDIF)
397 */
398static snd_pcm_hardware_t snd_rme96_capture_spdif_info =
399{
400/* info: */ (SNDRV_PCM_INFO_MMAP |
401 SNDRV_PCM_INFO_MMAP_VALID |
402 SNDRV_PCM_INFO_INTERLEAVED |
403 SNDRV_PCM_INFO_PAUSE),
404/* formats: */ (SNDRV_PCM_FMTBIT_S16_LE |
405 SNDRV_PCM_FMTBIT_S32_LE),
406/* rates: */ (SNDRV_PCM_RATE_32000 |
407 SNDRV_PCM_RATE_44100 |
408 SNDRV_PCM_RATE_48000 |
409 SNDRV_PCM_RATE_64000 |
410 SNDRV_PCM_RATE_88200 |
411 SNDRV_PCM_RATE_96000),
412/* rate_min: */ 32000,
413/* rate_max: */ 96000,
414/* channels_min: */ 2,
415/* channels_max: */ 2,
416/* buffer_bytes_max: */ RME96_BUFFER_SIZE,
417/* period_bytes_min: */ RME96_SMALL_BLOCK_SIZE,
418/* period_bytes_max: */ RME96_LARGE_BLOCK_SIZE,
419/* periods_min: */ RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
420/* periods_max: */ RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
421/* fifo_size: */ 0,
422};
423
424/*
425 * Digital output capabilites (ADAT)
426 */
427static snd_pcm_hardware_t snd_rme96_playback_adat_info =
428{
429/* info: */ (SNDRV_PCM_INFO_MMAP |
430 SNDRV_PCM_INFO_MMAP_VALID |
431 SNDRV_PCM_INFO_INTERLEAVED |
432 SNDRV_PCM_INFO_PAUSE),
433/* formats: */ SNDRV_PCM_FMTBIT_S16_LE,
434/* rates: */ (SNDRV_PCM_RATE_44100 |
435 SNDRV_PCM_RATE_48000),
436/* rate_min: */ 44100,
437/* rate_max: */ 48000,
438/* channels_min: */ 8,
439/* channels_max: */ 8,
440/* buffer_bytes_max: */ RME96_BUFFER_SIZE,
441/* period_bytes_min: */ RME96_SMALL_BLOCK_SIZE,
442/* period_bytes_max: */ RME96_LARGE_BLOCK_SIZE,
443/* periods_min: */ RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
444/* periods_max: */ RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
445/* fifo_size: */ 0,
446};
447
448/*
449 * Digital input capabilites (ADAT)
450 */
451static snd_pcm_hardware_t snd_rme96_capture_adat_info =
452{
453/* info: */ (SNDRV_PCM_INFO_MMAP |
454 SNDRV_PCM_INFO_MMAP_VALID |
455 SNDRV_PCM_INFO_INTERLEAVED |
456 SNDRV_PCM_INFO_PAUSE),
457/* formats: */ SNDRV_PCM_FMTBIT_S16_LE,
458/* rates: */ (SNDRV_PCM_RATE_44100 |
459 SNDRV_PCM_RATE_48000),
460/* rate_min: */ 44100,
461/* rate_max: */ 48000,
462/* channels_min: */ 8,
463/* channels_max: */ 8,
464/* buffer_bytes_max: */ RME96_BUFFER_SIZE,
465/* period_bytes_min: */ RME96_SMALL_BLOCK_SIZE,
466/* period_bytes_max: */ RME96_LARGE_BLOCK_SIZE,
467/* periods_min: */ RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
468/* periods_max: */ RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
469/* fifo_size: */ 0,
470};
471#else
472static snd_pcm_hardware_t snd_rme96_playback_spdif_info =
473{
474 info: (SNDRV_PCM_INFO_MMAP |
475 SNDRV_PCM_INFO_MMAP_VALID |
476 SNDRV_PCM_INFO_INTERLEAVED |
477 SNDRV_PCM_INFO_PAUSE),
478 formats: (SNDRV_PCM_FMTBIT_S16_LE |
479 SNDRV_PCM_FMTBIT_S32_LE),
480 rates: (SNDRV_PCM_RATE_32000 |
481 SNDRV_PCM_RATE_44100 |
482 SNDRV_PCM_RATE_48000 |
483 SNDRV_PCM_RATE_64000 |
484 SNDRV_PCM_RATE_88200 |
485 SNDRV_PCM_RATE_96000),
486 rate_min: 32000,
487 rate_max: 96000,
488 channels_min: 2,
489 channels_max: 2,
490 buffer_bytes_max: RME96_BUFFER_SIZE,
491 period_bytes_min: RME96_SMALL_BLOCK_SIZE,
492 period_bytes_max: RME96_LARGE_BLOCK_SIZE,
493 periods_min: RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
494 periods_max: RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
495 fifo_size: 0,
496};
497
498/*
499 * Digital input capabilites (S/PDIF)
500 */
501static snd_pcm_hardware_t snd_rme96_capture_spdif_info =
502{
503 info: (SNDRV_PCM_INFO_MMAP |
504 SNDRV_PCM_INFO_MMAP_VALID |
505 SNDRV_PCM_INFO_INTERLEAVED |
506 SNDRV_PCM_INFO_PAUSE),
507 formats: (SNDRV_PCM_FMTBIT_S16_LE |
508 SNDRV_PCM_FMTBIT_S32_LE),
509 rates: (SNDRV_PCM_RATE_32000 |
510 SNDRV_PCM_RATE_44100 |
511 SNDRV_PCM_RATE_48000 |
512 SNDRV_PCM_RATE_64000 |
513 SNDRV_PCM_RATE_88200 |
514 SNDRV_PCM_RATE_96000),
515 rate_min: 32000,
516 rate_max: 96000,
517 channels_min: 2,
518 channels_max: 2,
519 buffer_bytes_max: RME96_BUFFER_SIZE,
520 period_bytes_min: RME96_SMALL_BLOCK_SIZE,
521 period_bytes_max: RME96_LARGE_BLOCK_SIZE,
522 periods_min: RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
523 periods_max: RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
524 fifo_size: 0,
525};
526
527/*
528 * Digital output capabilites (ADAT)
529 */
530static snd_pcm_hardware_t snd_rme96_playback_adat_info =
531{
532 info: (SNDRV_PCM_INFO_MMAP |
533 SNDRV_PCM_INFO_MMAP_VALID |
534 SNDRV_PCM_INFO_INTERLEAVED |
535 SNDRV_PCM_INFO_PAUSE),
536 formats: SNDRV_PCM_FMTBIT_S16_LE,
537 rates: (SNDRV_PCM_RATE_44100 |
538 SNDRV_PCM_RATE_48000),
539 rate_min: 44100,
540 rate_max: 48000,
541 channels_min: 8,
542 channels_max: 8,
543 buffer_bytes_max: RME96_BUFFER_SIZE,
544 period_bytes_min: RME96_SMALL_BLOCK_SIZE,
545 period_bytes_max: RME96_LARGE_BLOCK_SIZE,
546 periods_min: RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
547 periods_max: RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
548 fifo_size: 0,
549};
550
551/*
552 * Digital input capabilites (ADAT)
553 */
554static snd_pcm_hardware_t snd_rme96_capture_adat_info =
555{
556 info: (SNDRV_PCM_INFO_MMAP |
557 SNDRV_PCM_INFO_MMAP_VALID |
558 SNDRV_PCM_INFO_INTERLEAVED |
559 SNDRV_PCM_INFO_PAUSE),
560 formats: SNDRV_PCM_FMTBIT_S16_LE,
561 rates: (SNDRV_PCM_RATE_44100 |
562 SNDRV_PCM_RATE_48000),
563 rate_min: 44100,
564 rate_max: 48000,
565 channels_min: 8,
566 channels_max: 8,
567 buffer_bytes_max: RME96_BUFFER_SIZE,
568 period_bytes_min: RME96_SMALL_BLOCK_SIZE,
569 period_bytes_max: RME96_LARGE_BLOCK_SIZE,
570 periods_min: RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
571 periods_max: RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
572 fifo_size: 0,
573};
574#endif
575
576/*
577 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
578 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
579 * on the falling edge of CCLK and be stable on the rising edge. The rising
580 * edge of CLATCH after the last data bit clocks in the whole data word.
581 * A fast processor could probably drive the SPI interface faster than the
582 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
583 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
584 *
585 * NOTE: increased delay from 1 to 10, since there where problems setting
586 * the volume.
587 */
588static void
589snd_rme96_write_SPI(rme96_t *rme96, u16 val)
590{
591 int i;
592
593 for (i = 0; i < 16; i++) {
594 if (val & 0x8000) {
595 rme96->areg |= RME96_AR_CDATA;
596 } else {
597 rme96->areg &= ~RME96_AR_CDATA;
598 }
599 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
600 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
601 udelay(10);
602 rme96->areg |= RME96_AR_CCLK;
603 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
604 udelay(10);
605 val <<= 1;
606 }
607 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
608 rme96->areg |= RME96_AR_CLATCH;
609 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
610 udelay(10);
611 rme96->areg &= ~RME96_AR_CLATCH;
612 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
613}
614
615static void
616snd_rme96_apply_dac_volume(rme96_t *rme96)
617{
618 if (RME96_DAC_IS_1852(rme96)) {
619 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
620 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
621 } else if (RME96_DAC_IS_1855(rme96)) {
622 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
623 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
624 }
625}
626
627static void
628snd_rme96_reset_dac(rme96_t *rme96)
629{
630 writel(rme96->wcreg | RME96_WCR_PD,
631 rme96->iobase + RME96_IO_CONTROL_REGISTER);
632 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
633}
634
635static int
636snd_rme96_getmontracks(rme96_t *rme96)
637{
638 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
639 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
640}
641
642static int
643snd_rme96_setmontracks(rme96_t *rme96,
644 int montracks)
645{
646 if (montracks & 1) {
647 rme96->wcreg |= RME96_WCR_MONITOR_0;
648 } else {
649 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
650 }
651 if (montracks & 2) {
652 rme96->wcreg |= RME96_WCR_MONITOR_1;
653 } else {
654 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
655 }
656 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
657 return 0;
658}
659
660static int
661snd_rme96_getattenuation(rme96_t *rme96)
662{
663 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
664 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
665}
666
667static int
668snd_rme96_setattenuation(rme96_t *rme96,
669 int attenuation)
670{
671 switch (attenuation) {
672 case 0:
673 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
674 ~RME96_WCR_GAIN_1;
675 break;
676 case 1:
677 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
678 ~RME96_WCR_GAIN_1;
679 break;
680 case 2:
681 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
682 RME96_WCR_GAIN_1;
683 break;
684 case 3:
685 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
686 RME96_WCR_GAIN_1;
687 break;
688 default:
689 return -EINVAL;
690 }
691 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
692 return 0;
693}
694
695
696static int
697snd_rme96_playback_getrate(rme96_t *rme96)
698{
699 int rate;
700
701 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
702 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
703 switch (rate) {
704 case 1:
705 rate = 32000;
706 break;
707 case 2:
708 rate = 44100;
709 break;
710 case 3:
711 rate = 48000;
712 break;
713 default:
714 return -1;
715 }
716 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
717}
718
719static int
720snd_rme96_capture_getrate(rme96_t *rme96,
721 int *is_adat)
722{
723 int n, rate;
724
725 *is_adat = 0;
726 if (rme96->areg & RME96_AR_ANALOG) {
727 /* Analog input, overrides S/PDIF setting */
728 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
729 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
730 switch (n) {
731 case 1:
732 rate = 32000;
733 break;
734 case 2:
735 rate = 44100;
736 break;
737 case 3:
738 rate = 48000;
739 break;
740 default:
741 return -1;
742 }
743 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
744 }
745
746 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
747 if (rme96->rcreg & RME96_RCR_LOCK) {
748 /* ADAT rate */
749 *is_adat = 1;
750 if (rme96->rcreg & RME96_RCR_T_OUT) {
751 return 48000;
752 }
753 return 44100;
754 }
755
756 if (rme96->rcreg & RME96_RCR_VERF) {
757 return -1;
758 }
759
760 /* S/PDIF rate */
761 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
762 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
763 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
764
765 switch (n) {
766 case 0:
767 if (rme96->rcreg & RME96_RCR_T_OUT) {
768 return 64000;
769 }
770 return -1;
771 case 3: return 96000;
772 case 4: return 88200;
773 case 5: return 48000;
774 case 6: return 44100;
775 case 7: return 32000;
776 default:
777 break;
778 }
779 return -1;
780}
781
782static int
783snd_rme96_playback_setrate(rme96_t *rme96,
784 int rate)
785{
786 int ds;
787
788 ds = rme96->wcreg & RME96_WCR_DS;
789 switch (rate) {
790 case 32000:
791 rme96->wcreg &= ~RME96_WCR_DS;
792 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
793 ~RME96_WCR_FREQ_1;
794 break;
795 case 44100:
796 rme96->wcreg &= ~RME96_WCR_DS;
797 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
798 ~RME96_WCR_FREQ_0;
799 break;
800 case 48000:
801 rme96->wcreg &= ~RME96_WCR_DS;
802 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
803 RME96_WCR_FREQ_1;
804 break;
805 case 64000:
806 rme96->wcreg |= RME96_WCR_DS;
807 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
808 ~RME96_WCR_FREQ_1;
809 break;
810 case 88200:
811 rme96->wcreg |= RME96_WCR_DS;
812 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
813 ~RME96_WCR_FREQ_0;
814 break;
815 case 96000:
816 rme96->wcreg |= RME96_WCR_DS;
817 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
818 RME96_WCR_FREQ_1;
819 break;
820 default:
821 return -EINVAL;
822 }
823 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
824 (ds && !(rme96->wcreg & RME96_WCR_DS)))
825 {
826 /* change to/from double-speed: reset the DAC (if available) */
827 snd_rme96_reset_dac(rme96);
828 } else {
829 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
830 }
831 return 0;
832}
833
834static int
835snd_rme96_capture_analog_setrate(rme96_t *rme96,
836 int rate)
837{
838 switch (rate) {
839 case 32000:
840 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
841 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
842 break;
843 case 44100:
844 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
845 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
846 break;
847 case 48000:
848 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
849 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
850 break;
851 case 64000:
852 if (rme96->rev < 4) {
853 return -EINVAL;
854 }
855 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
856 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
857 break;
858 case 88200:
859 if (rme96->rev < 4) {
860 return -EINVAL;
861 }
862 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
863 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
864 break;
865 case 96000:
866 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
867 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
868 break;
869 default:
870 return -EINVAL;
871 }
872 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
873 return 0;
874}
875
876static int
877snd_rme96_setclockmode(rme96_t *rme96,
878 int mode)
879{
880 switch (mode) {
881 case RME96_CLOCKMODE_SLAVE:
882 rme96->wcreg &= ~RME96_WCR_MASTER;
883 rme96->areg &= ~RME96_AR_WSEL;
884 break;
885 case RME96_CLOCKMODE_MASTER:
886 rme96->wcreg |= RME96_WCR_MASTER;
887 rme96->areg &= ~RME96_AR_WSEL;
888 break;
889 case RME96_CLOCKMODE_WORDCLOCK:
890 /* Word clock is a master mode */
891 rme96->wcreg |= RME96_WCR_MASTER;
892 rme96->areg |= RME96_AR_WSEL;
893 break;
894 default:
895 return -EINVAL;
896 }
897 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
898 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
899 return 0;
900}
901
902static int
903snd_rme96_getclockmode(rme96_t *rme96)
904{
905 if (rme96->areg & RME96_AR_WSEL) {
906 return RME96_CLOCKMODE_WORDCLOCK;
907 }
908 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
909 RME96_CLOCKMODE_SLAVE;
910}
911
912static int
913snd_rme96_setinputtype(rme96_t *rme96,
914 int type)
915{
916 int n;
917
918 switch (type) {
919 case RME96_INPUT_OPTICAL:
920 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
921 ~RME96_WCR_INP_1;
922 break;
923 case RME96_INPUT_COAXIAL:
924 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
925 ~RME96_WCR_INP_1;
926 break;
927 case RME96_INPUT_INTERNAL:
928 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
929 RME96_WCR_INP_1;
930 break;
931 case RME96_INPUT_XLR:
932 if (rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST ||
933 rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PRO ||
934 (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST &&
935 rme96->rev > 4))
936 {
937 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
938 return -EINVAL;
939 }
940 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
941 RME96_WCR_INP_1;
942 break;
943 case RME96_INPUT_ANALOG:
944 if (!RME96_HAS_ANALOG_IN(rme96)) {
945 return -EINVAL;
946 }
947 rme96->areg |= RME96_AR_ANALOG;
948 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
949 if (rme96->rev < 4) {
950 /*
951 * Revision less than 004 does not support 64 and
952 * 88.2 kHz
953 */
954 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
955 snd_rme96_capture_analog_setrate(rme96, 44100);
956 }
957 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
958 snd_rme96_capture_analog_setrate(rme96, 32000);
959 }
960 }
961 return 0;
962 default:
963 return -EINVAL;
964 }
965 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
966 rme96->areg &= ~RME96_AR_ANALOG;
967 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
968 }
969 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
970 return 0;
971}
972
973static int
974snd_rme96_getinputtype(rme96_t *rme96)
975{
976 if (rme96->areg & RME96_AR_ANALOG) {
977 return RME96_INPUT_ANALOG;
978 }
979 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
980 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
981}
982
983static void
984snd_rme96_setframelog(rme96_t *rme96,
985 int n_channels,
986 int is_playback)
987{
988 int frlog;
989
990 if (n_channels == 2) {
991 frlog = 1;
992 } else {
993 /* assume 8 channels */
994 frlog = 3;
995 }
996 if (is_playback) {
997 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
998 rme96->playback_frlog = frlog;
999 } else {
1000 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
1001 rme96->capture_frlog = frlog;
1002 }
1003}
1004
1005static int
1006snd_rme96_playback_setformat(rme96_t *rme96,
1007 int format)
1008{
1009 switch (format) {
1010 case SNDRV_PCM_FORMAT_S16_LE:
1011 rme96->wcreg &= ~RME96_WCR_MODE24;
1012 break;
1013 case SNDRV_PCM_FORMAT_S32_LE:
1014 rme96->wcreg |= RME96_WCR_MODE24;
1015 break;
1016 default:
1017 return -EINVAL;
1018 }
1019 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1020 return 0;
1021}
1022
1023static int
1024snd_rme96_capture_setformat(rme96_t *rme96,
1025 int format)
1026{
1027 switch (format) {
1028 case SNDRV_PCM_FORMAT_S16_LE:
1029 rme96->wcreg &= ~RME96_WCR_MODE24_2;
1030 break;
1031 case SNDRV_PCM_FORMAT_S32_LE:
1032 rme96->wcreg |= RME96_WCR_MODE24_2;
1033 break;
1034 default:
1035 return -EINVAL;
1036 }
1037 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1038 return 0;
1039}
1040
1041static void
1042snd_rme96_set_period_properties(rme96_t *rme96,
1043 size_t period_bytes)
1044{
1045 switch (period_bytes) {
1046 case RME96_LARGE_BLOCK_SIZE:
1047 rme96->wcreg &= ~RME96_WCR_ISEL;
1048 break;
1049 case RME96_SMALL_BLOCK_SIZE:
1050 rme96->wcreg |= RME96_WCR_ISEL;
1051 break;
1052 default:
1053 snd_BUG();
1054 break;
1055 }
1056 rme96->wcreg &= ~RME96_WCR_IDIS;
1057 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1058}
1059
1060static int
1061snd_rme96_playback_hw_params(snd_pcm_substream_t *substream,
1062 snd_pcm_hw_params_t *params)
1063{
1064 unsigned long flags;
1065 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1066 int err;
1067
1068 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params))) < 0)
1069 return err;
1070 spin_lock_irqsave(&rme96->lock, flags);
1071 if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
1072 spin_unlock_irqrestore(&rme96->lock, flags);
1073 return err;
1074 }
1075 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
1076 spin_unlock_irqrestore(&rme96->lock, flags);
1077 return err;
1078 }
1079 snd_rme96_setframelog(rme96, params_channels(params), 1);
1080 if (rme96->capture_periodsize != 0) {
1081 if (params_period_size(params) << rme96->playback_frlog !=
1082 rme96->capture_periodsize)
1083 {
1084 spin_unlock_irqrestore(&rme96->lock, flags);
1085 return -EBUSY;
1086 }
1087 }
1088 rme96->playback_periodsize =
1089 params_period_size(params) << rme96->playback_frlog;
1090 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1091 /* S/PDIF setup */
1092 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1093 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1094 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1095 }
1096 spin_unlock_irqrestore(&rme96->lock, flags);
1097
1098 return 0;
1099}
1100
1101static int
1102snd_rme96_playback_hw_free(snd_pcm_substream_t *substream)
1103{
1104 snd_pcm_lib_free_pages(substream);
1105 return 0;
1106}
1107
1108static int
1109snd_rme96_capture_hw_params(snd_pcm_substream_t *substream,
1110 snd_pcm_hw_params_t *params)
1111{
1112 unsigned long flags;
1113 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1114 int err, isadat;
1115
1116 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params))) < 0)
1117 return err;
1118 spin_lock_irqsave(&rme96->lock, flags);
1119 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1120 spin_unlock_irqrestore(&rme96->lock, flags);
1121 return err;
1122 }
1123 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1124 if ((err = snd_rme96_capture_analog_setrate(rme96,
1125 params_rate(params))) < 0)
1126 {
1127 spin_unlock_irqrestore(&rme96->lock, flags);
1128 return err;
1129 }
1130 } else if (params_rate(params) != snd_rme96_capture_getrate(rme96, &isadat)) {
1131 spin_unlock_irqrestore(&rme96->lock, flags);
1132 return -EBUSY;
1133 }
1134 snd_rme96_setframelog(rme96, params_channels(params), 0);
1135 if (rme96->playback_periodsize != 0) {
1136 if (params_period_size(params) << rme96->capture_frlog !=
1137 rme96->playback_periodsize)
1138 {
1139 spin_unlock_irqrestore(&rme96->lock, flags);
1140 return -EBUSY;
1141 }
1142 }
1143 rme96->capture_periodsize =
1144 params_period_size(params) << rme96->capture_frlog;
1145 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1146 spin_unlock_irqrestore(&rme96->lock, flags);
1147
1148 return 0;
1149}
1150
1151static int
1152snd_rme96_capture_hw_free(snd_pcm_substream_t *substream)
1153{
1154 snd_pcm_lib_free_pages(substream);
1155 return 0;
1156}
1157
1158static void
1159snd_rme96_playback_start(rme96_t *rme96,
1160 int from_pause)
1161{
1162 snd_pcm_runtime_t *runtime = rme96->playback_substream->runtime;
1163
1164 if (!from_pause) {
1165 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1166 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1167 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
1168 runtime->dma_area,
1169 rme96->playback_periodsize);
1170 rme96->playback_ptr = rme96->playback_periodsize;
1171 }
1172 }
1173
1174 rme96->wcreg |= RME96_WCR_START;
1175 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1176}
1177
1178static void
1179snd_rme96_capture_start(rme96_t *rme96,
1180 int from_pause)
1181{
1182 if (!from_pause) {
1183 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1184 }
1185
1186 rme96->wcreg |= RME96_WCR_START_2;
1187 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1188}
1189
1190static void
1191snd_rme96_playback_stop(rme96_t *rme96)
1192{
1193 /*
1194 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1195 * the hardware will not stop generating interrupts
1196 */
1197 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1198 if (rme96->rcreg & RME96_RCR_IRQ) {
1199 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1200 }
1201 rme96->wcreg &= ~RME96_WCR_START;
1202 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1203}
1204
1205static void
1206snd_rme96_capture_stop(rme96_t *rme96)
1207{
1208 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1209 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1210 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1211 }
1212 rme96->wcreg &= ~RME96_WCR_START_2;
1213 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1214}
1215
1216static void
1217snd_rme96_interrupt(int irq,
1218 void *dev_id,
1219 struct pt_regs *regs)
1220{
1221 rme96_t *rme96 = (rme96_t *)dev_id;
1222 snd_pcm_runtime_t *runtime;
1223
1224 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1225 /* fastpath out, to ease interrupt sharing */
1226 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1227 (rme96->rcreg & RME96_RCR_IRQ_2)))
1228 {
1229 return;
1230 }
1231
1232 if (rme96->rcreg & RME96_RCR_IRQ) {
1233 /* playback */
1234 runtime = rme96->playback_substream->runtime;
1235 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1236 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER +
1237 rme96->playback_ptr,
1238 runtime->dma_area + rme96->playback_ptr,
1239 rme96->playback_periodsize);
1240 rme96->playback_ptr += rme96->playback_periodsize;
1241 if (rme96->playback_ptr == RME96_BUFFER_SIZE) {
1242 rme96->playback_ptr = 0;
1243 }
1244 }
1245 snd_pcm_period_elapsed(rme96->playback_substream);
1246 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1247 }
1248 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1249 /* capture */
1250 runtime = rme96->capture_substream->runtime;
1251 if (runtime->access == SNDRV_PCM_ACCESS_MMAP_INTERLEAVED) {
1252 memcpy_fromio(runtime->dma_area + rme96->capture_ptr,
1253 rme96->iobase + RME96_IO_REC_BUFFER +
1254 rme96->capture_ptr,
1255 rme96->capture_periodsize);
1256 rme96->capture_ptr += rme96->capture_periodsize;
1257 if (rme96->capture_ptr == RME96_BUFFER_SIZE) {
1258 rme96->capture_ptr = 0;
1259 }
1260 }
1261 snd_pcm_period_elapsed(rme96->capture_substream);
1262 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1263 }
1264}
1265
1266static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1267
1268#define PERIOD_BYTES sizeof(period_bytes) / sizeof(period_bytes[0])
1269
1270#ifdef TARGET_OS2
1271static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
1272 PERIOD_BYTES,
1273 period_bytes,
1274 0
1275};
1276#else
1277static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
1278 count: PERIOD_BYTES,
1279 list: period_bytes,
1280 mask: 0
1281};
1282#endif
1283
1284static int
1285snd_rme96_playback_spdif_open(snd_pcm_substream_t *substream)
1286{
1287 unsigned long flags;
1288 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1289 snd_pcm_runtime_t *runtime = substream->runtime;
1290
1291 snd_pcm_set_sync(substream);
1292
1293 spin_lock_irqsave(&rme96->lock, flags);
1294 rme96->wcreg &= ~RME96_WCR_ADAT;
1295 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1296 rme96->playback_substream = substream;
1297 rme96->playback_ptr = 0;
1298 spin_unlock_irqrestore(&rme96->lock, flags);
1299
1300 runtime->hw = snd_rme96_playback_spdif_info;
1301 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1302 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1303
1304 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1305 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1306 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1307 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1308 return 0;
1309}
1310
1311static int
1312snd_rme96_capture_spdif_open(snd_pcm_substream_t *substream)
1313{
1314 unsigned long flags;
1315 int isadat;
1316 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1317 snd_pcm_runtime_t *runtime = substream->runtime;
1318
1319 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1320 if (snd_rme96_capture_getrate(rme96, &isadat) < 0) {
1321 /* no input */
1322 return -EIO;
1323 }
1324 if (isadat) {
1325 /* ADAT input */
1326 return -EBUSY;
1327 }
1328 snd_pcm_set_sync(substream);
1329
1330 spin_lock_irqsave(&rme96->lock, flags);
1331 rme96->capture_substream = substream;
1332 rme96->capture_ptr = 0;
1333 spin_unlock_irqrestore(&rme96->lock, flags);
1334
1335 runtime->hw = snd_rme96_capture_spdif_info;
1336
1337 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1338 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1339
1340 return 0;
1341}
1342
1343static int
1344snd_rme96_playback_adat_open(snd_pcm_substream_t *substream)
1345{
1346 unsigned long flags;
1347 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1348 snd_pcm_runtime_t *runtime = substream->runtime;
1349
1350 snd_pcm_set_sync(substream);
1351
1352 spin_lock_irqsave(&rme96->lock, flags);
1353 rme96->wcreg |= RME96_WCR_ADAT;
1354 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1355 rme96->playback_substream = substream;
1356 rme96->playback_ptr = 0;
1357 spin_unlock_irqrestore(&rme96->lock, flags);
1358
1359 runtime->hw = snd_rme96_playback_adat_info;
1360 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1361 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1362 return 0;
1363}
1364
1365static int
1366snd_rme96_capture_adat_open(snd_pcm_substream_t *substream)
1367{
1368 unsigned long flags;
1369 int isadat;
1370 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1371 snd_pcm_runtime_t *runtime = substream->runtime;
1372
1373 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1374 if (snd_rme96_capture_getrate(rme96, &isadat) < 0) {
1375 /* no input */
1376 return -EIO;
1377 }
1378 if (!isadat) {
1379 /* S/PDIF input */
1380 return -EBUSY;
1381 }
1382 snd_pcm_set_sync(substream);
1383
1384 spin_lock_irqsave(&rme96->lock, flags);
1385 rme96->capture_substream = substream;
1386 rme96->capture_ptr = 0;
1387 spin_unlock_irqrestore(&rme96->lock, flags);
1388
1389 runtime->hw = snd_rme96_capture_adat_info;
1390 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1391 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1392 return 0;
1393}
1394
1395static int
1396snd_rme96_playback_close(snd_pcm_substream_t *substream)
1397{
1398 unsigned long flags;
1399 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1400 int spdif = 0;
1401
1402 spin_lock_irqsave(&rme96->lock, flags);
1403 rme96->playback_substream = NULL;
1404 rme96->playback_periodsize = 0;
1405 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1406 spin_unlock_irqrestore(&rme96->lock, flags);
1407 if (spdif) {
1408 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1409 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1410 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1411 }
1412 return 0;
1413}
1414
1415static int
1416snd_rme96_capture_close(snd_pcm_substream_t *substream)
1417{
1418 unsigned long flags;
1419 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1420
1421 spin_lock_irqsave(&rme96->lock, flags);
1422 rme96->capture_substream = NULL;
1423 rme96->capture_periodsize = 0;
1424 spin_unlock_irqrestore(&rme96->lock, flags);
1425 return 0;
1426}
1427
1428static int
1429snd_rme96_playback_prepare(snd_pcm_substream_t *substream)
1430{
1431 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1432 unsigned long flags;
1433
1434 spin_lock_irqsave(&rme96->lock, flags);
1435 if (RME96_ISPLAYING(rme96)) {
1436 snd_rme96_playback_stop(rme96);
1437 }
1438 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1439 spin_unlock_irqrestore(&rme96->lock, flags);
1440 return 0;
1441}
1442
1443static int
1444snd_rme96_capture_prepare(snd_pcm_substream_t *substream)
1445{
1446 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1447 unsigned long flags;
1448
1449 spin_lock_irqsave(&rme96->lock, flags);
1450 if (RME96_ISRECORDING(rme96)) {
1451 snd_rme96_capture_stop(rme96);
1452 }
1453 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1454 spin_unlock_irqrestore(&rme96->lock, flags);
1455 return 0;
1456}
1457
1458static int
1459snd_rme96_playback_trigger(snd_pcm_substream_t *substream,
1460 int cmd)
1461{
1462 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1463
1464 switch (cmd) {
1465 case SNDRV_PCM_TRIGGER_START:
1466 if (!RME96_ISPLAYING(rme96)) {
1467 if (substream != rme96->playback_substream) {
1468 return -EBUSY;
1469 }
1470 snd_rme96_playback_start(rme96, 0);
1471 }
1472 break;
1473
1474 case SNDRV_PCM_TRIGGER_STOP:
1475 if (RME96_ISPLAYING(rme96)) {
1476 if (substream != rme96->playback_substream) {
1477 return -EBUSY;
1478 }
1479 snd_rme96_playback_stop(rme96);
1480 }
1481 break;
1482
1483 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1484 if (RME96_ISPLAYING(rme96)) {
1485 snd_rme96_playback_stop(rme96);
1486 }
1487 break;
1488
1489 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1490 if (!RME96_ISPLAYING(rme96)) {
1491 snd_rme96_playback_start(rme96, 1);
1492 }
1493 break;
1494
1495 default:
1496 return -EINVAL;
1497 }
1498 return 0;
1499}
1500
1501static int
1502snd_rme96_capture_trigger(snd_pcm_substream_t *substream,
1503 int cmd)
1504{
1505 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1506
1507 switch (cmd) {
1508 case SNDRV_PCM_TRIGGER_START:
1509 if (!RME96_ISRECORDING(rme96)) {
1510 if (substream != rme96->capture_substream) {
1511 return -EBUSY;
1512 }
1513 snd_rme96_capture_start(rme96, 0);
1514 }
1515 break;
1516
1517 case SNDRV_PCM_TRIGGER_STOP:
1518 if (RME96_ISRECORDING(rme96)) {
1519 if (substream != rme96->capture_substream) {
1520 return -EBUSY;
1521 }
1522 snd_rme96_capture_stop(rme96);
1523 }
1524 break;
1525
1526 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1527 if (RME96_ISRECORDING(rme96)) {
1528 snd_rme96_capture_stop(rme96);
1529 }
1530 break;
1531
1532 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1533 if (!RME96_ISRECORDING(rme96)) {
1534 snd_rme96_capture_start(rme96, 1);
1535 }
1536 break;
1537
1538 default:
1539 return -EINVAL;
1540 }
1541
1542 return 0;
1543}
1544
1545static snd_pcm_uframes_t
1546snd_rme96_playback_pointer(snd_pcm_substream_t *substream)
1547{
1548 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1549 return snd_rme96_playback_ptr(rme96);
1550}
1551
1552static snd_pcm_uframes_t
1553snd_rme96_capture_pointer(snd_pcm_substream_t *substream)
1554{
1555 rme96_t *rme96 = _snd_pcm_substream_chip(substream);
1556 return snd_rme96_capture_ptr(rme96);
1557}
1558
1559#ifdef TARGET_OS2
1560static snd_pcm_ops_t snd_rme96_playback_spdif_ops = {
1561/* open: */ snd_rme96_playback_spdif_open,
1562/* close: */ snd_rme96_playback_close,
1563/* ioctl: */ snd_pcm_lib_ioctl,
1564/* hw_params:*/ snd_rme96_playback_hw_params,
1565/* hw_free: */ snd_rme96_playback_hw_free,
1566/* prepare: */ snd_rme96_playback_prepare,
1567/* trigger: */ snd_rme96_playback_trigger,
1568/* pointer: */ snd_rme96_playback_pointer,
1569/* copy: */ snd_rme96_playback_copy,
1570/* silence: */ snd_rme96_playback_silence,
1571};
1572
1573static snd_pcm_ops_t snd_rme96_capture_spdif_ops = {
1574/* open: */ snd_rme96_capture_spdif_open,
1575/* close: */ snd_rme96_capture_close,
1576/* ioctl: */ snd_pcm_lib_ioctl,
1577/* hw_params:*/ snd_rme96_capture_hw_params,
1578/* hw_free: */ snd_rme96_capture_hw_free,
1579/* prepare: */ snd_rme96_capture_prepare,
1580/* trigger: */ snd_rme96_capture_trigger,
1581/* pointer: */ snd_rme96_capture_pointer,
1582/* copy: */ snd_rme96_capture_copy,
1583 0
1584};
1585
1586static snd_pcm_ops_t snd_rme96_playback_adat_ops = {
1587/* open: */ snd_rme96_playback_adat_open,
1588/* close: */ snd_rme96_playback_close,
1589/* ioctl: */ snd_pcm_lib_ioctl,
1590/* hw_params:*/ snd_rme96_playback_hw_params,
1591/* hw_free: */ snd_rme96_playback_hw_free,
1592/* prepare: */ snd_rme96_playback_prepare,
1593/* trigger: */ snd_rme96_playback_trigger,
1594/* pointer: */ snd_rme96_playback_pointer,
1595/* copy: */ snd_rme96_playback_copy,
1596/* silence: */ snd_rme96_playback_silence,
1597};
1598
1599static snd_pcm_ops_t snd_rme96_capture_adat_ops = {
1600/* open: */ snd_rme96_capture_adat_open,
1601/* close: */ snd_rme96_capture_close,
1602/* ioctl: */ snd_pcm_lib_ioctl,
1603/* hw_params:*/ snd_rme96_capture_hw_params,
1604/* hw_free: */ snd_rme96_capture_hw_free,
1605/* prepare: */ snd_rme96_capture_prepare,
1606/* trigger: */ snd_rme96_capture_trigger,
1607/* pointer: */ snd_rme96_capture_pointer,
1608/* copy: */ snd_rme96_capture_copy,
1609};
1610#else
1611static snd_pcm_ops_t snd_rme96_playback_spdif_ops = {
1612 open: snd_rme96_playback_spdif_open,
1613 close: snd_rme96_playback_close,
1614 ioctl: snd_pcm_lib_ioctl,
1615 hw_params: snd_rme96_playback_hw_params,
1616 hw_free: snd_rme96_playback_hw_free,
1617 prepare: snd_rme96_playback_prepare,
1618 trigger: snd_rme96_playback_trigger,
1619 pointer: snd_rme96_playback_pointer,
1620 copy: snd_rme96_playback_copy,
1621 silence: snd_rme96_playback_silence,
1622};
1623
1624static snd_pcm_ops_t snd_rme96_capture_spdif_ops = {
1625 open: snd_rme96_capture_spdif_open,
1626 close: snd_rme96_capture_close,
1627 ioctl: snd_pcm_lib_ioctl,
1628 hw_params: snd_rme96_capture_hw_params,
1629 hw_free: snd_rme96_capture_hw_free,
1630 prepare: snd_rme96_capture_prepare,
1631 trigger: snd_rme96_capture_trigger,
1632 pointer: snd_rme96_capture_pointer,
1633 copy: snd_rme96_capture_copy,
1634};
1635
1636static snd_pcm_ops_t snd_rme96_playback_adat_ops = {
1637 open: snd_rme96_playback_adat_open,
1638 close: snd_rme96_playback_close,
1639 ioctl: snd_pcm_lib_ioctl,
1640 hw_params: snd_rme96_playback_hw_params,
1641 hw_free: snd_rme96_playback_hw_free,
1642 prepare: snd_rme96_playback_prepare,
1643 trigger: snd_rme96_playback_trigger,
1644 pointer: snd_rme96_playback_pointer,
1645 copy: snd_rme96_playback_copy,
1646 silence: snd_rme96_playback_silence,
1647};
1648
1649static snd_pcm_ops_t snd_rme96_capture_adat_ops = {
1650 open: snd_rme96_capture_adat_open,
1651 close: snd_rme96_capture_close,
1652 ioctl: snd_pcm_lib_ioctl,
1653 hw_params: snd_rme96_capture_hw_params,
1654 hw_free: snd_rme96_capture_hw_free,
1655 prepare: snd_rme96_capture_prepare,
1656 trigger: snd_rme96_capture_trigger,
1657 pointer: snd_rme96_capture_pointer,
1658 copy: snd_rme96_capture_copy,
1659};
1660#endif
1661
1662static void
1663snd_rme96_free(void *private_data)
1664{
1665 rme96_t *rme96 = (rme96_t *)private_data;
1666
1667 if (rme96 == NULL) {
1668 return;
1669 }
1670 if (rme96->irq >= 0) {
1671 snd_rme96_playback_stop(rme96);
1672 snd_rme96_capture_stop(rme96);
1673 rme96->areg &= ~RME96_AR_DAC_EN;
1674 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1675 snd_rme96_proc_done(rme96);
1676 free_irq(rme96->irq, (void *)rme96);
1677 rme96->irq = -1;
1678 }
1679 if (rme96->iobase) {
1680 iounmap((void *)rme96->iobase);
1681 rme96->iobase = 0;
1682 }
1683 if (rme96->res_port != NULL) {
1684 release_resource(rme96->res_port);
1685 rme96->res_port = NULL;
1686 }
1687}
1688
1689static void
1690snd_rme96_free_spdif_pcm(snd_pcm_t *pcm)
1691{
1692 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1693 rme96->spdif_pcm = NULL;
1694 snd_pcm_lib_preallocate_free_for_all(pcm);
1695}
1696
1697static void
1698snd_rme96_free_adat_pcm(snd_pcm_t *pcm)
1699{
1700 rme96_t *rme96 = (rme96_t *) pcm->private_data;
1701 rme96->adat_pcm = NULL;
1702 snd_pcm_lib_preallocate_free_for_all(pcm);
1703}
1704
1705static int __init
1706snd_rme96_create(rme96_t *rme96)
1707{
1708 struct pci_dev *pci = rme96->pci;
1709 int err;
1710
1711 rme96->irq = -1;
1712
1713 if ((err = pci_enable_device(pci)) < 0)
1714 return err;
1715
1716 rme96->port = pci_resource_start(rme96->pci, 0);
1717
1718 if ((rme96->res_port = request_mem_region(rme96->port, RME96_IO_SIZE, "RME96")) == NULL) {
1719 snd_printk("unable to grab memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1720 return -EBUSY;
1721 }
1722
1723 if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) {
1724 snd_printk("unable to grab IRQ %d\n", pci->irq);
1725 return -EBUSY;
1726 }
1727 rme96->irq = pci->irq;
1728
1729 spin_lock_init(&rme96->lock);
1730 if ((rme96->iobase = (unsigned long) ioremap(rme96->port, RME96_IO_SIZE)) == 0) {
1731 snd_printk("unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1732 return -ENOMEM;
1733 }
1734
1735 /* read the card's revision number */
1736 pci_read_config_byte(pci, 8, &rme96->rev);
1737
1738 /* set up ALSA pcm device for S/PDIF */
1739 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1740 1, 1, &rme96->spdif_pcm)) < 0)
1741 {
1742 return err;
1743 }
1744 rme96->spdif_pcm->private_data = rme96;
1745 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1746 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1747 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1748 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1749
1750 rme96->spdif_pcm->info_flags = 0;
1751
1752 snd_pcm_lib_preallocate_pages_for_all(rme96->spdif_pcm, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE, GFP_KERNEL);
1753
1754 /* set up ALSA pcm device for ADAT */
1755 if (pci->device == PCI_DEVICE_ID_DIGI96) {
1756 /* ADAT is not available on the base model */
1757 rme96->adat_pcm = NULL;
1758 } else {
1759 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1760 1, 1, &rme96->adat_pcm)) < 0)
1761 {
1762 return err;
1763 }
1764 rme96->adat_pcm->private_data = rme96;
1765 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1766 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1767 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1768 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1769
1770 rme96->adat_pcm->info_flags = 0;
1771
1772 snd_pcm_lib_preallocate_pages_for_all(rme96->adat_pcm, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE, GFP_KERNEL);
1773 }
1774
1775 rme96->playback_periodsize = 0;
1776 rme96->capture_periodsize = 0;
1777
1778 /* make sure playback/capture is stopped, if by some reason active */
1779 snd_rme96_playback_stop(rme96);
1780 snd_rme96_capture_stop(rme96);
1781
1782 /* set default values in registers */
1783 rme96->wcreg =
1784 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1785 RME96_WCR_SEL | /* normal playback */
1786 RME96_WCR_MASTER | /* set to master clock mode */
1787 RME96_WCR_INP_0; /* set coaxial input */
1788
1789 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1790
1791 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1792 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1793
1794 /* reset the ADC */
1795 writel(rme96->areg | RME96_AR_PD2,
1796 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1797 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1798
1799 /* reset and enable the DAC (order is important). */
1800 snd_rme96_reset_dac(rme96);
1801 rme96->areg |= RME96_AR_DAC_EN;
1802 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1803
1804 /* reset playback and record buffer pointers */
1805 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1806 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1807
1808 /* reset volume */
1809 rme96->vol[0] = rme96->vol[1] = 0;
1810 if (RME96_HAS_ANALOG_OUT(rme96)) {
1811 snd_rme96_apply_dac_volume(rme96);
1812 }
1813
1814 /* init switch interface */
1815 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1816 return err;
1817 }
1818
1819 /* init proc interface */
1820 snd_rme96_proc_init(rme96);
1821
1822 return 0;
1823}
1824
1825/*
1826 * proc interface
1827 */
1828
1829static void
1830snd_rme96_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1831{
1832 int n;
1833 rme96_t *rme96 = (rme96_t *)entry->private_data;
1834
1835 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1836
1837 snd_iprintf(buffer, rme96->card->longname);
1838 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1839
1840 snd_iprintf(buffer, "\nGeneral settings\n");
1841 if (rme96->wcreg & RME96_WCR_IDIS) {
1842 snd_iprintf(buffer, " period size: N/A (interrupts "
1843 "disabled)\n");
1844 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1845 snd_iprintf(buffer, " period size: 2048 bytes\n");
1846 } else {
1847 snd_iprintf(buffer, " period size: 8192 bytes\n");
1848 }
1849 snd_iprintf(buffer, "\nInput settings\n");
1850 switch (snd_rme96_getinputtype(rme96)) {
1851 case RME96_INPUT_OPTICAL:
1852 snd_iprintf(buffer, " input: optical");
1853 break;
1854 case RME96_INPUT_COAXIAL:
1855 snd_iprintf(buffer, " input: coaxial");
1856 break;
1857 case RME96_INPUT_INTERNAL:
1858 snd_iprintf(buffer, " input: internal");
1859 break;
1860 case RME96_INPUT_XLR:
1861 snd_iprintf(buffer, " input: XLR");
1862 break;
1863 case RME96_INPUT_ANALOG:
1864 snd_iprintf(buffer, " input: analog");
1865 break;
1866 }
1867 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1868 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1869 } else {
1870 if (n) {
1871 snd_iprintf(buffer, " (8 channels)\n");
1872 } else {
1873 snd_iprintf(buffer, " (2 channels)\n");
1874 }
1875 snd_iprintf(buffer, " sample rate: %d Hz\n",
1876 snd_rme96_capture_getrate(rme96, &n));
1877 }
1878 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1879 snd_iprintf(buffer, " sample format: 24 bit\n");
1880 } else {
1881 snd_iprintf(buffer, " sample format: 16 bit\n");
1882 }
1883
1884 snd_iprintf(buffer, "\nOutput settings\n");
1885 if (rme96->wcreg & RME96_WCR_SEL) {
1886 snd_iprintf(buffer, " output signal: normal playback\n");
1887 } else {
1888 snd_iprintf(buffer, " output signal: same as input\n");
1889 }
1890 snd_iprintf(buffer, " sample rate: %d Hz\n",
1891 snd_rme96_playback_getrate(rme96));
1892 if (rme96->wcreg & RME96_WCR_MODE24) {
1893 snd_iprintf(buffer, " sample format: 24 bit\n");
1894 } else {
1895 snd_iprintf(buffer, " sample format: 16 bit\n");
1896 }
1897 if (rme96->areg & RME96_AR_WSEL) {
1898 snd_iprintf(buffer, " clock mode: word clock\n");
1899 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1900 snd_iprintf(buffer, " clock mode: master\n");
1901 } else {
1902 snd_iprintf(buffer, " clock mode: slave\n");
1903 }
1904 if (rme96->wcreg & RME96_WCR_PRO) {
1905 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1906 } else {
1907 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1908 }
1909 if (rme96->wcreg & RME96_WCR_EMP) {
1910 snd_iprintf(buffer, " emphasis: on\n");
1911 } else {
1912 snd_iprintf(buffer, " emphasis: off\n");
1913 }
1914 if (rme96->wcreg & RME96_WCR_DOLBY) {
1915 snd_iprintf(buffer, " non-audio (dolby): on\n");
1916 } else {
1917 snd_iprintf(buffer, " non-audio (dolby): off\n");
1918 }
1919 if (RME96_HAS_ANALOG_IN(rme96)) {
1920 snd_iprintf(buffer, "\nAnalog output settings\n");
1921 switch (snd_rme96_getmontracks(rme96)) {
1922 case RME96_MONITOR_TRACKS_1_2:
1923 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1924 break;
1925 case RME96_MONITOR_TRACKS_3_4:
1926 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1927 break;
1928 case RME96_MONITOR_TRACKS_5_6:
1929 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1930 break;
1931 case RME96_MONITOR_TRACKS_7_8:
1932 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1933 break;
1934 }
1935 switch (snd_rme96_getattenuation(rme96)) {
1936 case RME96_ATTENUATION_0:
1937 snd_iprintf(buffer, " attenuation: 0 dB\n");
1938 break;
1939 case RME96_ATTENUATION_6:
1940 snd_iprintf(buffer, " attenuation: -6 dB\n");
1941 break;
1942 case RME96_ATTENUATION_12:
1943 snd_iprintf(buffer, " attenuation: -12 dB\n");
1944 break;
1945 case RME96_ATTENUATION_18:
1946 snd_iprintf(buffer, " attenuation: -18 dB\n");
1947 break;
1948 }
1949 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1950 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1951 }
1952}
1953
1954static void __init
1955snd_rme96_proc_init(rme96_t *rme96)
1956{
1957 snd_info_entry_t *entry;
1958
1959 if ((entry = snd_info_create_card_entry(rme96->card, "rme96", rme96->card->proc_root)) != NULL) {
1960 entry->content = SNDRV_INFO_CONTENT_TEXT;
1961 entry->private_data = rme96;
1962 entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
1963 entry->c.text.read_size = 256;
1964 entry->c.text.read = snd_rme96_proc_read;
1965 if (snd_info_register(entry) < 0) {
1966 snd_info_free_entry(entry);
1967 entry = NULL;
1968 }
1969 }
1970 rme96->proc_entry = entry;
1971}
1972
1973static void
1974snd_rme96_proc_done(rme96_t * rme96)
1975{
1976 if (rme96->proc_entry) {
1977 snd_info_unregister(rme96->proc_entry);
1978 rme96->proc_entry = NULL;
1979 }
1980}
1981
1982/*
1983 * control interface
1984 */
1985
1986static int
1987snd_rme96_info_loopback_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1988{
1989 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1990 uinfo->count = 1;
1991 uinfo->value.integer.min = 0;
1992 uinfo->value.integer.max = 1;
1993 return 0;
1994}
1995static int
1996snd_rme96_get_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1997{
1998 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
1999 unsigned long flags;
2000
2001 spin_lock_irqsave(&rme96->lock, flags);
2002 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
2003 spin_unlock_irqrestore(&rme96->lock, flags);
2004 return 0;
2005}
2006static int
2007snd_rme96_put_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2008{
2009 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2010 unsigned long flags;
2011 unsigned int val;
2012 int change;
2013
2014 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
2015 spin_lock_irqsave(&rme96->lock, flags);
2016 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
2017 change = val != rme96->wcreg;
2018 writel(rme96->wcreg = val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2019 spin_unlock_irqrestore(&rme96->lock, flags);
2020 return change;
2021}
2022
2023static int
2024snd_rme96_info_inputtype_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2025{
2026#ifdef TARGET_OS2
2027 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
2028 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2029 char *texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
2030#else
2031 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
2032 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2033 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
2034#endif
2035
2036 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2037 uinfo->count = 1;
2038 switch (rme96->pci->device) {
2039 case PCI_DEVICE_ID_DIGI96:
2040 case PCI_DEVICE_ID_DIGI96_8:
2041 uinfo->value.enumerated.items = 3;
2042 break;
2043 case PCI_DEVICE_ID_DIGI96_8_PRO:
2044 uinfo->value.enumerated.items = 4;
2045 break;
2046 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2047 if (rme96->rev > 4) {
2048 /* PST */
2049 uinfo->value.enumerated.items = 4;
2050 texts[3] = _texts[4]; /* Analog instead of XLR */
2051 } else {
2052 /* PAD */
2053 uinfo->value.enumerated.items = 5;
2054 }
2055 break;
2056 default:
2057 snd_BUG();
2058 break;
2059 }
2060 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
2061 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2062 }
2063 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2064 return 0;
2065}
2066static int
2067snd_rme96_get_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2068{
2069 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2070 unsigned long flags;
2071 int items = 3;
2072
2073 spin_lock_irqsave(&rme96->lock, flags);
2074 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
2075
2076 switch (rme96->pci->device) {
2077 case PCI_DEVICE_ID_DIGI96:
2078 case PCI_DEVICE_ID_DIGI96_8:
2079 items = 3;
2080 break;
2081 case PCI_DEVICE_ID_DIGI96_8_PRO:
2082 items = 4;
2083 break;
2084 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2085 if (rme96->rev > 4) {
2086 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
2087 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
2088 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
2089 }
2090 items = 4;
2091 } else {
2092 items = 5;
2093 }
2094 break;
2095 default:
2096 snd_BUG();
2097 break;
2098 }
2099 if (ucontrol->value.enumerated.item[0] >= items) {
2100 ucontrol->value.enumerated.item[0] = items - 1;
2101 }
2102
2103 spin_unlock_irqrestore(&rme96->lock, flags);
2104 return 0;
2105}
2106static int
2107snd_rme96_put_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2108{
2109 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2110 unsigned long flags;
2111 unsigned int val;
2112 int change, items = 3;
2113
2114 switch (rme96->pci->device) {
2115 case PCI_DEVICE_ID_DIGI96:
2116 case PCI_DEVICE_ID_DIGI96_8:
2117 items = 3;
2118 break;
2119 case PCI_DEVICE_ID_DIGI96_8_PRO:
2120 items = 4;
2121 break;
2122 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2123 if (rme96->rev > 4) {
2124 items = 4;
2125 } else {
2126 items = 5;
2127 }
2128 break;
2129 default:
2130 snd_BUG();
2131 break;
2132 }
2133 val = ucontrol->value.enumerated.item[0] % items;
2134
2135 /* special case for PST */
2136 if (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
2137 if (val == RME96_INPUT_XLR) {
2138 val = RME96_INPUT_ANALOG;
2139 }
2140 }
2141
2142 spin_lock_irqsave(&rme96->lock, flags);
2143 change = val != snd_rme96_getinputtype(rme96);
2144 snd_rme96_setinputtype(rme96, val);
2145 spin_unlock_irqrestore(&rme96->lock, flags);
2146 return change;
2147}
2148
2149static int
2150snd_rme96_info_clockmode_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2151{
2152 static char *texts[3] = { "Slave", "Master", "Wordclock" };
2153
2154 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2155 uinfo->count = 1;
2156 uinfo->value.enumerated.items = 3;
2157 if (uinfo->value.enumerated.item > 2) {
2158 uinfo->value.enumerated.item = 2;
2159 }
2160 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2161 return 0;
2162}
2163static int
2164snd_rme96_get_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2165{
2166 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2167 unsigned long flags;
2168
2169 spin_lock_irqsave(&rme96->lock, flags);
2170 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2171 spin_unlock_irqrestore(&rme96->lock, flags);
2172 return 0;
2173}
2174static int
2175snd_rme96_put_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2176{
2177 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2178 unsigned long flags;
2179 unsigned int val;
2180 int change;
2181
2182 val = ucontrol->value.enumerated.item[0] % 3;
2183 spin_lock_irqsave(&rme96->lock, flags);
2184 change = val != snd_rme96_getclockmode(rme96);
2185 snd_rme96_setclockmode(rme96, val);
2186 spin_unlock_irqrestore(&rme96->lock, flags);
2187 return change;
2188}
2189
2190static int
2191snd_rme96_info_attenuation_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2192{
2193 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2194
2195 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2196 uinfo->count = 1;
2197 uinfo->value.enumerated.items = 4;
2198 if (uinfo->value.enumerated.item > 3) {
2199 uinfo->value.enumerated.item = 3;
2200 }
2201 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2202 return 0;
2203}
2204static int
2205snd_rme96_get_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2206{
2207 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2208 unsigned long flags;
2209
2210 spin_lock_irqsave(&rme96->lock, flags);
2211 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2212 spin_unlock_irqrestore(&rme96->lock, flags);
2213 return 0;
2214}
2215static int
2216snd_rme96_put_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2217{
2218 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2219 unsigned long flags;
2220 unsigned int val;
2221 int change;
2222
2223 val = ucontrol->value.enumerated.item[0] % 4;
2224 spin_lock_irqsave(&rme96->lock, flags);
2225 change = val != snd_rme96_getattenuation(rme96);
2226 snd_rme96_setattenuation(rme96, val);
2227 spin_unlock_irqrestore(&rme96->lock, flags);
2228 return change;
2229}
2230
2231static int
2232snd_rme96_info_montracks_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2233{
2234 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2235
2236 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2237 uinfo->count = 1;
2238 uinfo->value.enumerated.items = 4;
2239 if (uinfo->value.enumerated.item > 3) {
2240 uinfo->value.enumerated.item = 3;
2241 }
2242 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2243 return 0;
2244}
2245static int
2246snd_rme96_get_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2247{
2248 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2249 unsigned long flags;
2250
2251 spin_lock_irqsave(&rme96->lock, flags);
2252 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2253 spin_unlock_irqrestore(&rme96->lock, flags);
2254 return 0;
2255}
2256static int
2257snd_rme96_put_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2258{
2259 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2260 unsigned long flags;
2261 unsigned int val;
2262 int change;
2263
2264 val = ucontrol->value.enumerated.item[0] % 4;
2265 spin_lock_irqsave(&rme96->lock, flags);
2266 change = val != snd_rme96_getmontracks(rme96);
2267 snd_rme96_setmontracks(rme96, val);
2268 spin_unlock_irqrestore(&rme96->lock, flags);
2269 return change;
2270}
2271
2272static u32 snd_rme96_convert_from_aes(snd_aes_iec958_t *aes)
2273{
2274 u32 val = 0;
2275 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2276 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2277 if (val & RME96_WCR_PRO)
2278 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2279 else
2280 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2281 return val;
2282}
2283
2284static void snd_rme96_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
2285{
2286 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2287 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2288 if (val & RME96_WCR_PRO)
2289 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2290 else
2291 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2292}
2293
2294static int snd_rme96_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2295{
2296 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2297 uinfo->count = 1;
2298 return 0;
2299}
2300
2301static int snd_rme96_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2302{
2303 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2304
2305 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2306 return 0;
2307}
2308
2309static int snd_rme96_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2310{
2311 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2312 unsigned long flags;
2313 int change;
2314 u32 val;
2315
2316 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2317 spin_lock_irqsave(&rme96->lock, flags);
2318 change = val != rme96->wcreg_spdif;
2319 rme96->wcreg_spdif = val;
2320 spin_unlock_irqrestore(&rme96->lock, flags);
2321 return change;
2322}
2323
2324static int snd_rme96_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2325{
2326 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2327 uinfo->count = 1;
2328 return 0;
2329}
2330
2331static int snd_rme96_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2332{
2333 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2334
2335 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2336 return 0;
2337}
2338
2339static int snd_rme96_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2340{
2341 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2342 unsigned long flags;
2343 int change;
2344 u32 val;
2345
2346 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2347 spin_lock_irqsave(&rme96->lock, flags);
2348 change = val != rme96->wcreg_spdif_stream;
2349 rme96->wcreg_spdif_stream = val;
2350 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2351 writel(rme96->wcreg |= val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2352 spin_unlock_irqrestore(&rme96->lock, flags);
2353 return change;
2354}
2355
2356static int snd_rme96_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2357{
2358 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2359 uinfo->count = 1;
2360 return 0;
2361}
2362
2363static int snd_rme96_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2364{
2365 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2366 return 0;
2367}
2368
2369static int
2370snd_rme96_dac_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2371{
2372 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2373
2374 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2375 uinfo->count = 2;
2376 uinfo->value.integer.min = 0;
2377 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2378 return 0;
2379}
2380
2381static int
2382snd_rme96_dac_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2383{
2384 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2385 unsigned long flags;
2386
2387 spin_lock_irqsave(&rme96->lock, flags);
2388 u->value.integer.value[0] = rme96->vol[0];
2389 u->value.integer.value[1] = rme96->vol[1];
2390 spin_unlock_irqrestore(&rme96->lock, flags);
2391
2392 return 0;
2393}
2394
2395static int
2396snd_rme96_dac_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u)
2397{
2398 rme96_t *rme96 = _snd_kcontrol_chip(kcontrol);
2399 unsigned long flags;
2400 int change = 0;
2401
2402 if (!RME96_HAS_ANALOG_OUT(rme96)) {
2403 return -EINVAL;
2404 }
2405 spin_lock_irqsave(&rme96->lock, flags);
2406 if (u->value.integer.value[0] != rme96->vol[0]) {
2407 rme96->vol[0] = u->value.integer.value[0];
2408 change = 1;
2409 }
2410 if (u->value.integer.value[1] != rme96->vol[1]) {
2411 rme96->vol[1] = u->value.integer.value[1];
2412 change = 1;
2413 }
2414 if (change) {
2415 snd_rme96_apply_dac_volume(rme96);
2416 }
2417 spin_unlock_irqrestore(&rme96->lock, flags);
2418
2419 return change;
2420}
2421
2422#ifdef TARGET_OS2
2423static snd_kcontrol_new_t snd_rme96_controls[] = {
2424{
2425 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
2426 SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),0,0,0,
2427 snd_rme96_control_spdif_info,
2428 snd_rme96_control_spdif_get,
2429 snd_rme96_control_spdif_put,0
2430},
2431{
2432 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
2433 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),0,
2434 SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,0,
2435 snd_rme96_control_spdif_stream_info,
2436 snd_rme96_control_spdif_stream_get,
2437 snd_rme96_control_spdif_stream_put,0
2438},
2439{
2440 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
2441 SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),0,
2442 SNDRV_CTL_ELEM_ACCESS_READ,0,
2443 snd_rme96_control_spdif_mask_info,
2444 snd_rme96_control_spdif_mask_get,0,
2445 IEC958_AES0_NONAUDIO |
2446 IEC958_AES0_PROFESSIONAL |
2447 IEC958_AES0_CON_EMPHASIS
2448},
2449{
2450 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
2451 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),0,
2452 SNDRV_CTL_ELEM_ACCESS_READ,0,
2453 snd_rme96_control_spdif_mask_info,
2454 snd_rme96_control_spdif_mask_get,0,
2455 IEC958_AES0_NONAUDIO |
2456 IEC958_AES0_PROFESSIONAL |
2457 IEC958_AES0_PRO_EMPHASIS
2458},
2459{
2460 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
2461 "Input Connector",0,0,0,
2462 snd_rme96_info_inputtype_control,
2463 snd_rme96_get_inputtype_control,
2464 snd_rme96_put_inputtype_control, 0
2465},
2466{
2467 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
2468 "Loopback Input",0,0,0,
2469 snd_rme96_info_loopback_control,
2470 snd_rme96_get_loopback_control,
2471 snd_rme96_put_loopback_control,0
2472},
2473{
2474 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
2475 "Clock Mode",0,0,0,
2476 snd_rme96_info_clockmode_control,
2477 snd_rme96_get_clockmode_control,
2478 snd_rme96_put_clockmode_control,0
2479},
2480{
2481 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
2482 "Monitor Tracks",0,0,0,
2483 snd_rme96_info_montracks_control,
2484 snd_rme96_get_montracks_control,
2485 snd_rme96_put_montracks_control,0
2486},
2487{
2488 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
2489 "Attenuation",0,0,0,
2490 snd_rme96_info_attenuation_control,
2491 snd_rme96_get_attenuation_control,
2492 snd_rme96_put_attenuation_control,0
2493},
2494{
2495 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
2496 "DAC Playback Volume",0,0,0,
2497 snd_rme96_dac_volume_info,
2498 snd_rme96_dac_volume_get,
2499 snd_rme96_dac_volume_put,0
2500}
2501};
2502#else
2503static snd_kcontrol_new_t snd_rme96_controls[] = {
2504{
2505 iface: SNDRV_CTL_ELEM_IFACE_PCM,
2506 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2507 info: snd_rme96_control_spdif_info,
2508 get: snd_rme96_control_spdif_get,
2509 put: snd_rme96_control_spdif_put
2510},
2511{
2512 access: SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2513 iface: SNDRV_CTL_ELEM_IFACE_PCM,
2514 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2515 info: snd_rme96_control_spdif_stream_info,
2516 get: snd_rme96_control_spdif_stream_get,
2517 put: snd_rme96_control_spdif_stream_put
2518},
2519{
2520 access: SNDRV_CTL_ELEM_ACCESS_READ,
2521 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
2522 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2523 info: snd_rme96_control_spdif_mask_info,
2524 get: snd_rme96_control_spdif_mask_get,
2525 private_value: IEC958_AES0_NONAUDIO |
2526 IEC958_AES0_PROFESSIONAL |
2527 IEC958_AES0_CON_EMPHASIS
2528},
2529{
2530 access: SNDRV_CTL_ELEM_ACCESS_READ,
2531 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
2532 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2533 info: snd_rme96_control_spdif_mask_info,
2534 get: snd_rme96_control_spdif_mask_get,
2535 private_value: IEC958_AES0_NONAUDIO |
2536 IEC958_AES0_PROFESSIONAL |
2537 IEC958_AES0_PRO_EMPHASIS
2538},
2539{
2540 iface: SNDRV_CTL_ELEM_IFACE_PCM,
2541 name: "Input Connector",
2542 info: snd_rme96_info_inputtype_control,
2543 get: snd_rme96_get_inputtype_control,
2544 put: snd_rme96_put_inputtype_control
2545},
2546{
2547 iface: SNDRV_CTL_ELEM_IFACE_PCM,
2548 name: "Loopback Input",
2549 info: snd_rme96_info_loopback_control,
2550 get: snd_rme96_get_loopback_control,
2551 put: snd_rme96_put_loopback_control
2552},
2553{
2554 iface: SNDRV_CTL_ELEM_IFACE_PCM,
2555 name: "Clock Mode",
2556 info: snd_rme96_info_clockmode_control,
2557 get: snd_rme96_get_clockmode_control,
2558 put: snd_rme96_put_clockmode_control
2559},
2560{
2561 iface: SNDRV_CTL_ELEM_IFACE_PCM,
2562 name: "Monitor Tracks",
2563 info: snd_rme96_info_montracks_control,
2564 get: snd_rme96_get_montracks_control,
2565 put: snd_rme96_put_montracks_control
2566},
2567{
2568 iface: SNDRV_CTL_ELEM_IFACE_PCM,
2569 name: "Attenuation",
2570 info: snd_rme96_info_attenuation_control,
2571 get: snd_rme96_get_attenuation_control,
2572 put: snd_rme96_put_attenuation_control
2573},
2574{
2575 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
2576 name: "DAC Playback Volume",
2577 info: snd_rme96_dac_volume_info,
2578 get: snd_rme96_dac_volume_get,
2579 put: snd_rme96_dac_volume_put
2580}
2581};
2582#endif
2583
2584static int
2585snd_rme96_create_switches(snd_card_t *card,
2586 rme96_t *rme96)
2587{
2588 int idx, err;
2589 snd_kcontrol_t *kctl;
2590
2591 for (idx = 0; idx < 7; idx++) {
2592 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2593 return err;
2594 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2595 rme96->spdif_ctl = kctl;
2596 }
2597
2598 if (RME96_HAS_ANALOG_OUT(rme96)) {
2599 for (idx = 7; idx < 10; idx++)
2600 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2601 return err;
2602 }
2603
2604 return 0;
2605}
2606
2607/*
2608 * Card initialisation
2609 */
2610
2611static void snd_rme96_card_free(snd_card_t *card)
2612{
2613 snd_rme96_free(card->private_data);
2614}
2615
2616static int __init
2617snd_rme96_probe(struct pci_dev *pci,
2618 const struct pci_device_id *id)
2619{
2620 static int dev = 0;
2621 rme96_t *rme96;
2622 snd_card_t *card;
2623 int err;
2624 u8 val;
2625
2626 for ( ; dev < SNDRV_CARDS; dev++) {
2627 if (!snd_enable[dev]) {
2628 dev++;
2629 return -ENOENT;
2630 }
2631 break;
2632 }
2633 if (dev >= SNDRV_CARDS) {
2634 return -ENODEV;
2635 }
2636 if ((card = snd_card_new(snd_index[dev], snd_id[dev], THIS_MODULE,
2637 sizeof(rme96_t))) == NULL)
2638 return -ENOMEM;
2639 card->private_free = snd_rme96_card_free;
2640 rme96 = (rme96_t *)card->private_data;
2641 rme96->card = card;
2642 rme96->pci = pci;
2643 if ((err = snd_rme96_create(rme96)) < 0) {
2644 snd_card_free(card);
2645 return err;
2646 }
2647
2648 strcpy(card->driver, "Digi96");
2649 switch (rme96->pci->device) {
2650 case PCI_DEVICE_ID_DIGI96:
2651 strcpy(card->shortname, "RME Digi96");
2652 break;
2653 case PCI_DEVICE_ID_DIGI96_8:
2654 strcpy(card->shortname, "RME Digi96/8");
2655 break;
2656 case PCI_DEVICE_ID_DIGI96_8_PRO:
2657 strcpy(card->shortname, "RME Digi96/8 PRO");
2658 break;
2659 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST:
2660 pci_read_config_byte(rme96->pci, 8, &val);
2661 if (val < 5) {
2662 strcpy(card->shortname, "RME Digi96/8 PAD");
2663 } else {
2664 strcpy(card->shortname, "RME Digi96/8 PST");
2665 }
2666 break;
2667 }
2668 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2669 rme96->port, rme96->irq);
2670
2671 if ((err = snd_card_register(card)) < 0) {
2672 snd_card_free(card);
2673 return err;
2674 }
2675 PCI_SET_DRIVER_DATA(pci, card);
2676 dev++;
2677 return 0;
2678}
2679
2680static void __exit snd_rme96_remove(struct pci_dev *pci)
2681{
2682 snd_card_free(PCI_GET_DRIVER_DATA(pci));
2683 PCI_SET_DRIVER_DATA(pci, NULL);
2684}
2685
2686#ifdef TARGET_OS2
2687static struct pci_driver driver = {
2688 0,0,0, "RME Digi96",
2689 snd_rme96_ids,
2690 snd_rme96_probe,
2691 snd_rme96_remove,0,0
2692};
2693#else
2694static struct pci_driver driver = {
2695 name: "RME Digi96",
2696 id_table: snd_rme96_ids,
2697 probe: snd_rme96_probe,
2698 remove: snd_rme96_remove,
2699};
2700#endif
2701
2702static int __init alsa_card_rme96_init(void)
2703{
2704 int err;
2705
2706 if ((err = pci_module_init(&driver)) < 0) {
2707#ifdef MODULE
2708// snd_printk("No RME Digi96 cards found\n");
2709#endif
2710 return err;
2711 }
2712 return 0;
2713}
2714
2715static void __exit alsa_card_rme96_exit(void)
2716{
2717 pci_unregister_driver(&driver);
2718}
2719
2720module_init(alsa_card_rme96_init)
2721module_exit(alsa_card_rme96_exit)
2722
2723#ifndef MODULE
2724
2725/* format is: snd-card-rme96=snd_enable,snd_index,snd_id */
2726
2727static int __init alsa_card_rme96_setup(char *str)
2728{
2729 static unsigned __initdata nr_dev = 0;
2730
2731 if (nr_dev >= SNDRV_CARDS)
2732 return 0;
2733 (void)(get_option(&str,&snd_enable[nr_dev]) == 2 &&
2734 get_option(&str,&snd_index[nr_dev]) == 2 &&
2735 get_id(&str,&snd_id[nr_dev]) == 2);
2736 nr_dev++;
2737 return 1;
2738}
2739
2740__setup("snd-card-rme96=", alsa_card_rme96_setup);
2741
2742#endif /* ifndef MODULE */
Note: See TracBrowser for help on using the repository browser.