source: GPL/alsa-kernel/pci/intel8x0.c@ 18

Last change on this file since 18 was 18, checked in by vladest, 20 years ago

initial import
File size: 102.9 KB
Line 
1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/ac97_codec.h>
39#include <sound/info.h>
40#include <sound/mpu401.h>
41#define SNDRV_GET_ID
42#include <sound/initval.h>
43
44#define I810_DEBUG
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_CLASSES("{sound}");
50MODULE_DEVICES("{{Intel,82801AA-ICH},"
51 "{Intel,82901AB-ICH0},"
52 "{Intel,82801BA-ICH2},"
53 "{Intel,82801CA-ICH3},"
54 "{Intel,82801DB-ICH4},"
55 "{Intel,ICH5},"
56 "{Intel,ICH6},"
57 "{Intel,ICH7},"
58 "{Intel,6300ESB},"
59 "{Intel,ESB2},"
60 "{Intel,MX440},"
61 "{SiS,SI7012},"
62 "{NVidia,nForce Audio},"
63 "{NVidia,nForce2 Audio},"
64 "{AMD,AMD768},"
65 "{AMD,AMD8111},"
66 "{ALI,M5455}}");
67
68#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
69//#define SUPPORT_JOYSTICK 1
70#endif
71#define SUPPORT_MIDI 1
72
73extern int midi_port;
74
75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
78#ifdef TARGET_OS2
79static int ac97_clock[SNDRV_CARDS] = {REPEAT_SNDRV(0)};
80static char *ac97_quirk[SNDRV_CARDS];
81#else
82static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
83#endif
84#ifdef SUPPORT_JOYSTICK
85static int joystick[SNDRV_CARDS];
86#endif
87#ifdef SUPPORT_MIDI
88static int mpu_port[SNDRV_CARDS];// = {REPEAT_SNDRV(0x330)};;
89/* disabled */
90#endif
91
92static int buggy_semaphore;
93static int buggy_irq = -1; /* auto-check */
94
95MODULE_PARM(index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
96MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
97MODULE_PARM_SYNTAX(index, SNDRV_INDEX_DESC);
98MODULE_PARM(id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
99MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
100MODULE_PARM_SYNTAX(id, SNDRV_ID_DESC);
101MODULE_PARM(enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
102MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
103MODULE_PARM_SYNTAX(enable, SNDRV_ENABLE_DESC);
104MODULE_PARM(ac97_clock, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
105MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
106MODULE_PARM_SYNTAX(ac97_clock, SNDRV_ENABLED ",default:0");
107MODULE_PARM(ac97_quirk, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
108MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
109MODULE_PARM_SYNTAX(ac97_quirk, SNDRV_ENABLED ",allows:{{-1,3}},dialog:list,default:-1");
110#ifdef SUPPORT_JOYSTICK
111MODULE_PARM(joystick, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
112MODULE_PARM_DESC(joystick, "Enable joystick for Intel i8x0 soundcard.");
113MODULE_PARM_SYNTAX(joystick, SNDRV_ENABLED "," SNDRV_BOOLEAN_FALSE_DESC);
114#endif
115#ifdef SUPPORT_MIDI
116MODULE_PARM(mpu_port, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
117MODULE_PARM_DESC(mpu_port, "MPU401 port # for Intel i8x0 driver.");
118MODULE_PARM_SYNTAX(mpu_port, SNDRV_ENABLED ",allows:{{0},{0x330},{0x300}},dialog:list");
119#endif
120
121/*
122 * Direct registers
123 */
124
125#ifndef PCI_DEVICE_ID_INTEL_82801
126#define PCI_DEVICE_ID_INTEL_82801 0x2415
127#endif
128#ifndef PCI_DEVICE_ID_INTEL_82901
129#define PCI_DEVICE_ID_INTEL_82901 0x2425
130#endif
131#ifndef PCI_DEVICE_ID_INTEL_82801BA
132#define PCI_DEVICE_ID_INTEL_82801BA 0x2445
133#endif
134#ifndef PCI_DEVICE_ID_INTEL_440MX
135#define PCI_DEVICE_ID_INTEL_440MX 0x7195
136#endif
137#ifndef PCI_DEVICE_ID_INTEL_ICH3
138#define PCI_DEVICE_ID_INTEL_ICH3 0x2485
139#endif
140#ifndef PCI_DEVICE_ID_INTEL_ICH4
141#define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
142#endif
143#ifndef PCI_DEVICE_ID_INTEL_ICH5
144#define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
145#endif
146#ifndef PCI_DEVICE_ID_INTEL_ESB_5
147#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
148#endif
149#ifndef PCI_DEVICE_ID_INTEL_ICH6_18
150#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
151#endif
152#ifndef PCI_DEVICE_ID_INTEL_ICH7_20
153#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
154#endif
155#ifndef PCI_DEVICE_ID_INTEL_ESB2_14
156#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
157#endif
158#ifndef PCI_DEVICE_ID_SI_7012
159#define PCI_DEVICE_ID_SI_7012 0x7012
160#endif
161#ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
162#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
163#endif
164#ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
165#define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
166#endif
167#ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
168#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
169#endif
170#ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
171#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
172#endif
173#ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
174#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
175#endif
176#ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
177#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
178#endif
179
180enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_INTEL_ICH5, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
181
182#define ICHREG(x) ICH_REG_##x
183
184#define DEFINE_REGSET(name,base) \
185 enum { \
186 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
187 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
188 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
189 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
190 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
191 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
192 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
193 };
194
195/* busmaster blocks */
196DEFINE_REGSET(OFF, 0); /* offset */
197DEFINE_REGSET(PI, 0x00); /* PCM in */
198DEFINE_REGSET(PO, 0x10); /* PCM out */
199DEFINE_REGSET(MC, 0x20); /* Mic in */
200
201/* ICH4 busmaster blocks */
202DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
203DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
204DEFINE_REGSET(SP, 0x60); /* SPDIF out */
205
206/* values for each busmaster block */
207
208/* LVI */
209#define ICH_REG_LVI_MASK 0x1f
210
211/* SR */
212#define ICH_FIFOE 0x10 /* FIFO error */
213#define ICH_BCIS 0x08 /* buffer completion interrupt status */
214#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
215#define ICH_CELV 0x02 /* current equals last valid */
216#define ICH_DCH 0x01 /* DMA controller halted */
217
218/* PIV */
219#define ICH_REG_PIV_MASK 0x1f /* mask */
220
221/* CR */
222#define ICH_IOCE 0x10 /* interrupt on completion enable */
223#define ICH_FEIE 0x08 /* fifo error interrupt enable */
224#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
225#define ICH_RESETREGS 0x02 /* reset busmaster registers */
226#define ICH_STARTBM 0x01 /* start busmaster operation */
227
228
229/* global block */
230#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
231#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
232#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
233#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
234#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
235#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
236#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
237#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
238#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
239#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
240#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
241#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
242#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
243#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
244#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
245#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
246#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
247#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
248#define ICH_ACLINK 0x00000008 /* AClink shut off */
249#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
250#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
251#define ICH_GIE 0x00000001 /* GPI interrupt enable */
252#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
253#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
254#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
255#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
256#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
257#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
258#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
259#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
260#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
261#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
262#define ICH_MD3 0x00020000 /* modem power down semaphore */
263#define ICH_AD3 0x00010000 /* audio power down semaphore */
264#define ICH_RCS 0x00008000 /* read completion status */
265#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
266#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
267#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
268#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
269#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
270#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
271#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
272#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
273#define ICH_POINT 0x00000040 /* playback interrupt */
274#define ICH_PIINT 0x00000020 /* capture interrupt */
275#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
276#define ICH_MOINT 0x00000004 /* modem playback interrupt */
277#define ICH_MIINT 0x00000002 /* modem capture interrupt */
278#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
279#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
280#define ICH_CAS 0x01 /* codec access semaphore */
281#define ICH_REG_SDM 0x80
282#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
283#define ICH_DI2L_SHIFT 6
284#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
285#define ICH_DI1L_SHIFT 4
286#define ICH_SE 0x00000008 /* steer enable */
287#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
288
289#define ICH_MAX_FRAGS 32 /* max hw frags */
290
291
292/*
293 * registers for Ali5455
294 */
295
296/* ALi 5455 busmaster blocks */
297DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
298DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
299DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
300DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
301DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
302DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
303DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
304DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
305DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
306DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
307DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
308
309enum {
310 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
311 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
312 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
313 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
314 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
315 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
316 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
317 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
318 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
319 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
320 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
321 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
322 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
323 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
324 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
325 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
326 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
327 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
328 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
329 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
330 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
331};
332
333#define ALI_CAS_SEM_BUSY 0x80000000
334#define ALI_CPR_ADDR_SECONDARY 0x100
335#define ALI_CPR_ADDR_READ 0x80
336#define ALI_CSPSR_CODEC_READY 0x08
337#define ALI_CSPSR_READ_OK 0x02
338#define ALI_CSPSR_WRITE_OK 0x01
339
340/* interrupts for the whole chip by interrupt status register finish */
341
342#define ALI_INT_MICIN2 (1<<26)
343#define ALI_INT_PCMIN2 (1<<25)
344#define ALI_INT_I2SIN (1<<24)
345#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
346#define ALI_INT_SPDIFIN (1<<22)
347#define ALI_INT_LFEOUT (1<<21)
348#define ALI_INT_CENTEROUT (1<<20)
349#define ALI_INT_CODECSPDIFOUT (1<<19)
350#define ALI_INT_MICIN (1<<18)
351#define ALI_INT_PCMOUT (1<<17)
352#define ALI_INT_PCMIN (1<<16)
353#define ALI_INT_CPRAIS (1<<7) /* command port available */
354#define ALI_INT_SPRAIS (1<<5) /* status port available */
355#define ALI_INT_GPIO (1<<1)
356#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
357
358#define ICH_ALI_SC_RESET (1<<31) /* master reset */
359#define ICH_ALI_SC_AC97_DBL (1<<30)
360#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
361#define ICH_ALI_SC_IN_BITS (3<<18)
362#define ICH_ALI_SC_OUT_BITS (3<<16)
363#define ICH_ALI_SC_6CH_CFG (3<<14)
364#define ICH_ALI_SC_PCM_4 (1<<8)
365#define ICH_ALI_SC_PCM_6 (2<<8)
366#define ICH_ALI_SC_PCM_246_MASK (3<<8)
367
368#define ICH_ALI_SS_SEC_ID (3<<5)
369#define ICH_ALI_SS_PRI_ID (3<<3)
370
371#define ICH_ALI_IF_AC97SP (1<<21)
372#define ICH_ALI_IF_MC (1<<20)
373#define ICH_ALI_IF_PI (1<<19)
374#define ICH_ALI_IF_MC2 (1<<18)
375#define ICH_ALI_IF_PI2 (1<<17)
376#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
377#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
378#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
379#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
380#define ICH_ALI_IF_PO_SPDF (1<<3)
381#define ICH_ALI_IF_PO (1<<1)
382
383/*
384 *
385 */
386
387enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
388enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
389enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
390
391#define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
392
393typedef struct {
394 unsigned int ichd; /* ich device number */
395 unsigned long reg_offset; /* offset to bmaddr */
396 u32 *bdbar; /* CPU address (32bit) */
397 unsigned int bdbar_addr; /* PCI bus address (32bit) */
398 snd_pcm_substream_t *substream;
399 unsigned int physbuf; /* physical address (32bit) */
400 unsigned int size;
401 unsigned int fragsize;
402 unsigned int fragsize1;
403 unsigned int position;
404 unsigned int pos_shift;
405 int frags;
406 int lvi;
407 int lvi_frag;
408 int civ;
409 int ack;
410 int ack_reload;
411 unsigned int ack_bit;
412 unsigned int roff_sr;
413 unsigned int roff_picb;
414 unsigned int int_sta_mask; /* interrupt status mask */
415 unsigned int ali_slot; /* ALI DMA slot */
416 struct ac97_pcm *pcm;
417 int pcm_open_flag;
418 unsigned int page_attr_changed: 1;
419 unsigned int suspended: 1;
420} ichdev_t;
421
422typedef struct _snd_intel8x0 intel8x0_t;
423#define chip_t intel8x0_t
424
425struct _snd_intel8x0 {
426 unsigned int device_type;
427
428 int irq;
429
430 unsigned int mmio;
431 unsigned long addr;
432 unsigned long remap_addr;
433 unsigned int bm_mmio;
434 unsigned long bmaddr;
435 unsigned long remap_bmaddr;
436
437 struct pci_dev *pci;
438 snd_card_t *card;
439
440 int pcm_devs;
441 snd_pcm_t *pcm[6];
442 ichdev_t ichd[6];
443
444 int multi4: 1,
445 multi6: 1,
446 dra: 1,
447 smp20bit: 1;
448 int in_ac97_init: 1,
449 in_sdin_init: 1;
450 unsigned in_measurement: 1; /* during ac97 clock measurement */
451 unsigned fix_nocache: 1; /* workaround for 440MX */
452 unsigned buggy_irq: 1; /* workaround for buggy mobos */
453 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
454 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
455
456 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
457 unsigned int sdm_saved; /* SDM reg value */
458
459 ac97_bus_t *ac97_bus;
460 ac97_t *ac97[3];
461 unsigned int ac97_sdin[3];
462
463 snd_rawmidi_t *rmidi;
464
465 spinlock_t reg_lock;
466
467 u32 bdbars_count;
468 struct snd_dma_buffer bdbars;
469 u32 int_sta_reg; /* interrupt status register */
470 u32 int_sta_mask; /* interrupt status mask */
471};
472
473static struct pci_device_id snd_intel8x0_ids[] = {
474 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
475 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
476 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
477 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
478 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
479 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH5 */
480 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ESB */
481 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH6 */
482 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH5 }, /* ICH7 */
483 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
484 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
485 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
486 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
487 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
488 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
489 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
490 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
491 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
492 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
493 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
494 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
495 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
496 { 0 }
497};
498
499MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
500
501
502/*
503 * Lowlevel I/O - busmaster
504 */
505
506static u8 igetbyte(intel8x0_t *chip, u32 offset)
507{
508 if (chip->bm_mmio)
509 return readb(chip->remap_bmaddr + offset);
510 else
511 return inb(chip->bmaddr + offset);
512}
513
514static u16 igetword(intel8x0_t *chip, u32 offset)
515{
516 if (chip->bm_mmio)
517 return readw(chip->remap_bmaddr + offset);
518 else
519 return inw(chip->bmaddr + offset);
520}
521
522static u32 igetdword(intel8x0_t *chip, u32 offset)
523{
524 if (chip->bm_mmio)
525 return readl(chip->remap_bmaddr + offset);
526 else
527 return inl(chip->bmaddr + offset);
528}
529
530static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
531{
532 if (chip->bm_mmio)
533 writeb(val, chip->remap_bmaddr + offset);
534 else
535 outb(val, chip->bmaddr + offset);
536}
537
538static void iputword(intel8x0_t *chip, u32 offset, u16 val)
539{
540 if (chip->bm_mmio)
541 writew(val, chip->remap_bmaddr + offset);
542 else
543 outw(val, chip->bmaddr + offset);
544}
545
546static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
547{
548 if (chip->bm_mmio)
549 writel(val, chip->remap_bmaddr + offset);
550 else
551 outl(val, chip->bmaddr + offset);
552}
553
554/*
555 * Lowlevel I/O - AC'97 registers
556 */
557
558static u16 iagetword(intel8x0_t *chip, u32 offset)
559{
560 if (chip->mmio)
561 return readw(chip->remap_addr + offset);
562 else
563 return inw(chip->addr + offset);
564}
565
566static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
567{
568 if (chip->mmio)
569 writew(val, chip->remap_addr + offset);
570 else
571 outw(val, chip->addr + offset);
572}
573
574/*
575 * Basic I/O
576 */
577
578/*
579 * access to AC97 codec via normal i/o (for ICH and SIS7012)
580 */
581
582/* return the GLOB_STA bit for the corresponding codec */
583static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
584{
585 static unsigned int codec_bit[3] = {
586 ICH_PCR, ICH_SCR, ICH_TCR
587 };
588 snd_assert(codec < 3, return ICH_PCR);
589 if (chip->device_type == DEVICE_INTEL_ICH4 ||
590 chip->device_type == DEVICE_INTEL_ICH5)
591 codec = chip->ac97_sdin[codec];
592 return codec_bit[codec];
593}
594
595static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
596{
597 int time;
598
599 if (codec > 2)
600 return -EIO;
601 if (chip->in_sdin_init) {
602 /* we don't know the ready bit assignment at the moment */
603 /* so we check any */
604 codec = ICH_PCR | ICH_SCR | ICH_TCR;
605 } else {
606 codec = get_ich_codec_bit(chip, codec);
607 }
608
609 /* codec ready ? */
610 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
611 return -EIO;
612
613 /* Anyone holding a semaphore for 1 msec should be shot... */
614 time = 100;
615 do {
616 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
617 return 0;
618 udelay(10);
619 } while (time--);
620
621 /* access to some forbidden (non existant) ac97 registers will not
622 * reset the semaphore. So even if you don't get the semaphore, still
623 * continue the access. We don't need the semaphore anyway. */
624 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
625 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
626 iagetword(chip, 0); /* clear semaphore flag */
627 /* I don't care about the semaphore */
628 return -EBUSY;
629}
630
631static void snd_intel8x0_codec_write(ac97_t *ac97,
632 unsigned short reg,
633 unsigned short val)
634{
635 intel8x0_t *chip = ac97->private_data;
636
637 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
638 if (! chip->in_ac97_init)
639 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
640 }
641 iaputword(chip, reg + ac97->num * 0x80, val);
642}
643
644static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
645 unsigned short reg)
646{
647 intel8x0_t *chip = ac97->private_data;
648 unsigned short res;
649 unsigned int tmp;
650
651 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
652 if (! chip->in_ac97_init)
653 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
654 res = 0xffff;
655 } else {
656 res = iagetword(chip, reg + ac97->num * 0x80);
657 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
658 /* reset RCS and preserve other R/WC bits */
659 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
660 if (! chip->in_ac97_init)
661 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
662 res = 0xffff;
663 }
664 }
665 return res;
666}
667
668static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
669{
670 unsigned int tmp;
671
672 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
673 iagetword(chip, codec * 0x80);
674 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
675 /* reset RCS and preserve other R/WC bits */
676 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
677 }
678 }
679}
680
681/*
682 * access to AC97 for Ali5455
683 */
684static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
685{
686 int count = 0;
687 for (count = 0; count < 0x7f; count++) {
688 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
689 if (val & mask)
690 return 0;
691 }
692 if (! chip->in_ac97_init)
693 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
694 return -EBUSY;
695}
696
697static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
698{
699 int time = 100;
700 if (chip->buggy_semaphore)
701 return 0; /* just ignore ... */
702 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
703 udelay(1);
704 if (! time && ! chip->in_ac97_init)
705 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
706 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
707}
708
709static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
710{
711 intel8x0_t *chip = ac97->private_data;
712 unsigned short data = 0xffff;
713
714 if (snd_intel8x0_ali_codec_semaphore(chip))
715 goto __err;
716 reg |= ALI_CPR_ADDR_READ;
717 if (ac97->num)
718 reg |= ALI_CPR_ADDR_SECONDARY;
719 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
720 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
721 goto __err;
722 data = igetword(chip, ICHREG(ALI_SPR));
723__err:
724 return data;
725}
726
727static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
728{
729 intel8x0_t *chip = ac97->private_data;
730
731 if (snd_intel8x0_ali_codec_semaphore(chip))
732 return;
733 iputword(chip, ICHREG(ALI_CPR), val);
734 if (ac97->num)
735 reg |= ALI_CPR_ADDR_SECONDARY;
736 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
737 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
738}
739
740
741/*
742 * DMA I/O
743 */
744static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
745{
746 int idx;
747 u32 *bdbar = ichdev->bdbar;
748 unsigned long port = ichdev->reg_offset;
749
750 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
751 if (ichdev->size == ichdev->fragsize) {
752 ichdev->ack_reload = ichdev->ack = 2;
753 ichdev->fragsize1 = ichdev->fragsize >> 1;
754 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
755 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
756 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
757 ichdev->fragsize1 >> ichdev->pos_shift);
758 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
759 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
760 ichdev->fragsize1 >> ichdev->pos_shift);
761 }
762 ichdev->frags = 2;
763 } else {
764 ichdev->ack_reload = ichdev->ack = 1;
765 ichdev->fragsize1 = ichdev->fragsize;
766 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
767 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
768 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
769 ichdev->fragsize >> ichdev->pos_shift);
770 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
771 }
772 ichdev->frags = ichdev->size / ichdev->fragsize;
773 }
774 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
775 ichdev->civ = 0;
776 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
777 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
778 ichdev->position = 0;
779#if 0
780 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
781 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
782#endif
783 /* clear interrupts */
784 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
785}
786
787/*
788 * Interrupt handler
789 */
790
791static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
792{
793 unsigned long port = ichdev->reg_offset;
794 int status, civ, i, step;
795 int ack = 0;
796
797 spin_lock(&chip->reg_lock);
798 status = igetbyte(chip, port + ichdev->roff_sr);
799 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
800 if (!(status & ICH_BCIS)) {
801 step = 0;
802 } else if (civ == ichdev->civ) {
803 // snd_printd("civ same %d\n", civ);
804 step = 1;
805 ichdev->civ++;
806 ichdev->civ &= ICH_REG_LVI_MASK;
807 } else {
808 step = civ - ichdev->civ;
809 if (step < 0)
810 step += ICH_REG_LVI_MASK + 1;
811 // if (step != 1)
812 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
813 ichdev->civ = civ;
814 }
815
816 ichdev->position += step * ichdev->fragsize1;
817 ichdev->position %= ichdev->size;
818 ichdev->lvi += step;
819 ichdev->lvi &= ICH_REG_LVI_MASK;
820 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
821 for (i = 0; i < step; i++) {
822 ichdev->lvi_frag++;
823 ichdev->lvi_frag %= ichdev->frags;
824 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
825 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
826 if (--ichdev->ack == 0) {
827 ichdev->ack = ichdev->ack_reload;
828 ack = 1;
829 }
830 }
831 spin_unlock(&chip->reg_lock);
832 if (ack && ichdev->substream) {
833 snd_pcm_period_elapsed(ichdev->substream);
834 }
835 iputbyte(chip, port + ichdev->roff_sr,
836 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
837}
838
839static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
840{
841 intel8x0_t *chip = dev_id;
842 ichdev_t *ichdev;
843 unsigned int status;
844#ifdef TARGET_OS2
845 int fOurIrq = FALSE;
846#endif
847 unsigned int i;
848
849 status = igetdword(chip, chip->int_sta_reg);
850 if (status == 0xffffffff) /* we are not yet resumed */
851 return IRQ_NONE;
852
853 if ((status & chip->int_sta_mask) == 0) {
854 static int err_count = 10;
855 if (status) {
856 /* ack */
857 iputdword(chip, chip->int_sta_reg, status);
858 /* FIXME: on some ICH5 board shows the same
859 * problem. So we return IRQ_HANDLED
860 * in any cases.
861 * (or, maybe add a new module param to control this?)
862 */
863#if 0
864 if (chip->device_type != DEVICE_NFORCE)
865 status ^= igetdword(chip, chip->int_sta_reg);
866#endif
867 }
868 return IRQ_RETVAL(status);
869 }
870#ifdef TARGET_OS2
871 fOurIrq = TRUE;
872#endif
873
874 for (i = 0; i < chip->bdbars_count; i++) {
875 ichdev = &chip->ichd[i];
876 if (status & ichdev->int_sta_mask)
877 snd_intel8x0_update(chip, ichdev);
878 }
879
880 /* ack them */
881 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
882
883#ifdef TARGET_OS2
884 if (fOurIrq) {
885 eoi_irq(irq);
886 }
887#endif //TARGET_OS2
888
889 return IRQ_HANDLED;
890}
891
892/*
893 * PCM part
894 */
895
896static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
897{
898 intel8x0_t *chip = snd_pcm_substream_chip(substream);
899 ichdev_t *ichdev = get_ichdev(substream);
900 unsigned char val = 0;
901 unsigned long port = ichdev->reg_offset;
902
903 switch (cmd) {
904 case SNDRV_PCM_TRIGGER_RESUME:
905 ichdev->suspended = 0;
906 /* fallthru */
907 case SNDRV_PCM_TRIGGER_START:
908 val = ICH_IOCE | ICH_STARTBM;
909 break;
910 case SNDRV_PCM_TRIGGER_SUSPEND:
911 ichdev->suspended = 1;
912 /* fallthru */
913 case SNDRV_PCM_TRIGGER_STOP:
914 val = 0;
915 break;
916 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
917 val = ICH_IOCE;
918 break;
919 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
920 val = ICH_IOCE | ICH_STARTBM;
921 break;
922 default:
923 return -EINVAL;
924 }
925 iputbyte(chip, port + ICH_REG_OFF_CR, val);
926 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
927 /* wait until DMA stopped */
928 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
929 /* reset whole DMA things */
930 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
931 }
932 return 0;
933}
934
935static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
936{
937 intel8x0_t *chip = snd_pcm_substream_chip(substream);
938 ichdev_t *ichdev = get_ichdev(substream);
939 unsigned long port = ichdev->reg_offset;
940 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
941 unsigned int val, fifo;
942
943 val = igetdword(chip, ICHREG(ALI_DMACR));
944 switch (cmd) {
945 case SNDRV_PCM_TRIGGER_RESUME:
946 ichdev->suspended = 0;
947 /* fallthru */
948 case SNDRV_PCM_TRIGGER_START:
949 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
950 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
951 /* clear FIFO for synchronization of channels */
952 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
953 fifo &= ~(0xff << (ichdev->ali_slot % 4));
954 fifo |= 0x83 << (ichdev->ali_slot % 4);
955 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
956 }
957 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
958 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
959 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
960 break;
961 case SNDRV_PCM_TRIGGER_SUSPEND:
962 ichdev->suspended = 1;
963 /* fallthru */
964 case SNDRV_PCM_TRIGGER_STOP:
965 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
966 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
967 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
968 while (igetbyte(chip, port + ICH_REG_OFF_CR))
969 ;
970 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
971 break;
972 /* reset whole DMA things */
973 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
974 /* clear interrupts */
975 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
976 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
977 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
978 break;
979 default:
980 return -EINVAL;
981 }
982 return 0;
983}
984
985static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
986 snd_pcm_hw_params_t * hw_params)
987{
988 intel8x0_t *chip = snd_pcm_substream_chip(substream);
989 ichdev_t *ichdev = get_ichdev(substream);
990 int dbl = params_rate(hw_params) > 48000;
991 int err;
992
993 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
994 if (err < 0)
995 return err;
996 if (ichdev->pcm_open_flag) {
997 snd_ac97_pcm_close(ichdev->pcm);
998 ichdev->pcm_open_flag = 0;
999 }
1000 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
1001 params_channels(hw_params),
1002 ichdev->pcm->r[dbl].slots);
1003 if (err >= 0) {
1004 ichdev->pcm_open_flag = 1;
1005 /* Force SPDIF setting */
1006 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
1007 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
1008 }
1009 return err;
1010}
1011
1012static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
1013{
1014 ichdev_t *ichdev = get_ichdev(substream);
1015
1016 if (ichdev->pcm_open_flag) {
1017 snd_ac97_pcm_close(ichdev->pcm);
1018 ichdev->pcm_open_flag = 0;
1019 }
1020 return snd_pcm_lib_free_pages(substream);
1021}
1022
1023static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
1024 snd_pcm_runtime_t *runtime)
1025{
1026 unsigned int cnt;
1027 int dbl = runtime->rate > 48000;
1028
1029 spin_lock_irq(&chip->reg_lock);
1030 switch (chip->device_type) {
1031 case DEVICE_ALI:
1032 cnt = igetdword(chip, ICHREG(ALI_SCR));
1033 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1034 if (runtime->channels == 4 || dbl)
1035 cnt |= ICH_ALI_SC_PCM_4;
1036 else if (runtime->channels == 6)
1037 cnt |= ICH_ALI_SC_PCM_6;
1038 iputdword(chip, ICHREG(ALI_SCR), cnt);
1039 break;
1040 case DEVICE_SIS:
1041 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1042 cnt &= ~ICH_SIS_PCM_246_MASK;
1043 if (runtime->channels == 4 || dbl)
1044 cnt |= ICH_SIS_PCM_4;
1045 else if (runtime->channels == 6)
1046 cnt |= ICH_SIS_PCM_6;
1047 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1048 break;
1049 default:
1050 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1051 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1052 if (runtime->channels == 4 || dbl)
1053 cnt |= ICH_PCM_4;
1054 else if (runtime->channels == 6)
1055 cnt |= ICH_PCM_6;
1056 if (chip->device_type == DEVICE_NFORCE) {
1057 /* reset to 2ch once to keep the 6 channel data in alignment,
1058 * to start from Front Left always
1059 */
1060 if (cnt & ICH_PCM_246_MASK) {
1061 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1062 spin_unlock_irq(&chip->reg_lock);
1063 msleep(50); /* grrr... */
1064 spin_lock_irq(&chip->reg_lock);
1065 }
1066 } else if (chip->device_type == DEVICE_INTEL_ICH4 ||
1067 chip->device_type == DEVICE_INTEL_ICH5) {
1068 if (runtime->sample_bits > 16)
1069 cnt |= ICH_PCM_20BIT;
1070 }
1071 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1072 break;
1073 }
1074 spin_unlock_irq(&chip->reg_lock);
1075}
1076
1077static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1078{
1079 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1080 snd_pcm_runtime_t *runtime = substream->runtime;
1081 ichdev_t *ichdev = get_ichdev(substream);
1082
1083 ichdev->physbuf = runtime->dma_addr;
1084 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1085 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1086 if (ichdev->ichd == ICHD_PCMOUT) {
1087 snd_intel8x0_setup_pcm_out(chip, runtime);
1088 if (chip->device_type == DEVICE_INTEL_ICH4 ||
1089 chip->device_type == DEVICE_INTEL_ICH5)
1090 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1091 }
1092 snd_intel8x0_setup_periods(chip, ichdev);
1093 return 0;
1094}
1095
1096static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1097{
1098 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1099 ichdev_t *ichdev = get_ichdev(substream);
1100 size_t ptr1, ptr;
1101 int civ, timeout = 100;
1102 unsigned int position;
1103
1104 spin_lock(&chip->reg_lock);
1105 do {
1106 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1107 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1108 position = ichdev->position;
1109 if (ptr1 == 0) {
1110 udelay(10);
1111 continue;
1112 }
1113 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1114 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1115 break;
1116 } while (timeout--);
1117 ptr1 <<= ichdev->pos_shift;
1118 ptr = ichdev->fragsize1 - ptr1;
1119 ptr += position;
1120 spin_unlock(&chip->reg_lock);
1121 if (ptr >= ichdev->size)
1122 return 0;
1123 return bytes_to_frames(substream->runtime, ptr);
1124}
1125
1126static snd_pcm_hardware_t snd_intel8x0_stream =
1127{
1128 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1129 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1130 SNDRV_PCM_INFO_MMAP_VALID |
1131 SNDRV_PCM_INFO_PAUSE |
1132 SNDRV_PCM_INFO_RESUME),
1133 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1134 .rates = SNDRV_PCM_RATE_48000,
1135 .rate_min = 48000,
1136 .rate_max = 48000,
1137 .channels_min = 2,
1138 .channels_max = 2,
1139 .buffer_bytes_max = 128 * 1024,
1140 .period_bytes_min = 32,
1141 .period_bytes_max = 128 * 1024,
1142 .periods_min = 1,
1143 .periods_max = 1024,
1144 .fifo_size = 0,
1145};
1146
1147static unsigned int channels4[] = {
1148 2, 4,
1149};
1150
1151static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1152 .count = ARRAY_SIZE(channels4),
1153 .list = channels4,
1154 .mask = 0,
1155};
1156
1157static unsigned int channels6[] = {
1158 2, 4, 6,
1159};
1160
1161static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1162 .count = ARRAY_SIZE(channels6),
1163 .list = channels6,
1164 .mask = 0,
1165};
1166
1167static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1168{
1169 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1170 snd_pcm_runtime_t *runtime = substream->runtime;
1171 int err;
1172
1173 ichdev->substream = substream;
1174 runtime->hw = snd_intel8x0_stream;
1175 runtime->hw.rates = ichdev->pcm->rates;
1176 snd_pcm_limit_hw_rates(runtime);
1177 if (chip->device_type == DEVICE_SIS) {
1178 // vladest workaround
1179 if (!runtime->hw.rates)
1180 runtime->hw.rates = SNDRV_PCM_RATE_48000;
1181 runtime->hw.buffer_bytes_max = 64*1024;
1182 runtime->hw.period_bytes_max = 64*1024;
1183 }
1184 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1185 return err;
1186 runtime->private_data = ichdev;
1187 return 0;
1188}
1189
1190static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1191{
1192 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1193 snd_pcm_runtime_t *runtime = substream->runtime;
1194 int err;
1195
1196 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1197 if (err < 0)
1198 return err;
1199 if (chip->multi6) {
1200 runtime->hw.channels_max = 6;
1201 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1202 } else if (chip->multi4) {
1203 runtime->hw.channels_max = 4;
1204 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1205 }
1206 if (chip->dra) {
1207 snd_ac97_pcm_double_rate_rules(runtime);
1208 }
1209 if (chip->smp20bit)
1210 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1211 return 0;
1212}
1213
1214static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1215{
1216 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1217
1218 chip->ichd[ICHD_PCMOUT].substream = NULL;
1219 return 0;
1220}
1221
1222static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1223{
1224 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1225
1226 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1227}
1228
1229static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1230{
1231 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1232
1233 chip->ichd[ICHD_PCMIN].substream = NULL;
1234 return 0;
1235}
1236
1237static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1238{
1239 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1240
1241 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1242}
1243
1244static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1245{
1246 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1247
1248 chip->ichd[ICHD_MIC].substream = NULL;
1249 return 0;
1250}
1251
1252static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1253{
1254 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1255
1256 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1257}
1258
1259static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1260{
1261 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1262
1263 chip->ichd[ICHD_MIC2].substream = NULL;
1264 return 0;
1265}
1266
1267static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1268{
1269 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1270
1271 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1272}
1273
1274static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1275{
1276 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1277
1278 chip->ichd[ICHD_PCM2IN].substream = NULL;
1279 return 0;
1280}
1281
1282static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1283{
1284 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1285 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1286
1287 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1288}
1289
1290static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1291{
1292 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1293 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1294
1295 chip->ichd[idx].substream = NULL;
1296 return 0;
1297}
1298
1299static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1300{
1301 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1302 unsigned int val;
1303
1304 spin_lock_irq(&chip->reg_lock);
1305 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1306 val |= ICH_ALI_IF_AC97SP;
1307 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1308 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1309 spin_unlock_irq(&chip->reg_lock);
1310
1311 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1312}
1313
1314static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1315{
1316 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1317 unsigned int val;
1318
1319 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1320 spin_lock_irq(&chip->reg_lock);
1321 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1322 val &= ~ICH_ALI_IF_AC97SP;
1323 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1324 spin_unlock_irq(&chip->reg_lock);
1325
1326 return 0;
1327}
1328
1329static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1330{
1331 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1332
1333 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1334}
1335
1336static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1337{
1338 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1339
1340 chip->ichd[ALID_SPDIFIN].substream = NULL;
1341 return 0;
1342}
1343
1344#if 0 // NYI
1345static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1346{
1347 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1348
1349 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1350}
1351
1352static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1353{
1354 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1355
1356 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1357 return 0;
1358}
1359#endif
1360
1361static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1362 .open = snd_intel8x0_playback_open,
1363 .close = snd_intel8x0_playback_close,
1364 .ioctl = snd_pcm_lib_ioctl,
1365 .hw_params = snd_intel8x0_hw_params,
1366 .hw_free = snd_intel8x0_hw_free,
1367 .prepare = snd_intel8x0_pcm_prepare,
1368 .trigger = snd_intel8x0_pcm_trigger,
1369 .pointer = snd_intel8x0_pcm_pointer,
1370};
1371
1372static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1373 .open = snd_intel8x0_capture_open,
1374 .close = snd_intel8x0_capture_close,
1375 .ioctl = snd_pcm_lib_ioctl,
1376 .hw_params = snd_intel8x0_hw_params,
1377 .hw_free = snd_intel8x0_hw_free,
1378 .prepare = snd_intel8x0_pcm_prepare,
1379 .trigger = snd_intel8x0_pcm_trigger,
1380 .pointer = snd_intel8x0_pcm_pointer,
1381};
1382
1383static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1384 .open = snd_intel8x0_mic_open,
1385 .close = snd_intel8x0_mic_close,
1386 .ioctl = snd_pcm_lib_ioctl,
1387 .hw_params = snd_intel8x0_hw_params,
1388 .hw_free = snd_intel8x0_hw_free,
1389 .prepare = snd_intel8x0_pcm_prepare,
1390 .trigger = snd_intel8x0_pcm_trigger,
1391 .pointer = snd_intel8x0_pcm_pointer,
1392};
1393
1394static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1395 .open = snd_intel8x0_mic2_open,
1396 .close = snd_intel8x0_mic2_close,
1397 .ioctl = snd_pcm_lib_ioctl,
1398 .hw_params = snd_intel8x0_hw_params,
1399 .hw_free = snd_intel8x0_hw_free,
1400 .prepare = snd_intel8x0_pcm_prepare,
1401 .trigger = snd_intel8x0_pcm_trigger,
1402 .pointer = snd_intel8x0_pcm_pointer,
1403};
1404
1405static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1406 .open = snd_intel8x0_capture2_open,
1407 .close = snd_intel8x0_capture2_close,
1408 .ioctl = snd_pcm_lib_ioctl,
1409 .hw_params = snd_intel8x0_hw_params,
1410 .hw_free = snd_intel8x0_hw_free,
1411 .prepare = snd_intel8x0_pcm_prepare,
1412 .trigger = snd_intel8x0_pcm_trigger,
1413 .pointer = snd_intel8x0_pcm_pointer,
1414};
1415
1416static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1417 .open = snd_intel8x0_spdif_open,
1418 .close = snd_intel8x0_spdif_close,
1419 .ioctl = snd_pcm_lib_ioctl,
1420 .hw_params = snd_intel8x0_hw_params,
1421 .hw_free = snd_intel8x0_hw_free,
1422 .prepare = snd_intel8x0_pcm_prepare,
1423 .trigger = snd_intel8x0_pcm_trigger,
1424 .pointer = snd_intel8x0_pcm_pointer,
1425};
1426
1427static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1428 .open = snd_intel8x0_playback_open,
1429 .close = snd_intel8x0_playback_close,
1430 .ioctl = snd_pcm_lib_ioctl,
1431 .hw_params = snd_intel8x0_hw_params,
1432 .hw_free = snd_intel8x0_hw_free,
1433 .prepare = snd_intel8x0_pcm_prepare,
1434 .trigger = snd_intel8x0_ali_trigger,
1435 .pointer = snd_intel8x0_pcm_pointer,
1436};
1437
1438static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1439 .open = snd_intel8x0_capture_open,
1440 .close = snd_intel8x0_capture_close,
1441 .ioctl = snd_pcm_lib_ioctl,
1442 .hw_params = snd_intel8x0_hw_params,
1443 .hw_free = snd_intel8x0_hw_free,
1444 .prepare = snd_intel8x0_pcm_prepare,
1445 .trigger = snd_intel8x0_ali_trigger,
1446 .pointer = snd_intel8x0_pcm_pointer,
1447};
1448
1449static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1450 .open = snd_intel8x0_mic_open,
1451 .close = snd_intel8x0_mic_close,
1452 .ioctl = snd_pcm_lib_ioctl,
1453 .hw_params = snd_intel8x0_hw_params,
1454 .hw_free = snd_intel8x0_hw_free,
1455 .prepare = snd_intel8x0_pcm_prepare,
1456 .trigger = snd_intel8x0_ali_trigger,
1457 .pointer = snd_intel8x0_pcm_pointer,
1458};
1459
1460static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1461 .open = snd_intel8x0_ali_ac97spdifout_open,
1462 .close = snd_intel8x0_ali_ac97spdifout_close,
1463 .ioctl = snd_pcm_lib_ioctl,
1464 .hw_params = snd_intel8x0_hw_params,
1465 .hw_free = snd_intel8x0_hw_free,
1466 .prepare = snd_intel8x0_pcm_prepare,
1467 .trigger = snd_intel8x0_ali_trigger,
1468 .pointer = snd_intel8x0_pcm_pointer,
1469};
1470
1471static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1472 .open = snd_intel8x0_ali_spdifin_open,
1473 .close = snd_intel8x0_ali_spdifin_close,
1474 .ioctl = snd_pcm_lib_ioctl,
1475 .hw_params = snd_intel8x0_hw_params,
1476 .hw_free = snd_intel8x0_hw_free,
1477 .prepare = snd_intel8x0_pcm_prepare,
1478 .trigger = snd_intel8x0_pcm_trigger,
1479 .pointer = snd_intel8x0_pcm_pointer,
1480};
1481
1482#if 0 // NYI
1483static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1484 .open = snd_intel8x0_ali_spdifout_open,
1485 .close = snd_intel8x0_ali_spdifout_close,
1486 .ioctl = snd_pcm_lib_ioctl,
1487 .hw_params = snd_intel8x0_hw_params,
1488 .hw_free = snd_intel8x0_hw_free,
1489 .prepare = snd_intel8x0_pcm_prepare,
1490 .trigger = snd_intel8x0_pcm_trigger,
1491 .pointer = snd_intel8x0_pcm_pointer,
1492};
1493#endif // NYI
1494
1495
1496struct ich_pcm_table {
1497 char *suffix;
1498 snd_pcm_ops_t *playback_ops;
1499 snd_pcm_ops_t *capture_ops;
1500 size_t prealloc_size;
1501 size_t prealloc_max_size;
1502 int ac97_idx;
1503};
1504
1505static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1506{
1507 snd_pcm_t *pcm;
1508 int err;
1509 char name[32];
1510
1511 if (rec->suffix)
1512 sprintf(name, "Intel ICH - %s", rec->suffix);
1513 else
1514 strcpy(name, "Intel ICH");
1515 err = snd_pcm_new(chip->card, name, device,
1516 rec->playback_ops ? 1 : 0,
1517 rec->capture_ops ? 1 : 0, &pcm);
1518 if (err < 0)
1519 return err;
1520
1521 if (rec->playback_ops)
1522 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1523 if (rec->capture_ops)
1524 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1525
1526 pcm->private_data = chip;
1527 pcm->info_flags = 0;
1528 if (rec->suffix)
1529 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1530 else
1531 strcpy(pcm->name, chip->card->shortname);
1532 chip->pcm[device] = pcm;
1533
1534 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1535 rec->prealloc_size, rec->prealloc_max_size);
1536
1537 return 0;
1538}
1539
1540static struct ich_pcm_table intel_pcms[] __devinitdata = {
1541 {
1542 .playback_ops = &snd_intel8x0_playback_ops,
1543 .capture_ops = &snd_intel8x0_capture_ops,
1544 .prealloc_size = 64 * 1024,
1545 .prealloc_max_size = 128 * 1024,
1546 },
1547 {
1548 .suffix = "MIC ADC",
1549 .capture_ops = &snd_intel8x0_capture_mic_ops,
1550 .prealloc_size = 0,
1551 .prealloc_max_size = 128 * 1024,
1552 .ac97_idx = ICHD_MIC,
1553 },
1554 {
1555 .suffix = "MIC2 ADC",
1556 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1557 .prealloc_size = 0,
1558 .prealloc_max_size = 128 * 1024,
1559 .ac97_idx = ICHD_MIC2,
1560 },
1561 {
1562 .suffix = "ADC2",
1563 .capture_ops = &snd_intel8x0_capture2_ops,
1564 .prealloc_size = 0,
1565 .prealloc_max_size = 128 * 1024,
1566 .ac97_idx = ICHD_PCM2IN,
1567 },
1568 {
1569 .suffix = "IEC958",
1570 .playback_ops = &snd_intel8x0_spdif_ops,
1571 .prealloc_size = 64 * 1024,
1572 .prealloc_max_size = 128 * 1024,
1573 .ac97_idx = ICHD_SPBAR,
1574 },
1575};
1576
1577static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1578 {
1579 .playback_ops = &snd_intel8x0_playback_ops,
1580 .capture_ops = &snd_intel8x0_capture_ops,
1581 .prealloc_size = 64 * 1024,
1582 .prealloc_max_size = 128 * 1024,
1583 },
1584 {
1585 .suffix = "MIC ADC",
1586 .capture_ops = &snd_intel8x0_capture_mic_ops,
1587 .prealloc_size = 0,
1588 .prealloc_max_size = 128 * 1024,
1589 .ac97_idx = NVD_MIC,
1590 },
1591 {
1592 .suffix = "IEC958",
1593 .playback_ops = &snd_intel8x0_spdif_ops,
1594 .prealloc_size = 64 * 1024,
1595 .prealloc_max_size = 128 * 1024,
1596 .ac97_idx = NVD_SPBAR,
1597 },
1598};
1599
1600static struct ich_pcm_table ali_pcms[] __devinitdata = {
1601 {
1602 .playback_ops = &snd_intel8x0_ali_playback_ops,
1603 .capture_ops = &snd_intel8x0_ali_capture_ops,
1604 .prealloc_size = 64 * 1024,
1605 .prealloc_max_size = 128 * 1024,
1606 },
1607 {
1608 .suffix = "MIC ADC",
1609 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1610 .prealloc_size = 0,
1611 .prealloc_max_size = 128 * 1024,
1612 .ac97_idx = ALID_MIC,
1613 },
1614 {
1615 .suffix = "IEC958",
1616 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1617 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1618 .prealloc_size = 64 * 1024,
1619 .prealloc_max_size = 128 * 1024,
1620 .ac97_idx = ALID_AC97SPDIFOUT,
1621 },
1622#if 0 // NYI
1623 {
1624 .suffix = "HW IEC958",
1625 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1626 .prealloc_size = 64 * 1024,
1627 .prealloc_max_size = 128 * 1024,
1628 },
1629#endif
1630};
1631
1632
1633static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1634{
1635 int i, tblsize, device, err;
1636 struct ich_pcm_table *tbl, *rec;
1637
1638 switch (chip->device_type) {
1639 case DEVICE_INTEL_ICH4:
1640 case DEVICE_INTEL_ICH5:
1641 tbl = intel_pcms;
1642 tblsize = ARRAY_SIZE(intel_pcms);
1643 break;
1644 case DEVICE_NFORCE:
1645 tbl = nforce_pcms;
1646 tblsize = ARRAY_SIZE(nforce_pcms);
1647 break;
1648 case DEVICE_ALI:
1649 tbl = ali_pcms;
1650 tblsize = ARRAY_SIZE(ali_pcms);
1651 break;
1652 default:
1653 tbl = intel_pcms;
1654 tblsize = 2;
1655 break;
1656 }
1657
1658 device = 0;
1659 for (i = 0; i < tblsize; i++) {
1660 rec = tbl + i;
1661 if (i > 0 && rec->ac97_idx) {
1662 /* activate PCM only when associated AC'97 codec */
1663 if (! chip->ichd[rec->ac97_idx].pcm)
1664 continue;
1665 }
1666 err = snd_intel8x0_pcm1(chip, device, rec);
1667 if (err < 0)
1668 return err;
1669 device++;
1670 }
1671
1672 chip->pcm_devs = device;
1673 return 0;
1674}
1675
1676
1677/*
1678 * Mixer part
1679 */
1680
1681static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1682{
1683 intel8x0_t *chip = bus->private_data;
1684 chip->ac97_bus = NULL;
1685}
1686
1687static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1688{
1689 intel8x0_t *chip = ac97->private_data;
1690 chip->ac97[ac97->num] = NULL;
1691}
1692
1693static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1694 /* front PCM */
1695 {
1696 .exclusive = 1,
1697 .r =
1698 {
1699 {
1700 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1701 (1 << AC97_SLOT_PCM_RIGHT) |
1702 (1 << AC97_SLOT_PCM_CENTER) |
1703 (1 << AC97_SLOT_PCM_SLEFT) |
1704 (1 << AC97_SLOT_PCM_SRIGHT) |
1705 (1 << AC97_SLOT_LFE)
1706 },
1707 {
1708 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1709 (1 << AC97_SLOT_PCM_RIGHT) |
1710 (1 << AC97_SLOT_PCM_LEFT_0) |
1711 (1 << AC97_SLOT_PCM_RIGHT_0)
1712 }
1713 }
1714 },
1715 /* PCM IN #1 */
1716 {
1717 .stream = 1,
1718 .exclusive = 1,
1719 .r = { {
1720 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1721 (1 << AC97_SLOT_PCM_RIGHT)
1722 }
1723 }
1724 },
1725 /* MIC IN #1 */
1726 {
1727 .stream = 1,
1728 .exclusive = 1,
1729 .r = { {
1730 .slots = (1 << AC97_SLOT_MIC)
1731 }
1732 }
1733 },
1734 /* S/PDIF PCM */
1735 {
1736 .exclusive = 1,
1737 .spdif = 1,
1738 .r = { {
1739 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1740 (1 << AC97_SLOT_SPDIF_RIGHT2)
1741 }
1742 }
1743 },
1744 /* PCM IN #2 */
1745 {
1746 .stream = 1,
1747 .exclusive = 1,
1748 .r = { {
1749 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1750 (1 << AC97_SLOT_PCM_RIGHT)
1751 }
1752 }
1753 },
1754 /* MIC IN #2 */
1755 {
1756 .stream = 1,
1757 .exclusive = 1,
1758 .r = { {
1759 .slots = (1 << AC97_SLOT_MIC)
1760 }
1761 }
1762 },
1763};
1764
1765static struct ac97_quirk ac97_quirks[] __devinitdata = {
1766 {
1767 .subvendor = 0x0e11,
1768 .subdevice = 0x008a,
1769 .name = "Compaq Evo W4000", /* AD1885 */
1770 .type = AC97_TUNE_HP_ONLY
1771 },
1772 {
1773 .subvendor = 0x0e11,
1774 .subdevice = 0x00b8,
1775 .name = "Compaq Evo D510C",
1776 .type = AC97_TUNE_HP_ONLY
1777 },
1778 {
1779 .subvendor = 0x0e11,
1780 .subdevice = 0x0860,
1781 .name = "HP/Compaq nx7010",
1782 .type = AC97_TUNE_MUTE_LED
1783 },
1784 {
1785 .subvendor = 0x1014,
1786 .subdevice = 0x1f00,
1787 .name = "MS-9128",
1788 .type = AC97_TUNE_ALC_JACK
1789 },
1790 {
1791 .subvendor = 0x1014,
1792 .subdevice = 0x0267,
1793 .name = "IBM NetVista A30p", /* AD1981B */
1794 .type = AC97_TUNE_HP_ONLY
1795 },
1796 {
1797 .subvendor = 0x1025,
1798 .subdevice = 0x0083,
1799 .name = "Acer Aspire 3003LCi",
1800 .type = AC97_TUNE_HP_ONLY
1801 },
1802 {
1803 .subvendor = 0x1028,
1804 .subdevice = 0x00d8,
1805 .name = "Dell Precision 530", /* AD1885 */
1806 .type = AC97_TUNE_HP_ONLY
1807 },
1808 {
1809 .subvendor = 0x1028,
1810 .subdevice = 0x010d,
1811 .name = "Dell", /* which model? AD1885 */
1812 .type = AC97_TUNE_HP_ONLY
1813 },
1814 {
1815 .subvendor = 0x1028,
1816 .subdevice = 0x0126,
1817 .name = "Dell Optiplex GX260", /* AD1981A */
1818 .type = AC97_TUNE_HP_ONLY
1819 },
1820 {
1821 .subvendor = 0x1028,
1822 .subdevice = 0x012c,
1823 .name = "Dell Precision 650", /* AD1981A */
1824 .type = AC97_TUNE_HP_ONLY
1825 },
1826 {
1827 .subvendor = 0x1028,
1828 .subdevice = 0x012d,
1829 .name = "Dell Precision 450", /* AD1981B*/
1830 .type = AC97_TUNE_HP_ONLY
1831 },
1832 {
1833 .subvendor = 0x1028,
1834 .subdevice = 0x0147,
1835 .name = "Dell", /* which model? AD1981B*/
1836 .type = AC97_TUNE_HP_ONLY
1837 },
1838 {
1839 .subvendor = 0x1028,
1840 .subdevice = 0x0163,
1841 .name = "Dell Unknown", /* STAC9750/51 */
1842 .type = AC97_TUNE_HP_ONLY
1843 },
1844 {
1845 .subvendor = 0x1028,
1846 .subdevice = 0x0191,
1847 .name = "Dell Inspiron 8600",
1848 .type = AC97_TUNE_HP_ONLY
1849 },
1850 {
1851 .subvendor = 0x103c,
1852 .subdevice = 0x006d,
1853 .name = "HP zv5000",
1854 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1855 },
1856 { /* FIXME: which codec? */
1857 .subvendor = 0x103c,
1858 .subdevice = 0x00c3,
1859 .name = "HP xw6000",
1860 .type = AC97_TUNE_HP_ONLY
1861 },
1862 {
1863 .subvendor = 0x103c,
1864 .subdevice = 0x088c,
1865 .name = "HP nc8000",
1866 .type = AC97_TUNE_MUTE_LED
1867 },
1868 {
1869 .subvendor = 0x103c,
1870 .subdevice = 0x0890,
1871 .name = "HP nc6000",
1872 .type = AC97_TUNE_MUTE_LED
1873 },
1874 {
1875 .subvendor = 0x103c,
1876 .subdevice = 0x0934,
1877 .name = "HP nx8220",
1878 .type = AC97_TUNE_MUTE_LED
1879 },
1880 {
1881 .subvendor = 0x103c,
1882 .subdevice = 0x099c,
1883 .name = "HP nx6110", /* AD1981B */
1884 .type = AC97_TUNE_HP_ONLY
1885 },
1886 {
1887 .subvendor = 0x103c,
1888 .subdevice = 0x129d,
1889 .name = "HP xw8000",
1890 .type = AC97_TUNE_HP_ONLY
1891 },
1892 {
1893 .subvendor = 0x103c,
1894 .subdevice = 0x12f1,
1895 .name = "HP xw8200", /* AD1981B*/
1896 .type = AC97_TUNE_HP_ONLY
1897 },
1898 {
1899 .subvendor = 0x103c,
1900 .subdevice = 0x12f2,
1901 .name = "HP xw6200",
1902 .type = AC97_TUNE_HP_ONLY
1903 },
1904 {
1905 .subvendor = 0x103c,
1906 .subdevice = 0x3008,
1907 .name = "HP xw4200", /* AD1981B*/
1908 .type = AC97_TUNE_HP_ONLY
1909 },
1910 {
1911 .subvendor = 0x104d,
1912 .subdevice = 0x8197,
1913 .name = "Sony S1XP",
1914 .type = AC97_TUNE_INV_EAPD
1915 },
1916 {
1917 .subvendor = 0x1043,
1918 .subdevice = 0x80f3,
1919 .name = "ASUS ICH5/AD1985",
1920 .type = AC97_TUNE_AD_SHARING
1921 },
1922 {
1923 .subvendor = 0x10cf,
1924 .subdevice = 0x11c3,
1925 .name = "Fujitsu-Siemens E4010",
1926 .type = AC97_TUNE_HP_ONLY
1927 },
1928 {
1929 .subvendor = 0x10cf,
1930 .subdevice = 0x1225,
1931 .name = "Fujitsu-Siemens T3010",
1932 .type = AC97_TUNE_HP_ONLY
1933 },
1934 {
1935 .subvendor = 0x10cf,
1936 .subdevice = 0x1253,
1937 .name = "Fujitsu S6210", /* STAC9750/51 */
1938 .type = AC97_TUNE_HP_ONLY
1939 },
1940 {
1941 .subvendor = 0x10cf,
1942 .subdevice = 0x12ec,
1943 .name = "Fujitsu-Siemens 4010",
1944 .type = AC97_TUNE_HP_ONLY
1945 },
1946 {
1947 .subvendor = 0x10f1,
1948 .subdevice = 0x2665,
1949 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1950 .type = AC97_TUNE_HP_ONLY
1951 },
1952 {
1953 .subvendor = 0x10f1,
1954 .subdevice = 0x2885,
1955 .name = "AMD64 Mobo", /* ALC650 */
1956 .type = AC97_TUNE_HP_ONLY
1957 },
1958 {
1959 .subvendor = 0x110a,
1960 .subdevice = 0x0056,
1961 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1962 .type = AC97_TUNE_HP_ONLY
1963 },
1964 {
1965 .subvendor = 0x11d4,
1966 .subdevice = 0x5375,
1967 .name = "ADI AD1985 (discrete)",
1968 .type = AC97_TUNE_HP_ONLY
1969 },
1970 {
1971 .subvendor = 0x1462,
1972 .subdevice = 0x5470,
1973 .name = "MSI P4 ATX 645 Ultra",
1974 .type = AC97_TUNE_HP_ONLY
1975 },
1976 {
1977 .subvendor = 0x1734,
1978 .subdevice = 0x0088,
1979 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1980 .type = AC97_TUNE_HP_ONLY
1981 },
1982 {
1983 .subvendor = 0x8086,
1984 .subdevice = 0x2000,
1985 .mask = 0xfff0,
1986 .name = "Intel ICH5/AD1985",
1987 .type = AC97_TUNE_AD_SHARING
1988 },
1989 {
1990 .subvendor = 0x8086,
1991 .subdevice = 0x4000,
1992 .mask = 0xfff0,
1993 .name = "Intel ICH5/AD1985",
1994 .type = AC97_TUNE_AD_SHARING
1995 },
1996 {
1997 .subvendor = 0x8086,
1998 .subdevice = 0x4856,
1999 .name = "Intel D845WN (82801BA)",
2000 .type = AC97_TUNE_SWAP_HP
2001 },
2002 {
2003 .subvendor = 0x8086,
2004 .subdevice = 0x4d44,
2005 .name = "Intel D850EMV2", /* AD1885 */
2006 .type = AC97_TUNE_HP_ONLY
2007 },
2008 {
2009 .subvendor = 0x8086,
2010 .subdevice = 0x4d56,
2011 .name = "Intel ICH/AD1885",
2012 .type = AC97_TUNE_HP_ONLY
2013 },
2014 {
2015 .subvendor = 0x8086,
2016 .subdevice = 0x6000,
2017 .mask = 0xfff0,
2018 .name = "Intel ICH5/AD1985",
2019 .type = AC97_TUNE_AD_SHARING
2020 },
2021 {
2022 .subvendor = 0x8086,
2023 .subdevice = 0xe000,
2024 .mask = 0xfff0,
2025 .name = "Intel ICH5/AD1985",
2026 .type = AC97_TUNE_AD_SHARING
2027 },
2028#if 0 /* FIXME: this seems wrong on most boards */
2029 {
2030 .subvendor = 0x8086,
2031 .subdevice = 0xa000,
2032 .mask = 0xfff0,
2033 .name = "Intel ICH5/AD1985",
2034 .type = AC97_TUNE_HP_ONLY
2035 },
2036#endif
2037 {0} /* terminator */
2038};
2039
2040static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, char *quirk_override)
2041{
2042 ac97_bus_t *pbus;
2043 ac97_template_t ac97;
2044 int err;
2045 unsigned int i, codecs;
2046 unsigned int glob_sta = 0;
2047 ac97_bus_ops_t *ops;
2048 static ac97_bus_ops_t standard_bus_ops = {
2049 0,snd_intel8x0_codec_write,
2050 snd_intel8x0_codec_read,0,0
2051 };
2052 static ac97_bus_ops_t ali_bus_ops = {
2053 0,snd_intel8x0_ali_codec_write,
2054 snd_intel8x0_ali_codec_read,0,0
2055 };
2056 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2057 switch (chip->device_type) {
2058 case DEVICE_NFORCE:
2059 chip->spdif_idx = NVD_SPBAR;
2060 break;
2061 case DEVICE_ALI:
2062 chip->spdif_idx = ALID_AC97SPDIFOUT;
2063 break;
2064 case DEVICE_INTEL_ICH4:
2065 case DEVICE_INTEL_ICH5:
2066 chip->spdif_idx = ICHD_SPBAR;
2067 break;
2068 };
2069
2070 chip->in_ac97_init = 1;
2071
2072 memset(&ac97, 0, sizeof(ac97));
2073 ac97.private_data = chip;
2074 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2075 ac97.scaps = AC97_SCAP_SKIP_MODEM;
2076 if (chip->device_type != DEVICE_ALI) {
2077 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2078 ops = &standard_bus_ops;
2079 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2080 chip->device_type == DEVICE_INTEL_ICH5) {
2081 codecs = 0;
2082 if (glob_sta & ICH_PCR)
2083 codecs++;
2084 if (glob_sta & ICH_SCR)
2085 codecs++;
2086 if (glob_sta & ICH_TCR)
2087 codecs++;
2088 chip->in_sdin_init = 1;
2089#if 1 //vladest 06.10.2003 15:55 - bull shit!!! it doesnt works here
2090 for (i = 0; i < codecs; i++) {
2091 printk("codec %i read test begins...", i);
2092 snd_intel8x0_codec_read_test(chip, i);
2093 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2094 printk("finished\n");
2095 }
2096#endif
2097 chip->in_sdin_init = 0;
2098 } else {
2099 codecs = glob_sta & ICH_SCR ? 2 : 1;
2100 }
2101 } else {
2102 ops = &ali_bus_ops;
2103 codecs = 1;
2104 /* detect the secondary codec */
2105 for (i = 0; i < 100; i++) {
2106 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2107 if (reg & 0x40) {
2108 codecs = 2;
2109 break;
2110 }
2111 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2112 udelay(1);
2113 }
2114 }
2115 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2116 goto __err;
2117 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2118 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */
2119 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2120 pbus->clock = ac97_clock;
2121 /* FIXME: my test board doesn't work well with VRA... */
2122 if (chip->device_type == DEVICE_ALI)
2123 pbus->no_vra = 1;
2124 else
2125 pbus->dra = 1;
2126 chip->ac97_bus = pbus;
2127
2128 ac97.pci = chip->pci;
2129 for (i = 0; i < codecs; i++) {
2130 ac97.num = i;
2131 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2132 if (err != -EACCES)
2133 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2134 if (i == 0)
2135 goto __err;
2136 continue;
2137 }
2138 }
2139 /* tune up the primary codec */
2140 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2141 /* enable separate SDINs for ICH4 */
2142 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2143 chip->device_type == DEVICE_INTEL_ICH5)
2144 pbus->isdin = 1;
2145 /* find the available PCM streams */
2146 i = ARRAY_SIZE(ac97_pcm_defs);
2147 if (chip->device_type != DEVICE_INTEL_ICH4 &&
2148 chip->device_type != DEVICE_INTEL_ICH5)
2149 i -= 2; /* do not allocate PCM2IN and MIC2 */
2150 if (chip->spdif_idx < 0)
2151 i--; /* do not allocate S/PDIF */
2152 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2153 if (err < 0)
2154 goto __err;
2155 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2156 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2157 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2158 if (chip->spdif_idx >= 0)
2159 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2160 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2161 chip->device_type == DEVICE_INTEL_ICH5) {
2162 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2163 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2164 }
2165 /* enable separate SDINs for ICH4 */
2166 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2167 chip->device_type == DEVICE_INTEL_ICH5) {
2168 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2169 u8 tmp = igetbyte(chip, ICHREG(SDM));
2170 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2171 if (pcm) {
2172 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2173 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2174 for (i = 1; i < 4; i++) {
2175 if (pcm->r[0].codec[i]) {
2176 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2177 break;
2178 }
2179 }
2180 } else {
2181 tmp &= ~ICH_SE; /* steer disable */
2182 }
2183 iputbyte(chip, ICHREG(SDM), tmp);
2184 }
2185 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2186 chip->multi4 = 1;
2187 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2188 chip->multi6 = 1;
2189 }
2190 if (pbus->pcms[0].r[1].rslots[0]) {
2191 chip->dra = 1;
2192 }
2193 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2194 chip->device_type == DEVICE_INTEL_ICH5) {
2195 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2196 chip->smp20bit = 1;
2197 }
2198 if (chip->device_type == DEVICE_NFORCE) {
2199 /* 48kHz only */
2200 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2201 }
2202
2203 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2204 chip->device_type == DEVICE_INTEL_ICH5) {
2205 /* use slot 10/11 for SPDIF */
2206 u32 val;
2207 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2208 val |= ICH_PCM_SPDIF_1011;
2209 iputdword(chip, ICHREG(GLOB_CNT), val);
2210 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2211 }
2212 chip->in_ac97_init = 0;
2213 return 0;
2214
2215 __err:
2216 /* clear the cold-reset bit for the next chance */
2217 if (chip->device_type != DEVICE_ALI)
2218 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2219 return err;
2220}
2221
2222
2223/*
2224 *
2225 */
2226
2227static void do_ali_reset(intel8x0_t *chip)
2228{
2229 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2230 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2231 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2232 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2233 iputdword(chip, ICHREG(ALI_INTERFACECR),
2234 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2235 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2236 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2237}
2238
2239#define do_delay(chip) do {\
2240 set_current_state(TASK_UNINTERRUPTIBLE);\
2241 schedule_timeout(1);\
2242 } while (0)
2243
2244static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2245{
2246 unsigned long end_time;
2247 unsigned int cnt, status, nstatus,i;
2248
2249#ifdef DEBUG
2250 dprintf(("ICH chip init begins"));
2251#endif
2252 /* put logic to right state */
2253 /* first clear status bits */
2254#if 1 // noone do it. wtf? //vladest 06.10.2003 13:51
2255 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2256 if (chip->device_type == DEVICE_NFORCE)
2257 status |= ICH_NVSPINT;
2258 cnt = igetdword(chip, ICHREG(GLOB_STA));
2259 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2260#endif
2261 // hmm. at least we should try
2262 //iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2263 /* ACLink on, 2 channels */
2264 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2265 // added by vladest
2266 // cnt &= ~ICH_ACLINK;
2267 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2268 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2269
2270 // ??? 25.03.2004 by vladest cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2271 // FIXME!!! cmi drivers didnt uses ICH_PCM_246_MASK
2272 /* finish cold or do warm reset */
2273#ifdef DEBUG
2274 dprintf(("ICH chip init try to wake up ACLink with %x",cnt));
2275#endif
2276 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2277// mdelay(500); //vladest 06.10.2003 15:08
2278 end_time = (jiffies + (HZ / 4)) + 1;
2279 i = 0;
2280 do {
2281 cnt=igetdword(chip, ICHREG(GLOB_CNT));
2282 if ((cnt & ICH_AC97WARM) == 0)
2283 goto __ok;
2284#ifdef DEBUG
2285 dprintf(("ICH chip init ACLink ON. try no %d got %x",i,cnt));
2286#endif
2287 do_delay(chip);
2288 i++;
2289 } while (i<100); //(time_after_eq(end_time, jiffies));
2290 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2291 return -EIO;
2292__ok:
2293#ifdef DEBUG
2294 dprintf(("ICH chip init ACLink ON"));
2295#endif
2296
2297// mdelay(50);
2298
2299 if (probing) {
2300 /* wait for any codec ready status.
2301 * Once it becomes ready it should remain ready
2302 * as long as we do not disable the ac97 link.
2303 */
2304 end_time = jiffies + HZ;
2305 i = 0;
2306 do {
2307 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2308 if (status)
2309 break;
2310 mdelay(1);
2311 //do_delay(chip);
2312 i++;
2313 } while (i<100);/*(time_after_eq(end_time, jiffies));*/
2314
2315 if (! status) {
2316 /* no codec is found */
2317 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2318 return -EIO;
2319 }
2320#ifdef DEBUG
2321 dprintf(("ICH chip init codec ready"));
2322#endif
2323// mdelay(50);
2324
2325 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2326 chip->device_type == DEVICE_INTEL_ICH5)
2327 /* ICH4 can have three codecs */
2328 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2329 else
2330 /* others up to two codecs */
2331 nstatus = ICH_PCR | ICH_SCR;
2332 /* wait for other codecs ready status. */
2333 end_time = jiffies + HZ / 4;
2334 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2335 do_delay(chip);
2336 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2337 }
2338 } else {
2339 /* resume phase */
2340 int i;
2341 status = 0;
2342 for (i = 0; i < 3; i++)
2343 if (chip->ac97[i])
2344 status |= get_ich_codec_bit(chip, i);
2345 /* wait until all the probed codecs are ready */
2346 end_time = jiffies + HZ;
2347 do {
2348 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2349 if (status == nstatus)
2350 break;
2351 do_delay(chip);
2352 } while (time_after_eq(end_time, jiffies));
2353 }
2354
2355 if (chip->device_type == DEVICE_SIS) {
2356 /* unmute the output on SIS7012 */
2357 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2358 }
2359 if (chip->device_type == DEVICE_NFORCE) {
2360 /* enable SPDIF interrupt */
2361 unsigned int val;
2362 pci_read_config_dword(chip->pci, 0x4c, &val);
2363 val |= 0x1000000;
2364 pci_write_config_dword(chip->pci, 0x4c, val);
2365 }
2366#ifdef DEBUG
2367 dprintf(("ICH chip init finished"));
2368#endif
2369
2370 return 0;
2371}
2372
2373static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2374{
2375 u32 reg;
2376 int i = 0;
2377
2378 reg = igetdword(chip, ICHREG(ALI_SCR));
2379 if ((reg & 2) == 0) /* Cold required */
2380 reg |= 2;
2381 else
2382 reg |= 1; /* Warm */
2383 reg &= ~0x80000000; /* ACLink on */
2384 iputdword(chip, ICHREG(ALI_SCR), reg);
2385
2386 for (i = 0; i < HZ / 2; i++) {
2387 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2388 goto __ok;
2389 do_delay(chip);
2390 }
2391 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2392 if (probing)
2393 return -EIO;
2394
2395 __ok:
2396 for (i = 0; i < HZ / 2; i++) {
2397 reg = igetdword(chip, ICHREG(ALI_RTSR));
2398 if (reg & 0x80) /* primary codec */
2399 break;
2400 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2401 do_delay(chip);
2402 }
2403
2404 do_ali_reset(chip);
2405 return 0;
2406}
2407
2408static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2409{
2410 unsigned int i;
2411 int err;
2412
2413 if (chip->device_type != DEVICE_ALI) {
2414 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2415 return err;
2416 iagetword(chip, 0); /* clear semaphore flag */
2417 } else {
2418 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2419 return err;
2420 }
2421
2422 /* disable interrupts */
2423 for (i = 0; i < chip->bdbars_count; i++)
2424 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2425 /* reset channels */
2426 for (i = 0; i < chip->bdbars_count; i++)
2427 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2428 /* initialize Buffer Descriptor Lists */
2429 for (i = 0; i < chip->bdbars_count; i++)
2430 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2431 return 0;
2432}
2433
2434static int snd_intel8x0_free(intel8x0_t *chip)
2435{
2436 unsigned int i;
2437
2438 if (chip->irq < 0)
2439 goto __hw_end;
2440 /* disable interrupts */
2441 for (i = 0; i < chip->bdbars_count; i++)
2442 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2443 /* reset channels */
2444 for (i = 0; i < chip->bdbars_count; i++)
2445 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2446 if (chip->device_type == DEVICE_NFORCE) {
2447 /* stop the spdif interrupt */
2448 unsigned int val;
2449 pci_read_config_dword(chip->pci, 0x4c, &val);
2450 val &= ~0x1000000;
2451 pci_write_config_dword(chip->pci, 0x4c, val);
2452 }
2453 /* --- */
2454 synchronize_irq(chip->irq);
2455__hw_end:
2456 if (chip->irq >= 0)
2457 free_irq(chip->irq, (void *)chip);
2458 if (chip->bdbars.area)
2459 snd_dma_free_pages(&chip->bdbars);
2460 if (chip->remap_addr)
2461 iounmap((void *) chip->remap_addr);
2462 if (chip->remap_bmaddr)
2463 iounmap((void *) chip->remap_bmaddr);
2464 pci_release_regions(chip->pci);
2465 kfree(chip);
2466 return 0;
2467}
2468
2469#ifdef CONFIG_PM
2470/*
2471 * power management
2472 */
2473static int intel8x0_suspend(snd_card_t *card, unsigned int state)
2474{
2475 intel8x0_t *chip = card->pm_private_data;
2476#ifdef TARGET_OS2
2477 int i;
2478#endif
2479
2480#ifdef TARGET_OS2
2481 for (i = 0; i < 3; i++)
2482 if (chip->ac97[i])
2483 snd_ac97_suspend(chip->ac97[i]);
2484#endif
2485 for (i = 0; i < chip->pcm_devs; i++)
2486 snd_pcm_suspend_all(chip->pcm[i]);
2487 for (i = 0; i < 3; i++)
2488 if (chip->ac97[i])
2489 snd_ac97_suspend(chip->ac97[i]);
2490 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2491 chip->device_type == DEVICE_INTEL_ICH5)
2492 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2493
2494 if (chip->irq >= 0)
2495 free_irq(chip->irq, (void *)chip);
2496 pci_disable_device(chip->pci);
2497 return 0;
2498}
2499
2500static int intel8x0_resume(snd_card_t *card, unsigned int state)
2501{
2502 intel8x0_t *chip = card->pm_private_data;
2503 int i;
2504
2505 pci_enable_device(chip->pci);
2506 pci_set_master(chip->pci);
2507 request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip);
2508 synchronize_irq(chip->irq);
2509 snd_intel8x0_chip_init(chip, 1);
2510 /* re-initialize mixer stuff */
2511 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2512 chip->device_type == DEVICE_INTEL_ICH5) {
2513 /* enable separate SDINs for ICH4 */
2514 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2515 /* use slot 10/11 for SPDIF */
2516 iputdword(chip, ICHREG(GLOB_CNT),
2517 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2518 ICH_PCM_SPDIF_1011);
2519 }
2520
2521 for (i = 0; i < 3; i++)
2522 if (chip->ac97[i])
2523 snd_ac97_resume(chip->ac97[i]);
2524 /* resume status */
2525 for (i = 0; i < chip->bdbars_count; i++) {
2526 ichdev_t *ichdev = &chip->ichd[i];
2527 unsigned long port = ichdev->reg_offset;
2528 if (! ichdev->substream || ! ichdev->suspended)
2529 continue;
2530 if (ichdev->ichd == ICHD_PCMOUT)
2531 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2532 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2533 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2534 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2535 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2536 }
2537 return 0;
2538}
2539
2540#endif /* CONFIG_PM */
2541
2542#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2543
2544static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2545{
2546 snd_pcm_substream_t *subs;
2547 ichdev_t *ichdev;
2548 unsigned long port;
2549 unsigned long pos, t;
2550 struct timeval start_time, stop_time;
2551
2552 if (chip->ac97_bus->clock != 48000)
2553 return; /* specified in module option */
2554
2555 subs = chip->pcm[0]->streams[0].substream;
2556 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2557 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2558 return;
2559 }
2560 ichdev = &chip->ichd[ICHD_PCMOUT];
2561 ichdev->physbuf = subs->dma_buffer.addr;
2562 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2563 ichdev->substream = NULL; /* don't process interrupts */
2564
2565 /* set rate */
2566 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2567 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2568 return;
2569 }
2570 snd_intel8x0_setup_periods(chip, ichdev);
2571 port = ichdev->reg_offset;
2572 spin_lock_irq(&chip->reg_lock);
2573 /* trigger */
2574 if (chip->device_type != DEVICE_ALI)
2575 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2576 else {
2577 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2578 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2579 }
2580 do_gettimeofday(&start_time);
2581 spin_unlock_irq(&chip->reg_lock);
2582 mdelay(50);
2583
2584 spin_lock_irq(&chip->reg_lock);
2585 /* check the position */
2586 pos = ichdev->fragsize1;
2587 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2588 pos += ichdev->position;
2589 do_gettimeofday(&stop_time);
2590 /* stop */
2591 if (chip->device_type == DEVICE_ALI) {
2592 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
2593 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2594 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2595 ;
2596 } else {
2597 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2598 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2599 ;
2600 }
2601 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2602 spin_unlock_irq(&chip->reg_lock);
2603
2604 t = stop_time.tv_sec - start_time.tv_sec;
2605 t *= 1000000;
2606 t += stop_time.tv_usec - start_time.tv_usec;
2607 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2608 if (t == 0) {
2609 snd_printk(KERN_ERR "?? calculation error..\n");
2610 return;
2611 }
2612 pos = (pos / 4) * 1000;
2613 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2614 if (pos < 40000 || pos >= 60000)
2615 /* abnormal value. hw problem? */
2616 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2617 else if (pos < 47500 || pos > 48500)
2618 /* not 48000Hz, tuning the clock.. */
2619 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2620 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2621}
2622
2623static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2624 snd_info_buffer_t * buffer)
2625{
2626 intel8x0_t *chip = entry->private_data;
2627 unsigned int tmp;
2628
2629 snd_iprintf(buffer, "Intel8x0\n\n");
2630 if (chip->device_type == DEVICE_ALI)
2631 return;
2632 tmp = igetdword(chip, ICHREG(GLOB_STA));
2633 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2634 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2635 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2636 chip->device_type == DEVICE_INTEL_ICH5)
2637 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2638 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2639 tmp & ICH_PCR ? " primary" : "",
2640 tmp & ICH_SCR ? " secondary" : "",
2641 tmp & ICH_TCR ? " tertiary" : "",
2642 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2643 if (chip->device_type == DEVICE_INTEL_ICH4 ||
2644 chip->device_type == DEVICE_INTEL_ICH5)
2645 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2646 chip->ac97_sdin[0],
2647 chip->ac97_sdin[1],
2648 chip->ac97_sdin[2]);
2649}
2650
2651static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2652{
2653 snd_info_entry_t *entry;
2654
2655 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2656 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2657}
2658
2659
2660static int snd_intel8x0_dev_free(snd_device_t *device)
2661{
2662 intel8x0_t *chip = device->device_data;
2663 return snd_intel8x0_free(chip);
2664}
2665
2666struct ich_reg_info {
2667 unsigned int int_sta_mask;
2668 unsigned int offset;
2669};
2670
2671
2672static int __devinit snd_intel8x0_create(snd_card_t * card,
2673 struct pci_dev *pci,
2674 unsigned long device_type,
2675 intel8x0_t ** r_intel8x0)
2676{
2677 intel8x0_t *chip;
2678 int err;
2679 unsigned int i,pci_dword;
2680 unsigned int int_sta_masks;
2681 unsigned short pci_word;
2682 unsigned char pci_byte;
2683
2684 ichdev_t *ichdev;
2685#ifdef TARGET_OS2
2686 static snd_device_ops_t ops = {
2687 snd_intel8x0_dev_free,0,0,0
2688 };
2689#else
2690 static snd_device_ops_t ops = {
2691 .dev_free = snd_intel8x0_dev_free,
2692 };
2693#endif
2694 static unsigned int bdbars[] = {
2695 3, /* DEVICE_INTEL */
2696 6, /* DEVICE_INTEL_ICH4 */
2697 6, /* DEVICE_INTEL_ICH5 */
2698 3, /* DEVICE_SIS */
2699 6, /* DEVICE_ALI */
2700 4, /* DEVICE_NFORCE */
2701 };
2702 static struct ich_reg_info intel_regs[6] = {
2703 { ICH_PIINT, 0 },
2704 { ICH_POINT, 0x10 },
2705 { ICH_MCINT, 0x20 },
2706 { ICH_M2INT, 0x40 },
2707 { ICH_P2INT, 0x50 },
2708 { ICH_SPINT, 0x60 },
2709 };
2710 static struct ich_reg_info nforce_regs[4] = {
2711 { ICH_PIINT, 0 },
2712 { ICH_POINT, 0x10 },
2713 { ICH_MCINT, 0x20 },
2714 { ICH_NVSPINT, 0x70 },
2715 };
2716 static struct ich_reg_info ali_regs[6] = {
2717 { ALI_INT_PCMIN, 0x40 },
2718 { ALI_INT_PCMOUT, 0x50 },
2719 { ALI_INT_MICIN, 0x60 },
2720 { ALI_INT_CODECSPDIFOUT, 0x70 },
2721 { ALI_INT_SPDIFIN, 0xa0 },
2722 { ALI_INT_SPDIFOUT, 0xb0 },
2723 };
2724 struct ich_reg_info *tbl;
2725
2726 *r_intel8x0 = NULL;
2727
2728 if ((err = pci_enable_device(pci)) < 0)
2729 return err;
2730 pci_set_master(pci);
2731
2732// pci_write_config_byte(pci, 0x40, 0xff); // added by vladest
2733
2734 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2735 if (chip == NULL)
2736 return -ENOMEM;
2737 spin_lock_init(&chip->reg_lock);
2738 chip->device_type = device_type;
2739 chip->card = card;
2740 chip->pci = pci;
2741 chip->irq = -1;
2742 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2743 kfree(chip);
2744 return err;
2745 }
2746 if (device_type == DEVICE_ALI) {
2747 /* ALI5455 has no ac97 region */
2748 chip->bmaddr = pci_resource_start(pci, 0);
2749 goto port_inited;
2750 }
2751 /*
2752 ¥áâì €¢  ­î ­á .  €® ᬮâà¥âì. ¥à¢®¥: pci_cfg_space 54h,
2753 €¢  ¬« €èšå ¡šâ  㪠§ë¢ îâ á®áâ®ï­š¥ 皯 . ¥á«š â ¬ 11, â®
2754 ªà®¬¥ ª®­äš£á¯¥©á  ¡®«ìè¥ ­š å७  ­¥ à ¡®â ¥â.
2755 ’〠 ­ €® § ¯šá âì 00.
2756 ‚â®à®¥: ॣšáâà PCICMD, íâ® 16-¡šâ­ë© ॣšáâà ¯® ᬥ饭šî 04h
2757 ¢ cfg_space. šâ 1 ¢ëáâ ¢šâì ¢ 1
2758 */
2759#if 1
2760 if (chip->device_type == DEVICE_INTEL_ICH5 ||
2761 chip->device_type == DEVICE_INTEL_ICH4)
2762 {
2763 pci_read_config_dword(pci, 0x40, &pci_dword);
2764 printk("acpi_base %x\n", pci_dword);
2765 pci_read_config_byte(pci, 0x44, &pci_byte);
2766 printk("acpi_cntl %i\n", pci_byte);
2767// pci_write_config_byte(pci, 0x44, pci_byte & ~(0x10));
2768 pci_read_config_word(pci, 0x54, &pci_word);
2769// pci_write_config_word(pci, 0x54, pci_word & ~(0x3));
2770
2771 pci_read_config_word(pci, PCI_COMMAND, &pci_word);
2772// pci_write_config_word(pci, PCI_COMMAND, pci_word | (PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
2773
2774 pci_read_config_byte(pci, 0x55, &pci_byte);
2775 printk("pci config at 0x55 %i\n", pci_byte);
2776
2777 pci_write_config_byte(pci, 0x55, 0x01);
2778 }
2779#endif
2780 // make sure that pci allow mmio operations
2781
2782 if (pci_resource_flags(pci, /*2*/0) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2783 chip->mmio = 1;
2784 chip->addr = pci_resource_start(pci, /*2*/0);
2785 chip->remap_addr = (unsigned long)
2786 ioremap_nocache(chip->addr, pci_resource_len(pci, /*2*/0));
2787 if (chip->remap_addr == 0) {
2788 snd_printk("AC'97 space ioremap problem\n");
2789 snd_intel8x0_free(chip);
2790 return -EIO;
2791 }
2792 printk("ioremap %x len %i remap addr: %x\n",
2793 chip->addr, pci_resource_len(pci, /*2*/0), chip->remap_addr);
2794 }
2795 else if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2796 chip->mmio = 1;
2797 chip->addr = pci_resource_start(pci, 2);
2798 chip->remap_addr = (unsigned long)
2799 ioremap_nocache(chip->addr, pci_resource_len(pci, 2));
2800 if (chip->remap_addr == 0) {
2801 snd_printk("AC'97 space ioremap problem\n");
2802 snd_intel8x0_free(chip);
2803 return -EIO;
2804 }
2805 printk("ioremap %x len %i remap addr: %x\n",
2806 chip->addr, pci_resource_len(pci, 2), chip->remap_addr);
2807 } else {
2808 chip->addr = pci_resource_start(pci, 0);
2809 }
2810
2811 if (pci_resource_flags(pci, /*3*/1) & IORESOURCE_MEM) { /* ICH4 */
2812 chip->bm_mmio = 1;
2813 chip->bmaddr = pci_resource_start(pci, /*3*/1);
2814 chip->remap_bmaddr = (unsigned long)
2815 ioremap_nocache(chip->bmaddr, pci_resource_len(pci, /*3*/1));
2816 if (chip->remap_bmaddr == 0) {
2817 snd_printk("Controller space ioremap problem\n");
2818 snd_intel8x0_free(chip);
2819 return -EIO;
2820 }
2821 printk("ioremap bm %x len %i remap addr: %x\n",
2822 chip->bmaddr, pci_resource_len(pci, /*3*/1), chip->remap_bmaddr);
2823 }
2824 else if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2825 chip->bm_mmio = 1;
2826 chip->bmaddr = pci_resource_start(pci, 3);
2827 chip->remap_bmaddr = (unsigned long)
2828 ioremap_nocache(chip->bmaddr, pci_resource_len(pci, 3));
2829 if (chip->remap_bmaddr == 0) {
2830 snd_printk("Controller space ioremap problem\n");
2831 snd_intel8x0_free(chip);
2832 return -EIO;
2833 }
2834 printk("ioremap bm %x len %i remap addr: %x\n",
2835 chip->bmaddr, pci_resource_len(pci, 3), chip->remap_bmaddr);
2836 } else {
2837 chip->bmaddr = pci_resource_start(pci, 1);
2838 }
2839
2840port_inited:
2841 chip->bdbars_count = bdbars[device_type];
2842
2843 /* initialize offsets */
2844 switch (device_type) {
2845 case DEVICE_NFORCE:
2846 tbl = nforce_regs;
2847 break;
2848 case DEVICE_ALI:
2849 tbl = ali_regs;
2850 break;
2851 default:
2852 tbl = intel_regs;
2853 break;
2854 }
2855 for (i = 0; i < chip->bdbars_count; i++) {
2856 ichdev = &chip->ichd[i];
2857 ichdev->ichd = i;
2858 ichdev->reg_offset = tbl[i].offset;
2859 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2860 if (device_type == DEVICE_SIS) {
2861 /* SiS 7012 swaps the registers */
2862 ichdev->roff_sr = ICH_REG_OFF_PICB;
2863 ichdev->roff_picb = ICH_REG_OFF_SR;
2864 } else {
2865 ichdev->roff_sr = ICH_REG_OFF_SR;
2866 ichdev->roff_picb = ICH_REG_OFF_PICB;
2867 }
2868 if (device_type == DEVICE_ALI)
2869 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2870 /* SIS7012 handles the pcm data in bytes, others are in samples */
2871 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2872 }
2873
2874 /* allocate buffer descriptor lists */
2875 /* the start of each lists must be aligned to 8 bytes */
2876 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2877 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2878 &chip->bdbars) < 0) {
2879 snd_intel8x0_free(chip);
2880 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2881 return -ENOMEM;
2882 }
2883 /* tables must be aligned to 8 bytes here, but the kernel pages
2884 are much bigger, so we don't care (on i386) */
2885
2886 int_sta_masks = 0;
2887 for (i = 0; i < chip->bdbars_count; i++) {
2888 ichdev = &chip->ichd[i];
2889 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2890 (i * ICH_MAX_FRAGS * 2);
2891 ichdev->bdbar_addr = chip->bdbars.addr +
2892 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2893 int_sta_masks |= ichdev->int_sta_mask;
2894 }
2895 chip->int_sta_reg = device_type == DEVICE_ALI ?
2896 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2897 chip->int_sta_mask = int_sta_masks;
2898
2899 /* request irq after initializaing int_sta_mask, etc */
2900 if (request_irq(pci->irq, snd_intel8x0_interrupt,
2901 SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2902 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2903 snd_intel8x0_free(chip);
2904 return -EBUSY;
2905 }
2906 chip->irq = pci->irq;
2907 pci_set_master(pci);
2908 synchronize_irq(chip->irq);
2909
2910 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2911 snd_intel8x0_free(chip);
2912 return err;
2913 }
2914
2915 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2916
2917 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2918 snd_intel8x0_free(chip);
2919 return err;
2920 }
2921
2922 *r_intel8x0 = chip;
2923 return 0;
2924}
2925
2926static struct shortname_table {
2927 unsigned int id;
2928 const char *s;
2929} shortnames[] __devinitdata = {
2930 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2931 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2932 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2933 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2934 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2935 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2936 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2937 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel ICH 6300ESB" },
2938 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2939 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2940 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2941 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2942 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2943 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2944 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2945 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2946 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2947 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2948 { 0x003a, "NVidia MCP04" },
2949 { 0x746d, "AMD AMD8111" },
2950 { 0x7445, "AMD AMD768" },
2951 { 0x5455, "ALi M5455" },
2952 { 0, 0 },
2953};
2954
2955static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2956 const struct pci_device_id *pci_id)
2957{
2958 static int dev;
2959 snd_card_t *card;
2960 intel8x0_t *chip;
2961 int err;
2962 struct shortname_table *name;
2963
2964 if (dev >= SNDRV_CARDS)
2965 return -ENODEV;
2966 if (!enable[dev]) {
2967 dev++;
2968 return -ENOENT;
2969 }
2970
2971 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2972 if (card == NULL)
2973 return -ENOMEM;
2974 switch (pci_id->driver_data) {
2975 case DEVICE_NFORCE:
2976 strcpy(card->driver, "NFORCE");
2977 break;
2978 case DEVICE_INTEL_ICH4:
2979 strcpy(card->driver, "ICH4");
2980 break;
2981 case DEVICE_INTEL_ICH5:
2982 strcpy(card->driver, "ICH5");
2983 break;
2984 default:
2985 strcpy(card->driver, "ICH");
2986 break;
2987 }
2988
2989 strcpy(card->shortname, "Intel ICH");
2990 for (name = shortnames; name->id; name++) {
2991 if (pci->device == name->id) {
2992 strcpy(card->shortname, name->s);
2993 break;
2994 }
2995 }
2996 // card->dev = &pci->dev;
2997 if (buggy_irq < 0) {
2998 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2999 * Needs to return IRQ_HANDLED for unknown irqs.
3000 */
3001 if (pci_id->driver_data == DEVICE_NFORCE)
3002 buggy_irq = 1;
3003 else
3004 buggy_irq = 0;
3005 }
3006
3007 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
3008 snd_card_free(card);
3009 printk(KERN_ERR "ICH: create error. err = %x\n",err);
3010 return err;
3011 }
3012 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0){
3013 snd_card_free(card);
3014 // printk(KERN_ERR "ICH: mixer error. err = %x\n",err);
3015 return err;
3016 }
3017 if ((err = snd_intel8x0_pcm(chip)) < 0) {
3018 snd_card_free(card);
3019 printk(KERN_ERR "ICH: pcm error. err = %x\n",err);
3020 return err;
3021 }
3022
3023 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
3024 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_INTEL8X0,
3025 mpu_port[dev], 0,
3026 -1, 0, &chip->rmidi)) < 0) {
3027 printk(KERN_ERR "intel8x0: no UART401 device at 0x%x, skipping.\n", mpu_port[dev]);
3028 mpu_port[dev] = 0;
3029 }
3030 } else
3031 mpu_port[dev] = 0;
3032
3033 snd_intel8x0_proc_init(chip);
3034
3035 sprintf(card->longname, "%s at 0x%lx, irq %i",
3036 card->shortname, chip->addr, chip->irq);
3037
3038 if (! ac97_clock[dev])
3039 intel8x0_measure_ac97_clock(chip);
3040
3041 if ((err = snd_card_register(card)) < 0) {
3042 snd_card_free(card);
3043 printk(KERN_ERR "ICH: card register error. err = %x\n",err);
3044 return err;
3045 }
3046 pci_set_drvdata(pci, card);
3047 dev++;
3048 return 0;
3049}
3050
3051static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
3052{
3053 snd_card_free(pci_get_drvdata(pci));
3054 pci_set_drvdata(pci, NULL);
3055}
3056
3057static struct pci_driver driver = {
3058 .name = "Intel ICH",
3059 .id_table = snd_intel8x0_ids,
3060 .probe = snd_intel8x0_probe,
3061 .remove = snd_intel8x0_remove,
3062 SND_PCI_PM_CALLBACKS
3063};
3064
3065#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3066/*
3067 * initialize joystick/midi addresses
3068 */
3069#ifdef SUPPORT_JOYSTICK
3070/* there is only one available device, so we keep it here */
3071static struct pci_dev *ich_gameport_pci;
3072static struct gameport ich_gameport = { .io = 0x200 };
3073#endif
3074
3075
3076static int __devinit snd_intel8x0_joystick_probe(struct pci_dev *pci,
3077 const struct pci_device_id *id)
3078{
3079 u16 val;
3080 static int dev;
3081 if (dev >= SNDRV_CARDS)
3082 return -ENODEV;
3083 if (!enable[dev]) {
3084 dev++;
3085 return -ENOENT;
3086 }
3087
3088 pci_read_config_word(pci, 0xe6, &val);
3089#ifdef SUPPORT_JOYSTICK
3090 if (joystick[dev]) {
3091 if (! request_region(ich_gameport.io, 8, "ICH gameport")) {
3092 printk(KERN_WARNING "intel8x0: cannot grab gameport 0x%x\n", ich_gameport.io);
3093 joystick[dev] = 0;
3094 } else {
3095 ich_gameport_pci = pci;
3096 gameport_register_port(&ich_gameport);
3097 val |= 0x100;
3098 }
3099 }
3100#endif
3101#ifdef SUPPORT_MIDI
3102 if (mpu_port[dev] > 0) {
3103 if (mpu_port[dev] == 0x300 || mpu_port[dev] == 0x330) {
3104 u8 b;
3105 val |= 0x20;
3106 pci_read_config_byte(pci, 0xe2, &b);
3107 if (mpu_port[dev] == 0x300)
3108 b |= 0x08;
3109 else
3110 b &= ~0x08;
3111 pci_write_config_byte(pci, 0xe2, b);
3112 }
3113 }
3114#endif
3115 pci_write_config_word(pci, 0xe6, val);
3116 return 0;
3117}
3118
3119static void __devexit snd_intel8x0_joystick_remove(struct pci_dev *pci)
3120{
3121 u16 val;
3122#ifdef SUPPORT_JOYSTICK
3123 if (ich_gameport_pci == pci) {
3124 gameport_unregister_port(&ich_gameport);
3125 release_region(ich_gameport.io, 8);
3126 ich_gameport_pci = NULL;
3127 }
3128#endif
3129 /* disable joystick and MIDI */
3130 pci_read_config_word(pci, 0xe6, &val);
3131 val &= ~0x120;
3132 pci_write_config_word(pci, 0xe6, val);
3133}
3134
3135static struct pci_device_id snd_intel8x0_joystick_ids[] = {
3136 { 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82801AA */
3137 { 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 82901AB */
3138 { 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2 */
3139 { 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH2M */
3140 { 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH3 */
3141 // { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 440MX */
3142 // { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SI7012 */
3143 { 0x10de, 0x01b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE */
3144 // { 0x10de, 0x006b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE2 */
3145 { 0x10de, 0x00db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NFORCE3 */
3146 { 0, }
3147};
3148
3149static struct pci_driver joystick_driver = {
3150 0, 0, 0,
3151 /* name: */ "Intel ICH Joystick",
3152 /* id_table: */ snd_intel8x0_joystick_ids,
3153 /* probe: */ snd_intel8x0_joystick_probe,
3154 0,0,0
3155};
3156static int have_joystick;
3157#endif
3158
3159static int __init alsa_card_intel8x0_init(void)
3160{
3161 int err = 0;
3162
3163 // printk(KERN_ERR "alsa_card_intel8x0_init\n");
3164#ifdef TARGET_OS2
3165 if (midi_port > 0) mpu_port[0] = midi_port;
3166#endif
3167
3168 if ((err = pci_module_init(&driver)) < 0) {
3169#ifdef MODULE
3170 // printk(KERN_ERR "Intel ICH soundcard not found or device busy. err = %x\n",err);
3171#endif
3172 return err;
3173 }
3174#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3175 if (pci_module_init(&joystick_driver) < 0) {
3176 snd_printdd(KERN_INFO "no joystick found\n");
3177 have_joystick = 0;
3178 } else {
3179 snd_printdd(KERN_INFO "joystick(s) found\n");
3180 have_joystick = 1;
3181 }
3182#endif
3183 return 0;
3184}
3185
3186static void __exit alsa_card_intel8x0_exit(void)
3187{
3188 pci_unregister_driver(&driver);
3189#if defined(SUPPORT_JOYSTICK) || defined(SUPPORT_MIDI)
3190 if (have_joystick)
3191 pci_unregister_driver(&joystick_driver);
3192#endif
3193}
3194
3195module_init(alsa_card_intel8x0_init)
3196module_exit(alsa_card_intel8x0_exit)
3197
3198#ifndef MODULE
3199
3200/* format is: snd-intel8x0=enable,index,id,ac97_clock,mpu_port,joystick */
3201
3202static int __init alsa_card_intel8x0_setup(char *str)
3203{
3204 static unsigned __initdata nr_dev = 0;
3205
3206 if (nr_dev >= SNDRV_CARDS)
3207 return 0;
3208 (void)(get_option(&str,&enable[nr_dev]) == 2 &&
3209 get_option(&str,&index[nr_dev]) == 2 &&
3210 get_id(&str,&id[nr_dev]) == 2 &&
3211 get_option(&str,&ac97_clock[nr_dev]) == 2 &&
3212 get_option(&str,&ac97_quirk[nr_dev]) == 2
3213#ifdef SUPPORT_MIDI
3214 && get_option(&str,&mpu_port[nr_dev]) == 2
3215#endif
3216#ifdef SUPPORT_JOYSTICK
3217 && get_option(&str,&joystick[nr_dev]) == 2
3218#endif
3219 );
3220 nr_dev++;
3221 return 1;
3222}
3223
3224__setup("snd-intel8x0=", alsa_card_intel8x0_setup);
3225
3226#endif /* ifndef MODULE */
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