source: GPL/alsa-kernel/pci/ice1712.c@ 1

Last change on this file since 1 was 1, checked in by vladest, 20 years ago

initial import
File size: 157.9 KB
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1/*
2 * ALSA driver for ICEnsemble ICE1712 (Envy24)
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22/*
23 NOTES:
24 - spdif nonaudio consumer mode does not work (at least with my
25 Sony STR-DB830)
26*/
27
28#define SNDRV_MAIN_OBJECT_FILE
29
30#include <sound/driver.h>
31#include <sound/control.h>
32#include <sound/pcm.h>
33#include <sound/ac97_codec.h>
34#include <sound/mpu401.h>
35#include <sound/info.h>
36#define SNDRV_GET_ID
37#include <sound/initval.h>
38
39EXPORT_NO_SYMBOLS;
40MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
41MODULE_CLASSES("{sound}");
42MODULE_DEVICES("{{Hoontech SoundTrack DSP 24},"
43 "{MidiMan M Audio,Delta 1010},"
44 "{MidiMan M Audio,Delta DiO 2496},"
45 "{MidiMan M Audio,Delta 66},"
46 "{MidiMan M Audio,Delta 44},"
47 "{MidiMan M Audio,Audiophile 24/96},"
48 "{TerraTec,EWX 24/96},"
49 "{TerraTec,EWS 88MT},"
50 "{TerraTec,EWS 88D},"
51 "{ICEnsemble,Generic ICE1712},"
52 "{ICEnsemble,Generic Envy24}}");
53MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
54
55static int snd_index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
56static char *snd_id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
57static int snd_enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE; /* Enable this card */
58
59MODULE_PARM(snd_index, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
60MODULE_PARM_DESC(snd_index, "Index value for ICE1712 soundcard.");
61MODULE_PARM_SYNTAX(snd_index, SNDRV_INDEX_DESC);
62MODULE_PARM(snd_id, "1-" __MODULE_STRING(SNDRV_CARDS) "s");
63MODULE_PARM_DESC(snd_id, "ID string for ICE1712 soundcard.");
64MODULE_PARM_SYNTAX(snd_id, SNDRV_ID_DESC);
65MODULE_PARM(snd_enable, "1-" __MODULE_STRING(SNDRV_CARDS) "i");
66MODULE_PARM_DESC(snd_enable, "Enable ICE1712 soundcard.");
67MODULE_PARM_SYNTAX(snd_enable, SNDRV_ENABLE_DESC);
68
69#ifndef PCI_VENDOR_ID_ICE
70#define PCI_VENDOR_ID_ICE 0x1412
71#endif
72#ifndef PCI_DEVICE_ID_ICE_1712
73#define PCI_DEVICE_ID_ICE_1712 0x1712
74#endif
75
76#define ICE1712_SUBDEVICE_STDSP24 0x12141217 /* Hoontech SoundTrack Audio DSP 24 */
77#define ICE1712_SUBDEVICE_DELTA1010 0x121430d6
78#define ICE1712_SUBDEVICE_DELTADIO2496 0x121431d6
79#define ICE1712_SUBDEVICE_DELTA66 0x121432d6
80#define ICE1712_SUBDEVICE_DELTA44 0x121433d6
81#define ICE1712_SUBDEVICE_AUDIOPHILE 0x121434d6
82#define ICE1712_SUBDEVICE_EWX2496 0x3b153011
83#define ICE1712_SUBDEVICE_EWS88MT 0x3b151511
84#define ICE1712_SUBDEVICE_EWS88D 0x3b152b11
85
86/*
87 * Direct registers
88 */
89
90#define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x)
91
92#define ICE1712_REG_CONTROL 0x00 /* byte */
93#define ICE1712_RESET 0x80 /* reset whole chip */
94#define ICE1712_SERR_LEVEL 0x04 /* SERR# level otherwise edge */
95#define ICE1712_NATIVE 0x01 /* native mode otherwise SB */
96#define ICE1712_REG_IRQMASK 0x01 /* byte */
97#define ICE1712_IRQ_MPU1 0x80
98#define ICE1712_IRQ_TIMER 0x40
99#define ICE1712_IRQ_MPU2 0x20
100#define ICE1712_IRQ_PROPCM 0x10
101#define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */
102#define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */
103#define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */
104#define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */
105#define ICE1712_REG_IRQSTAT 0x02 /* byte */
106/* look to ICE1712_IRQ_* */
107#define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */
108#define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */
109#define ICE1712_REG_NMI_STAT1 0x05 /* byte */
110#define ICE1712_REG_NMI_DATA 0x06 /* byte */
111#define ICE1712_REG_NMI_INDEX 0x07 /* byte */
112#define ICE1712_REG_AC97_INDEX 0x08 /* byte */
113#define ICE1712_REG_AC97_CMD 0x09 /* byte */
114#define ICE1712_AC97_COLD 0x80 /* cold reset */
115#define ICE1712_AC97_WARM 0x40 /* warm reset */
116#define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */
117#define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */
118#define ICE1712_AC97_READY 0x08 /* codec ready status bit */
119#define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */
120#define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */
121#define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */
122#define ICE1712_REG_MPU1_CTRL 0x0c /* byte */
123#define ICE1712_REG_MPU1_DATA 0x0d /* byte */
124#define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */
125#define ICE1712_I2C_WRITE 0x01 /* write direction */
126#define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */
127#define ICE1712_REG_I2C_DATA 0x12 /* byte */
128#define ICE1712_REG_I2C_CTRL 0x13 /* byte */
129#define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */
130#define ICE1712_I2C_BUSY 0x01 /* busy bit */
131#define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */
132#define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */
133#define ICE1712_REG_SERR_SHADOW 0x1b /* byte */
134#define ICE1712_REG_MPU2_CTRL 0x1c /* byte */
135#define ICE1712_REG_MPU2_DATA 0x1d /* byte */
136#define ICE1712_REG_TIMER 0x1e /* word */
137
138/*
139 * Indirect registers
140 */
141
142#define ICE1712_IREG_PBK_COUNT_HI 0x00
143#define ICE1712_IREG_PBK_COUNT_LO 0x01
144#define ICE1712_IREG_PBK_CTRL 0x02
145#define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */
146#define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */
147#define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */
148#define ICE1712_IREG_PBK_RATE_LO 0x06
149#define ICE1712_IREG_PBK_RATE_MID 0x07
150#define ICE1712_IREG_PBK_RATE_HI 0x08
151#define ICE1712_IREG_CAP_COUNT_HI 0x10
152#define ICE1712_IREG_CAP_COUNT_LO 0x11
153#define ICE1712_IREG_CAP_CTRL 0x12
154#define ICE1712_IREG_GPIO_DATA 0x20
155#define ICE1712_IREG_GPIO_WRITE_MASK 0x21
156#define ICE1712_IREG_GPIO_DIRECTION 0x22
157#define ICE1712_IREG_CONSUMER_POWERDOWN 0x30
158#define ICE1712_IREG_PRO_POWERDOWN 0x31
159
160/*
161 * Consumer section direct DMA registers
162 */
163
164#define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x)
165
166#define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */
167#define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */
168#define ICE1712_DS_DATA 0x04 /* dword - channel data */
169#define ICE1712_DS_INDEX 0x08 /* dword - channel index */
170
171/*
172 * Consumer section channel registers
173 */
174
175#define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */
176#define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */
177#define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */
178#define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */
179#define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */
180#define ICE1712_BUFFER1 0x80 /* buffer1 is active */
181#define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */
182#define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */
183#define ICE1712_FLUSH 0x10 /* flush FIFO */
184#define ICE1712_STEREO 0x08 /* stereo */
185#define ICE1712_16BIT 0x04 /* 16-bit data */
186#define ICE1712_PAUSE 0x02 /* pause */
187#define ICE1712_START 0x01 /* start */
188#define ICE1712_DSC_RATE 0x05 /* dword - rate */
189#define ICE1712_DSC_VOLUME 0x06 /* word - volume control */
190
191/*
192 * Professional multi-track direct control registers
193 */
194
195#define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x)
196
197#define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */
198#define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */
199#define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */
200#define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */
201#define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */
202#define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */
203#define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */
204#define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */
205#define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */
206#define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */
207/* look to ICE1712_AC97_* */
208#define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */
209#define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */
210#define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */
211#define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */
212#define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */
213#define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */
214#define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */
215#define ICE1712_PLAYBACK_START 0x01 /* playback start */
216#define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */
217#define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */
218#define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */
219#define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */
220#define ICE1712_CAPTURE_START 0x01 /* capture start */
221#define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */
222#define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */
223#define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */
224#define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */
225#define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */
226#define ICE1712_MT_MONITOR_RATE 0x3b /* byte */
227#define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */
228#define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */
229#define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */
230#define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */
231
232/*
233 * Codec configuration bits
234 */
235
236/* PCI[60] System Configuration */
237#define ICE1712_CFG_CLOCK 0xc0
238#define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
239#define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
240#define ICE1712_CFG_EXT 0x80 /* external clock */
241#define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */
242#define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */
243#define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */
244#define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */
245/* PCI[61] AC-Link Configuration */
246#define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */
247#define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */
248/* PCI[62] I2S Features */
249#define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */
250#define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */
251#define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */
252#define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */
253/* PCI[63] S/PDIF Configuration */
254#define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */
255#define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */
256#define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */
257
258/* MidiMan Delta GPIO definitions */
259
260#define ICE1712_DELTA_DFS 0x01 /* fast/slow sample rate mode */
261 /* (>48kHz must be 1) */
262 /* all cards */
263#define ICE1712_DELTA_SPDIF_IN_STAT 0x02
264 /* S/PDIF input status */
265 /* 0 = valid signal is present */
266 /* all except Delta44 */
267 /* look to CS8414 datasheet */
268#define ICE1712_DELTA_SPDIF_OUT_STAT_CLOCK 0x04
269 /* S/PDIF output status clock */
270 /* (writting on rising edge - 0->1) */
271 /* all except Delta44 */
272 /* look to CS8404A datasheet */
273#define ICE1712_DELTA_SPDIF_OUT_STAT_DATA 0x08
274 /* S/PDIF output status data */
275 /* all except Delta44 */
276 /* look to CS8404A datasheet */
277#define ICE1712_DELTA_SPDIF_INPUT_SELECT 0x10
278 /* coaxial (0), optical (1) */
279 /* S/PDIF input select*/
280 /* DeltaDiO only */
281#define ICE1712_DELTA_WORD_CLOCK_SELECT 0x10
282 /* 1 - clock are taken from S/PDIF input */
283 /* 0 - clock are taken from Word Clock input */
284 /* Delta1010 only (affected SPMCLKIN pin of Envy24) */
285#define ICE1712_DELTA_CODEC_SERIAL_DATA 0x10
286 /* AKM4524 serial data */
287 /* Delta66 and Delta44 */
288#define ICE1712_DELTA_WORD_CLOCK_STATUS 0x20
289 /* 0 = valid word clock signal is present */
290 /* Delta1010 only */
291#define ICE1712_DELTA_CODEC_SERIAL_CLOCK 0x20
292 /* AKM4524 serial clock */
293 /* (writting on rising edge - 0->1 */
294 /* Delta66 and Delta44 */
295#define ICE1712_DELTA_CODEC_CHIP_A 0x40
296#define ICE1712_DELTA_CODEC_CHIP_B 0x80
297 /* 1 - select chip A or B */
298 /* Delta66 and Delta44 */
299
300/* M-Audio Audiophile definitions */
301/* 0x01 = DFS */
302#define ICE1712_DELTA_AP_CCLK 0x02 /* AudioPhile only */
303 /* SPI clock */
304 /* (clocking on rising edge - 0->1) */
305#define ICE1712_DELTA_AP_DIN 0x04 /* AudioPhile only - data input */
306#define ICE1712_DELTA_AP_DOUT 0x08 /* AudioPhile only - data output */
307#define ICE1712_DELTA_AP_CS_DIGITAL 0x10 /* AudioPhile only - CS8427 chip select */
308 /* low signal = select */
309#define ICE1712_DELTA_AP_CS_CODEC 0x20 /* AudioPhile only - AK4528 chip select */
310 /* low signal = select */
311
312/* Hoontech SoundTrack Audio DSP 24 GPIO definitions */
313
314#define ICE1712_STDSP24_0_BOX(r, x) r[0] = ((r[0] & ~3) | ((x)&3))
315#define ICE1712_STDSP24_0_DAREAR(r, x) r[0] = ((r[0] & ~4) | (((x)&1)<<2))
316#define ICE1712_STDSP24_1_CHN1(r, x) r[1] = ((r[1] & ~1) | ((x)&1))
317#define ICE1712_STDSP24_1_CHN2(r, x) r[1] = ((r[1] & ~2) | (((x)&1)<<1))
318#define ICE1712_STDSP24_1_CHN3(r, x) r[1] = ((r[1] & ~4) | (((x)&1)<<2))
319#define ICE1712_STDSP24_2_CHN4(r, x) r[2] = ((r[2] & ~1) | ((x)&1))
320#define ICE1712_STDSP24_2_MIDIIN(r, x) r[2] = ((r[2] & ~2) | (((x)&1)<<1))
321#define ICE1712_STDSP24_2_MIDI1(r, x) r[2] = ((r[2] & ~4) | (((x)&1)<<2))
322#define ICE1712_STDSP24_3_MIDI2(r, x) r[3] = ((r[3] & ~1) | ((x)&1))
323#define ICE1712_STDSP24_3_MUTE(r, x) r[3] = ((r[3] & ~2) | (((x)&1)<<1))
324#define ICE1712_STDSP24_3_INSEL(r, x) r[3] = ((r[3] & ~4) | (((x)&1)<<2))
325#define ICE1712_STDSP24_SET_ADDR(r, a) r[a&3] = ((r[a&3] & ~0x18) | (((a)&3)<<3))
326#define ICE1712_STDSP24_CLOCK(r, a, c) r[a&3] = ((r[a&3] & ~0x20) | (((c)&1)<<5))
327#define ICE1712_STDSP24_CLOCK_BIT (1<<5)
328
329/* Hoontech SoundTrack Audio DSP 24 box configuration definitions */
330
331#define ICE1712_STDSP24_DAREAR (1<<0)
332#define ICE1712_STDSP24_MUTE (1<<1)
333#define ICE1712_STDSP24_INSEL (1<<2)
334
335#define ICE1712_STDSP24_BOX_CHN1 (1<<0) /* input channel 1 */
336#define ICE1712_STDSP24_BOX_CHN2 (1<<1) /* input channel 2 */
337#define ICE1712_STDSP24_BOX_CHN3 (1<<2) /* input channel 3 */
338#define ICE1712_STDSP24_BOX_CHN4 (1<<3) /* input channel 4 */
339#define ICE1712_STDSP24_BOX_MIDI1 (1<<8)
340#define ICE1712_STDSP24_BOX_MIDI2 (1<<9)
341
342/* TerraTec EWX 24/96 configuration definitions */
343
344#define ICE1712_EWX2496_AK4524_CS 0x01 /* AK4524 chip select; low = active */
345#define ICE1712_EWX2496_AIN_SEL 0x02 /* input sensitivity switch; high = louder */
346#define ICE1712_EWX2496_AOUT_SEL 0x04 /* output sensitivity switch; high = louder */
347#define ICE1712_EWX2496_RW 0x08 /* read/write switch for i2c; high = write */
348#define ICE1712_EWX2496_SERIAL_DATA 0x10 /* i2c & ak4524 data */
349#define ICE1712_EWX2496_SERIAL_CLOCK 0x20 /* i2c & ak4524 clock */
350#define ICE1712_EWX2496_TX2 0x40 /* MIDI2 (not used) */
351#define ICE1712_EWX2496_RX2 0x80 /* MIDI2 (not used) */
352
353/* TerraTec EWS 88MT/D configuration definitions */
354/* RW, SDA snd SCLK are identical with EWX24/96 */
355
356#define ICE1712_EWS88_CS8414_RATE 0x07 /* CS8414 sample rate: gpio 0-2 */
357#define ICE1712_EWS88_RW 0x08 /* read/write switch for i2c; high = write */
358#define ICE1712_EWS88_SERIAL_DATA 0x10 /* i2c & ak4524 data */
359#define ICE1712_EWS88_SERIAL_CLOCK 0x20 /* i2c & ak4524 clock */
360#define ICE1712_EWS88_TX2 0x40 /* MIDI2 (only on 88D) */
361#define ICE1712_EWS88_RX2 0x80 /* MIDI2 (only on 88D) */
362
363/* i2c address */
364#define ICE1712_EWS88MT_CS8404_ADDR 0x40
365#define ICE1712_EWS88MT_INPUT_ADDR 0x46
366#define ICE1712_EWS88MT_OUTPUT_ADDR 0x48
367#define ICE1712_EWS88MT_OUTPUT_SENSE 0x40 /* mask */
368#define ICE1712_EWS88D_PCF_ADDR 0x40
369
370/*
371 * DMA mode values
372 * identical with DMA_XXX on i386 architecture.
373 */
374#define ICE1712_DMA_MODE_WRITE 0x48
375#define ICE1712_DMA_AUTOINIT 0x10
376
377
378/*
379 *
380 */
381
382typedef struct _snd_ice1712 ice1712_t;
383
384typedef struct {
385 void (*write)(ice1712_t *ice, unsigned char reg, unsigned char data);
386 unsigned char (*read)(ice1712_t *ice, unsigned char reg);
387 void (*write_bytes)(ice1712_t *ice, unsigned char reg, int bytes, unsigned char *data);
388 void (*read_bytes)(ice1712_t *ice, unsigned char reg, int bytes, unsigned char *data);
389} ice1712_cs8427_ops_t;
390
391typedef struct {
392 unsigned int subvendor; /* PCI[2c-2f] */
393 unsigned char size; /* size of EEPROM image in bytes */
394 unsigned char version; /* must be 1 */
395 unsigned char codec; /* codec configuration PCI[60] */
396 unsigned char aclink; /* ACLink configuration PCI[61] */
397 unsigned char i2sID; /* PCI[62] */
398 unsigned char spdif; /* S/PDIF configuration PCI[63] */
399 unsigned char gpiomask; /* GPIO initial mask, 0 = write, 1 = don't */
400 unsigned char gpiostate; /* GPIO initial state */
401 unsigned char gpiodir; /* GPIO direction state */
402 unsigned short ac97main;
403 unsigned short ac97pcm;
404 unsigned short ac97rec;
405 unsigned char ac97recsrc;
406 unsigned char dacID[4]; /* I2S IDs for DACs */
407 unsigned char adcID[4]; /* I2S IDs for ADCs */
408 unsigned char extra[4];
409} ice1712_eeprom_t;
410
411struct _snd_ice1712 {
412 unsigned long conp_dma_size;
413 unsigned long conc_dma_size;
414 unsigned long prop_dma_size;
415 unsigned long proc_dma_size;
416 int irq;
417
418 unsigned long port;
419 struct resource *res_port;
420 unsigned long ddma_port;
421 struct resource *res_ddma_port;
422 unsigned long dmapath_port;
423 struct resource *res_dmapath_port;
424 unsigned long profi_port;
425 struct resource *res_profi_port;
426
427 unsigned int config; /* system configuration */
428
429 struct pci_dev *pci;
430 snd_card_t *card;
431 snd_pcm_t *pcm;
432 snd_pcm_t *pcm_ds;
433 snd_pcm_t *pcm_pro;
434 snd_pcm_substream_t *playback_con_substream;
435 snd_pcm_substream_t *playback_con_substream_ds[6];
436 snd_pcm_substream_t *capture_con_substream;
437 snd_pcm_substream_t *playback_pro_substream;
438 snd_pcm_substream_t *capture_pro_substream;
439 unsigned int playback_pro_size;
440 unsigned int capture_pro_size;
441 unsigned int playback_con_virt_addr[6];
442 unsigned int playback_con_active_buf[6];
443 unsigned int capture_con_virt_addr;
444 unsigned int ac97_ext_id;
445 ac97_t *ac97;
446 snd_rawmidi_t *rmidi[2];
447
448 spinlock_t reg_lock;
449 struct semaphore gpio_mutex;
450 snd_info_entry_t *proc_entry;
451
452 ice1712_eeprom_t eeprom;
453
454 unsigned int pro_volumes[20];
455 int num_adcs;
456 int num_dacs;
457 unsigned char ak4524_images[4][8];
458 unsigned char hoontech_boxbits[4];
459 unsigned int hoontech_config;
460 unsigned short hoontech_boxconfig[4];
461
462 unsigned char cs8403_spdif_bits;
463 unsigned char cs8403_spdif_stream_bits;
464 snd_kcontrol_t *spdif_stream_ctl;
465
466 unsigned char cs8427_spdif_status[5];
467 unsigned char cs8427_spdif_stream_status[5];
468 ice1712_cs8427_ops_t *cs8427_ops;
469
470 unsigned char gpio_direction, gpio_write_mask;
471};
472
473#define chip_t ice1712_t
474
475static struct pci_device_id snd_ice1712_ids[] __devinitdata = {
476 { PCI_VENDOR_ID_ICE, PCI_DEVICE_ID_ICE_1712, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ICE1712 */
477 { 0, }
478};
479
480MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
481
482static int snd_ice1712_build_pro_mixer(ice1712_t *ice);
483static int snd_ice1712_build_controls(ice1712_t *ice);
484
485/*
486 * Basic I/O
487 */
488
489static inline void snd_ice1712_write(ice1712_t * ice, u8 addr, u8 data)
490{
491 outb(addr, ICEREG(ice, INDEX));
492 outb(data, ICEREG(ice, DATA));
493}
494
495static inline u8 snd_ice1712_read(ice1712_t * ice, u8 addr)
496{
497 outb(addr, ICEREG(ice, INDEX));
498 return inb(ICEREG(ice, DATA));
499}
500
501static inline void snd_ice1712_ds_write(ice1712_t * ice, u8 channel, u8 addr, u32 data)
502{
503 outb((channel << 4) | addr, ICEDS(ice, INDEX));
504 outl(data, ICEDS(ice, DATA));
505}
506
507static inline u32 snd_ice1712_ds_read(ice1712_t * ice, u8 channel, u8 addr)
508{
509 outb((channel << 4) | addr, ICEDS(ice, INDEX));
510 return inl(ICEDS(ice, DATA));
511}
512
513static void snd_ice1712_ac97_write(ac97_t *ac97,
514 unsigned short reg,
515 unsigned short val)
516{
517 ice1712_t *ice = (ice1712_t *)ac97->private_data;
518 int tm;
519 unsigned char old_cmd = 0;
520
521 for (tm = 0; tm < 0x10000; tm++) {
522 old_cmd = inb(ICEREG(ice, AC97_CMD));
523 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
524 continue;
525 if (!(old_cmd & ICE1712_AC97_READY))
526 continue;
527 break;
528 }
529 outb(reg, ICEREG(ice, AC97_INDEX));
530 outw(val, ICEREG(ice, AC97_DATA));
531 old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
532 outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
533 for (tm = 0; tm < 0x10000; tm++)
534 if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
535 break;
536}
537
538static unsigned short snd_ice1712_ac97_read(ac97_t *ac97,
539 unsigned short reg)
540{
541 ice1712_t *ice = (ice1712_t *)ac97->private_data;
542 int tm;
543 unsigned char old_cmd = 0;
544
545 for (tm = 0; tm < 0x10000; tm++) {
546 old_cmd = inb(ICEREG(ice, AC97_CMD));
547 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
548 continue;
549 if (!(old_cmd & ICE1712_AC97_READY))
550 continue;
551 break;
552 }
553 outb(reg, ICEREG(ice, AC97_INDEX));
554 outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
555 for (tm = 0; tm < 0x10000; tm++)
556 if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
557 break;
558 if (tm >= 0x10000) /* timeout */
559 return ~0;
560 return inw(ICEREG(ice, AC97_DATA));
561}
562
563/*
564 * pro ac97 section
565 */
566
567static void snd_ice1712_pro_ac97_write(ac97_t *ac97,
568 unsigned short reg,
569 unsigned short val)
570{
571 ice1712_t *ice = (ice1712_t *)ac97->private_data;
572 int tm;
573 unsigned char old_cmd = 0;
574
575 for (tm = 0; tm < 0x10000; tm++) {
576 old_cmd = inb(ICEMT(ice, AC97_CMD));
577 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
578 continue;
579 if (!(old_cmd & ICE1712_AC97_READY))
580 continue;
581 break;
582 }
583 outb(reg, ICEMT(ice, AC97_INDEX));
584 outw(val, ICEMT(ice, AC97_DATA));
585 old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
586 outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
587 for (tm = 0; tm < 0x10000; tm++)
588 if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
589 break;
590}
591
592
593static unsigned short snd_ice1712_pro_ac97_read(ac97_t *ac97,
594 unsigned short reg)
595{
596 ice1712_t *ice = (ice1712_t *)ac97->private_data;
597 int tm;
598 unsigned char old_cmd = 0;
599
600 for (tm = 0; tm < 0x10000; tm++) {
601 old_cmd = inb(ICEMT(ice, AC97_CMD));
602 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
603 continue;
604 if (!(old_cmd & ICE1712_AC97_READY))
605 continue;
606 break;
607 }
608 outb(reg, ICEMT(ice, AC97_INDEX));
609 outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
610 for (tm = 0; tm < 0x10000; tm++)
611 if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
612 break;
613 if (tm >= 0x10000) /* timeout */
614 return ~0;
615 return inw(ICEMT(ice, AC97_DATA));
616}
617
618static int snd_ice1712_digmix_route_ac97_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
619{
620 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
621 uinfo->count = 1;
622 uinfo->value.integer.min = 0;
623 uinfo->value.integer.max = 1;
624 return 0;
625}
626
627static int snd_ice1712_digmix_route_ac97_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
628{
629 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
630 unsigned long flags;
631
632 spin_lock_irqsave(&ice->reg_lock, flags);
633 ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
634 spin_unlock_irqrestore(&ice->reg_lock, flags);
635 return 0;
636}
637
638static int snd_ice1712_digmix_route_ac97_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
639{
640 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
641 unsigned char val, nval;
642 unsigned long flags;
643
644 spin_lock_irqsave(&ice->reg_lock, flags);
645 val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
646 nval = val & ~ICE1712_ROUTE_AC97;
647 if (ucontrol->value.integer.value[0]) nval |= ICE1712_ROUTE_AC97;
648 outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
649 spin_unlock_irqrestore(&ice->reg_lock, flags);
650 return val != nval;
651}
652
653static snd_kcontrol_new_t snd_ice1712_mixer_digmix_route_ac97 = {
654#ifdef TARGET_OS2
655 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
656 "Digital Mixer To AC97",0,0,
657 snd_ice1712_digmix_route_ac97_info,
658 snd_ice1712_digmix_route_ac97_get,
659 snd_ice1712_digmix_route_ac97_put,0
660#else
661 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
662 name: "Digital Mixer To AC97",
663 info: snd_ice1712_digmix_route_ac97_info,
664 get: snd_ice1712_digmix_route_ac97_get,
665 put: snd_ice1712_digmix_route_ac97_put,
666#endif
667};
668
669
670/*
671 */
672static void snd_ice1712_delta_cs8403_spdif_write(ice1712_t *ice, unsigned char bits)
673{
674 unsigned char tmp, mask1, mask2;
675 int idx;
676 /* send byte to transmitter */
677 mask1 = ICE1712_DELTA_SPDIF_OUT_STAT_CLOCK;
678 mask2 = ICE1712_DELTA_SPDIF_OUT_STAT_DATA;
679 down(&ice->gpio_mutex);
680 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
681 for (idx = 7; idx >= 0; idx--) {
682 tmp &= ~(mask1 | mask2);
683 if (bits & (1 << idx))
684 tmp |= mask2;
685 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
686 udelay(100);
687 tmp |= mask1;
688 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
689 udelay(100);
690 }
691 tmp &= ~mask1;
692 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
693 up(&ice->gpio_mutex);
694}
695
696static void snd_ice1712_decode_cs8403_spdif_bits(snd_aes_iec958_t *diga,
697 unsigned char bits)
698{
699 if (bits & 0x01) { /* consumer */
700 if (!(bits & 0x02))
701 diga->status[0] |= IEC958_AES0_NONAUDIO;
702 if (!(bits & 0x08))
703 diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT;
704 switch (bits & 0x10) {
705 case 0x10: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_NONE; break;
706 case 0x00: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015; break;
707 }
708 if (!(bits & 0x80))
709 diga->status[1] |= IEC958_AES1_CON_ORIGINAL;
710 switch (bits & 0x60) {
711 case 0x00: diga->status[1] |= IEC958_AES1_CON_MAGNETIC_ID; break;
712 case 0x20: diga->status[1] |= IEC958_AES1_CON_DIGDIGCONV_ID; break;
713 case 0x40: diga->status[1] |= IEC958_AES1_CON_LASEROPT_ID; break;
714 case 0x60: diga->status[1] |= IEC958_AES1_CON_GENERAL; break;
715 }
716 switch (bits & 0x06) {
717 case 0x00: diga->status[3] |= IEC958_AES3_CON_FS_44100; break;
718 case 0x02: diga->status[3] |= IEC958_AES3_CON_FS_48000; break;
719 case 0x04: diga->status[3] |= IEC958_AES3_CON_FS_32000; break;
720 }
721 } else {
722 diga->status[0] = IEC958_AES0_PROFESSIONAL;
723 switch (bits & 0x18) {
724 case 0x00: diga->status[0] |= IEC958_AES0_PRO_FS_32000; break;
725 case 0x10: diga->status[0] |= IEC958_AES0_PRO_FS_44100; break;
726 case 0x08: diga->status[0] |= IEC958_AES0_PRO_FS_48000; break;
727 case 0x18: diga->status[0] |= IEC958_AES0_PRO_FS_NOTID; break;
728 }
729 switch (bits & 0x60) {
730 case 0x20: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NONE; break;
731 case 0x40: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015; break;
732 case 0x00: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_CCITT; break;
733 case 0x60: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NOTID; break;
734 }
735 if (bits & 0x80)
736 diga->status[1] |= IEC958_AES1_PRO_MODE_STEREOPHONIC;
737 }
738}
739
740static unsigned char snd_ice1712_encode_cs8403_spdif_bits(snd_aes_iec958_t *diga)
741{
742 unsigned char bits;
743
744 if (!(diga->status[0] & IEC958_AES0_PROFESSIONAL)) {
745 bits = 0x01; /* consumer mode */
746 if (diga->status[0] & IEC958_AES0_NONAUDIO)
747 bits &= ~0x02;
748 else
749 bits |= 0x02;
750 if (diga->status[0] & IEC958_AES0_CON_NOT_COPYRIGHT)
751 bits &= ~0x08;
752 else
753 bits |= 0x08;
754 switch (diga->status[0] & IEC958_AES0_CON_EMPHASIS) {
755 default:
756 case IEC958_AES0_CON_EMPHASIS_NONE: bits |= 0x10; break;
757 case IEC958_AES0_CON_EMPHASIS_5015: bits |= 0x00; break;
758 }
759 if (diga->status[1] & IEC958_AES1_CON_ORIGINAL)
760 bits &= ~0x80;
761 else
762 bits |= 0x80;
763 if ((diga->status[1] & IEC958_AES1_CON_CATEGORY) == IEC958_AES1_CON_GENERAL)
764 bits |= 0x60;
765 else {
766 switch(diga->status[1] & IEC958_AES1_CON_MAGNETIC_MASK) {
767 case IEC958_AES1_CON_MAGNETIC_ID:
768 bits |= 0x00; break;
769 case IEC958_AES1_CON_DIGDIGCONV_ID:
770 bits |= 0x20; break;
771 default:
772 case IEC958_AES1_CON_LASEROPT_ID:
773 bits |= 0x40; break;
774 }
775 }
776 switch (diga->status[3] & IEC958_AES3_CON_FS) {
777 default:
778 case IEC958_AES3_CON_FS_44100: bits |= 0x00; break;
779 case IEC958_AES3_CON_FS_48000: bits |= 0x02; break;
780 case IEC958_AES3_CON_FS_32000: bits |= 0x04; break;
781 }
782 } else {
783 bits = 0x00; /* professional mode */
784 if (diga->status[0] & IEC958_AES0_NONAUDIO)
785 bits &= ~0x02;
786 else
787 bits |= 0x02;
788 /* CHECKME: I'm not sure about the bit order in val here */
789 switch (diga->status[0] & IEC958_AES0_PRO_FS) {
790 case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break;
791 case IEC958_AES0_PRO_FS_44100: bits |= 0x10; break; /* 44.1kHz */
792 case IEC958_AES0_PRO_FS_48000: bits |= 0x08; break; /* 48kHz */
793 default:
794 case IEC958_AES0_PRO_FS_NOTID: bits |= 0x18; break;
795 }
796 switch (diga->status[0] & IEC958_AES0_PRO_EMPHASIS) {
797 case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x20; break;
798 case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x40; break;
799 case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break;
800 default:
801 case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x60; break;
802 }
803 switch (diga->status[1] & IEC958_AES1_PRO_MODE) {
804 case IEC958_AES1_PRO_MODE_TWO:
805 case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break;
806 default: bits |= 0x80; break;
807 }
808 }
809 return bits;
810}
811
812
813/*
814 * set gpio direction, write mask and data
815 */
816static void snd_ice1712_gpio_write_bits(ice1712_t *ice, int mask, int bits)
817{
818 ice->gpio_direction |= mask;
819 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, ice->gpio_direction);
820 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~mask);
821 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, mask & bits);
822}
823
824/*
825 */
826static void save_gpio_status(ice1712_t *ice, unsigned char *tmp)
827{
828 down(&ice->gpio_mutex);
829 tmp[0] = ice->gpio_direction;
830 tmp[1] = ice->gpio_write_mask;
831}
832
833static void restore_gpio_status(ice1712_t *ice, unsigned char *tmp)
834{
835 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, tmp[0]);
836 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, tmp[1]);
837 ice->gpio_direction = tmp[0];
838 ice->gpio_write_mask = tmp[1];
839 up(&ice->gpio_mutex);
840}
841
842/*
843 * CS8427 via SPI mode (for Audiophile)
844 */
845
846/* send 8 bits */
847static void ap_cs8427_write_byte(ice1712_t *ice, unsigned char data, unsigned char tmp)
848{
849 int idx;
850
851 for (idx = 7; idx >= 0; idx--) {
852 tmp &= ~(ICE1712_DELTA_AP_DOUT|ICE1712_DELTA_AP_CCLK);
853 if (data & (1 << idx))
854 tmp |= ICE1712_DELTA_AP_DOUT;
855 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
856 udelay(5);
857 tmp |= ICE1712_DELTA_AP_CCLK;
858 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
859 udelay(5);
860 }
861}
862
863/* read 8 bits */
864static unsigned char ap_cs8427_read_byte(ice1712_t *ice, unsigned char tmp)
865{
866 unsigned char data = 0;
867 int idx;
868
869 for (idx = 7; idx >= 0; idx--) {
870 tmp &= ~ICE1712_DELTA_AP_CCLK;
871 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
872 udelay(5);
873 if (snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & ICE1712_DELTA_AP_DIN)
874 data |= 1 << idx;
875 tmp |= ICE1712_DELTA_AP_CCLK;
876 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
877 udelay(5);
878 }
879 return data;
880}
881
882/* assert chip select */
883static unsigned char ap_cs8427_codec_select(ice1712_t *ice)
884{
885 unsigned char tmp;
886 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
887 tmp |= ICE1712_DELTA_AP_CCLK | ICE1712_DELTA_AP_CS_CODEC;
888 tmp &= ~ICE1712_DELTA_AP_CS_DIGITAL;
889 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
890 udelay(5);
891 return tmp;
892}
893
894/* deassert chip select */
895static void ap_cs8427_codec_deassert(ice1712_t *ice, unsigned char tmp)
896{
897 tmp |= ICE1712_DELTA_AP_CS_DIGITAL;
898 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
899}
900
901/* write a register */
902static void snd_ice1712_ap_cs8427_write(ice1712_t *ice, unsigned char reg, unsigned char data)
903{
904 unsigned char tmp;
905 down(&ice->gpio_mutex);
906 tmp = ap_cs8427_codec_select(ice);
907 ap_cs8427_write_byte(ice, 0x20, tmp); /* address + write mode */
908 ap_cs8427_write_byte(ice, reg, tmp);
909 ap_cs8427_write_byte(ice, data, tmp);
910 ap_cs8427_codec_deassert(ice, tmp);
911 up(&ice->gpio_mutex);
912}
913
914/* read a register */
915static unsigned char snd_ice1712_ap_cs8427_read(ice1712_t *ice, unsigned char reg)
916{
917 unsigned char tmp, data;
918
919 down(&ice->gpio_mutex);
920 tmp = ap_cs8427_codec_select(ice);
921 ap_cs8427_write_byte(ice, 0x20, tmp); /* address + write mode */
922 ap_cs8427_write_byte(ice, reg, tmp);
923 ap_cs8427_codec_deassert(ice, tmp);
924 udelay(5);
925 tmp = ap_cs8427_codec_select(ice);
926 ap_cs8427_write_byte(ice, 0x21, tmp); /* address + read mode */
927 data = ap_cs8427_read_byte(ice, tmp);
928 ap_cs8427_codec_deassert(ice, tmp);
929 up(&ice->gpio_mutex);
930 return data;
931}
932
933/* sequential write */
934static void snd_ice1712_ap_cs8427_write_bytes(ice1712_t *ice, unsigned char reg, int bytes, unsigned char *data)
935{
936#if 1
937 unsigned char tmp;
938 down(&ice->gpio_mutex);
939 tmp = ap_cs8427_codec_select(ice);
940 ap_cs8427_write_byte(ice, 0x20, tmp); /* address + write mode */
941 ap_cs8427_write_byte(ice, reg | 0x80, tmp); /* incremental mode */
942 while (bytes-- > 0)
943 ap_cs8427_write_byte(ice, *data++, tmp);
944 ap_cs8427_codec_deassert(ice, tmp);
945 up(&ice->gpio_mutex);
946#else
947 while (bytes-- > 0)
948 snd_ice1712_ap_cs8427_write(ice, reg++, *data++);
949#endif
950}
951
952/* sequential read */
953static void snd_ice1712_ap_cs8427_read_bytes(ice1712_t *ice, unsigned char reg, int bytes, unsigned char *data)
954{
955#if 0 // is this working? -- ti
956 unsigned char tmp;
957
958 down(&ice->gpio_mutex);
959 tmp = ap_cs8427_codec_select(ice);
960 ap_cs8427_write_byte(ice, 0x20, tmp); /* address + write mode */
961 ap_cs8427_write_byte(ice, reg | 0x80, tmp); /* incremental mode */
962 ap_cs8427_codec_deassert(ice, tmp);
963 udelay(5);
964 tmp = ap_cs8427_codec_select(ice);
965 ap_cs8427_write_byte(ice, 0x21, tmp); /* address + read mode */
966 while (bytes-- > 0)
967 *data++ = ap_cs8427_read_byte(ice, tmp);
968 ap_cs8427_codec_deassert(ice, tmp);
969 up(&ice->gpio_mutex);
970#else
971 while (bytes-- > 0)
972 *data++ = snd_ice1712_ap_cs8427_read(ice, reg++);
973#endif
974}
975
976#ifdef TARGET_OS2
977static ice1712_cs8427_ops_t snd_ice1712_ap_cs8427_ops = {
978 snd_ice1712_ap_cs8427_write,
979 snd_ice1712_ap_cs8427_read,
980 snd_ice1712_ap_cs8427_write_bytes,
981 snd_ice1712_ap_cs8427_read_bytes
982};
983#else
984static ice1712_cs8427_ops_t snd_ice1712_ap_cs8427_ops = {
985 write: snd_ice1712_ap_cs8427_write,
986 read: snd_ice1712_ap_cs8427_read,
987 write_bytes: snd_ice1712_ap_cs8427_write_bytes,
988 read_bytes: snd_ice1712_ap_cs8427_read_bytes,
989};
990#endif
991
992
993/*
994 * access via i2c mode (for EWX 24/96, EWS 88MT&D)
995 */
996
997/* send SDA and SCL */
998static void ewx_i2c_set(ice1712_t *ice, int clk, int data)
999{
1000 unsigned char tmp = 0;
1001 if (clk)
1002 tmp |= ICE1712_EWX2496_SERIAL_CLOCK;
1003 if (data)
1004 tmp |= ICE1712_EWX2496_SERIAL_DATA;
1005 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
1006 udelay(5);
1007}
1008
1009/* send one bit */
1010static void ewx_i2c_send(ice1712_t *ice, int data)
1011{
1012 ewx_i2c_set(ice, 0, data);
1013 ewx_i2c_set(ice, 1, data);
1014 ewx_i2c_set(ice, 0, data);
1015}
1016
1017/* start i2c */
1018static void ewx_i2c_start(ice1712_t *ice)
1019{
1020 ewx_i2c_set(ice, 0, 1);
1021 ewx_i2c_set(ice, 1, 1);
1022 ewx_i2c_set(ice, 1, 0);
1023 ewx_i2c_set(ice, 0, 0);
1024}
1025
1026/* stop i2c */
1027static void ewx_i2c_stop(ice1712_t *ice)
1028{
1029 ewx_i2c_set(ice, 0, 0);
1030 ewx_i2c_set(ice, 1, 0);
1031 ewx_i2c_set(ice, 1, 1);
1032}
1033
1034/* send a byte and get ack */
1035static void ewx_i2c_write(ice1712_t *ice, unsigned char val)
1036{
1037 int i;
1038 for (i = 7; i >= 0; i--)
1039 ewx_i2c_send(ice, val & (1 << i));
1040 ewx_i2c_send(ice, 1); /* ack */
1041}
1042
1043/* prepare for write and send i2c_start */
1044static void ewx_i2c_write_prepare(ice1712_t *ice)
1045{
1046 /* set RW high */
1047 unsigned char mask = ICE1712_EWX2496_RW;
1048 if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_EWX2496)
1049 mask |= ICE1712_EWX2496_AK4524_CS; /* CS high also */
1050 snd_ice1712_gpio_write_bits(ice, mask, mask);
1051 /* set direction both SDA and SCL write */
1052 ice->gpio_direction |= ICE1712_EWX2496_SERIAL_CLOCK|ICE1712_EWX2496_SERIAL_DATA;
1053 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, ice->gpio_direction);
1054 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~(ICE1712_EWX2496_SERIAL_CLOCK|ICE1712_EWX2496_SERIAL_DATA));
1055
1056 ewx_i2c_start(ice);
1057}
1058
1059/* read a bit from serial data;
1060 this changes write mask
1061 SDA direction must be set to low
1062*/
1063static int ewx_i2c_read_bit(ice1712_t *ice)
1064{
1065 int data;
1066 /* set RW pin to low */
1067 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~ICE1712_EWX2496_RW);
1068 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, 0);
1069 data = (snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & ICE1712_EWX2496_SERIAL_DATA) ? 1 : 0;
1070 /* set RW pin to high */
1071 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, ICE1712_EWX2496_RW);
1072 return data;
1073}
1074
1075static void ewx_i2c_read_prepare(ice1712_t *ice)
1076{
1077 /* set SCL - write, SDA - read */
1078 ice->gpio_direction |= ICE1712_EWX2496_SERIAL_CLOCK;
1079 ice->gpio_direction &= ~ICE1712_EWX2496_SERIAL_DATA;
1080 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, ice->gpio_direction);
1081 /* set write mask only to SCL */
1082 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~ICE1712_EWX2496_SERIAL_CLOCK);
1083}
1084
1085static void ewx_i2c_read_post(ice1712_t *ice)
1086{
1087 /* reset direction both SDA and SCL to write */
1088 ice->gpio_direction |= ICE1712_EWX2496_SERIAL_CLOCK|ICE1712_EWX2496_SERIAL_DATA;
1089 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, ice->gpio_direction);
1090 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ~(ICE1712_EWX2496_SERIAL_CLOCK|ICE1712_EWX2496_SERIAL_DATA));
1091}
1092
1093/* read a byte (and ack bit) */
1094static unsigned char ewx_i2c_read(ice1712_t *ice)
1095{
1096 int i;
1097 unsigned char data = 0;
1098
1099 for (i = 7; i >= 0; i--) {
1100 ewx_i2c_set(ice, 1, 0);
1101 data |= ewx_i2c_read_bit(ice) << i;
1102 /* reset write mask */
1103 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
1104 ~ICE1712_EWX2496_SERIAL_CLOCK);
1105 ewx_i2c_set(ice, 0, 0);
1106 }
1107 /* reset write mask */
1108 ewx_i2c_read_post(ice);
1109 ewx_i2c_send(ice, 1); /* ack */
1110 return data;
1111}
1112
1113
1114/*
1115 * CS8427 on EWX 24/96; Address 0x20
1116 */
1117/* write a register */
1118static void snd_ice1712_ewx_cs8427_write(ice1712_t *ice, unsigned char reg, unsigned char data)
1119{
1120 unsigned char saved[2];
1121
1122 save_gpio_status(ice, saved);
1123 ewx_i2c_write_prepare(ice);
1124 ewx_i2c_write(ice, 0x20); /* address + write */
1125 ewx_i2c_write(ice, reg); /* MAP */
1126 ewx_i2c_write(ice, data);
1127 ewx_i2c_stop(ice);
1128 restore_gpio_status(ice, saved);
1129}
1130
1131/* sequential write */
1132static void snd_ice1712_ewx_cs8427_write_bytes(ice1712_t *ice, unsigned char reg, int bytes, unsigned char *data)
1133{
1134 unsigned char saved[2];
1135
1136 save_gpio_status(ice, saved);
1137 ewx_i2c_write_prepare(ice);
1138 ewx_i2c_write(ice, 0x20); /* address + write */
1139 ewx_i2c_write(ice, reg | 0x80); /* MAP incremental mode */
1140 while (bytes-- > 0)
1141 ewx_i2c_write(ice, *data++);
1142 ewx_i2c_stop(ice);
1143 restore_gpio_status(ice, saved);
1144}
1145
1146/* read a register */
1147static unsigned char snd_ice1712_ewx_cs8427_read(ice1712_t *ice, unsigned char reg)
1148{
1149 unsigned char saved[2];
1150 unsigned char data;
1151
1152 save_gpio_status(ice, saved);
1153 ewx_i2c_write_prepare(ice);
1154 ewx_i2c_write(ice, 0x20); /* address + write */
1155 ewx_i2c_write(ice, reg); /* MAP */
1156 /* we set up the address first but without data */
1157 ewx_i2c_stop(ice);
1158
1159 /* now read */
1160 ewx_i2c_start(ice);
1161 ewx_i2c_write(ice, 0x21); /* address + read */
1162 ewx_i2c_read_prepare(ice);
1163 data = ewx_i2c_read(ice);
1164 ewx_i2c_read_post(ice);
1165 ewx_i2c_stop(ice);
1166
1167 restore_gpio_status(ice, saved);
1168 return data;
1169}
1170
1171/* sequential read */
1172static void snd_ice1712_ewx_cs8427_read_bytes(ice1712_t *ice, unsigned char reg, int bytes, unsigned char *data)
1173{
1174#if 0 // the sequential read seems not working (yet)..
1175 unsigned char saved[2];
1176
1177 save_gpio_status(ice, saved);
1178 ewx_i2c_write_prepare(ice);
1179 ewx_i2c_write(ice, 0x20); /* address + write */
1180 ewx_i2c_write(ice, reg | 0x80); /* MAP incremental mode */
1181 /* we set up the address first but without data */
1182 ewx_i2c_stop(ice);
1183
1184 /* now read */
1185 ewx_i2c_start(ice);
1186 ewx_i2c_write(ice, 0x21); /* address + read */
1187 ewx_i2c_read_prepare(ice);
1188 while (bytes-- > 0)
1189 *data++ = ewx_i2c_read(ice);
1190 ewx_i2c_read_post(ice);
1191 ewx_i2c_stop(ice);
1192 restore_gpio_status(ice, saved);
1193#else
1194 while (bytes-- > 0)
1195 *data++ = snd_ice1712_ewx_cs8427_read(ice, reg++);
1196#endif
1197}
1198
1199#ifdef TARGET_OS2
1200static ice1712_cs8427_ops_t snd_ice1712_ewx_cs8427_ops = {
1201 snd_ice1712_ewx_cs8427_write,
1202 snd_ice1712_ewx_cs8427_read,
1203 snd_ice1712_ewx_cs8427_write_bytes,
1204 snd_ice1712_ewx_cs8427_read_bytes,
1205};
1206#else
1207static ice1712_cs8427_ops_t snd_ice1712_ewx_cs8427_ops = {
1208 write: snd_ice1712_ewx_cs8427_write,
1209 read: snd_ice1712_ewx_cs8427_read,
1210 write_bytes: snd_ice1712_ewx_cs8427_write_bytes,
1211 read_bytes: snd_ice1712_ewx_cs8427_read_bytes,
1212};
1213#endif
1214
1215/*
1216 * PCF8574 on EWS88MT
1217 */
1218static void snd_ice1712_ews88mt_pcf8574_write(ice1712_t *ice, unsigned char addr, unsigned char data)
1219{
1220 ewx_i2c_write_prepare(ice);
1221 ewx_i2c_write(ice, addr); /* address + write */
1222 ewx_i2c_write(ice, data);
1223 ewx_i2c_stop(ice);
1224}
1225
1226static unsigned char snd_ice1712_ews88mt_pcf8574_read(ice1712_t *ice, unsigned char addr)
1227{
1228 unsigned char data;
1229 ewx_i2c_write_prepare(ice);
1230 ewx_i2c_write(ice, addr | 0x01); /* address + read */
1231 ewx_i2c_read_prepare(ice);
1232 data = ewx_i2c_read(ice);
1233 ewx_i2c_read_post(ice);
1234 ewx_i2c_stop(ice);
1235 return data;
1236}
1237
1238/* AK4524 chip select; address 0x48 bit 0-3 */
1239static void snd_ice1712_ews88mt_chip_select(ice1712_t *ice, int chip_mask)
1240{
1241 unsigned char data, ndata;
1242
1243 snd_assert(chip_mask >= 0 && chip_mask <= 0x0f, return);
1244 data = snd_ice1712_ews88mt_pcf8574_read(ice, ICE1712_EWS88MT_OUTPUT_ADDR);
1245 ndata = (data & 0xf0) | chip_mask;
1246 if (ndata != data)
1247 snd_ice1712_ews88mt_pcf8574_write(ice, ICE1712_EWS88MT_OUTPUT_ADDR, ndata);
1248}
1249
1250
1251/*
1252 * PCF8575 on EWS88D (16bit)
1253 */
1254static void snd_ice1712_ews88d_pcf8575_write(ice1712_t *ice, unsigned char addr, unsigned short data)
1255{
1256 ewx_i2c_write_prepare(ice);
1257 ewx_i2c_write(ice, addr); /* address + write */
1258 ewx_i2c_write(ice, data & 0xff);
1259 ewx_i2c_write(ice, (data >> 8) & 0xff);
1260 ewx_i2c_stop(ice);
1261}
1262
1263static unsigned short snd_ice1712_ews88d_pcf8575_read(ice1712_t *ice, unsigned char addr)
1264{
1265 unsigned short data;
1266 ewx_i2c_write_prepare(ice);
1267 ewx_i2c_write(ice, addr | 0x01); /* address + read */
1268 ewx_i2c_read_prepare(ice);
1269 data = ewx_i2c_read(ice);
1270 data |= (unsigned short)ewx_i2c_read(ice) << 8;
1271 //printk("pcf: read = 0x%x\n", data);
1272 ewx_i2c_read_post(ice);
1273 ewx_i2c_stop(ice);
1274 return data;
1275}
1276
1277/*
1278 * write AK4524 register
1279 */
1280static void snd_ice1712_ak4524_write(ice1712_t *ice, int chip,
1281 unsigned char addr, unsigned char data)
1282{
1283 unsigned char tmp, data_mask, clk_mask, saved[2];
1284 unsigned char codecs_mask;
1285 int idx, cif;
1286 unsigned int addrdata;
1287
1288 snd_assert(chip >=0 && chip < 4, return);
1289 if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_EWS88MT) {
1290 /* assert AK4524 CS */
1291 snd_ice1712_ews88mt_chip_select(ice, ~(1 << chip) & 0x0f);
1292 //snd_ice1712_ews88mt_chip_select(ice, 0x0f);
1293 }
1294
1295 cif = 0; /* the default level of the CIF pin from AK4524 */
1296 save_gpio_status(ice, saved);
1297 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
1298 switch (ice->eeprom.subvendor) {
1299 case ICE1712_SUBDEVICE_AUDIOPHILE:
1300 data_mask = ICE1712_DELTA_AP_DOUT;
1301 clk_mask = ICE1712_DELTA_AP_CCLK;
1302 codecs_mask = ICE1712_DELTA_AP_CS_CODEC; /* select AK4528 codec */
1303 tmp |= ICE1712_DELTA_AP_CS_DIGITAL; /* assert digital high */
1304 break;
1305 case ICE1712_SUBDEVICE_EWX2496:
1306 data_mask = ICE1712_EWX2496_SERIAL_DATA;
1307 clk_mask = ICE1712_EWX2496_SERIAL_CLOCK;
1308 codecs_mask = ICE1712_EWX2496_AK4524_CS;
1309 tmp |= ICE1712_EWX2496_RW; /* set rw bit high */
1310 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
1311 ice->gpio_direction | data_mask | clk_mask |
1312 codecs_mask | ICE1712_EWX2496_RW);
1313 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
1314 ~(data_mask | clk_mask |
1315 codecs_mask | ICE1712_EWX2496_RW));
1316 cif = 1; /* CIF high */
1317 break;
1318 case ICE1712_SUBDEVICE_EWS88MT:
1319 data_mask = ICE1712_EWS88_SERIAL_DATA;
1320 clk_mask = ICE1712_EWS88_SERIAL_CLOCK;
1321 codecs_mask = 0; /* no chip select on gpio */
1322 tmp |= ICE1712_EWS88_RW; /* set rw bit high */
1323 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
1324 ice->gpio_direction | data_mask | clk_mask |
1325 codecs_mask | ICE1712_EWS88_RW);
1326 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
1327 ~(data_mask | clk_mask |
1328 codecs_mask | ICE1712_EWS88_RW));
1329 cif = 1; /* CIF high */
1330 break;
1331 default:
1332 data_mask = ICE1712_DELTA_CODEC_SERIAL_DATA;
1333 clk_mask = ICE1712_DELTA_CODEC_SERIAL_CLOCK;
1334 codecs_mask = chip == 0 ? ICE1712_DELTA_CODEC_CHIP_A : ICE1712_DELTA_CODEC_CHIP_B;
1335 break;
1336 }
1337
1338 if (cif) {
1339 tmp |= codecs_mask; /* start without chip select */
1340 } else {
1341 tmp &= ~codecs_mask; /* chip select low */
1342 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
1343 udelay(1);
1344 }
1345
1346 addr &= 0x07;
1347 /* build I2C address + data byte */
1348 addrdata = 0xa000 | (addr << 8) | data;
1349 for (idx = 15; idx >= 0; idx--) {
1350 tmp &= ~(data_mask|clk_mask);
1351 if (addrdata & (1 << idx))
1352 tmp |= data_mask;
1353 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
1354 //udelay(200);
1355 udelay(1);
1356 tmp |= clk_mask;
1357 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
1358 udelay(1);
1359 }
1360
1361 if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_EWS88MT) {
1362 //snd_ice1712_ews88mt_chip_select(ice, ~(1 << chip) & 0x0f);
1363 udelay(1);
1364 snd_ice1712_ews88mt_chip_select(ice, 0x0f);
1365 } else {
1366 if (cif) {
1367 /* assert a cs pulse to trigger */
1368 tmp &= ~codecs_mask;
1369 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
1370 udelay(1);
1371 }
1372 tmp |= codecs_mask; /* chip select high to trigger */
1373 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
1374 udelay(1);
1375 }
1376
1377 ice->ak4524_images[chip][addr] = data;
1378 restore_gpio_status(ice, saved);
1379}
1380
1381
1382/*
1383 * decode/encode channel status bits from CS8404A on EWS88MT&D
1384 */
1385static void snd_ice1712_ews_decode_cs8404_spdif_bits(snd_aes_iec958_t *diga,
1386 unsigned char bits)
1387{
1388 if (bits & 0x10) { /* consumer */
1389 if (!(bits & 0x20))
1390 diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT;
1391 if (!(bits & 0x40))
1392 diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
1393 if (!(bits & 0x80))
1394 diga->status[1] |= IEC958_AES1_CON_ORIGINAL;
1395 switch (bits & 0x03) {
1396 case 0x00: diga->status[1] |= IEC958_AES1_CON_DAT; break;
1397 case 0x03: diga->status[1] |= IEC958_AES1_CON_GENERAL; break;
1398 }
1399 switch (bits & 0x06) {
1400 case 0x02: diga->status[3] |= IEC958_AES3_CON_FS_32000; break;
1401 case 0x04: diga->status[3] |= IEC958_AES3_CON_FS_48000; break;
1402 case 0x06: diga->status[3] |= IEC958_AES3_CON_FS_44100; break;
1403 }
1404 } else {
1405 diga->status[0] = IEC958_AES0_PROFESSIONAL;
1406 if (!(bits & 0x04))
1407 diga->status[0] |= IEC958_AES0_NONAUDIO;
1408 switch (bits & 0x60) {
1409 case 0x00: diga->status[0] |= IEC958_AES0_PRO_FS_32000; break;
1410 case 0x40: diga->status[0] |= IEC958_AES0_PRO_FS_44100; break;
1411 case 0x20: diga->status[0] |= IEC958_AES0_PRO_FS_48000; break;
1412 case 0x60: diga->status[0] |= IEC958_AES0_PRO_FS_NOTID; break;
1413 }
1414 switch (bits & 0x03) {
1415 case 0x02: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NONE; break;
1416 case 0x01: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015; break;
1417 case 0x00: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_CCITT; break;
1418 case 0x03: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NOTID; break;
1419 }
1420 if (!(bits & 0x80))
1421 diga->status[1] |= IEC958_AES1_PRO_MODE_STEREOPHONIC;
1422 }
1423}
1424
1425static unsigned char snd_ice1712_ews_encode_cs8404_spdif_bits(snd_aes_iec958_t *diga)
1426{
1427 unsigned char bits;
1428
1429 if (!(diga->status[0] & IEC958_AES0_PROFESSIONAL)) {
1430 bits = 0x10; /* consumer mode */
1431 if (!(diga->status[0] & IEC958_AES0_CON_NOT_COPYRIGHT))
1432 bits |= 0x20;
1433 if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) == IEC958_AES0_CON_EMPHASIS_NONE)
1434 bits |= 0x40;
1435 if (!(diga->status[1] & IEC958_AES1_CON_ORIGINAL))
1436 bits |= 0x80;
1437 if ((diga->status[1] & IEC958_AES1_CON_CATEGORY) == IEC958_AES1_CON_GENERAL)
1438 bits |= 0x03;
1439 switch (diga->status[3] & IEC958_AES3_CON_FS) {
1440 default:
1441 case IEC958_AES3_CON_FS_44100: bits |= 0x06; break;
1442 case IEC958_AES3_CON_FS_48000: bits |= 0x04; break;
1443 case IEC958_AES3_CON_FS_32000: bits |= 0x02; break;
1444 }
1445 } else {
1446 bits = 0x00; /* professional mode */
1447 if (!(diga->status[0] & IEC958_AES0_NONAUDIO))
1448 bits |= 0x04;
1449 switch (diga->status[0] & IEC958_AES0_PRO_FS) {
1450 case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break;
1451 case IEC958_AES0_PRO_FS_44100: bits |= 0x40; break; /* 44.1kHz */
1452 case IEC958_AES0_PRO_FS_48000: bits |= 0x20; break; /* 48kHz */
1453 default:
1454 case IEC958_AES0_PRO_FS_NOTID: bits |= 0x00; break;
1455 }
1456 switch (diga->status[0] & IEC958_AES0_PRO_EMPHASIS) {
1457 case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x02; break;
1458 case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x01; break;
1459 case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break;
1460 default:
1461 case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x03; break;
1462 }
1463 switch (diga->status[1] & IEC958_AES1_PRO_MODE) {
1464 case IEC958_AES1_PRO_MODE_TWO:
1465 case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break;
1466 default: bits |= 0x80; break;
1467 }
1468 }
1469 return bits;
1470}
1471
1472/* write on i2c address 0x40 */
1473static void snd_ice1712_ews_cs8404_spdif_write(ice1712_t *ice, unsigned char bits)
1474{
1475 unsigned short val, nval;
1476
1477 switch (ice->eeprom.subvendor) {
1478 case ICE1712_SUBDEVICE_EWS88MT:
1479 snd_ice1712_ews88mt_pcf8574_write(ice, ICE1712_EWS88MT_CS8404_ADDR, bits);
1480 break;
1481 case ICE1712_SUBDEVICE_EWS88D:
1482 val = snd_ice1712_ews88d_pcf8575_read(ice, ICE1712_EWS88D_PCF_ADDR);
1483 nval = val & 0xff;
1484 nval |= bits << 8;
1485 if (val != nval)
1486 snd_ice1712_ews88d_pcf8575_write(ice, ICE1712_EWS88D_PCF_ADDR, nval);
1487 break;
1488 }
1489}
1490
1491
1492/*
1493 * change the input clock selection
1494 * spdif_clock = 1 - IEC958 input, 0 - Envy24
1495 */
1496static int snd_ice1712_cs8427_set_input_clock(ice1712_t *ice, int spdif_clock)
1497{
1498 unsigned char val, nval;
1499 val = ice->cs8427_ops->read(ice, 4);
1500 nval = val & 0xf0;
1501 if (spdif_clock)
1502 nval |= 0x01;
1503 else
1504 nval |= 0x04;
1505 if (val != nval) {
1506 ice->cs8427_ops->write(ice, 4, nval);
1507 return 1;
1508 }
1509 return 0;
1510}
1511
1512#if 0 // we change clock selection automatically according to the ice1712 clock source
1513static int snd_ice1712_cs8427_clock_select_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1514{
1515 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1516 uinfo->count = 1;
1517 uinfo->value.integer.min = 0;
1518 uinfo->value.integer.max = 1;
1519 return 0;
1520}
1521
1522static int snd_ice1712_cs8427_clock_select_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1523{
1524 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
1525 int val;
1526 val = ice->cs8427_ops->read(ice, 4);
1527 ucontrol->value.integer.value[0] = (val & 0x01) ? 1 : 0;
1528 return 0;
1529}
1530
1531static int snd_ice1712_cs8427_clock_select_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
1532{
1533 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
1534 return snd_ice1712_cs8427_set_input_clock(ice, ucontrol->value.integer.value[0]);
1535}
1536
1537static snd_kcontrol_new_t snd_ice1712_cs8427_clock_select = {
1538 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
1539 name: "CS8427 Clock Select",
1540 info: snd_ice1712_cs8427_clock_select_info,
1541 get: snd_ice1712_cs8427_clock_select_get,
1542 put: snd_ice1712_cs8427_clock_select_put,
1543};
1544#endif
1545
1546
1547/*
1548 */
1549static int snd_ice1712_cs8427_in_status_info(snd_kcontrol_t *kcontrol,
1550 snd_ctl_elem_info_t *uinfo)
1551{
1552 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1553 uinfo->count = 1;
1554 uinfo->value.integer.min = 0;
1555 uinfo->value.integer.max = 255;
1556 return 0;
1557}
1558
1559static int snd_ice1712_cs8427_in_status_get(snd_kcontrol_t *kcontrol,
1560 snd_ctl_elem_value_t *ucontrol)
1561{
1562 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
1563 ucontrol->value.integer.value[0] = ice->cs8427_ops->read(ice, 15);
1564 return 0;
1565}
1566
1567static snd_kcontrol_new_t snd_ice1712_cs8427_in_status = {
1568#ifdef TARGET_OS2
1569 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
1570 "IEC958 Input Status",0,
1571 SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1572 snd_ice1712_cs8427_in_status_info,
1573 snd_ice1712_cs8427_in_status_get,0,0
1574#else
1575 iface: SNDRV_CTL_ELEM_IFACE_PCM,
1576 info: snd_ice1712_cs8427_in_status_info,
1577 name: "IEC958 Input Status",
1578 access: SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1579 get: snd_ice1712_cs8427_in_status_get,
1580#endif
1581};
1582
1583
1584/*
1585 */
1586static void snd_ice1712_set_pro_rate(ice1712_t *ice, snd_pcm_substream_t *substream)
1587{
1588 unsigned long flags;
1589 unsigned int rate;
1590 unsigned char val, tmp;
1591
1592 spin_lock_irqsave(&ice->reg_lock, flags);
1593 if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
1594 ICE1712_PLAYBACK_PAUSE|
1595 ICE1712_PLAYBACK_START))
1596 goto __end;
1597 if (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER)
1598 goto __end;
1599 rate = substream->runtime->rate;
1600 switch (rate) {
1601 case 8000: val = 6; break;
1602 case 9600: val = 3; break;
1603 case 11025: val = 10; break;
1604 case 12000: val = 2; break;
1605 case 16000: val = 5; break;
1606 case 22050: val = 9; break;
1607 case 24000: val = 1; break;
1608 case 32000: val = 4; break;
1609 case 44100: val = 8; break;
1610 case 48000: val = 0; break;
1611 case 64000: val = 15; break;
1612 case 88200: val = 11; break;
1613 case 96000: val = 7; break;
1614 default:
1615 snd_BUG();
1616 val = 0;
1617 break;
1618 }
1619 outb(val, ICEMT(ice, RATE));
1620 switch (ice->eeprom.subvendor) {
1621 case ICE1712_SUBDEVICE_DELTA1010:
1622 case ICE1712_SUBDEVICE_DELTADIO2496:
1623 case ICE1712_SUBDEVICE_DELTA66:
1624 case ICE1712_SUBDEVICE_DELTA44:
1625 case ICE1712_SUBDEVICE_AUDIOPHILE:
1626 /* FIXME: we should put AK452x codecs to reset state
1627 when this bit is being changed */
1628 spin_unlock_irqrestore(&ice->reg_lock, flags);
1629 down(&ice->gpio_mutex);
1630 tmp = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
1631 if (val == 15 || val == 11 || val == 7) {
1632 tmp |= ICE1712_DELTA_DFS;
1633 } else {
1634 tmp &= ~ICE1712_DELTA_DFS;
1635 }
1636 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, tmp);
1637 up(&ice->gpio_mutex);
1638 return;
1639 }
1640 __end:
1641 spin_unlock_irqrestore(&ice->reg_lock, flags);
1642}
1643
1644/*
1645 * Interrupt handler
1646 */
1647
1648static void snd_ice1712_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1649{
1650 ice1712_t *ice = snd_magic_cast(ice1712_t, dev_id, return);
1651 unsigned char status;
1652
1653 while (1) {
1654 status = inb(ICEREG(ice, IRQSTAT));
1655 if (status == 0)
1656 break;
1657 if (status & ICE1712_IRQ_MPU1) {
1658 if (ice->rmidi[0])
1659 snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data, regs);
1660 outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
1661 status &= ~ICE1712_IRQ_MPU1;
1662 }
1663 if (status & ICE1712_IRQ_TIMER)
1664 outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
1665 if (status & ICE1712_IRQ_MPU2) {
1666 if (ice->rmidi[1])
1667 snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data, regs);
1668 outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
1669 status &= ~ICE1712_IRQ_MPU2;
1670 }
1671 if (status & ICE1712_IRQ_PROPCM) {
1672 unsigned char mtstat = inb(ICEMT(ice, IRQ));
1673 if (mtstat & ICE1712_MULTI_PBKSTATUS) {
1674 if (ice->playback_pro_substream)
1675 snd_pcm_period_elapsed(ice->playback_pro_substream);
1676 outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
1677 }
1678 if (mtstat & ICE1712_MULTI_CAPSTATUS) {
1679 if (ice->capture_pro_substream)
1680 snd_pcm_period_elapsed(ice->capture_pro_substream);
1681 outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
1682 }
1683 }
1684 if (status & ICE1712_IRQ_FM)
1685 outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
1686 if (status & ICE1712_IRQ_PBKDS) {
1687 u32 idx;
1688 u16 pbkstatus;
1689 snd_pcm_substream_t *substream;
1690 pbkstatus = inw(ICEDS(ice, INTSTAT));
1691 //printk("pbkstatus = 0x%x\n", pbkstatus);
1692 for (idx = 0; idx < 6; idx++) {
1693 if ((pbkstatus & (3 << (idx * 2))) == 0)
1694 continue;
1695 if ((substream = ice->playback_con_substream_ds[idx]) != NULL)
1696 snd_pcm_period_elapsed(substream);
1697 outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
1698 }
1699 outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
1700 }
1701 if (status & ICE1712_IRQ_CONCAP) {
1702 if (ice->capture_con_substream)
1703 snd_pcm_period_elapsed(ice->capture_con_substream);
1704 outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
1705 }
1706 if (status & ICE1712_IRQ_CONPBK) {
1707 if (ice->playback_con_substream)
1708 snd_pcm_period_elapsed(ice->playback_con_substream);
1709 outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
1710 }
1711 }
1712}
1713
1714/*
1715 * PCM part - misc
1716 */
1717
1718static int snd_ice1712_hw_params(snd_pcm_substream_t * substream,
1719 snd_pcm_hw_params_t * hw_params)
1720{
1721 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1722}
1723
1724static int snd_ice1712_hw_free(snd_pcm_substream_t * substream)
1725{
1726 return snd_pcm_lib_free_pages(substream);
1727}
1728
1729/*
1730 * PCM part - consumer I/O
1731 */
1732
1733static int snd_ice1712_playback_trigger(snd_pcm_substream_t * substream,
1734 int cmd)
1735{
1736 ice1712_t *ice = snd_pcm_substream_chip(substream);
1737 int result = 0;
1738 u32 tmp;
1739
1740 spin_lock(&ice->reg_lock);
1741 tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
1742 if (cmd == SNDRV_PCM_TRIGGER_START) {
1743 tmp |= 1;
1744 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
1745 tmp &= ~1;
1746 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
1747 tmp |= 2;
1748 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
1749 tmp &= ~2;
1750 } else {
1751 result = -EINVAL;
1752 }
1753 snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
1754 spin_unlock(&ice->reg_lock);
1755 return result;
1756}
1757
1758static int snd_ice1712_playback_ds_trigger(snd_pcm_substream_t * substream,
1759 int cmd)
1760{
1761 ice1712_t *ice = snd_pcm_substream_chip(substream);
1762 int result = 0;
1763 u32 tmp;
1764
1765 spin_lock(&ice->reg_lock);
1766 tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
1767 if (cmd == SNDRV_PCM_TRIGGER_START) {
1768 tmp |= 1;
1769 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
1770 tmp &= ~1;
1771 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
1772 tmp |= 2;
1773 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
1774 tmp &= ~2;
1775 } else {
1776 result = -EINVAL;
1777 }
1778 snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
1779 spin_unlock(&ice->reg_lock);
1780 return result;
1781}
1782
1783static int snd_ice1712_capture_trigger(snd_pcm_substream_t * substream,
1784 int cmd)
1785{
1786 ice1712_t *ice = snd_pcm_substream_chip(substream);
1787 int result = 0;
1788 u8 tmp;
1789
1790 spin_lock(&ice->reg_lock);
1791 tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
1792 if (cmd == SNDRV_PCM_TRIGGER_START) {
1793 tmp |= 1;
1794 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
1795 tmp &= ~1;
1796 } else {
1797 result = -EINVAL;
1798 }
1799 snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
1800 spin_unlock(&ice->reg_lock);
1801 return result;
1802}
1803
1804static int snd_ice1712_playback_prepare(snd_pcm_substream_t * substream)
1805{
1806 unsigned long flags;
1807 ice1712_t *ice = snd_pcm_substream_chip(substream);
1808 snd_pcm_runtime_t *runtime = substream->runtime;
1809 u32 period_size, buf_size, rate, tmp;
1810
1811 period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
1812 buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
1813 tmp = 0x0000;
1814 if (snd_pcm_format_width(runtime->format) == 16)
1815 tmp |= 0x10;
1816 if (runtime->channels == 2)
1817 tmp |= 0x08;
1818 rate = (runtime->rate * 8192) / 375;
1819 if (rate > 0x000fffff)
1820 rate = 0x000fffff;
1821 spin_lock_irqsave(&ice->reg_lock, flags);
1822 outb(0, ice->ddma_port + 15);
1823 outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
1824 outl(runtime->dma_addr, ice->ddma_port + 0);
1825 outw(buf_size, ice->ddma_port + 4);
1826 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
1827 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
1828 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
1829 snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
1830 snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
1831 snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
1832 snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
1833 snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
1834 spin_unlock_irqrestore(&ice->reg_lock, flags);
1835 return 0;
1836}
1837
1838static int snd_ice1712_playback_ds_prepare(snd_pcm_substream_t * substream)
1839{
1840 unsigned long flags;
1841 ice1712_t *ice = snd_pcm_substream_chip(substream);
1842 snd_pcm_runtime_t *runtime = substream->runtime;
1843 u32 period_size, buf_size, rate, tmp, chn;
1844
1845 period_size = snd_pcm_lib_period_bytes(substream) - 1;
1846 buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
1847 tmp = 0x0064;
1848 if (snd_pcm_format_width(runtime->format) == 16)
1849 tmp &= ~0x04;
1850 if (runtime->channels == 2)
1851 tmp |= 0x08;
1852 rate = (runtime->rate * 8192) / 375;
1853 if (rate > 0x000fffff)
1854 rate = 0x000fffff;
1855 ice->playback_con_active_buf[substream->number] = 0;
1856 ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
1857 chn = substream->number * 2;
1858 spin_lock_irqsave(&ice->reg_lock, flags);
1859 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
1860 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
1861 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
1862 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
1863 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
1864 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
1865 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
1866 if (runtime->channels == 2) {
1867 snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
1868 snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
1869 }
1870 spin_unlock_irqrestore(&ice->reg_lock, flags);
1871 return 0;
1872}
1873
1874static int snd_ice1712_capture_prepare(snd_pcm_substream_t * substream)
1875{
1876 unsigned long flags;
1877 ice1712_t *ice = snd_pcm_substream_chip(substream);
1878 snd_pcm_runtime_t *runtime = substream->runtime;
1879 u32 period_size, buf_size;
1880 u8 tmp;
1881
1882 period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
1883 buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
1884 tmp = 0x06;
1885 if (snd_pcm_format_width(runtime->format) == 16)
1886 tmp &= ~0x04;
1887 if (runtime->channels == 2)
1888 tmp &= ~0x02;
1889 spin_lock_irqsave(&ice->reg_lock, flags);
1890 outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
1891 outw(buf_size, ICEREG(ice, CONCAP_COUNT));
1892 snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
1893 snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
1894 snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
1895 spin_unlock_irqrestore(&ice->reg_lock, flags);
1896 snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
1897 return 0;
1898}
1899
1900static snd_pcm_uframes_t snd_ice1712_playback_pointer(snd_pcm_substream_t * substream)
1901{
1902 ice1712_t *ice = snd_pcm_substream_chip(substream);
1903 snd_pcm_runtime_t *runtime = substream->runtime;
1904 size_t ptr;
1905
1906 if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
1907 return 0;
1908 ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
1909 return bytes_to_frames(substream->runtime, ptr);
1910}
1911
1912static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(snd_pcm_substream_t * substream)
1913{
1914 ice1712_t *ice = snd_pcm_substream_chip(substream);
1915 u8 addr;
1916 size_t ptr;
1917
1918 if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
1919 return 0;
1920 if (ice->playback_con_active_buf[substream->number])
1921 addr = ICE1712_DSC_ADDR1;
1922 else
1923 addr = ICE1712_DSC_ADDR0;
1924 ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
1925 ice->playback_con_virt_addr[substream->number];
1926 return bytes_to_frames(substream->runtime, ptr);
1927}
1928
1929static snd_pcm_uframes_t snd_ice1712_capture_pointer(snd_pcm_substream_t * substream)
1930{
1931 ice1712_t *ice = snd_pcm_substream_chip(substream);
1932 size_t ptr;
1933
1934 if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
1935 return 0;
1936 ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
1937 return bytes_to_frames(substream->runtime, ptr);
1938}
1939
1940#ifdef TARGET_OS2
1941static snd_pcm_hardware_t snd_ice1712_playback =
1942{
1943/* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1944 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1945 SNDRV_PCM_INFO_MMAP_VALID |
1946 SNDRV_PCM_INFO_PAUSE),
1947/* formats: */ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1948/* rates: */ SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1949/* rate_min: */ 4000,
1950/* rate_max: */ 48000,
1951/* channels_min: */ 1,
1952/* channels_max: */ 2,
1953/* buffer_bytes_max: */ (64*1024),
1954/* period_bytes_min: */ 64,
1955/* period_bytes_max: */ (64*1024),
1956/* periods_min: */ 1,
1957/* periods_max: */ 1024,
1958/* fifo_size: */ 0,
1959};
1960
1961static snd_pcm_hardware_t snd_ice1712_playback_ds =
1962{
1963/* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1964 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1965 SNDRV_PCM_INFO_MMAP_VALID |
1966 SNDRV_PCM_INFO_PAUSE),
1967/* formats: */ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1968/* rates: */ SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1969/* rate_min: */ 4000,
1970/* rate_max: */ 48000,
1971/* channels_min: */ 1,
1972/* channels_max: */ 2,
1973/* buffer_bytes_max: */ (128*1024),
1974/* period_bytes_min: */ 64,
1975/* period_bytes_max: */ (128*1024),
1976/* periods_min: */ 2,
1977/* periods_max: */ 2,
1978/* fifo_size: */ 0,
1979};
1980
1981static snd_pcm_hardware_t snd_ice1712_capture =
1982{
1983/* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1984 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1985 SNDRV_PCM_INFO_MMAP_VALID),
1986/* formats: */ SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1987/* rates: */ SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1988/* rate_min: */ 4000,
1989/* rate_max: */ 48000,
1990/* channels_min: */ 1,
1991/* channels_max: */ 2,
1992/* buffer_bytes_max: */ (64*1024),
1993/* period_bytes_min: */ 64,
1994/* period_bytes_max: */ (64*1024),
1995/* periods_min: */ 1,
1996/* periods_max: */ 1024,
1997/* fifo_size: */ 0,
1998};
1999#else
2000static snd_pcm_hardware_t snd_ice1712_playback =
2001{
2002 info: (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
2003 SNDRV_PCM_INFO_BLOCK_TRANSFER |
2004 SNDRV_PCM_INFO_MMAP_VALID |
2005 SNDRV_PCM_INFO_PAUSE),
2006 formats: SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
2007 rates: SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
2008 rate_min: 4000,
2009 rate_max: 48000,
2010 channels_min: 1,
2011 channels_max: 2,
2012 buffer_bytes_max: (64*1024),
2013 period_bytes_min: 64,
2014 period_bytes_max: (64*1024),
2015 periods_min: 1,
2016 periods_max: 1024,
2017 fifo_size: 0,
2018};
2019
2020static snd_pcm_hardware_t snd_ice1712_playback_ds =
2021{
2022 info: (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
2023 SNDRV_PCM_INFO_BLOCK_TRANSFER |
2024 SNDRV_PCM_INFO_MMAP_VALID |
2025 SNDRV_PCM_INFO_PAUSE),
2026 formats: SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
2027 rates: SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
2028 rate_min: 4000,
2029 rate_max: 48000,
2030 channels_min: 1,
2031 channels_max: 2,
2032 buffer_bytes_max: (128*1024),
2033 period_bytes_min: 64,
2034 period_bytes_max: (128*1024),
2035 periods_min: 2,
2036 periods_max: 2,
2037 fifo_size: 0,
2038};
2039
2040static snd_pcm_hardware_t snd_ice1712_capture =
2041{
2042 info: (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
2043 SNDRV_PCM_INFO_BLOCK_TRANSFER |
2044 SNDRV_PCM_INFO_MMAP_VALID),
2045 formats: SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
2046 rates: SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
2047 rate_min: 4000,
2048 rate_max: 48000,
2049 channels_min: 1,
2050 channels_max: 2,
2051 buffer_bytes_max: (64*1024),
2052 period_bytes_min: 64,
2053 period_bytes_max: (64*1024),
2054 periods_min: 1,
2055 periods_max: 1024,
2056 fifo_size: 0,
2057};
2058#endif
2059
2060static int snd_ice1712_playback_open(snd_pcm_substream_t * substream)
2061{
2062 snd_pcm_runtime_t *runtime = substream->runtime;
2063 ice1712_t *ice = snd_pcm_substream_chip(substream);
2064
2065 ice->playback_con_substream = substream;
2066 runtime->hw = snd_ice1712_playback;
2067 return 0;
2068}
2069
2070static int snd_ice1712_playback_ds_open(snd_pcm_substream_t * substream)
2071{
2072 snd_pcm_runtime_t *runtime = substream->runtime;
2073 ice1712_t *ice = snd_pcm_substream_chip(substream);
2074 unsigned long flags;
2075 u32 tmp;
2076
2077 ice->playback_con_substream_ds[substream->number] = substream;
2078 runtime->hw = snd_ice1712_playback_ds;
2079 spin_lock_irqsave(&ice->reg_lock, flags);
2080 tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
2081 outw(tmp, ICEDS(ice, INTMASK));
2082 spin_unlock_irqrestore(&ice->reg_lock, flags);
2083 return 0;
2084}
2085
2086static int snd_ice1712_capture_open(snd_pcm_substream_t * substream)
2087{
2088 snd_pcm_runtime_t *runtime = substream->runtime;
2089 ice1712_t *ice = snd_pcm_substream_chip(substream);
2090
2091 ice->capture_con_substream = substream;
2092 runtime->hw = snd_ice1712_capture;
2093 runtime->hw.rates = ice->ac97->rates_adc;
2094 if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
2095 runtime->hw.rate_min = 48000;
2096 return 0;
2097}
2098
2099static int snd_ice1712_playback_close(snd_pcm_substream_t * substream)
2100{
2101 ice1712_t *ice = snd_pcm_substream_chip(substream);
2102
2103 ice->playback_con_substream = NULL;
2104 return 0;
2105}
2106
2107static int snd_ice1712_playback_ds_close(snd_pcm_substream_t * substream)
2108{
2109 ice1712_t *ice = snd_pcm_substream_chip(substream);
2110 unsigned long flags;
2111 u32 tmp;
2112
2113 spin_lock_irqsave(&ice->reg_lock, flags);
2114 tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
2115 outw(tmp, ICEDS(ice, INTMASK));
2116 spin_unlock_irqrestore(&ice->reg_lock, flags);
2117 ice->playback_con_substream_ds[substream->number] = NULL;
2118 return 0;
2119}
2120
2121static int snd_ice1712_capture_close(snd_pcm_substream_t * substream)
2122{
2123 ice1712_t *ice = snd_pcm_substream_chip(substream);
2124
2125 /* disable ADC power */
2126 snd_ac97_update_bits(ice->ac97, AC97_POWERDOWN, 0x0100, 0x0100);
2127 ice->capture_con_substream = NULL;
2128 return 0;
2129}
2130
2131#ifdef TARGET_OS2
2132static snd_pcm_ops_t snd_ice1712_playback_ops = {
2133 snd_ice1712_playback_open,
2134 snd_ice1712_playback_close,
2135 snd_pcm_lib_ioctl,
2136 snd_ice1712_hw_params,
2137 snd_ice1712_hw_free,
2138 snd_ice1712_playback_prepare,
2139 snd_ice1712_playback_trigger,
2140 snd_ice1712_playback_pointer,0,0
2141};
2142
2143static snd_pcm_ops_t snd_ice1712_playback_ds_ops = {
2144 snd_ice1712_playback_ds_open,
2145 snd_ice1712_playback_ds_close,
2146 snd_pcm_lib_ioctl,
2147 snd_ice1712_hw_params,
2148 snd_ice1712_hw_free,
2149 snd_ice1712_playback_ds_prepare,
2150 snd_ice1712_playback_ds_trigger,
2151 snd_ice1712_playback_ds_pointer,0,0
2152};
2153
2154static snd_pcm_ops_t snd_ice1712_capture_ops = {
2155 snd_ice1712_capture_open,
2156 snd_ice1712_capture_close,
2157 snd_pcm_lib_ioctl,
2158 snd_ice1712_hw_params,
2159 snd_ice1712_hw_free,
2160 snd_ice1712_capture_prepare,
2161 snd_ice1712_capture_trigger,
2162 snd_ice1712_capture_pointer,0,0
2163};
2164#else
2165static snd_pcm_ops_t snd_ice1712_playback_ops = {
2166 open: snd_ice1712_playback_open,
2167 close: snd_ice1712_playback_close,
2168 ioctl: snd_pcm_lib_ioctl,
2169 hw_params: snd_ice1712_hw_params,
2170 hw_free: snd_ice1712_hw_free,
2171 prepare: snd_ice1712_playback_prepare,
2172 trigger: snd_ice1712_playback_trigger,
2173 pointer: snd_ice1712_playback_pointer,
2174};
2175
2176static snd_pcm_ops_t snd_ice1712_playback_ds_ops = {
2177 open: snd_ice1712_playback_ds_open,
2178 close: snd_ice1712_playback_ds_close,
2179 ioctl: snd_pcm_lib_ioctl,
2180 hw_params: snd_ice1712_hw_params,
2181 hw_free: snd_ice1712_hw_free,
2182 prepare: snd_ice1712_playback_ds_prepare,
2183 trigger: snd_ice1712_playback_ds_trigger,
2184 pointer: snd_ice1712_playback_ds_pointer,
2185};
2186
2187static snd_pcm_ops_t snd_ice1712_capture_ops = {
2188 open: snd_ice1712_capture_open,
2189 close: snd_ice1712_capture_close,
2190 ioctl: snd_pcm_lib_ioctl,
2191 hw_params: snd_ice1712_hw_params,
2192 hw_free: snd_ice1712_hw_free,
2193 prepare: snd_ice1712_capture_prepare,
2194 trigger: snd_ice1712_capture_trigger,
2195 pointer: snd_ice1712_capture_pointer,
2196};
2197#endif
2198
2199static void __exit snd_ice1712_pcm_free(snd_pcm_t *pcm)
2200{
2201 ice1712_t *ice = snd_magic_cast(ice1712_t, pcm->private_data, return);
2202 ice->pcm = NULL;
2203 snd_pcm_lib_preallocate_free_for_all(pcm);
2204}
2205
2206static int __init snd_ice1712_pcm(ice1712_t * ice, int device, snd_pcm_t ** rpcm)
2207{
2208 snd_pcm_t *pcm;
2209 int err;
2210
2211 if (rpcm)
2212 *rpcm = NULL;
2213 err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
2214 if (err < 0)
2215 return err;
2216
2217 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
2218 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
2219
2220 pcm->private_data = ice;
2221 pcm->private_free = snd_ice1712_pcm_free;
2222 pcm->info_flags = 0;
2223 strcpy(pcm->name, "ICE1712 consumer");
2224 ice->pcm = pcm;
2225
2226 snd_pcm_lib_preallocate_pci_pages_for_all(ice->pci, pcm, 64*1024, 64*1024);
2227
2228 if (rpcm)
2229 *rpcm = pcm;
2230
2231 printk("Consumer PCM code does not work well at the moment --jk\n");
2232
2233 return 0;
2234}
2235
2236static void __exit snd_ice1712_pcm_free_ds(snd_pcm_t *pcm)
2237{
2238 ice1712_t *ice = snd_magic_cast(ice1712_t, pcm->private_data, return);
2239 ice->pcm_ds = NULL;
2240 snd_pcm_lib_preallocate_free_for_all(pcm);
2241}
2242
2243static int __init snd_ice1712_pcm_ds(ice1712_t * ice, int device, snd_pcm_t ** rpcm)
2244{
2245 snd_pcm_t *pcm;
2246 int err;
2247
2248 if (rpcm)
2249 *rpcm = NULL;
2250 err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
2251 if (err < 0)
2252 return err;
2253
2254 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
2255
2256 pcm->private_data = ice;
2257 pcm->private_free = snd_ice1712_pcm_free_ds;
2258 pcm->info_flags = 0;
2259 strcpy(pcm->name, "ICE1712 consumer (DS)");
2260 ice->pcm_ds = pcm;
2261
2262 snd_pcm_lib_preallocate_pci_pages_for_all(ice->pci, pcm, 64*1024, 128*1024);
2263
2264 if (rpcm)
2265 *rpcm = pcm;
2266
2267 return 0;
2268}
2269
2270/*
2271 * PCM code - professional part (multitrack)
2272 */
2273
2274static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
2275 32000, 44100, 48000, 64000, 88200, 96000 };
2276
2277#define RATES sizeof(rates) / sizeof(rates[0])
2278
2279#ifdef TARGET_OS2
2280static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
2281 RATES,
2282 rates,
2283 0,
2284};
2285#else
2286static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
2287 count: RATES,
2288 list: rates,
2289 mask: 0,
2290};
2291#endif
2292
2293#if 0
2294
2295static int snd_ice1712_playback_pro_ioctl(snd_pcm_substream_t * substream,
2296 unsigned int cmd,
2297 void *arg)
2298{
2299 ice1712_t *ice = snd_pcm_substream_chip(substream);
2300
2301 switch (cmd) {
2302 case SNDRV_PCM_IOCTL1_DIG_INFO:
2303 {
2304 snd_pcm_dig_info_t *info = arg;
2305 switch (ice->eeprom.subvendor) {
2306 case ICE1712_SUBDEVICE_DELTA1010:
2307 case ICE1712_SUBDEVICE_DELTADIO2496:
2308 case ICE1712_SUBDEVICE_DELTA66:
2309 return snd_ice1712_dig_cs8403_info(substream, info);
2310 }
2311 }
2312 case SNDRV_PCM_IOCTL1_DIG_PARAMS:
2313 {
2314 snd_pcm_dig_params_t *params = arg;
2315 switch (ice->eeprom.subvendor) {
2316 case ICE1712_SUBDEVICE_DELTA1010:
2317 case ICE1712_SUBDEVICE_DELTADIO2496:
2318 case ICE1712_SUBDEVICE_DELTA66:
2319 return snd_ice1712_dig_cs8403_params(substream, params);
2320 }
2321 }
2322 default:
2323 break;
2324 }
2325 return snd_pcm_lib_ioctl(substream, cmd, arg);
2326}
2327
2328#endif
2329
2330static int snd_ice1712_pro_trigger(snd_pcm_substream_t *substream,
2331 int cmd)
2332{
2333 ice1712_t *ice = snd_pcm_substream_chip(substream);
2334 switch (cmd) {
2335 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2336 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2337 {
2338 unsigned int what;
2339 unsigned int old;
2340 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
2341 return -EINVAL;
2342 what = ICE1712_PLAYBACK_PAUSE;
2343 snd_pcm_trigger_done(substream, substream);
2344 spin_lock(&ice->reg_lock);
2345 old = inl(ICEMT(ice, PLAYBACK_CONTROL));
2346 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
2347 old |= what;
2348 else
2349 old &= ~what;
2350 outl(old, ICEMT(ice, PLAYBACK_CONTROL));
2351 spin_unlock(&ice->reg_lock);
2352 break;
2353 }
2354 case SNDRV_PCM_TRIGGER_START:
2355 case SNDRV_PCM_TRIGGER_STOP:
2356 {
2357 unsigned int what = 0;
2358 unsigned int old;
2359 snd_pcm_substream_t *s = substream;
2360 do {
2361 if (s == ice->playback_pro_substream) {
2362 what |= ICE1712_PLAYBACK_START;
2363 snd_pcm_trigger_done(s, substream);
2364 } else if (s == ice->capture_pro_substream) {
2365 what |= ICE1712_CAPTURE_START_SHADOW;
2366 snd_pcm_trigger_done(s, substream);
2367 }
2368 s = s->link_next;
2369 } while (s != substream);
2370 spin_lock(&ice->reg_lock);
2371 old = inl(ICEMT(ice, PLAYBACK_CONTROL));
2372 if (cmd == SNDRV_PCM_TRIGGER_START)
2373 old |= what;
2374 else
2375 old &= ~what;
2376 outl(old, ICEMT(ice, PLAYBACK_CONTROL));
2377 spin_unlock(&ice->reg_lock);
2378 break;
2379 }
2380 default:
2381 return -EINVAL;
2382 }
2383 return 0;
2384}
2385
2386static void snd_ice1712_cs8427_set_status(ice1712_t *ice, snd_pcm_runtime_t *runtime,
2387 unsigned char *status)
2388{
2389 if (status[0] & IEC958_AES0_PROFESSIONAL) {
2390 status[0] &= ~IEC958_AES0_PRO_FS;
2391 switch (runtime->rate) {
2392 case 32000: status[0] |= IEC958_AES0_PRO_FS_32000; break;
2393 case 44100: status[0] |= IEC958_AES0_PRO_FS_44100; break;
2394 case 48000: status[0] |= IEC958_AES0_PRO_FS_48000; break;
2395 default: status[0] |= IEC958_AES0_PRO_FS_NOTID; break;
2396 }
2397 } else {
2398 status[3] &= ~IEC958_AES3_CON_FS;
2399 switch (runtime->rate) {
2400 case 32000: status[3] |= IEC958_AES3_CON_FS_32000; break;
2401 case 44100: status[3] |= IEC958_AES3_CON_FS_44100; break;
2402 case 48000: status[3] |= IEC958_AES3_CON_FS_48000; break;
2403 }
2404 }
2405}
2406
2407static int snd_ice1712_playback_pro_prepare(snd_pcm_substream_t * substream)
2408{
2409 unsigned long flags;
2410 ice1712_t *ice = snd_pcm_substream_chip(substream);
2411 unsigned int tmp;
2412 unsigned char tmpst[5];
2413 int change;
2414
2415 ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
2416 snd_ice1712_set_pro_rate(ice, substream);
2417 spin_lock_irqsave(&ice->reg_lock, flags);
2418 outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
2419 outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
2420 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
2421 switch (ice->eeprom.subvendor) {
2422 case ICE1712_SUBDEVICE_DELTA1010:
2423 case ICE1712_SUBDEVICE_DELTADIO2496:
2424 case ICE1712_SUBDEVICE_DELTA66:
2425 /* setup S/PDIF */
2426 tmp = ice->cs8403_spdif_stream_bits;
2427 if (tmp & 0x01) /* consumer */
2428 tmp &= (tmp & 0x01) ? ~0x06 : ~0x18;
2429 switch (substream->runtime->rate) {
2430 case 32000: tmp |= (tmp & 0x01) ? 0x04 : 0x00; break;
2431 case 44100: tmp |= (tmp & 0x01) ? 0x00 : 0x10; break;
2432 case 48000: tmp |= (tmp & 0x01) ? 0x02 : 0x08; break;
2433 default: tmp |= (tmp & 0x01) ? 0x00 : 0x18; break;
2434 }
2435 change = ice->cs8403_spdif_stream_bits != tmp;
2436 ice->cs8403_spdif_stream_bits = tmp;
2437 spin_unlock_irqrestore(&ice->reg_lock, flags);
2438 if (change)
2439 snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE, &ice->spdif_stream_ctl->id);
2440 snd_ice1712_delta_cs8403_spdif_write(ice, tmp);
2441 return 0;
2442 case ICE1712_SUBDEVICE_EWX2496:
2443 case ICE1712_SUBDEVICE_AUDIOPHILE:
2444 /* setup S/PDIF */
2445 memcpy(tmpst, ice->cs8427_spdif_stream_status, 5);
2446 snd_ice1712_cs8427_set_status(ice, substream->runtime, tmpst);
2447 change = memcmp(tmpst, ice->cs8427_spdif_stream_status, 5) != 0;
2448 memcpy(ice->cs8427_spdif_stream_status, tmpst, 5);
2449 spin_unlock_irqrestore(&ice->reg_lock, flags);
2450 if (change) {
2451 snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE, &ice->spdif_stream_ctl->id);
2452 ice->cs8427_ops->write_bytes(ice, 32, 5, tmpst);
2453 }
2454 return 0;
2455 case ICE1712_SUBDEVICE_EWS88MT:
2456 case ICE1712_SUBDEVICE_EWS88D:
2457 /* setup S/PDIF */
2458 tmp = ice->cs8403_spdif_stream_bits;
2459 if (tmp & 0x10) /* consumer */
2460 tmp &= (tmp & 0x01) ? ~0x06 : ~0x60;
2461 switch (substream->runtime->rate) {
2462 case 32000: tmp |= (tmp & 0x01) ? 0x02 : 0x00; break;
2463 case 44100: tmp |= (tmp & 0x01) ? 0x06 : 0x40; break;
2464 case 48000: tmp |= (tmp & 0x01) ? 0x04 : 0x20; break;
2465 default: tmp |= (tmp & 0x01) ? 0x06 : 0x40; break;
2466 }
2467 change = ice->cs8403_spdif_stream_bits != tmp;
2468 ice->cs8403_spdif_stream_bits = tmp;
2469 spin_unlock_irqrestore(&ice->reg_lock, flags);
2470 if (change)
2471 snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE, &ice->spdif_stream_ctl->id);
2472 snd_ice1712_ews_cs8404_spdif_write(ice, tmp);
2473 return 0;
2474 }
2475
2476 spin_unlock_irqrestore(&ice->reg_lock, flags);
2477 return 0;
2478}
2479
2480static int snd_ice1712_capture_pro_prepare(snd_pcm_substream_t * substream)
2481{
2482 unsigned long flags;
2483 ice1712_t *ice = snd_pcm_substream_chip(substream);
2484
2485 ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
2486 snd_ice1712_set_pro_rate(ice, substream);
2487 spin_lock_irqsave(&ice->reg_lock, flags);
2488 outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
2489 outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
2490 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
2491 spin_unlock_irqrestore(&ice->reg_lock, flags);
2492 return 0;
2493}
2494
2495static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(snd_pcm_substream_t * substream)
2496{
2497 ice1712_t *ice = snd_pcm_substream_chip(substream);
2498 size_t ptr;
2499
2500 if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
2501 return 0;
2502 ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
2503 return bytes_to_frames(substream->runtime, ptr);
2504}
2505
2506static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(snd_pcm_substream_t * substream)
2507{
2508 ice1712_t *ice = snd_pcm_substream_chip(substream);
2509 size_t ptr;
2510
2511 if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
2512 return 0;
2513 ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
2514 return bytes_to_frames(substream->runtime, ptr);
2515}
2516
2517#ifdef TARGET_OS2
2518static snd_pcm_hardware_t snd_ice1712_playback_pro =
2519{
2520/* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
2521 SNDRV_PCM_INFO_BLOCK_TRANSFER |
2522 SNDRV_PCM_INFO_MMAP_VALID |
2523 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
2524/* formats: */ SNDRV_PCM_FMTBIT_S32_LE,
2525/* rates: */ SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
2526/* rate_min: */ 4000,
2527/* rate_max: */ 96000,
2528/* channels_min: */ 10,
2529/* channels_max: */ 10,
2530/* buffer_bytes_max: */ (256*1024),
2531/* period_bytes_min: */ 10 * 4 * 2,
2532/* period_bytes_max: */ 131040,
2533/* periods_min: */ 1,
2534/* periods_max: */ 1024,
2535/* fifo_size: */ 0,
2536};
2537
2538static snd_pcm_hardware_t snd_ice1712_capture_pro =
2539{
2540/* info: */ (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
2541 SNDRV_PCM_INFO_BLOCK_TRANSFER |
2542 SNDRV_PCM_INFO_MMAP_VALID |
2543 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
2544/* formats: */ SNDRV_PCM_FMTBIT_S32_LE,
2545/* rates: */ SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
2546/* rate_min: */ 4000,
2547/* rate_max: */ 96000,
2548/* channels_min: */ 12,
2549/* channels_max: */ 12,
2550/* buffer_bytes_max: */ (256*1024),
2551/* period_bytes_min: */ 12 * 4 * 2,
2552/* period_bytes_max: */ 131040,
2553/* periods_min: */ 1,
2554/* periods_max: */ 1024,
2555/* fifo_size: */ 0,
2556};
2557#else
2558static snd_pcm_hardware_t snd_ice1712_playback_pro =
2559{
2560 info: (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
2561 SNDRV_PCM_INFO_BLOCK_TRANSFER |
2562 SNDRV_PCM_INFO_MMAP_VALID |
2563 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
2564 formats: SNDRV_PCM_FMTBIT_S32_LE,
2565 rates: SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
2566 rate_min: 4000,
2567 rate_max: 96000,
2568 channels_min: 10,
2569 channels_max: 10,
2570 buffer_bytes_max: (256*1024),
2571 period_bytes_min: 10 * 4 * 2,
2572 period_bytes_max: 131040,
2573 periods_min: 1,
2574 periods_max: 1024,
2575 fifo_size: 0,
2576};
2577
2578static snd_pcm_hardware_t snd_ice1712_capture_pro =
2579{
2580 info: (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
2581 SNDRV_PCM_INFO_BLOCK_TRANSFER |
2582 SNDRV_PCM_INFO_MMAP_VALID |
2583 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
2584 formats: SNDRV_PCM_FMTBIT_S32_LE,
2585 rates: SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
2586 rate_min: 4000,
2587 rate_max: 96000,
2588 channels_min: 12,
2589 channels_max: 12,
2590 buffer_bytes_max: (256*1024),
2591 period_bytes_min: 12 * 4 * 2,
2592 period_bytes_max: 131040,
2593 periods_min: 1,
2594 periods_max: 1024,
2595 fifo_size: 0,
2596};
2597#endif
2598
2599static int snd_ice1712_playback_pro_open(snd_pcm_substream_t * substream)
2600{
2601 snd_pcm_runtime_t *runtime = substream->runtime;
2602 ice1712_t *ice = snd_pcm_substream_chip(substream);
2603
2604 ice->playback_pro_substream = substream;
2605 runtime->hw = snd_ice1712_playback_pro;
2606 snd_pcm_set_sync(substream);
2607 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2608 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
2609
2610 ice->cs8403_spdif_stream_bits = ice->cs8403_spdif_bits;
2611 memcpy(ice->cs8427_spdif_stream_status, ice->cs8427_spdif_status, 5);
2612 if (ice->spdif_stream_ctl != NULL) {
2613 ice->spdif_stream_ctl->access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2614 snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE |
2615 SNDRV_CTL_EVENT_MASK_INFO, &ice->spdif_stream_ctl->id);
2616 }
2617
2618 return 0;
2619}
2620
2621static int snd_ice1712_capture_pro_open(snd_pcm_substream_t * substream)
2622{
2623 ice1712_t *ice = snd_pcm_substream_chip(substream);
2624 snd_pcm_runtime_t *runtime = substream->runtime;
2625
2626 ice->capture_pro_substream = substream;
2627 runtime->hw = snd_ice1712_capture_pro;
2628 snd_pcm_set_sync(substream);
2629 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
2630 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
2631 return 0;
2632}
2633
2634static int snd_ice1712_playback_pro_close(snd_pcm_substream_t * substream)
2635{
2636 ice1712_t *ice = snd_pcm_substream_chip(substream);
2637
2638 ice->playback_pro_substream = NULL;
2639
2640 if (ice->spdif_stream_ctl != NULL) {
2641 ice->spdif_stream_ctl->access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2642 snd_ctl_notify(ice->card, SNDRV_CTL_EVENT_MASK_VALUE |
2643 SNDRV_CTL_EVENT_MASK_INFO, &ice->spdif_stream_ctl->id);
2644 }
2645
2646 return 0;
2647}
2648
2649static int snd_ice1712_capture_pro_close(snd_pcm_substream_t * substream)
2650{
2651 ice1712_t *ice = snd_pcm_substream_chip(substream);
2652
2653 ice->capture_pro_substream = NULL;
2654 return 0;
2655}
2656
2657static void __exit snd_ice1712_pcm_profi_free(snd_pcm_t *pcm)
2658{
2659 ice1712_t *ice = snd_magic_cast(ice1712_t, pcm->private_data, return);
2660 ice->pcm_pro = NULL;
2661 snd_pcm_lib_preallocate_free_for_all(pcm);
2662}
2663
2664#ifdef TARGET_OS2
2665static snd_pcm_ops_t snd_ice1712_playback_pro_ops = {
2666 snd_ice1712_playback_pro_open,
2667 snd_ice1712_playback_pro_close,
2668 snd_pcm_lib_ioctl,
2669 snd_ice1712_hw_params,
2670 snd_ice1712_hw_free,
2671 snd_ice1712_playback_pro_prepare,
2672 snd_ice1712_pro_trigger,
2673 snd_ice1712_playback_pro_pointer,0,0
2674};
2675
2676static snd_pcm_ops_t snd_ice1712_capture_pro_ops = {
2677 snd_ice1712_capture_pro_open,
2678 snd_ice1712_capture_pro_close,
2679 snd_pcm_lib_ioctl,
2680 snd_ice1712_hw_params,
2681 snd_ice1712_hw_free,
2682 snd_ice1712_capture_pro_prepare,
2683 snd_ice1712_pro_trigger,
2684 snd_ice1712_capture_pro_pointer,0,0
2685};
2686#else
2687static snd_pcm_ops_t snd_ice1712_playback_pro_ops = {
2688 open: snd_ice1712_playback_pro_open,
2689 close: snd_ice1712_playback_pro_close,
2690 ioctl: snd_pcm_lib_ioctl,
2691 hw_params: snd_ice1712_hw_params,
2692 hw_free: snd_ice1712_hw_free,
2693 prepare: snd_ice1712_playback_pro_prepare,
2694 trigger: snd_ice1712_pro_trigger,
2695 pointer: snd_ice1712_playback_pro_pointer,
2696};
2697
2698static snd_pcm_ops_t snd_ice1712_capture_pro_ops = {
2699 open: snd_ice1712_capture_pro_open,
2700 close: snd_ice1712_capture_pro_close,
2701 ioctl: snd_pcm_lib_ioctl,
2702 hw_params: snd_ice1712_hw_params,
2703 hw_free: snd_ice1712_hw_free,
2704 prepare: snd_ice1712_capture_pro_prepare,
2705 trigger: snd_ice1712_pro_trigger,
2706 pointer: snd_ice1712_capture_pro_pointer,
2707};
2708#endif
2709
2710static int __init snd_ice1712_pcm_profi(ice1712_t * ice, int device, snd_pcm_t ** rpcm)
2711{
2712 snd_pcm_t *pcm;
2713 int err;
2714
2715 if (rpcm)
2716 *rpcm = NULL;
2717 err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
2718 if (err < 0)
2719 return err;
2720
2721 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
2722 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
2723
2724 pcm->private_data = ice;
2725 pcm->private_free = snd_ice1712_pcm_profi_free;
2726 pcm->info_flags = 0;
2727 strcpy(pcm->name, "ICE1712 multi");
2728
2729 snd_pcm_lib_preallocate_pci_pages_for_all(ice->pci, pcm, 256*1024, 256*1024);
2730
2731 ice->pcm_pro = pcm;
2732 if (rpcm)
2733 *rpcm = pcm;
2734
2735 if ((err = snd_ice1712_build_pro_mixer(ice)) < 0)
2736 return err;
2737 return 0;
2738}
2739
2740/*
2741 * Mixer section
2742 */
2743
2744static void snd_ice1712_update_volume(ice1712_t *ice, int index)
2745{
2746 unsigned int vol = ice->pro_volumes[index];
2747 unsigned short val = 0;
2748
2749 val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
2750 val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
2751 outb(index, ICEMT(ice, MONITOR_INDEX));
2752 outw(val, ICEMT(ice, MONITOR_VOLUME));
2753}
2754
2755static int snd_ice1712_pro_mixer_switch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2756{
2757 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2758 uinfo->count = 2;
2759 uinfo->value.integer.min = 0;
2760 uinfo->value.integer.max = 1;
2761 return 0;
2762}
2763
2764static int snd_ice1712_pro_mixer_switch_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2765{
2766 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
2767 unsigned long flags;
2768 int index = kcontrol->private_value;
2769
2770 spin_lock_irqsave(&ice->reg_lock, flags);
2771 ucontrol->value.integer.value[0] = !((ice->pro_volumes[index] >> 15) & 1);
2772 ucontrol->value.integer.value[1] = !((ice->pro_volumes[index] >> 31) & 1);
2773 spin_unlock_irqrestore(&ice->reg_lock, flags);
2774 return 0;
2775}
2776
2777static int snd_ice1712_pro_mixer_switch_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2778{
2779 unsigned long flags;
2780 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
2781 int index = kcontrol->private_value;
2782 unsigned int nval, change;
2783
2784 nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
2785 (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
2786 spin_lock_irqsave(&ice->reg_lock, flags);
2787 nval |= ice->pro_volumes[index] & ~0x80008000;
2788 change = nval != ice->pro_volumes[index];
2789 ice->pro_volumes[index] = nval;
2790 snd_ice1712_update_volume(ice, index);
2791 spin_unlock_irqrestore(&ice->reg_lock, flags);
2792 return change;
2793}
2794
2795static int snd_ice1712_pro_mixer_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2796{
2797 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2798 uinfo->count = 2;
2799 uinfo->value.integer.min = 0;
2800 uinfo->value.integer.max = 96;
2801 return 0;
2802}
2803
2804static int snd_ice1712_pro_mixer_volume_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2805{
2806 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
2807 unsigned long flags;
2808 int index = kcontrol->private_value;
2809
2810 spin_lock_irqsave(&ice->reg_lock, flags);
2811 ucontrol->value.integer.value[0] = (ice->pro_volumes[index] >> 0) & 127;
2812 ucontrol->value.integer.value[1] = (ice->pro_volumes[index] >> 16) & 127;
2813 spin_unlock_irqrestore(&ice->reg_lock, flags);
2814 return 0;
2815}
2816
2817static int snd_ice1712_pro_mixer_volume_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2818{
2819 unsigned long flags;
2820 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
2821 int index = kcontrol->private_value;
2822 unsigned int nval, change;
2823
2824 nval = (ucontrol->value.integer.value[0] & 127) |
2825 ((ucontrol->value.integer.value[1] & 127) << 16);
2826 spin_lock_irqsave(&ice->reg_lock, flags);
2827 nval |= ice->pro_volumes[index] & ~0x007f007f;
2828 change = nval != ice->pro_volumes[index];
2829 ice->pro_volumes[index] = nval;
2830 snd_ice1712_update_volume(ice, index);
2831 spin_unlock_irqrestore(&ice->reg_lock, flags);
2832 return change;
2833}
2834
2835static int snd_ice1712_ak4524_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2836{
2837 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2838 uinfo->count = 1;
2839 uinfo->value.integer.min = 0;
2840 uinfo->value.integer.max = 127;
2841 return 0;
2842}
2843
2844static int snd_ice1712_ak4524_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2845{
2846 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
2847 int chip = kcontrol->private_value / 8;
2848 int addr = kcontrol->private_value % 8;
2849 ucontrol->value.integer.value[0] = ice->ak4524_images[chip][addr];
2850 return 0;
2851}
2852
2853static int snd_ice1712_ak4524_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2854{
2855 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
2856 int chip = kcontrol->private_value / 8;
2857 int addr = kcontrol->private_value % 8;
2858 unsigned char nval = ucontrol->value.integer.value[0];
2859 int change = ice->ak4524_images[chip][addr] != nval;
2860 if (change)
2861 snd_ice1712_ak4524_write(ice, chip, addr, nval);
2862 return change;
2863}
2864
2865static int snd_ice1712_ak4524_deemphasis_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
2866{
2867 static char *texts[4] = {
2868 "44.1kHz", "Off", "48kHz", "32kHz",
2869 };
2870 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2871 uinfo->count = 1;
2872 uinfo->value.enumerated.items = 4;
2873 if (uinfo->value.enumerated.item >= 4)
2874 uinfo->value.enumerated.item = 3;
2875 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2876 return 0;
2877}
2878
2879static int snd_ice1712_ak4524_deemphasis_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
2880{
2881 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
2882 int chip = kcontrol->id.index;
2883 ucontrol->value.enumerated.item[0] = ice->ak4524_images[chip][3] & 3;
2884 return 0;
2885}
2886
2887static int snd_ice1712_ak4524_deemphasis_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
2888{
2889 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
2890 int chip = kcontrol->id.index;
2891 unsigned char nval = ucontrol->value.enumerated.item[0];
2892 int change;
2893 nval |= (nval & 3) | (ice->ak4524_images[chip][3] & ~3);
2894 change = ice->ak4524_images[chip][3] != nval;
2895 if (change)
2896 snd_ice1712_ak4524_write(ice, chip, 3, nval);
2897 return change;
2898}
2899
2900static int __init snd_ice1712_build_pro_mixer(ice1712_t *ice)
2901{
2902 snd_card_t * card = ice->card;
2903 snd_kcontrol_t ctl;
2904 int idx, err;
2905
2906 /* PCM playback */
2907 for (idx = 0; idx < 10; idx++) {
2908 memset(&ctl, 0, sizeof(ctl));
2909 strcpy(ctl.id.name, "Multi Playback Switch");
2910 ctl.id.index = idx;
2911 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2912 ctl.info = snd_ice1712_pro_mixer_switch_info;
2913 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE;
2914 ctl.get = snd_ice1712_pro_mixer_switch_get;
2915 ctl.put = snd_ice1712_pro_mixer_switch_put;
2916 ctl.private_value = idx;
2917 ctl.private_data = ice;
2918 if ((err = snd_ctl_add(card, snd_ctl_new(&ctl))) < 0)
2919 return err;
2920 memset(&ctl, 0, sizeof(ctl));
2921 strcpy(ctl.id.name, "Multi Playback Volume");
2922 ctl.id.index = idx;
2923 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2924 ctl.info = snd_ice1712_pro_mixer_volume_info;
2925 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE;
2926 ctl.get = snd_ice1712_pro_mixer_volume_get;
2927 ctl.put = snd_ice1712_pro_mixer_volume_put;
2928 ctl.private_value = idx;
2929 ctl.private_data = ice;
2930 if ((err = snd_ctl_add(card, snd_ctl_new(&ctl))) < 0)
2931 return err;
2932 }
2933
2934 /* PCM capture */
2935 for (idx = 0; idx < 10; idx++) {
2936 memset(&ctl, 0, sizeof(ctl));
2937 strcpy(ctl.id.name, "Multi Capture Switch");
2938 ctl.id.index = idx;
2939 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2940 ctl.info = snd_ice1712_pro_mixer_switch_info;
2941 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE;
2942 ctl.get = snd_ice1712_pro_mixer_switch_get;
2943 ctl.put = snd_ice1712_pro_mixer_switch_put;
2944 ctl.private_value = idx + 10;
2945 ctl.private_data = ice;
2946 if ((err = snd_ctl_add(card, snd_ctl_new(&ctl))) < 0)
2947 return err;
2948 memset(&ctl, 0, sizeof(ctl));
2949 strcpy(ctl.id.name, "Multi Capture Volume");
2950 ctl.id.index = idx;
2951 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2952 ctl.info = snd_ice1712_pro_mixer_volume_info;
2953 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE;
2954 ctl.get = snd_ice1712_pro_mixer_volume_get;
2955 ctl.put = snd_ice1712_pro_mixer_volume_put;
2956 ctl.private_value = idx + 10;
2957 ctl.private_data = ice;
2958 if ((err = snd_ctl_add(card, snd_ctl_new(&ctl))) < 0)
2959 return err;
2960 }
2961
2962 return 0;
2963}
2964
2965static void /*__init*/ snd_ice1712_ac97_init(ac97_t *ac97)
2966{
2967 // ice1712_t *ice = snd_magic_cast(ice1712_t, ac97->private_data, return);
2968
2969 /* disable center DAC/surround DAC/LFE DAC/MIC ADC */
2970 snd_ac97_update_bits(ac97, AC97_EXTENDED_STATUS, 0xe800, 0xe800);
2971}
2972
2973static void __exit snd_ice1712_mixer_free_ac97(ac97_t *ac97)
2974{
2975 ice1712_t *ice = snd_magic_cast(ice1712_t, ac97->private_data, return);
2976 ice->ac97 = NULL;
2977}
2978
2979static int __init snd_ice1712_ac97_mixer(ice1712_t * ice)
2980{
2981 int err;
2982
2983 if (!(ice->eeprom.codec & ICE1712_CFG_NO_CON_AC97)) {
2984 ac97_t ac97;
2985 memset(&ac97, 0, sizeof(ac97));
2986 ac97.write = snd_ice1712_ac97_write;
2987 ac97.read = snd_ice1712_ac97_read;
2988 ac97.init = snd_ice1712_ac97_init;
2989 ac97.private_data = ice;
2990 ac97.private_free = snd_ice1712_mixer_free_ac97;
2991 if ((err = snd_ac97_mixer(ice->card, &ac97, &ice->ac97)) < 0)
2992 return err;
2993 return 0;
2994 }
2995 /* hmm.. can we have both consumer and pro ac97 mixers? */
2996 if (! (ice->eeprom.aclink & ICE1712_CFG_PRO_I2S)) {
2997 ac97_t ac97;
2998 memset(&ac97, 0, sizeof(ac97));
2999 ac97.write = snd_ice1712_pro_ac97_write;
3000 ac97.read = snd_ice1712_pro_ac97_read;
3001 ac97.init = snd_ice1712_ac97_init;
3002 ac97.private_data = ice;
3003 ac97.private_free = snd_ice1712_mixer_free_ac97;
3004 if ((err = snd_ac97_mixer(ice->card, &ac97, &ice->ac97)) < 0)
3005 return err;
3006 if ((err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97, ice))) < 0)
3007 return err;
3008 return 0;
3009 }
3010 /* I2S mixer only */
3011 strcat(ice->card->mixername, "ICE1712 - multitrack");
3012 return 0;
3013}
3014
3015/*
3016 *
3017 */
3018
3019static void snd_ice1712_proc_read(snd_info_entry_t *entry,
3020 snd_info_buffer_t * buffer)
3021{
3022 ice1712_t *ice = snd_magic_cast(ice1712_t, entry->private_data, return);
3023 unsigned int idx;
3024
3025 snd_iprintf(buffer, "ICE1712\n\n");
3026 snd_iprintf(buffer, "EEPROM:\n");
3027 snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
3028 snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
3029 snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
3030 snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.codec);
3031 snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.aclink);
3032 snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.i2sID);
3033 snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.spdif);
3034 snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
3035 snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
3036 snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
3037 snd_iprintf(buffer, " AC'97 main : 0x%x\n", ice->eeprom.ac97main);
3038 snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", ice->eeprom.ac97pcm);
3039 snd_iprintf(buffer, " AC'97 record : 0x%x\n", ice->eeprom.ac97rec);
3040 snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.ac97recsrc);
3041 for (idx = 0; idx < 4; idx++)
3042 snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.dacID[idx]);
3043 for (idx = 0; idx < 4; idx++)
3044 snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.adcID[idx]);
3045 for (idx = 0x1c; idx < ice->eeprom.size && idx < 0x1c + sizeof(ice->eeprom.extra); idx++)
3046 snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.extra[idx - 0x1c]);
3047}
3048
3049static void __init snd_ice1712_proc_init(ice1712_t * ice)
3050{
3051 snd_info_entry_t *entry;
3052
3053 if ((entry = snd_info_create_card_entry(ice->card, "ice1712", ice->card->proc_root)) != NULL) {
3054 entry->content = SNDRV_INFO_CONTENT_TEXT;
3055 entry->private_data = ice;
3056 entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
3057 entry->c.text.read_size = 2048;
3058 entry->c.text.read = snd_ice1712_proc_read;
3059 if (snd_info_register(entry) < 0) {
3060 snd_info_free_entry(entry);
3061 entry = NULL;
3062 }
3063 }
3064 ice->proc_entry = entry;
3065}
3066
3067static void __exit snd_ice1712_proc_done(ice1712_t * ice)
3068{
3069 if (ice->proc_entry) {
3070 snd_info_unregister(ice->proc_entry);
3071 ice->proc_entry = NULL;
3072 }
3073}
3074
3075/*
3076 *
3077 */
3078
3079static int snd_ice1712_eeprom_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3080{
3081 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
3082 uinfo->count = 32;
3083 return 0;
3084}
3085
3086static int snd_ice1712_eeprom_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3087{
3088 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3089
3090 memcpy(ucontrol->value.bytes.data, &ice->eeprom, 32);
3091 return 0;
3092}
3093
3094static snd_kcontrol_new_t snd_ice1712_eeprom = {
3095#ifdef TARGET_OS2
3096 SNDRV_CTL_ELEM_IFACE_CARD,0,0,
3097 "ICE1712 EEPROM",0,
3098 SNDRV_CTL_ELEM_ACCESS_READ,
3099 snd_ice1712_eeprom_info,
3100 snd_ice1712_eeprom_get,0,0
3101#else
3102 iface: SNDRV_CTL_ELEM_IFACE_CARD,
3103 name: "ICE1712 EEPROM",
3104 access: SNDRV_CTL_ELEM_ACCESS_READ,
3105 info: snd_ice1712_eeprom_info,
3106 get: snd_ice1712_eeprom_get
3107#endif
3108};
3109
3110/*
3111 */
3112static int snd_ice1712_spdif_default_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3113{
3114 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
3115 uinfo->count = 1;
3116 return 0;
3117}
3118
3119static int snd_ice1712_spdif_default_get(snd_kcontrol_t * kcontrol,
3120 snd_ctl_elem_value_t * ucontrol)
3121{
3122 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3123
3124 switch (ice->eeprom.subvendor) {
3125 case ICE1712_SUBDEVICE_DELTA1010:
3126 case ICE1712_SUBDEVICE_DELTADIO2496:
3127 case ICE1712_SUBDEVICE_DELTA66:
3128 snd_ice1712_decode_cs8403_spdif_bits(&ucontrol->value.iec958, ice->cs8403_spdif_bits);
3129 break;
3130 case ICE1712_SUBDEVICE_AUDIOPHILE:
3131 case ICE1712_SUBDEVICE_EWX2496:
3132 memcpy(ucontrol->value.iec958.status, ice->cs8427_spdif_status, 5);
3133 break;
3134 case ICE1712_SUBDEVICE_EWS88MT:
3135 case ICE1712_SUBDEVICE_EWS88D:
3136 snd_ice1712_ews_decode_cs8404_spdif_bits(&ucontrol->value.iec958, ice->cs8403_spdif_bits);
3137 break;
3138 }
3139 return 0;
3140}
3141
3142static int snd_ice1712_spdif_default_put(snd_kcontrol_t * kcontrol,
3143 snd_ctl_elem_value_t * ucontrol)
3144{
3145 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3146 unsigned long flags;
3147 unsigned int val;
3148 int change;
3149
3150 switch (ice->eeprom.subvendor) {
3151 case ICE1712_SUBDEVICE_DELTA1010:
3152 case ICE1712_SUBDEVICE_DELTADIO2496:
3153 case ICE1712_SUBDEVICE_DELTA66:
3154 val = snd_ice1712_encode_cs8403_spdif_bits(&ucontrol->value.iec958);
3155 spin_lock_irqsave(&ice->reg_lock, flags);
3156 change = ice->cs8403_spdif_bits != val;
3157 ice->cs8403_spdif_bits = val;
3158 if (change && ice->playback_pro_substream == NULL) {
3159 spin_unlock_irqrestore(&ice->reg_lock, flags);
3160 snd_ice1712_delta_cs8403_spdif_write(ice, val);
3161 } else {
3162 spin_unlock_irqrestore(&ice->reg_lock, flags);
3163 }
3164 break;
3165 case ICE1712_SUBDEVICE_AUDIOPHILE:
3166 case ICE1712_SUBDEVICE_EWX2496:
3167 spin_lock_irqsave(&ice->reg_lock, flags);
3168 change = memcmp(ucontrol->value.iec958.status, ice->cs8427_spdif_status, 5) != 0;
3169 memcpy(ice->cs8427_spdif_status, ucontrol->value.iec958.status, 5);
3170 if (change && ice->playback_pro_substream == NULL) {
3171 spin_unlock_irqrestore(&ice->reg_lock, flags);
3172 ice->cs8427_ops->write_bytes(ice, 32, 5, ice->cs8427_spdif_status);
3173 } else
3174 spin_unlock_irqrestore(&ice->reg_lock, flags);
3175 break;
3176 case ICE1712_SUBDEVICE_EWS88MT:
3177 case ICE1712_SUBDEVICE_EWS88D:
3178 val = snd_ice1712_ews_encode_cs8404_spdif_bits(&ucontrol->value.iec958);
3179 spin_lock_irqsave(&ice->reg_lock, flags);
3180 change = ice->cs8403_spdif_bits != val;
3181 ice->cs8403_spdif_bits = val;
3182 if (change && ice->playback_pro_substream == NULL) {
3183 spin_unlock_irqrestore(&ice->reg_lock, flags);
3184 snd_ice1712_ews_cs8404_spdif_write(ice, val);
3185 } else {
3186 spin_unlock_irqrestore(&ice->reg_lock, flags);
3187 }
3188 break;
3189 default:
3190 change = 0;
3191 }
3192 return change;
3193}
3194
3195static snd_kcontrol_new_t snd_ice1712_spdif_default =
3196{
3197#ifdef TARGET_OS2
3198 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
3199 SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),0,0,
3200 snd_ice1712_spdif_default_info,
3201 snd_ice1712_spdif_default_get,
3202 snd_ice1712_spdif_default_put,0
3203#else
3204 iface: SNDRV_CTL_ELEM_IFACE_PCM,
3205 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3206 info: snd_ice1712_spdif_default_info,
3207 get: snd_ice1712_spdif_default_get,
3208 put: snd_ice1712_spdif_default_put
3209#endif
3210};
3211
3212static int snd_ice1712_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3213{
3214 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
3215 uinfo->count = 1;
3216 return 0;
3217}
3218
3219static int snd_ice1712_spdif_maskc_get(snd_kcontrol_t * kcontrol,
3220 snd_ctl_elem_value_t * ucontrol)
3221{
3222 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3223
3224 switch (ice->eeprom.subvendor) {
3225 case ICE1712_SUBDEVICE_DELTA1010:
3226 case ICE1712_SUBDEVICE_DELTADIO2496:
3227 case ICE1712_SUBDEVICE_DELTA66:
3228 case ICE1712_SUBDEVICE_EWS88MT:
3229 case ICE1712_SUBDEVICE_EWS88D:
3230 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
3231 IEC958_AES0_PROFESSIONAL |
3232 IEC958_AES0_CON_NOT_COPYRIGHT |
3233 IEC958_AES0_CON_EMPHASIS;
3234 ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
3235 IEC958_AES1_CON_CATEGORY;
3236 ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
3237 break;
3238 case ICE1712_SUBDEVICE_AUDIOPHILE:
3239 case ICE1712_SUBDEVICE_EWX2496:
3240 ucontrol->value.iec958.status[0] = 0xff;
3241 ucontrol->value.iec958.status[1] = 0xff;
3242 ucontrol->value.iec958.status[2] = 0xff;
3243 ucontrol->value.iec958.status[3] = 0xff;
3244 ucontrol->value.iec958.status[4] = 0xff;
3245 break;
3246 }
3247 return 0;
3248}
3249
3250static int snd_ice1712_spdif_maskp_get(snd_kcontrol_t * kcontrol,
3251 snd_ctl_elem_value_t * ucontrol)
3252{
3253 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3254
3255 switch (ice->eeprom.subvendor) {
3256 case ICE1712_SUBDEVICE_DELTA1010:
3257 case ICE1712_SUBDEVICE_DELTADIO2496:
3258 case ICE1712_SUBDEVICE_DELTA66:
3259 case ICE1712_SUBDEVICE_EWS88MT:
3260 case ICE1712_SUBDEVICE_EWS88D:
3261 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
3262 IEC958_AES0_PROFESSIONAL |
3263 IEC958_AES0_PRO_FS |
3264 IEC958_AES0_PRO_EMPHASIS;
3265 ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
3266 break;
3267 case ICE1712_SUBDEVICE_AUDIOPHILE:
3268 case ICE1712_SUBDEVICE_EWX2496:
3269 ucontrol->value.iec958.status[0] = 0xff;
3270 ucontrol->value.iec958.status[1] = 0xff;
3271 ucontrol->value.iec958.status[2] = 0xff;
3272 ucontrol->value.iec958.status[3] = 0xff;
3273 ucontrol->value.iec958.status[4] = 0xff;
3274 break;
3275 }
3276 return 0;
3277}
3278
3279static snd_kcontrol_new_t snd_ice1712_spdif_maskc =
3280{
3281#ifdef TARGET_OS2
3282 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3283 SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),0,
3284 SNDRV_CTL_ELEM_ACCESS_READ,
3285 snd_ice1712_spdif_mask_info,
3286 snd_ice1712_spdif_maskc_get,0,0
3287#else
3288 access: SNDRV_CTL_ELEM_ACCESS_READ,
3289 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3290 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3291 info: snd_ice1712_spdif_mask_info,
3292 get: snd_ice1712_spdif_maskc_get,
3293#endif
3294};
3295
3296static snd_kcontrol_new_t snd_ice1712_spdif_maskp =
3297{
3298#ifdef TARGET_OS2
3299 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3300 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),0,
3301 SNDRV_CTL_ELEM_ACCESS_READ,
3302 snd_ice1712_spdif_mask_info,
3303 snd_ice1712_spdif_maskp_get,0,0
3304#else
3305 access: SNDRV_CTL_ELEM_ACCESS_READ,
3306 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3307 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3308 info: snd_ice1712_spdif_mask_info,
3309 get: snd_ice1712_spdif_maskp_get,
3310#endif
3311};
3312
3313static int snd_ice1712_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3314{
3315 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
3316 uinfo->count = 1;
3317 return 0;
3318}
3319
3320static int snd_ice1712_spdif_stream_get(snd_kcontrol_t * kcontrol,
3321 snd_ctl_elem_value_t * ucontrol)
3322{
3323 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3324
3325 switch (ice->eeprom.subvendor) {
3326 case ICE1712_SUBDEVICE_DELTA1010:
3327 case ICE1712_SUBDEVICE_DELTADIO2496:
3328 case ICE1712_SUBDEVICE_DELTA66:
3329 snd_ice1712_decode_cs8403_spdif_bits(&ucontrol->value.iec958, ice->cs8403_spdif_stream_bits);
3330 break;
3331 case ICE1712_SUBDEVICE_AUDIOPHILE:
3332 case ICE1712_SUBDEVICE_EWX2496:
3333 //ice->cs8427_ops->read_bytes(ice, 32, 5, ucontrol->value.iec958.status);
3334 memcpy(ucontrol->value.iec958.status, ice->cs8427_spdif_stream_status, 5);
3335 break;
3336 case ICE1712_SUBDEVICE_EWS88MT:
3337 case ICE1712_SUBDEVICE_EWS88D:
3338 snd_ice1712_ews_decode_cs8404_spdif_bits(&ucontrol->value.iec958, ice->cs8403_spdif_stream_bits);
3339 break;
3340 }
3341 return 0;
3342}
3343
3344static int snd_ice1712_spdif_stream_put(snd_kcontrol_t * kcontrol,
3345 snd_ctl_elem_value_t * ucontrol)
3346{
3347 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3348 unsigned long flags;
3349 unsigned int val;
3350 int change;
3351
3352 switch (ice->eeprom.subvendor) {
3353 case ICE1712_SUBDEVICE_DELTA1010:
3354 case ICE1712_SUBDEVICE_DELTADIO2496:
3355 case ICE1712_SUBDEVICE_DELTA66:
3356 val = snd_ice1712_encode_cs8403_spdif_bits(&ucontrol->value.iec958);
3357 spin_lock_irqsave(&ice->reg_lock, flags);
3358 change = ice->cs8403_spdif_stream_bits != val;
3359 ice->cs8403_spdif_stream_bits = val;
3360 if (change && ice->playback_pro_substream != NULL) {
3361 spin_unlock_irqrestore(&ice->reg_lock, flags);
3362 snd_ice1712_delta_cs8403_spdif_write(ice, val);
3363 } else {
3364 spin_unlock_irqrestore(&ice->reg_lock, flags);
3365 }
3366 break;
3367 case ICE1712_SUBDEVICE_AUDIOPHILE:
3368 case ICE1712_SUBDEVICE_EWX2496:
3369 spin_lock_irqsave(&ice->reg_lock, flags);
3370 change = memcmp(ice->cs8427_spdif_stream_status,
3371 ucontrol->value.iec958.status, 5) != 0;
3372 if (change && ice->playback_pro_substream != NULL) {
3373 memcpy(ice->cs8427_spdif_stream_status,
3374 ucontrol->value.iec958.status, 5);
3375 spin_unlock_irqrestore(&ice->reg_lock, flags);
3376 ice->cs8427_ops->write_bytes(ice, 32, 5, ucontrol->value.iec958.status);
3377 } else
3378 spin_unlock_irqrestore(&ice->reg_lock, flags);
3379 break;
3380 case ICE1712_SUBDEVICE_EWS88MT:
3381 case ICE1712_SUBDEVICE_EWS88D:
3382 val = snd_ice1712_ews_encode_cs8404_spdif_bits(&ucontrol->value.iec958);
3383 spin_lock_irqsave(&ice->reg_lock, flags);
3384 change = ice->cs8403_spdif_stream_bits != val;
3385 ice->cs8403_spdif_stream_bits = val;
3386 if (change && ice->playback_pro_substream != NULL) {
3387 spin_unlock_irqrestore(&ice->reg_lock, flags);
3388 snd_ice1712_ews_cs8404_spdif_write(ice, val);
3389 } else {
3390 spin_unlock_irqrestore(&ice->reg_lock, flags);
3391 }
3392 break;
3393 default:
3394 change = 0;
3395 }
3396 return change;
3397}
3398
3399static snd_kcontrol_new_t snd_ice1712_spdif_stream =
3400{
3401#ifdef TARGET_OS2
3402 SNDRV_CTL_ELEM_IFACE_PCM,0,0,
3403 SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),0,
3404 SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3405 snd_ice1712_spdif_stream_info,
3406 snd_ice1712_spdif_stream_get,
3407 snd_ice1712_spdif_stream_put,0
3408#else
3409 access: SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3410 iface: SNDRV_CTL_ELEM_IFACE_PCM,
3411 name: SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3412 info: snd_ice1712_spdif_stream_info,
3413 get: snd_ice1712_spdif_stream_get,
3414 put: snd_ice1712_spdif_stream_put
3415#endif
3416};
3417
3418#ifdef TARGET_OS2
3419#define ICE1712_GPIO(xiface, xname, xindex, shift, xaccess) \
3420{ xiface, 0, 0, xname, 0, xaccess, snd_ice1712_gpio_info, \
3421 snd_ice1712_gpio_get, snd_ice1712_gpio_put, \
3422 shift }
3423#else
3424#define ICE1712_GPIO(xiface, xname, xindex, shift, xaccess) \
3425{ iface: xiface, name: xname, access: xaccess, info: snd_ice1712_gpio_info, \
3426 get: snd_ice1712_gpio_get, put: snd_ice1712_gpio_put, \
3427 private_value: shift }
3428#endif
3429
3430static int snd_ice1712_gpio_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3431{
3432 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
3433 uinfo->count = 1;
3434 uinfo->value.integer.min = 0;
3435 uinfo->value.integer.max = 1;
3436 return 0;
3437}
3438
3439static int snd_ice1712_gpio_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3440{
3441 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3442 unsigned char mask = kcontrol->private_value & 0xff;
3443 unsigned char saved[2];
3444
3445 save_gpio_status(ice, saved);
3446 ucontrol->value.integer.value[0] = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & mask ? 1 : 0;
3447 restore_gpio_status(ice, saved);
3448 return 0;
3449}
3450
3451static int snd_ice1712_gpio_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3452{
3453 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3454 unsigned char mask = kcontrol->private_value & 0xff;
3455 unsigned char saved[2];
3456 int val, nval;
3457
3458 if (kcontrol->private_value & (1 << 31))
3459 return -EPERM;
3460 nval = ucontrol->value.integer.value[0] ? mask : 0;
3461 save_gpio_status(ice, saved);
3462 val = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
3463 nval |= val & ~mask;
3464 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, nval);
3465 restore_gpio_status(ice, saved);
3466 return val != nval;
3467}
3468
3469static snd_kcontrol_new_t snd_ice1712_delta1010_wordclock_select =
3470ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "Word Clock Sync", 0, ICE1712_DELTA_WORD_CLOCK_SELECT, 0);
3471static snd_kcontrol_new_t snd_ice1712_delta1010_wordclock_status =
3472ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "Word Clock Status", 0, ICE1712_DELTA_WORD_CLOCK_STATUS, SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE);
3473static snd_kcontrol_new_t snd_ice1712_deltadio2496_spdif_in_select =
3474ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "IEC958 Input Optical", 0, ICE1712_DELTA_SPDIF_INPUT_SELECT, 0);
3475static snd_kcontrol_new_t snd_ice1712_delta_spdif_in_status =
3476ICE1712_GPIO(SNDRV_CTL_ELEM_IFACE_PCM, "Delta IEC958 Input Status", 0, ICE1712_DELTA_SPDIF_IN_STAT, SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE);
3477
3478static int snd_ice1712_pro_spdif_master_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3479{
3480 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
3481 uinfo->count = 1;
3482 uinfo->value.integer.min = 0;
3483 uinfo->value.integer.max = 1;
3484 return 0;
3485}
3486
3487static int snd_ice1712_pro_spdif_master_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3488{
3489 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3490 unsigned long flags;
3491
3492 spin_lock_irqsave(&ice->reg_lock, flags);
3493 ucontrol->value.integer.value[0] = inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER ? 1 : 0;
3494 spin_unlock_irqrestore(&ice->reg_lock, flags);
3495 return 0;
3496}
3497
3498static int snd_ice1712_pro_spdif_master_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3499{
3500 unsigned long flags;
3501 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3502 int nval, change;
3503
3504 nval = ucontrol->value.integer.value[0] ? ICE1712_SPDIF_MASTER : 0;
3505 spin_lock_irqsave(&ice->reg_lock, flags);
3506 nval |= inb(ICEMT(ice, RATE)) & ~ICE1712_SPDIF_MASTER;
3507 change = inb(ICEMT(ice, RATE)) != nval;
3508 outb(nval, ICEMT(ice, RATE));
3509 spin_unlock_irqrestore(&ice->reg_lock, flags);
3510
3511 if (ice->cs8427_ops) {
3512 /* change CS8427 clock source too */
3513 snd_ice1712_cs8427_set_input_clock(ice, ucontrol->value.integer.value[0]);
3514 }
3515
3516 return change;
3517}
3518
3519static snd_kcontrol_new_t snd_ice1712_pro_spdif_master = {
3520#ifdef TARGET_OS2
3521 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3522 "Multi Track IEC958 Master",0,0,
3523 snd_ice1712_pro_spdif_master_info,
3524 snd_ice1712_pro_spdif_master_get,
3525 snd_ice1712_pro_spdif_master_put,0
3526#else
3527 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3528 name: "Multi Track IEC958 Master",
3529 info: snd_ice1712_pro_spdif_master_info,
3530 get: snd_ice1712_pro_spdif_master_get,
3531 put: snd_ice1712_pro_spdif_master_put
3532#endif
3533};
3534
3535/*
3536 * routing
3537 */
3538static int snd_ice1712_pro_route_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3539{
3540 static char *texts[] = {
3541 "PCM Out", /* 0 */
3542 "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
3543 "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
3544 "IEC958 In L", "IEC958 In R", /* 9-10 */
3545 "Digital Mixer", /* 11 - optional */
3546 };
3547
3548 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3549 uinfo->count = 1;
3550 uinfo->value.enumerated.items = kcontrol->id.index < 2 ? 12 : 11;
3551 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3552 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3553 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3554 return 0;
3555}
3556
3557static int snd_ice1712_pro_route_analog_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
3558{
3559 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3560 int idx = kcontrol->id.index;
3561 unsigned int val, cval;
3562 val = inw(ICEMT(ice, ROUTE_PSDOUT03));
3563 val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
3564 val &= 3;
3565 cval = inw(ICEMT(ice, ROUTE_CAPTURE));
3566 cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
3567 if (val == 1 && idx < 2)
3568 ucontrol->value.enumerated.item[0] = 11;
3569 else if (val == 2)
3570 ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
3571 else if (val == 3)
3572 ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
3573 else
3574 ucontrol->value.enumerated.item[0] = 0;
3575 return 0;
3576}
3577
3578static int snd_ice1712_pro_route_analog_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
3579{
3580 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3581 int change, shift;
3582 int idx = kcontrol->id.index;
3583 unsigned int val, old_val, nval;
3584
3585 /* update PSDOUT */
3586 if (ucontrol->value.enumerated.item[0] >= 11)
3587 nval = idx < 2 ? 1 : 0;
3588 else if (ucontrol->value.enumerated.item[0] >= 9)
3589 nval = 3;
3590 else if (ucontrol->value.enumerated.item[0] >= 1)
3591 nval = 2;
3592 else
3593 nval = 0;
3594 shift = ((idx % 2) * 8) + ((idx / 2) * 2);
3595 val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
3596 val &= ~(0x03 << shift);
3597 val |= nval << shift;
3598 change = val != old_val;
3599 if (change)
3600 outw(val, ICEMT(ice, ROUTE_PSDOUT03));
3601 if (nval < 2)
3602 return change;
3603
3604 /* update CAPTURE */
3605 val = old_val = inw(ICEMT(ice, ROUTE_CAPTURE));
3606 shift = ((idx / 2) * 8) + ((idx % 2) * 4);
3607 if (nval == 2) {
3608 nval = ucontrol->value.enumerated.item[0] - 1;
3609 val &= ~(0x07 << shift);
3610 val |= nval << shift;
3611 } else {
3612 nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
3613 val &= ~(0x08 << shift);
3614 val |= nval << shift;
3615 }
3616 if (val != old_val) {
3617 change = 1;
3618 outw(val, ICEMT(ice, ROUTE_CAPTURE));
3619 }
3620 return change;
3621}
3622
3623static int snd_ice1712_pro_route_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
3624{
3625 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3626 int idx = kcontrol->id.index;
3627 unsigned int val, cval;
3628 val = inw(ICEMT(ice, ROUTE_SPDOUT));
3629 cval = (val >> (idx * 4 + 8)) & 0x0f;
3630 val = (val >> (idx * 2)) & 0x03;
3631 if (val == 1)
3632 ucontrol->value.enumerated.item[0] = 11;
3633 else if (val == 2)
3634 ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
3635 else if (val == 3)
3636 ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
3637 else
3638 ucontrol->value.enumerated.item[0] = 0;
3639 return 0;
3640}
3641
3642static int snd_ice1712_pro_route_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t *ucontrol)
3643{
3644 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3645 int change, shift;
3646 int idx = kcontrol->id.index;
3647 unsigned int val, old_val, nval;
3648
3649 /* update SPDOUT */
3650 val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
3651 if (ucontrol->value.enumerated.item[0] >= 11)
3652 nval = 1;
3653 else if (ucontrol->value.enumerated.item[0] >= 9)
3654 nval = 3;
3655 else if (ucontrol->value.enumerated.item[0] >= 1)
3656 nval = 2;
3657 else
3658 nval = 0;
3659 shift = idx * 2;
3660 val &= ~(0x03 << shift);
3661 val |= nval << shift;
3662 shift = idx * 4 + 8;
3663 if (nval == 2) {
3664 nval = ucontrol->value.enumerated.item[0] - 1;
3665 val &= ~(0x07 << shift);
3666 val |= nval << shift;
3667 } else if (nval == 3) {
3668 nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
3669 val &= ~(0x08 << shift);
3670 val |= nval << shift;
3671 }
3672 change = val != old_val;
3673 if (change)
3674 outw(val, ICEMT(ice, ROUTE_SPDOUT));
3675 return change;
3676}
3677
3678static snd_kcontrol_new_t snd_ice1712_mixer_pro_analog_route = {
3679#ifdef TARGET_OS2
3680 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3681 "H/W Playback Route",0,0,
3682 snd_ice1712_pro_route_info,
3683 snd_ice1712_pro_route_analog_get,
3684 snd_ice1712_pro_route_analog_put,0
3685#else
3686 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3687 name: "H/W Playback Route",
3688 info: snd_ice1712_pro_route_info,
3689 get: snd_ice1712_pro_route_analog_get,
3690 put: snd_ice1712_pro_route_analog_put,
3691#endif
3692};
3693
3694static snd_kcontrol_new_t snd_ice1712_mixer_pro_spdif_route = {
3695#ifdef TARGET_OS2
3696 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3697 "IEC958 Playback Route",0,0,
3698 snd_ice1712_pro_route_info,
3699 snd_ice1712_pro_route_spdif_get,
3700 snd_ice1712_pro_route_spdif_put,0
3701#else
3702 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3703 name: "IEC958 Playback Route",
3704 info: snd_ice1712_pro_route_info,
3705 get: snd_ice1712_pro_route_spdif_get,
3706 put: snd_ice1712_pro_route_spdif_put,
3707#endif
3708};
3709
3710
3711static int snd_ice1712_pro_volume_rate_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3712{
3713 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3714 uinfo->count = 1;
3715 uinfo->value.integer.min = 0;
3716 uinfo->value.integer.max = 255;
3717 return 0;
3718}
3719
3720static int snd_ice1712_pro_volume_rate_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3721{
3722 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3723 unsigned long flags;
3724
3725 spin_lock_irqsave(&ice->reg_lock, flags);
3726 ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
3727 spin_unlock_irqrestore(&ice->reg_lock, flags);
3728 return 0;
3729}
3730
3731static int snd_ice1712_pro_volume_rate_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3732{
3733 unsigned long flags;
3734 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3735 int change;
3736
3737 spin_lock_irqsave(&ice->reg_lock, flags);
3738 change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
3739 outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
3740 spin_unlock_irqrestore(&ice->reg_lock, flags);
3741 return change;
3742}
3743
3744static snd_kcontrol_new_t snd_ice1712_mixer_pro_volume_rate = {
3745#ifdef TARGET_OS2
3746 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3747 "Multi Track Volume Rate",0,0,
3748 snd_ice1712_pro_volume_rate_info,
3749 snd_ice1712_pro_volume_rate_get,
3750 snd_ice1712_pro_volume_rate_put,0
3751#else
3752 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3753 name: "Multi Track Volume Rate",
3754 info: snd_ice1712_pro_volume_rate_info,
3755 get: snd_ice1712_pro_volume_rate_get,
3756 put: snd_ice1712_pro_volume_rate_put
3757#endif
3758};
3759
3760static int snd_ice1712_pro_peak_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
3761{
3762 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3763 uinfo->count = 22;
3764 uinfo->value.integer.min = 0;
3765 uinfo->value.integer.max = 255;
3766 return 0;
3767}
3768
3769static int snd_ice1712_pro_peak_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3770{
3771 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3772 unsigned long flags;
3773 int idx;
3774
3775 spin_lock_irqsave(&ice->reg_lock, flags);
3776 for (idx = 0; idx < 22; idx++) {
3777 outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
3778 ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
3779 }
3780 spin_unlock_irqrestore(&ice->reg_lock, flags);
3781 return 0;
3782}
3783
3784static snd_kcontrol_new_t snd_ice1712_mixer_pro_peak = {
3785#ifdef TARGET_OS2
3786 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3787 "Multi Track Peak",0,
3788 SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
3789 snd_ice1712_pro_peak_info,
3790 snd_ice1712_pro_peak_get,0,0
3791#else
3792 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3793 name: "Multi Track Peak",
3794 access: SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
3795 info: snd_ice1712_pro_peak_info,
3796 get: snd_ice1712_pro_peak_get
3797#endif
3798};
3799
3800/*
3801 * EWX 24/96
3802 */
3803
3804static int snd_ice1712_ewx_io_sense_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo){
3805
3806 static char *texts[4] = {
3807 "+4dBu", "-10dBV",
3808 };
3809 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3810 uinfo->count = 1;
3811 uinfo->value.enumerated.items = 2;
3812 if (uinfo->value.enumerated.item >= 2)
3813 uinfo->value.enumerated.item = 1;
3814 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3815 return 0;
3816}
3817
3818static int snd_ice1712_ewx_io_sense_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3819{
3820 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3821 unsigned char mask = kcontrol->private_value & 0xff;
3822 unsigned char saved[2];
3823
3824 save_gpio_status(ice, saved);
3825 ucontrol->value.enumerated.item[0] = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA) & mask ? 1 : 0;
3826 restore_gpio_status(ice, saved);
3827 return 0;
3828}
3829
3830static int snd_ice1712_ewx_io_sense_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3831{
3832 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3833 unsigned char mask = kcontrol->private_value & 0xff;
3834 unsigned char saved[2];
3835 int val, nval;
3836
3837 if (kcontrol->private_value & (1 << 31))
3838 return -EPERM;
3839 nval = ucontrol->value.enumerated.item[0] ? mask : 0;
3840 save_gpio_status(ice, saved);
3841 val = snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
3842 nval |= val & ~mask;
3843 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, nval);
3844 restore_gpio_status(ice, saved);
3845 return val != nval;
3846}
3847
3848static snd_kcontrol_new_t snd_ice1712_ewx_input_sense = {
3849#ifdef TARGET_OS2
3850 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3851 "Input Sensitivity Switch",0,0,
3852 snd_ice1712_ewx_io_sense_info,
3853 snd_ice1712_ewx_io_sense_get,
3854 snd_ice1712_ewx_io_sense_put,
3855 ICE1712_EWX2496_AIN_SEL,
3856#else
3857 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3858 name: "Input Sensitivity Switch",
3859 info: snd_ice1712_ewx_io_sense_info,
3860 get: snd_ice1712_ewx_io_sense_get,
3861 put: snd_ice1712_ewx_io_sense_put,
3862 private_value: ICE1712_EWX2496_AIN_SEL,
3863#endif
3864};
3865
3866static snd_kcontrol_new_t snd_ice1712_ewx_output_sense = {
3867#ifdef TARGET_OS2
3868 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3869 "Output Sensitivity Switch",0,0,
3870 snd_ice1712_ewx_io_sense_info,
3871 snd_ice1712_ewx_io_sense_get,
3872 snd_ice1712_ewx_io_sense_put,
3873 ICE1712_EWX2496_AOUT_SEL,
3874#else
3875 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3876 name: "Output Sensitivity Switch",
3877 info: snd_ice1712_ewx_io_sense_info,
3878 get: snd_ice1712_ewx_io_sense_get,
3879 put: snd_ice1712_ewx_io_sense_put,
3880 private_value: ICE1712_EWX2496_AOUT_SEL,
3881#endif
3882};
3883
3884
3885/*
3886 * EWS88MT
3887 */
3888/* analog output sensitivity;; address 0x48 bit 6 */
3889static int snd_ice1712_ews88mt_output_sense_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
3890{
3891 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3892 unsigned char saved[2];
3893 unsigned char data;
3894
3895 save_gpio_status(ice, saved);
3896 data = snd_ice1712_ews88mt_pcf8574_read(ice, ICE1712_EWS88MT_OUTPUT_ADDR);
3897 restore_gpio_status(ice, saved);
3898 ucontrol->value.enumerated.item[0] = data & ICE1712_EWS88MT_OUTPUT_SENSE ? 1 : 0; /* high = -10dBV, low = +4dBu */
3899 return 0;
3900}
3901
3902/* analog output sensitivity;; address 0x48 bit 6 */
3903static int snd_ice1712_ews88mt_output_sense_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
3904{
3905 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3906 unsigned char saved[2];
3907 unsigned char data, ndata;
3908
3909 save_gpio_status(ice, saved);
3910 data = snd_ice1712_ews88mt_pcf8574_read(ice, ICE1712_EWS88MT_OUTPUT_ADDR);
3911 ndata = (data & ~ICE1712_EWS88MT_OUTPUT_SENSE) | (ucontrol->value.enumerated.item[0] ? ICE1712_EWS88MT_OUTPUT_SENSE : 0);
3912 if (ndata != data)
3913 snd_ice1712_ews88mt_pcf8574_write(ice, ICE1712_EWS88MT_OUTPUT_ADDR, ndata);
3914 restore_gpio_status(ice, saved);
3915 return ndata != data;
3916
3917}
3918
3919/* analog input sensitivity; address 0x46 */
3920static int snd_ice1712_ews88mt_input_sense_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
3921{
3922 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3923 int channel = kcontrol->id.index;
3924 unsigned char saved[2];
3925 unsigned char data;
3926
3927 snd_assert(channel >= 0 && channel <= 7, return 0);
3928 save_gpio_status(ice, saved);
3929 data = snd_ice1712_ews88mt_pcf8574_read(ice, ICE1712_EWS88MT_INPUT_ADDR);
3930 restore_gpio_status(ice, saved);
3931 /* reversed; high = +4dBu, low = -10dBV */
3932 ucontrol->value.enumerated.item[0] = data & (1 << channel) ? 0 : 1;
3933 return 0;
3934}
3935
3936/* analog output sensitivity; address 0x46 */
3937static int snd_ice1712_ews88mt_input_sense_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
3938{
3939 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
3940 int channel = kcontrol->id.index;
3941 unsigned char saved[2];
3942 unsigned char data, ndata;
3943
3944 snd_assert(channel >= 0 && channel <= 7, return 0);
3945 save_gpio_status(ice, saved);
3946 data = snd_ice1712_ews88mt_pcf8574_read(ice, ICE1712_EWS88MT_INPUT_ADDR);
3947 ndata = (data & ~(1 << channel)) | (ucontrol->value.enumerated.item[0] ? 0 : (1 << channel));
3948 if (ndata != data)
3949 snd_ice1712_ews88mt_pcf8574_write(ice, ICE1712_EWS88MT_INPUT_ADDR, ndata);
3950 restore_gpio_status(ice, saved);
3951 return ndata != data;
3952}
3953
3954static snd_kcontrol_new_t snd_ice1712_ews88mt_input_sense = {
3955#ifdef TARGET_OS2
3956 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3957 "Input Sensitivity Switch",0,0,
3958 snd_ice1712_ewx_io_sense_info,
3959 snd_ice1712_ews88mt_input_sense_get,
3960 snd_ice1712_ews88mt_input_sense_put,0
3961#else
3962 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3963 name: "Input Sensitivity Switch",
3964 info: snd_ice1712_ewx_io_sense_info,
3965 get: snd_ice1712_ews88mt_input_sense_get,
3966 put: snd_ice1712_ews88mt_input_sense_put,
3967#endif
3968};
3969
3970static snd_kcontrol_new_t snd_ice1712_ews88mt_output_sense = {
3971#ifdef TARGET_OS2
3972 SNDRV_CTL_ELEM_IFACE_MIXER,0,0,
3973 "Output Sensitivity Switch",0,0,
3974 snd_ice1712_ewx_io_sense_info,
3975 snd_ice1712_ews88mt_output_sense_get,
3976 snd_ice1712_ews88mt_output_sense_put,0
3977#else
3978 iface: SNDRV_CTL_ELEM_IFACE_MIXER,
3979 name: "Output Sensitivity Switch",
3980 info: snd_ice1712_ewx_io_sense_info,
3981 get: snd_ice1712_ews88mt_output_sense_get,
3982 put: snd_ice1712_ews88mt_output_sense_put,
3983#endif
3984};
3985
3986
3987/*
3988 * EWS88D controls
3989 */
3990
3991static int snd_ice1712_ews88d_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
3992{
3993 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
3994 uinfo->count = 1;
3995 uinfo->value.integer.min = 0;
3996 uinfo->value.integer.max = 1;
3997 return 0;
3998}
3999
4000static int snd_ice1712_ews88d_control_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
4001{
4002 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
4003 int shift = kcontrol->private_value & 0xff;
4004 int invert = (kcontrol->private_value >> 8) & 1;
4005 unsigned short data;
4006
4007 data = snd_ice1712_ews88d_pcf8575_read(ice, ICE1712_EWS88D_PCF_ADDR);
4008 //printk("pcf: read 0x%x\n", data);
4009 data = (data >> shift) & 0x01;
4010 if (invert)
4011 data ^= 0x01;
4012 ucontrol->value.integer.value[0] = data;
4013 return 0;
4014}
4015
4016static int snd_ice1712_ews88d_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
4017{
4018 ice1712_t *ice = snd_kcontrol_chip(kcontrol);
4019 int shift = kcontrol->private_value & 0xff;
4020 int invert = (kcontrol->private_value >> 8) & 1;
4021 unsigned short data, ndata;
4022 int change;
4023
4024 data = snd_ice1712_ews88d_pcf8575_read(ice, ICE1712_EWS88D_PCF_ADDR);
4025 ndata = data & ~(1 << shift);
4026 if (invert) {
4027 if (! ucontrol->value.integer.value[0])
4028 ndata |= (1 << shift);
4029 } else {
4030 if (ucontrol->value.integer.value[0])
4031 ndata |= (1 << shift);
4032 }
4033 change = (data != ndata);
4034 if (change) {
4035 ndata &= 0xff;
4036 ndata |= (unsigned short)ice->cs8403_spdif_stream_bits << 8;
4037 snd_ice1712_ews88d_pcf8575_write(ice, ICE1712_EWS88D_PCF_ADDR, ndata);
4038 //printk("pcf: write 0x%x\n", ndata);
4039 }
4040 return change;
4041}
4042
4043#ifdef TARGET_OS2
4044#define EWS88D_CONTROL(xiface, xname, xindex, xshift, xinvert, xaccess) \
4045{ xiface,0,0,\
4046 xname, 0,\
4047 xaccess,\
4048 snd_ice1712_ews88d_control_info,\
4049 snd_ice1712_ews88d_control_get,\
4050 snd_ice1712_ews88d_control_put,\
4051 xshift | (xinvert << 8),\
4052}
4053#else
4054#define EWS88D_CONTROL(xiface, xname, xindex, xshift, xinvert, xaccess) \
4055{ iface: xiface,\
4056 name: xname,\
4057 access: xaccess,\
4058 info: snd_ice1712_ews88d_control_info,\
4059 get: snd_ice1712_ews88d_control_get,\
4060 put: snd_ice1712_ews88d_control_put,\
4061 private_value: xshift | (xinvert << 8),\
4062}
4063#endif
4064
4065static snd_kcontrol_new_t snd_ice1712_ews88d_spdif_in_opt =
4066EWS88D_CONTROL(SNDRV_CTL_ELEM_IFACE_MIXER, "IEC958 Input Optical", 0, 0, 1, 0); /* inverted */
4067static snd_kcontrol_new_t snd_ice1712_ews88d_opt_out_adat =
4068EWS88D_CONTROL(SNDRV_CTL_ELEM_IFACE_MIXER, "ADAT Output Optical", 0, 1, 0, 0);
4069static snd_kcontrol_new_t snd_ice1712_ews88d_master_adat =
4070EWS88D_CONTROL(SNDRV_CTL_ELEM_IFACE_MIXER, "ADAT External Master Clock", 0, 2, 0, 0);
4071static snd_kcontrol_new_t snd_ice1712_ews88d_adat_enable =
4072EWS88D_CONTROL(SNDRV_CTL_ELEM_IFACE_MIXER, "Enable ADAT", 0, 3, 0, 0);
4073static snd_kcontrol_new_t snd_ice1712_ews88d_adat_through =
4074EWS88D_CONTROL(SNDRV_CTL_ELEM_IFACE_MIXER, "ADAT Through", 0, 4, 1, 0);
4075
4076
4077/*
4078 *
4079 */
4080
4081static unsigned char __init snd_ice1712_read_i2c(ice1712_t *ice,
4082 unsigned char dev,
4083 unsigned char addr)
4084{
4085 long t = 0x10000;
4086
4087 outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
4088 outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
4089 while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
4090 return inb(ICEREG(ice, I2C_DATA));
4091}
4092
4093static int __init snd_ice1712_read_eeprom(ice1712_t *ice)
4094{
4095 int dev = 0xa0; /* EEPROM device address */
4096 unsigned int idx;
4097
4098 if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) == 0) {
4099 snd_printk("ICE1712 has not detected EEPROM\n");
4100 return -EIO;
4101 }
4102 ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
4103 (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
4104 (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
4105 (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
4106 ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
4107 if (ice->eeprom.size < 28) {
4108 snd_printk("invalid EEPROM (size = %i)\n", ice->eeprom.size);
4109 return -EIO;
4110 }
4111 ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
4112 if (ice->eeprom.version != 1) {
4113 snd_printk("invalid EEPROM version %i\n", ice->eeprom.version);
4114 return -EIO;
4115 }
4116 ice->eeprom.codec = snd_ice1712_read_i2c(ice, dev, 0x06);
4117 ice->eeprom.aclink = snd_ice1712_read_i2c(ice, dev, 0x07);
4118 ice->eeprom.i2sID = snd_ice1712_read_i2c(ice, dev, 0x08);
4119 ice->eeprom.spdif = snd_ice1712_read_i2c(ice, dev, 0x09);
4120 ice->eeprom.gpiomask = snd_ice1712_read_i2c(ice, dev, 0x0a);
4121 ice->eeprom.gpiostate = snd_ice1712_read_i2c(ice, dev, 0x0b);
4122 ice->eeprom.gpiodir = snd_ice1712_read_i2c(ice, dev, 0x0c);
4123 ice->eeprom.ac97main = (snd_ice1712_read_i2c(ice, dev, 0x0d) << 0) |
4124 (snd_ice1712_read_i2c(ice, dev, 0x0e) << 8);
4125 ice->eeprom.ac97pcm = (snd_ice1712_read_i2c(ice, dev, 0x0f) << 0) |
4126 (snd_ice1712_read_i2c(ice, dev, 0x10) << 8);
4127 ice->eeprom.ac97rec = (snd_ice1712_read_i2c(ice, dev, 0x11) << 0) |
4128 (snd_ice1712_read_i2c(ice, dev, 0x12) << 8);
4129 ice->eeprom.ac97recsrc = snd_ice1712_read_i2c(ice, dev, 0x13) << 0;
4130 for (idx = 0; idx < 4; idx++) {
4131 ice->eeprom.dacID[idx] = snd_ice1712_read_i2c(ice, dev, 0x14 + idx);
4132 ice->eeprom.adcID[idx] = snd_ice1712_read_i2c(ice, dev, 0x18 + idx);
4133 }
4134 for (idx = 0x1c; idx < ice->eeprom.size && idx < 0x1c + sizeof(ice->eeprom.extra); idx++)
4135 ice->eeprom.extra[idx - 0x1c] = snd_ice1712_read_i2c(ice, dev, idx);
4136 return 0;
4137}
4138
4139static void __init snd_ice1712_ak4524_init(ice1712_t *ice)
4140{
4141 static unsigned char inits[8] = {
4142 0x07, /* 0: all power up */
4143 0x03, /* 1: ADC/DAC reset */
4144 0x60, /* 2: 24bit I2S */
4145 0x19, /* 3: deemphasis off */
4146 0x00, /* 4: ADC left muted */
4147 0x00, /* 5: ADC right muted */
4148 0x00, /* 6: DAC left muted */
4149 0x00, /* 7: DAC right muted */
4150 };
4151 int chip;
4152 unsigned char reg;
4153
4154 for (chip = 0; chip < ice->num_dacs/2; chip++) {
4155 for (reg = 0; reg < 8; ++reg)
4156 snd_ice1712_ak4524_write(ice, chip, reg, inits[reg]);
4157 }
4158}
4159
4160/* init CS8427 transciever */
4161static void __init snd_ice1712_cs8427_init(ice1712_t *ice)
4162{
4163 static unsigned char initvals[] = {
4164 /* RMCK to OMCK, no validity, disable mutes, TCBL=output */
4165 0x80,
4166 /* hold last valid audio sample, RMCK=256*Fs, normal stereo operation */
4167 0x00,
4168 /* output drivers normal operation, Tx<=serial, Rx=>serial */
4169 0x0c,
4170 /* Run off, CMCK=256*Fs, output time base = OMCK, input time base =
4171 covered input clock, recovered input clock source is Envy24 */
4172 0x04,
4173 /* Serial audio input port data format = I2S */
4174 0x05, /* SIDEL=1, SILRPOL=1 */
4175 /* Serial audio output port data format = I2S */
4176 0x05, /* SODEL=1, SOLRPOL=1 */
4177 };
4178 unsigned char buf[32];
4179
4180 /* verify CS8427 ID */
4181 if (ice->cs8427_ops->read(ice, 127) != 0x71) {
4182 snd_printk("unable to find CS8427 signature, initialization is not completed\n");
4183 return;
4184 }
4185 /* turn off run bit while making changes to configuration */
4186 ice->cs8427_ops->write(ice, 4, 0x00);
4187 /* send initial values */
4188 ice->cs8427_ops->write_bytes(ice, 1, 6, initvals);
4189 /* Turn off CS8427 interrupt stuff that is not used in hardware */
4190 memset(buf, 0, sizeof(buf));
4191 /* from address 9 to 15 */
4192 ice->cs8427_ops->write_bytes(ice, 9, 7, buf);
4193 /* unmask the input PLL clock, V, confidence, biphase, parity status bits */
4194 //buf[0] = 0x1f;
4195 buf[0] = 0;
4196 /* Registers 32-55 window to CS buffer
4197 Inhibit D->E transfers from overwriting first 5 bytes of CS data.
4198 Allow D->E transfers (all) of CS data.
4199 Allow E->F transfer of CS data.
4200 One byte mode; both A/B channels get same written CB data.
4201 A channel info is output to chip's EMPH* pin. */
4202 buf[1] = 0x10;
4203 /* Use internal buffer to transmit User (U) data.
4204 Chip's U pin is an output.
4205 Transmit all O's for user data. */
4206 //buf[2] = 0x10;
4207 buf[2] = 0x00;
4208 ice->cs8427_ops->write_bytes(ice, 17, 3, buf);
4209 /* turn on run bit and rock'n'roll */
4210 ice->cs8427_ops->write(ice, 4, initvals[3] | 0x40);
4211 /* write default channel status bytes */
4212 ice->cs8427_ops->write_bytes(ice, 32, 5, ice->cs8427_spdif_status);
4213
4214 /*
4215 * add controls..
4216 */
4217 snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_cs8427_in_status, ice));
4218#if 0
4219 snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_cs8427_clock_select, ice));
4220#endif
4221}
4222
4223static void __init snd_ice1712_stdsp24_gpio_write(ice1712_t *ice, unsigned char byte)
4224{
4225 byte |= ICE1712_STDSP24_CLOCK_BIT;
4226 udelay(100);
4227 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
4228 byte &= ~ICE1712_STDSP24_CLOCK_BIT;
4229 udelay(100);
4230 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
4231 byte |= ICE1712_STDSP24_CLOCK_BIT;
4232 udelay(100);
4233 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, byte);
4234}
4235
4236static void __init snd_ice1712_stdsp24_darear(ice1712_t *ice, int activate)
4237{
4238 down(&ice->gpio_mutex);
4239 ICE1712_STDSP24_0_DAREAR(ice->hoontech_boxbits, activate);
4240 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[0]);
4241 up(&ice->gpio_mutex);
4242}
4243
4244static void __init snd_ice1712_stdsp24_mute(ice1712_t *ice, int activate)
4245{
4246 down(&ice->gpio_mutex);
4247 ICE1712_STDSP24_3_MUTE(ice->hoontech_boxbits, activate);
4248 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[3]);
4249 up(&ice->gpio_mutex);
4250}
4251
4252static void __init snd_ice1712_stdsp24_insel(ice1712_t *ice, int activate)
4253{
4254 down(&ice->gpio_mutex);
4255 ICE1712_STDSP24_3_INSEL(ice->hoontech_boxbits, activate);
4256 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[3]);
4257 up(&ice->gpio_mutex);
4258}
4259
4260static void __init snd_ice1712_stdsp24_box_channel(ice1712_t *ice, int box, int chn, int activate)
4261{
4262 down(&ice->gpio_mutex);
4263
4264 /* select box */
4265 ICE1712_STDSP24_0_BOX(ice->hoontech_boxbits, box);
4266 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[0]);
4267
4268 /* prepare for write */
4269 if (chn == 3)
4270 ICE1712_STDSP24_2_CHN4(ice->hoontech_boxbits, 0);
4271 ICE1712_STDSP24_2_MIDI1(ice->hoontech_boxbits, activate);
4272 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[2]);
4273
4274 ICE1712_STDSP24_1_CHN1(ice->hoontech_boxbits, 1);
4275 ICE1712_STDSP24_1_CHN2(ice->hoontech_boxbits, 1);
4276 ICE1712_STDSP24_1_CHN3(ice->hoontech_boxbits, 1);
4277 ICE1712_STDSP24_2_CHN4(ice->hoontech_boxbits, 1);
4278 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[1]);
4279 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[2]);
4280 udelay(100);
4281 if (chn == 3) {
4282 ICE1712_STDSP24_2_CHN4(ice->hoontech_boxbits, 0);
4283 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[2]);
4284 } else {
4285 switch (chn) {
4286 case 0: ICE1712_STDSP24_1_CHN1(ice->hoontech_boxbits, 0); break;
4287 case 1: ICE1712_STDSP24_1_CHN2(ice->hoontech_boxbits, 0); break;
4288 case 2: ICE1712_STDSP24_1_CHN3(ice->hoontech_boxbits, 0); break;
4289 }
4290 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[1]);
4291 }
4292 udelay(100);
4293 ICE1712_STDSP24_1_CHN1(ice->hoontech_boxbits, 1);
4294 ICE1712_STDSP24_1_CHN2(ice->hoontech_boxbits, 1);
4295 ICE1712_STDSP24_1_CHN3(ice->hoontech_boxbits, 1);
4296 ICE1712_STDSP24_2_CHN4(ice->hoontech_boxbits, 1);
4297 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[1]);
4298 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[2]);
4299 udelay(100);
4300
4301 ICE1712_STDSP24_2_MIDI1(ice->hoontech_boxbits, 0);
4302 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[2]);
4303
4304 up(&ice->gpio_mutex);
4305}
4306
4307static void __init snd_ice1712_stdsp24_box_midi(ice1712_t *ice, int box, int master, int slave)
4308{
4309 down(&ice->gpio_mutex);
4310
4311 /* select box */
4312 ICE1712_STDSP24_0_BOX(ice->hoontech_boxbits, box);
4313 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[0]);
4314
4315 ICE1712_STDSP24_2_MIDIIN(ice->hoontech_boxbits, 1);
4316 ICE1712_STDSP24_2_MIDI1(ice->hoontech_boxbits, master);
4317 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[2]);
4318
4319 udelay(100);
4320
4321 ICE1712_STDSP24_2_MIDIIN(ice->hoontech_boxbits, 0);
4322 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[2]);
4323
4324 udelay(100);
4325
4326 ICE1712_STDSP24_2_MIDIIN(ice->hoontech_boxbits, 1);
4327 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[2]);
4328
4329 udelay(100);
4330
4331 /* MIDI2 is direct */
4332 ICE1712_STDSP24_3_MIDI2(ice->hoontech_boxbits, slave);
4333 snd_ice1712_stdsp24_gpio_write(ice, ice->hoontech_boxbits[3]);
4334
4335 up(&ice->gpio_mutex);
4336}
4337
4338static void __init snd_ice1712_stdsp24_init(ice1712_t *ice)
4339{
4340 int box, chn;
4341
4342 ice->hoontech_boxbits[0] =
4343 ice->hoontech_boxbits[1] =
4344 ice->hoontech_boxbits[2] =
4345 ice->hoontech_boxbits[3] = 0; /* should be already */
4346
4347 ICE1712_STDSP24_SET_ADDR(ice->hoontech_boxbits, 0);
4348 ICE1712_STDSP24_CLOCK(ice->hoontech_boxbits, 0, 1);
4349 ICE1712_STDSP24_0_BOX(ice->hoontech_boxbits, 0);
4350 ICE1712_STDSP24_0_DAREAR(ice->hoontech_boxbits, 0);
4351
4352 ICE1712_STDSP24_SET_ADDR(ice->hoontech_boxbits, 1);
4353 ICE1712_STDSP24_CLOCK(ice->hoontech_boxbits, 1, 1);
4354 ICE1712_STDSP24_1_CHN1(ice->hoontech_boxbits, 1);
4355 ICE1712_STDSP24_1_CHN2(ice->hoontech_boxbits, 1);
4356 ICE1712_STDSP24_1_CHN3(ice->hoontech_boxbits, 1);
4357
4358 ICE1712_STDSP24_SET_ADDR(ice->hoontech_boxbits, 2);
4359 ICE1712_STDSP24_CLOCK(ice->hoontech_boxbits, 2, 1);
4360 ICE1712_STDSP24_2_CHN4(ice->hoontech_boxbits, 1);
4361 ICE1712_STDSP24_2_MIDIIN(ice->hoontech_boxbits, 1);
4362 ICE1712_STDSP24_2_MIDI1(ice->hoontech_boxbits, 0);
4363
4364 ICE1712_STDSP24_SET_ADDR(ice->hoontech_boxbits, 3);
4365 ICE1712_STDSP24_CLOCK(ice->hoontech_boxbits, 3, 1);
4366 ICE1712_STDSP24_3_MIDI2(ice->hoontech_boxbits, 0);
4367 ICE1712_STDSP24_3_MUTE(ice->hoontech_boxbits, 1);
4368 ICE1712_STDSP24_3_INSEL(ice->hoontech_boxbits, 0);
4369
4370 /* let's go - activate only functions in first box */
4371 ice->hoontech_config = 0;
4372 /* ICE1712_STDSP24_MUTE |
4373 ICE1712_STDSP24_INSEL |
4374 ICE1712_STDSP24_DAREAR; */
4375 ice->hoontech_boxconfig[0] = ICE1712_STDSP24_BOX_CHN1 |
4376 ICE1712_STDSP24_BOX_CHN2 |
4377 ICE1712_STDSP24_BOX_CHN3 |
4378 ICE1712_STDSP24_BOX_CHN4 |
4379 ICE1712_STDSP24_BOX_MIDI1 |
4380 ICE1712_STDSP24_BOX_MIDI2;
4381 ice->hoontech_boxconfig[1] =
4382 ice->hoontech_boxconfig[2] =
4383 ice->hoontech_boxconfig[3] = 0;
4384 snd_ice1712_stdsp24_darear(ice, (ice->hoontech_config & ICE1712_STDSP24_DAREAR) ? 1 : 0);
4385 snd_ice1712_stdsp24_mute(ice, (ice->hoontech_config & ICE1712_STDSP24_MUTE) ? 1 : 0);
4386 snd_ice1712_stdsp24_insel(ice, (ice->hoontech_config & ICE1712_STDSP24_INSEL) ? 1 : 0);
4387 for (box = 0; box < 4; box++) {
4388 for (chn = 0; chn < 4; chn++)
4389 snd_ice1712_stdsp24_box_channel(ice, box, chn, (ice->hoontech_boxconfig[box] & (1 << chn)) ? 1 : 0);
4390 snd_ice1712_stdsp24_box_midi(ice, box,
4391 (ice->hoontech_boxconfig[box] & ICE1712_STDSP24_BOX_MIDI1) ? 1 : 0,
4392 (ice->hoontech_boxconfig[box] & ICE1712_STDSP24_BOX_MIDI2) ? 1 : 0);
4393 }
4394}
4395
4396static int __init snd_ice1712_chip_init(ice1712_t *ice)
4397{
4398 outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
4399 udelay(200);
4400 outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
4401 udelay(200);
4402 pci_write_config_byte(ice->pci, 0x60, ice->eeprom.codec);
4403 pci_write_config_byte(ice->pci, 0x61, ice->eeprom.aclink);
4404 pci_write_config_byte(ice->pci, 0x62, ice->eeprom.i2sID);
4405 pci_write_config_byte(ice->pci, 0x63, ice->eeprom.spdif);
4406 if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
4407 ice->gpio_write_mask = ice->eeprom.gpiomask;
4408 ice->gpio_direction = ice->eeprom.gpiodir;
4409 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, ice->eeprom.gpiomask);
4410 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, ice->eeprom.gpiodir);
4411 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, ice->eeprom.gpiostate);
4412 } else {
4413 ice->gpio_write_mask = 0xc0;
4414 ice->gpio_direction = 0xff;
4415 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
4416 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
4417 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, ICE1712_STDSP24_CLOCK_BIT);
4418 }
4419 snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
4420 if (!(ice->eeprom.codec & ICE1712_CFG_NO_CON_AC97)) {
4421 outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
4422 udelay(100);
4423 outb(0, ICEREG(ice, AC97_CMD));
4424 udelay(200);
4425 snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
4426 }
4427
4428 switch (ice->eeprom.subvendor) {
4429 case ICE1712_SUBDEVICE_AUDIOPHILE:
4430 case ICE1712_SUBDEVICE_EWX2496:
4431 ice->num_adcs = ice->num_dacs = 2;
4432 break;
4433 case ICE1712_SUBDEVICE_DELTA44:
4434 case ICE1712_SUBDEVICE_DELTA66:
4435 ice->num_adcs = ice->num_dacs = 4;
4436 break;
4437 case ICE1712_SUBDEVICE_EWS88MT:
4438 ice->num_adcs = ice->num_dacs = 8;
4439 break;
4440 }
4441
4442 switch (ice->eeprom.subvendor) {
4443 case ICE1712_SUBDEVICE_DELTA66:
4444 case ICE1712_SUBDEVICE_DELTA44:
4445 case ICE1712_SUBDEVICE_AUDIOPHILE:
4446 case ICE1712_SUBDEVICE_EWX2496:
4447 case ICE1712_SUBDEVICE_EWS88MT:
4448 snd_ice1712_ak4524_init(ice);
4449 break;
4450 case ICE1712_SUBDEVICE_STDSP24:
4451 snd_ice1712_stdsp24_init(ice);
4452 break;
4453 }
4454 switch (ice->eeprom.subvendor) {
4455 case ICE1712_SUBDEVICE_AUDIOPHILE:
4456 ice->cs8427_ops = &snd_ice1712_ap_cs8427_ops;
4457 snd_ice1712_cs8427_init(ice);
4458 break;
4459 case ICE1712_SUBDEVICE_EWX2496:
4460 ice->cs8427_ops = &snd_ice1712_ewx_cs8427_ops;
4461 snd_ice1712_cs8427_init(ice);
4462 break;
4463 case ICE1712_SUBDEVICE_DELTA1010:
4464 case ICE1712_SUBDEVICE_DELTADIO2496:
4465 case ICE1712_SUBDEVICE_DELTA66:
4466 /* Set spdif defaults */
4467 snd_ice1712_delta_cs8403_spdif_write(ice, ice->cs8403_spdif_bits);
4468 break;
4469 case ICE1712_SUBDEVICE_EWS88MT:
4470 case ICE1712_SUBDEVICE_EWS88D:
4471 /* Set spdif defaults */
4472 snd_ice1712_ews_cs8404_spdif_write(ice, ice->cs8403_spdif_bits);
4473 break;
4474 }
4475 return 0;
4476}
4477
4478static int __init snd_ice1712_build_controls(ice1712_t *ice)
4479{
4480 unsigned int idx;
4481 snd_kcontrol_t *kctl;
4482 int err;
4483
4484 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
4485 if (err < 0)
4486 return err;
4487 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_spdif_master, ice));
4488 if (err < 0)
4489 return err;
4490 for (idx = 0; idx < ice->num_dacs; idx++) {
4491 kctl = snd_ctl_new1(&snd_ice1712_mixer_pro_analog_route, ice);
4492 if (kctl == NULL)
4493 return -ENOMEM;
4494 kctl->id.index = idx;
4495 err = snd_ctl_add(ice->card, kctl);
4496 if (err < 0)
4497 return err;
4498 }
4499 for (idx = 0; idx < 2; idx++) {
4500 kctl = snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice);
4501 if (kctl == NULL)
4502 return -ENOMEM;
4503 kctl->id.index = idx;
4504 err = snd_ctl_add(ice->card, kctl);
4505 if (err < 0)
4506 return err;
4507 }
4508 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
4509 if (err < 0)
4510 return err;
4511 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
4512 if (err < 0)
4513 return err;
4514 switch (ice->eeprom.subvendor) {
4515 case ICE1712_SUBDEVICE_DELTA1010:
4516 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010_wordclock_select, ice));
4517 if (err < 0)
4518 return err;
4519 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta1010_wordclock_status, ice));
4520 if (err < 0)
4521 return err;
4522 break;
4523 case ICE1712_SUBDEVICE_DELTADIO2496:
4524 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_deltadio2496_spdif_in_select, ice));
4525 if (err < 0)
4526 return err;
4527 break;
4528 }
4529 switch (ice->eeprom.subvendor) {
4530 case ICE1712_SUBDEVICE_DELTA1010:
4531 case ICE1712_SUBDEVICE_DELTADIO2496:
4532 case ICE1712_SUBDEVICE_DELTA66:
4533 case ICE1712_SUBDEVICE_AUDIOPHILE:
4534 case ICE1712_SUBDEVICE_EWX2496:
4535 case ICE1712_SUBDEVICE_EWS88MT:
4536 case ICE1712_SUBDEVICE_EWS88D:
4537 snd_assert(ice->pcm_pro != NULL, return -EIO);
4538 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
4539 if (err < 0)
4540 return err;
4541 kctl->id.device = ice->pcm_pro->device;
4542 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
4543 if (err < 0)
4544 return err;
4545 kctl->id.device = ice->pcm_pro->device;
4546 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
4547 if (err < 0)
4548 return err;
4549 kctl->id.device = ice->pcm_pro->device;
4550 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
4551 if (err < 0)
4552 return err;
4553 kctl->id.device = ice->pcm_pro->device;
4554 ice->spdif_stream_ctl = kctl;
4555 break;
4556 }
4557 switch (ice->eeprom.subvendor) {
4558 case ICE1712_SUBDEVICE_DELTA1010:
4559 case ICE1712_SUBDEVICE_DELTADIO2496:
4560 case ICE1712_SUBDEVICE_DELTA66:
4561 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_delta_spdif_in_status, ice));
4562 if (err < 0)
4563 return err;
4564 break;
4565 }
4566 switch (ice->eeprom.subvendor) {
4567 case ICE1712_SUBDEVICE_EWX2496:
4568 case ICE1712_SUBDEVICE_AUDIOPHILE:
4569 case ICE1712_SUBDEVICE_DELTA44:
4570 case ICE1712_SUBDEVICE_DELTA66:
4571 case ICE1712_SUBDEVICE_EWS88MT:
4572 for (idx = 0; idx < ice->num_dacs; ++idx) {
4573 snd_kcontrol_t ctl;
4574 memset(&ctl, 0, sizeof(ctl));
4575 strcpy(ctl.id.name, "DAC Volume");
4576 ctl.id.index = idx;
4577 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
4578 ctl.info = snd_ice1712_ak4524_volume_info;
4579 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE;
4580 ctl.get = snd_ice1712_ak4524_volume_get;
4581 ctl.put = snd_ice1712_ak4524_volume_put;
4582 ctl.private_value = (idx / 2) * 8 + (idx % 2) + 6; /* reigster 6 & 7 */
4583 ctl.private_data = ice;
4584 if ((err = snd_ctl_add(ice->card, snd_ctl_new(&ctl))) < 0)
4585 return err;
4586 }
4587 for (idx = 0; idx < ice->num_adcs; ++idx) {
4588 snd_kcontrol_t ctl;
4589 memset(&ctl, 0, sizeof(ctl));
4590 strcpy(ctl.id.name, "ADC Volume");
4591 ctl.id.index = idx;
4592 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
4593 ctl.info = snd_ice1712_ak4524_volume_info;
4594 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE;
4595 ctl.get = snd_ice1712_ak4524_volume_get;
4596 ctl.put = snd_ice1712_ak4524_volume_put;
4597 ctl.private_value = (idx / 2) * 8 + (idx % 2) + 4; /* reigster 4 & 5 */
4598 ctl.private_data = ice;
4599 if ((err = snd_ctl_add(ice->card, snd_ctl_new(&ctl))) < 0)
4600 return err;
4601 }
4602 for (idx = 0; idx < ice->num_dacs/2; idx++) {
4603 snd_kcontrol_t ctl;
4604 memset(&ctl, 0, sizeof(ctl));
4605 strcpy(ctl.id.name, "Deemphasis");
4606 ctl.id.index = idx;
4607 ctl.id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
4608 ctl.info = snd_ice1712_ak4524_deemphasis_info;
4609 ctl.access = SNDRV_CTL_ELEM_ACCESS_READ|SNDRV_CTL_ELEM_ACCESS_WRITE;
4610 ctl.get = snd_ice1712_ak4524_deemphasis_get;
4611 ctl.put = snd_ice1712_ak4524_deemphasis_put;
4612 ctl.private_data = ice;
4613 if ((err = snd_ctl_add(ice->card, snd_ctl_new(&ctl))) < 0)
4614 return err;
4615 }
4616 break;
4617 }
4618 switch (ice->eeprom.subvendor) {
4619 case ICE1712_SUBDEVICE_EWX2496:
4620 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ewx_input_sense, ice));
4621 if (err < 0)
4622 return err;
4623 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ewx_output_sense, ice));
4624 if (err < 0)
4625 return err;
4626 break;
4627 case ICE1712_SUBDEVICE_EWS88MT:
4628 for (idx = 0; idx < 8; idx++) {
4629 kctl = snd_ctl_new1(&snd_ice1712_ews88mt_input_sense, ice);
4630 kctl->id.index = idx;
4631 err = snd_ctl_add(ice->card, kctl);
4632 if (err < 0)
4633 return err;
4634 }
4635 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ews88mt_output_sense, ice));
4636 if (err < 0)
4637 return err;
4638 break;
4639 case ICE1712_SUBDEVICE_EWS88D:
4640 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ews88d_spdif_in_opt, ice));
4641 if (err < 0)
4642 return err;
4643 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ews88d_opt_out_adat, ice));
4644 if (err < 0)
4645 return err;
4646 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ews88d_master_adat, ice));
4647 if (err < 0)
4648 return err;
4649 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ews88d_adat_enable, ice));
4650 if (err < 0)
4651 return err;
4652 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_ews88d_adat_through, ice));
4653 if (err < 0)
4654 return err;
4655 break;
4656 }
4657
4658 return 0;
4659}
4660
4661static int __exit snd_ice1712_free(ice1712_t *ice)
4662{
4663 if (ice->res_port == NULL)
4664 goto __hw_end;
4665 /* mask all interrupts */
4666 outb(0xc0, ICEMT(ice, IRQ));
4667 outb(0xff, ICEREG(ice, IRQMASK));
4668 /* --- */
4669 __hw_end:
4670 snd_ice1712_proc_done(ice);
4671 synchronize_irq();
4672 if (ice->irq)
4673 free_irq(ice->irq, (void *) ice);
4674 if (ice->res_port)
4675 release_resource(ice->res_port);
4676 if (ice->res_ddma_port)
4677 release_resource(ice->res_ddma_port);
4678 if (ice->res_dmapath_port)
4679 release_resource(ice->res_dmapath_port);
4680 if (ice->res_profi_port)
4681 release_resource(ice->res_profi_port);
4682 snd_magic_kfree(ice);
4683 return 0;
4684}
4685
4686static int __exit snd_ice1712_dev_free(snd_device_t *device)
4687{
4688 ice1712_t *ice = snd_magic_cast(ice1712_t, device->device_data, return -ENXIO);
4689 return snd_ice1712_free(ice);
4690}
4691
4692static int __init snd_ice1712_create(snd_card_t * card,
4693 struct pci_dev *pci,
4694 ice1712_t ** r_ice1712)
4695{
4696 ice1712_t *ice;
4697 int err;
4698#ifdef TARGET_OS2
4699 static snd_device_ops_t ops = {
4700 snd_ice1712_dev_free,0,0,0
4701 };
4702#else
4703 static snd_device_ops_t ops = {
4704 dev_free: snd_ice1712_dev_free,
4705 };
4706#endif
4707 *r_ice1712 = NULL;
4708
4709 /* enable PCI device */
4710 if ((err = pci_enable_device(pci)) < 0)
4711 return err;
4712 /* check, if we can restrict PCI DMA transfers to 28 bits */
4713 if (!pci_dma_supported(pci, 0x0fffffff)) {
4714 snd_printk("architecture does not support 28bit PCI busmaster DMA\n");
4715 return -ENXIO;
4716 }
4717 pci_set_dma_mask(pci, 0x0fffffff);
4718
4719 ice = snd_magic_kcalloc(ice1712_t, 0, GFP_KERNEL);
4720 if (ice == NULL)
4721 return -ENOMEM;
4722 spin_lock_init(&ice->reg_lock);
4723 init_MUTEX(&ice->gpio_mutex);
4724 ice->cs8403_spdif_bits =
4725 ice->cs8403_spdif_stream_bits = (0x01 | /* consumer format */
4726 0x10 | /* no emphasis */
4727 0x20); /* PCM encoder/decoder */
4728 ice->cs8427_spdif_status[0] = (SNDRV_PCM_DEFAULT_CON_SPDIF >> 0) & 0xff;
4729 ice->cs8427_spdif_status[1] = (SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff;
4730 ice->cs8427_spdif_status[2] = (SNDRV_PCM_DEFAULT_CON_SPDIF >> 16) & 0xff;
4731 ice->cs8427_spdif_status[3] = (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff;
4732 memcpy(ice->cs8427_spdif_stream_status, ice->cs8427_spdif_status, 5);
4733 ice->card = card;
4734 ice->pci = pci;
4735 ice->irq = -1;
4736 ice->port = pci_resource_start(pci, 0);
4737 ice->ddma_port = pci_resource_start(pci, 1);
4738 ice->dmapath_port = pci_resource_start(pci, 2);
4739 ice->profi_port = pci_resource_start(pci, 3);
4740 pci_set_master(pci);
4741 pci_write_config_word(ice->pci, 0x40, 0x807f);
4742 pci_write_config_word(ice->pci, 0x42, 0x0006);
4743 snd_ice1712_proc_init(ice);
4744 synchronize_irq();
4745
4746 if ((ice->res_port = request_region(ice->port, 32, "ICE1712 - Controller")) == NULL) {
4747 snd_ice1712_free(ice);
4748 snd_printk("unable to grab ports 0x%lx-0x%lx\n", ice->port, ice->port + 32 - 1);
4749 return -EIO;
4750 }
4751 if ((ice->res_ddma_port = request_region(ice->ddma_port, 16, "ICE1712 - DDMA")) == NULL) {
4752 snd_ice1712_free(ice);
4753 snd_printk("unable to grab ports 0x%lx-0x%lx\n", ice->ddma_port, ice->ddma_port + 16 - 1);
4754 return -EIO;
4755 }
4756 if ((ice->res_dmapath_port = request_region(ice->dmapath_port, 16, "ICE1712 - DMA path")) == NULL) {
4757 snd_ice1712_free(ice);
4758 snd_printk("unable to grab ports 0x%lx-0x%lx\n", ice->dmapath_port, ice->dmapath_port + 16 - 1);
4759 return -EIO;
4760 }
4761 if ((ice->res_profi_port = request_region(ice->profi_port, 64, "ICE1712 - Professional")) == NULL) {
4762 snd_ice1712_free(ice);
4763 snd_printk("unable to grab ports 0x%lx-0x%lx\n", ice->profi_port, ice->profi_port + 16 - 1);
4764 return -EIO;
4765 }
4766 if (request_irq(pci->irq, snd_ice1712_interrupt, SA_INTERRUPT|SA_SHIRQ, "ICE1712", (void *) ice)) {
4767 snd_ice1712_free(ice);
4768 snd_printk("unable to grab IRQ %d\n", pci->irq);
4769 return -EIO;
4770 }
4771 ice->irq = pci->irq;
4772
4773 if (snd_ice1712_read_eeprom(ice) < 0) {
4774 snd_ice1712_free(ice);
4775 return -EIO;
4776 }
4777 if (snd_ice1712_chip_init(ice) < 0) {
4778 snd_ice1712_free(ice);
4779 return -EIO;
4780 }
4781
4782 /* unmask used interrupts */
4783 outb((ice->eeprom.codec & ICE1712_CFG_2xMPU401) == 0 ? ICE1712_IRQ_MPU2 : 0 |
4784 (ice->eeprom.codec & ICE1712_CFG_NO_CON_AC97) ? ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0,
4785 ICEREG(ice, IRQMASK));
4786 outb(0x00, ICEMT(ice, IRQ));
4787
4788 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops)) < 0) {
4789 snd_ice1712_free(ice);
4790 return err;
4791 }
4792
4793 *r_ice1712 = ice;
4794 return 0;
4795}
4796
4797static int __init snd_ice1712_probe(struct pci_dev *pci,
4798 const struct pci_device_id *id)
4799{
4800 static int dev = 0;
4801 snd_card_t *card;
4802 ice1712_t *ice;
4803 int pcm_dev = 0, err;
4804
4805 for ( ; dev < SNDRV_CARDS; dev++) {
4806 if (!snd_enable[dev]) {
4807 dev++;
4808 return -ENOENT;
4809 }
4810 break;
4811 }
4812 if (dev >= SNDRV_CARDS)
4813 return -ENODEV;
4814
4815 card = snd_card_new(snd_index[dev], snd_id[dev], THIS_MODULE, 0);
4816 if (card == NULL)
4817 return -ENOMEM;
4818
4819 if ((err = snd_ice1712_create(card, pci, &ice)) < 0) {
4820 snd_card_free(card);
4821 return err;
4822 }
4823
4824 if ((err = snd_ice1712_pcm_profi(ice, pcm_dev++, NULL)) < 0) {
4825 snd_card_free(card);
4826 return err;
4827 }
4828
4829 if (!(ice->eeprom.codec & ICE1712_CFG_NO_CON_AC97))
4830 if ((err = snd_ice1712_pcm(ice, pcm_dev++, NULL)) < 0) {
4831 snd_card_free(card);
4832 return err;
4833 }
4834
4835 if ((err = snd_ice1712_ac97_mixer(ice)) < 0) {
4836 snd_card_free(card);
4837 return err;
4838 }
4839
4840 if ((err = snd_ice1712_build_controls(ice)) < 0) {
4841 snd_card_free(card);
4842 return err;
4843 }
4844
4845 if (!(ice->eeprom.codec & ICE1712_CFG_NO_CON_AC97))
4846 if ((err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL)) < 0) {
4847 snd_card_free(card);
4848 return err;
4849 }
4850
4851 strcpy(card->driver, "ICE1712");
4852 strcpy(card->shortname, "ICEnsemble ICE1712");
4853
4854 switch (ice->eeprom.subvendor) {
4855 case ICE1712_SUBDEVICE_STDSP24:
4856 strcpy(card->shortname, "Hoontech SoundTrack Audio DSP24");
4857 break;
4858 case ICE1712_SUBDEVICE_DELTA1010:
4859 strcpy(card->shortname, "M Audio Delta 1010");
4860 break;
4861 case ICE1712_SUBDEVICE_DELTADIO2496:
4862 strcpy(card->shortname, "M Audio Delta DiO 2496");
4863 goto __no_mpu401;
4864 case ICE1712_SUBDEVICE_DELTA66:
4865 strcpy(card->shortname, "M Audio Delta 66");
4866 goto __no_mpu401;
4867 case ICE1712_SUBDEVICE_DELTA44:
4868 strcpy(card->shortname, "M Audio Delta 44");
4869 goto __no_mpu401;
4870 case ICE1712_SUBDEVICE_AUDIOPHILE:
4871 strcpy(card->shortname, "M Audio Audiophile 24/96");
4872 break;
4873 case ICE1712_SUBDEVICE_EWX2496:
4874 strcpy(card->shortname, "TerraTec EWX 24/96");
4875 break;
4876 case ICE1712_SUBDEVICE_EWS88MT:
4877 strcpy(card->shortname, "TerraTec EWS 88MT");
4878 break;
4879 case ICE1712_SUBDEVICE_EWS88D:
4880 strcpy(card->shortname, "TerraTec EWS 88D");
4881 break;
4882 }
4883
4884 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
4885 ICEREG(ice, MPU1_CTRL), 1,
4886 ice->irq, 0,
4887 &ice->rmidi[0])) < 0) {
4888 snd_card_free(card);
4889 return err;
4890 }
4891
4892 if (ice->eeprom.codec & ICE1712_CFG_2xMPU401)
4893 if ((err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
4894 ICEREG(ice, MPU2_CTRL), 1,
4895 ice->irq, 0,
4896 &ice->rmidi[1])) < 0) {
4897 snd_card_free(card);
4898 return err;
4899 }
4900
4901 __no_mpu401:
4902 sprintf(card->longname, "%s at 0x%lx, irq %i",
4903 card->shortname, ice->port, ice->irq);
4904
4905 if ((err = snd_card_register(card)) < 0) {
4906 snd_card_free(card);
4907 return err;
4908 }
4909 PCI_SET_DRIVER_DATA(pci, card);
4910 dev++;
4911 return 0;
4912}
4913
4914static void __exit snd_ice1712_remove(struct pci_dev *pci)
4915{
4916 snd_card_free(PCI_GET_DRIVER_DATA(pci));
4917 PCI_SET_DRIVER_DATA(pci, NULL);
4918}
4919
4920#ifdef TARGET_OS2
4921static struct pci_driver driver = {
4922 0,0,"ICE1712",
4923 snd_ice1712_ids,
4924 snd_ice1712_probe,
4925 snd_ice1712_remove,0,0
4926};
4927#else
4928static struct pci_driver driver = {
4929 name: "ICE1712",
4930 id_table: snd_ice1712_ids,
4931 probe: snd_ice1712_probe,
4932 remove: snd_ice1712_remove,
4933};
4934#endif
4935
4936static int __init alsa_card_ice1712_init(void)
4937{
4938 int err;
4939
4940 if ((err = pci_module_init(&driver)) < 0) {
4941#ifdef MODULE
4942 snd_printk("ICE1712 soundcard not found or device busy\n");
4943#endif
4944 return err;
4945 }
4946 return 0;
4947}
4948
4949static void __exit alsa_card_ice1712_exit(void)
4950{
4951 pci_unregister_driver(&driver);
4952}
4953
4954module_init(alsa_card_ice1712_init)
4955module_exit(alsa_card_ice1712_exit)
4956
4957#ifndef MODULE
4958
4959/* format is: snd-card-ice1712=snd_enable,snd_index,snd_id */
4960
4961static int __init alsa_card_ice1712_setup(char *str)
4962{
4963 static unsigned __initdata nr_dev = 0;
4964
4965 if (nr_dev >= SNDRV_CARDS)
4966 return 0;
4967 (void)(get_option(&str,&snd_enable[nr_dev]) == 2 &&
4968 get_option(&str,&snd_index[nr_dev]) == 2 &&
4969 get_id(&str,&snd_id[nr_dev]) == 2);
4970 nr_dev++;
4971 return 1;
4972}
4973
4974__setup("snd-card-ice1712=", alsa_card_ice1712_setup);
4975
4976#endif /* ifndef MODULE */
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