source: GPL/alsa-kernel/include/sound/hal2.h@ 1

Last change on this file since 1 was 1, checked in by vladest, 20 years ago

initial import
File size: 14.1 KB
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1#ifndef __HAL2_H
2#define __HAL2_H
3
4/*
5 * Global structures used for HAL2 part of ALSA driver
6 * Copyright (c) by Ulf Carlsson <ulfc@bun.falkenberg.se>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include "pcm.h"
26#include "rawmidi.h"
27#include "timer.h"
28
29#include <asm/addrspace.h>
30#include <asm/sgi/sgihpc.h>
31
32/* We can possibly use the addresses in hpc_regs instead of giving the adress in
33 * an absolute way. This will at least save us if someone breaks the hpc_regs
34 * structure again :-)
35 */
36
37#define H2_HAL2_BASE (HPC3_CHIP0_PBASE + 0x58000)
38#define H2_CTL_PIO (H2_HAL2_BASE + 0 * 0x400)
39#define H2_AES_PIO (H2_HAL2_BASE + 1 * 0x400)
40#define H2_VOL_PIO (H2_HAL2_BASE + 2 * 0x400)
41#define H2_SYN_PIO (H2_HAL2_BASE + 3 * 0x400)
42
43/* Indirect status register */
44
45#define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */
46#define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */
47#define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */
48#define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
49#define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
50
51 /* Revision register */
52
53#define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */
54#define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */
55#define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */
56#define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
57
58/* Indirect address register */
59
60/*
61 * Address of indirect internal register to be accessed. A write to this
62 * register initiates read or write access to the indirect registers in the
63 * HAL2. Note that there af four indirect data registers for write access to
64 * registers larger than 16 byte.
65 */
66
67#define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */
68 /* block the register resides in */
69 /* 1=DMA Port */
70 /* 9=Global DMA Control */
71 /* 2=Bresenham */
72 /* 3=Unix Timer */
73#define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */
74 /* blockin which the indirect */
75 /* register resides */
76 /* If IAR_TYPE_M=DMA Port: */
77 /* 1=Synth In */
78 /* 2=AES In */
79 /* 3=AES Out */
80 /* 4=DAC Out */
81 /* 5=ADC Out */
82 /* 6=Synth Control */
83 /* If IAR_TYPE_M=Global DMA Control: */
84 /* 1=Control */
85 /* If IAR_TYPE_M=Bresenham: */
86 /* 1=Bresenham Clock Gen 1 */
87 /* 2=Bresenham Clock Gen 2 */
88 /* 3=Bresenham Clock Gen 3 */
89 /* If IAR_TYPE_M=Unix Timer: */
90 /* 1=Unix Timer */
91#define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
92#define H2_IAR_PARAM 0x000C /* Parameter Select */
93#define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */
94 /* 00:word0 */
95 /* 01:word1 */
96 /* 10:word2 */
97 /* 11:word3 */
98/*
99 * HAL2 internal addressing
100 *
101 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
102 * Indirect Data registers. Write the address to the Indirect Address register
103 * to transfer the data.
104 *
105 * We define the H2IR_* to the read address and H2IW_* to the write address and
106 * H2I_* to be fields in whatever register is referred to.
107 *
108 * When we write to indirect registers which are larger than one word (16 bit)
109 * we have to fill more than one indirect register before writing. When we read
110 * back however we have to read several times, each time with different Read
111 * Back Indexes (there are defs for doing this easily).
112 */
113
114/*
115 * Relay Control
116 */
117#define H2I_RELAY_C 0x9100
118#define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */
119
120/* DMA port enable */
121
122#define H2I_DMA_PORT_EN 0x9104
123#define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
124#define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
125#define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
126#define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */
127#define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */
128
129#define H2I_DMA_END 0x9108 /* global dma endian select */
130#define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */
131#define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */
132#define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */
133#define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */
134#define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */
135 /* 0=b_end 1=l_end */
136
137#define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
138
139#define H2I_SYNTH_C 0x1104 /* Synth DMA control */
140
141#define H2I_AESRX_C 0x1204 /* AES RX dma control */
142#define H2I_AESRX_C_TS_EN 0x20 /* timestamp enable */
143#define H2I_AESRX_C_TS_FMT 0x40 /* timestamp format */
144#define H2I_AESRX_C_NAUDIO 0x80 /* PBUS DMA data format */
145
146/* AESRX CTL, 16 bit */
147
148#define H2I_AESTX_C 0x1304 /* AES TX DMA control */
149#define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
150#define H2I_AESTX_C_CLKID_M 0x18
151#define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
152#define H2I_AESTX_C_DATAT_M 0x300
153
154/* DAC CTL1, 16 bit */
155
156#define H2I_DAC_C1 0x1404 /* DAC dma control */
157#define H2I_DAC_C1_DMA_SHIFT 0 /* DMA channel */
158#define H2I_DAC_C1_DMA_M 0x7
159#define H2I_DAC_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
160#define H2I_DAC_C1_CLKID_M 0x18
161#define H2I_DAC_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
162#define H2I_DAC_C1_DATAT_M 0x300
163
164/* DAC CTL2, 32 bit */
165
166#define H2I_DAC_C2 0x1408
167#define H2I_DAC_C2_R_GAIN_SHIFT 0 /* right a/d input gain */
168#define H2I_DAC_C2_R_GAIN_M 0xf
169#define H2I_DAC_C2_L_GAIN_SHIFT 4 /* left a/d input gain */
170#define H2I_DAC_C2_L_GAIN_M 0xf0
171#define H2I_DAC_C2_R_SEL 0x100 /* right input select */
172#define H2I_DAC_C2_L_SEL 0x200 /* left input select */
173#define H2I_DAC_C2_MUTE 0x400 /* mute */
174#define H2I_DAC_C2_DO1 0x10000 /* digital output port bit 0 */
175#define H2I_DAC_C2_DO2 0x20000 /* digital output port bit 1 */
176#define H2I_DAC_C2_R_ATT_SHIFT 18 /* right a/d output - */
177#define H2I_DAC_C2_R_ATT_M 0x7c0000 /* attenuation */
178#define H2I_DAC_C2_L_ATT_SHIFT 23 /* left a/d output - */
179#define H2I_DAC_C2_L_ATT_M 0x0000f80 /* attenuation */
180
181/* ADC CTL1, 16 bit */
182
183#define H2I_ADC_C1 0x1504 /* DAC dma control */
184#define H2I_ADC_C1_DMA_SHIFT 0 /* DMA channel */
185#define H2I_ADC_C1_DMA_M 0x7
186#define H2I_ADC_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
187#define H2I_ADC_C1_CLKID_M 0x18
188#define H2I_ADC_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
189#define H2I_ADC_C1_DATAT_M 0x300
190
191/* ADC CTL2, 32 bit */
192
193#define H2I_ADC_C2 0x1508
194#define H2I_ADC_C2_RGAIN_SHIFT 0 /* right a/d input gain */
195#define H2I_ADC_C2_R_GAIN_M 0xf
196#define H2I_ADC_C2_L_GAIN_SHIFT 4 /* left a/d input gain */
197#define H2I_ADC_C2_L_GAIN_M 0xf0
198#define H2I_ADC_C2_R_SEL 0x100 /* right input select */
199#define H2I_ADC_C2_L_SEL 0x200 /* left input select */
200#define H2I_ADC_C2_MUTE 0x400 /* mute */
201#define H2I_ADC_C2_DO1 0x10000 /* digital output port bit 0 */
202#define H2I_ADC_C2_DO2 0x20000 /* digital output port bit 1 */
203#define H2I_ADC_C2_R_ATT_SHIFT 18 /* right a/d output - */
204#define H2I_ADC_C2_R_ATT_M 0x7c0000 /* attenuation */
205#define H2I_ADC_C2_L_ATT_SHIFT 23 /* left a/d output - */
206#define H2I_ADC_C2_L_ATT_M 0x0000f80 /* attenuation */
207
208
209#define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
210
211/* Clock generator 1 CTL 1, 16 bit */
212
213#define H2I_BRES1_C1 0x2104
214#define H2I_BRES1_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
215#define H2I_BRES1_C1_M 0x03
216
217/* Clock generator 1 CTL 2, 32 bit */
218
219#define H2I_BRES1_C2 0x2108
220#define H2I_BRES1_C2_INC_SHIFT 0 /* increment value */
221#define H2I_BRES1_C2_INC_M 0xffff
222#define H2I_BRES1_C2_MOD_SHIFT 16 /* modcontrol value */
223#define H2I_BRES1_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
224
225/* Clock generator 2 CTL 1, 16 bit */
226
227#define H2I_BRES2_C1 0x2204
228#define H2I_BRES2_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
229#define H2I_BRES2_C1_M 0x03
230
231/* Clock generator 2 CTL 2, 32 bit */
232
233#define H2I_BRES2_C2 0x2208
234#define H2I_BRES2_C2_INC_SHIFT 0 /* increment value */
235#define H2I_BRES2_C2_INC_M 0xffff
236#define H2I_BRES2_C2_MOD_SHIFT 16 /* modcontrol value */
237#define H2I_BRES2_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
238
239/* Clock generator 3 CTL 1, 16 bit */
240
241#define H2I_BRES3_C1 0x2304
242#define H2I_BRES3_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
243#define H2I_BRES3_C1_M 0x03
244
245/* Clock generator 3 CTL 2, 32 bit */
246
247#define H2I_BRES3_C2 0x2308
248#define H2I_BRES3_C2_INC_SHIFT 0 /* increment value */
249#define H2I_BRES3_C2_INC_M 0xffff
250#define H2I_BRES3_C2_MOD_SHIFT 16 /* modcontrol value */
251#define H2I_BRES3_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
252
253/* Unix timer, 64 bit */
254
255#define H2I_UTIME 0x3104
256#define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */
257#define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */
258#define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */
259#define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */
260#define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */
261
262typedef volatile unsigned long snd_hal2_reg_t;
263
264typedef struct _snd_hal2_ctl_regs snd_hal2_ctl_regs_t;
265
266struct _snd_hal2_ctl_regs {
267 snd_hal2_reg_t _unused0[4];
268 snd_hal2_reg_t isr; /* 0x10 Status Register */
269 snd_hal2_reg_t _unused1[3];
270 snd_hal2_reg_t rev; /* 0x20 Revision Register */
271 snd_hal2_reg_t _unused2[3];
272 snd_hal2_reg_t iar; /* 0x30 Indirect Address Register */
273 snd_hal2_reg_t _unused3[3];
274 snd_hal2_reg_t idr0; /* 0x40 Indirect Data Register 0 */
275 snd_hal2_reg_t _unused4[3];
276 snd_hal2_reg_t idr1; /* 0x50 Indirect Data Register 1 */
277 snd_hal2_reg_t _unused5[3];
278 snd_hal2_reg_t idr2; /* 0x60 Indirect Data Register 2 */
279 snd_hal2_reg_t _unused6[3];
280 snd_hal2_reg_t idr3; /* 0x70 Indirect Data Register 3 */
281};
282
283typedef struct _snd_hal2_aes_regs snd_hal2_aes_regs_t;
284
285struct _snd_hal2_aes_regs {
286 snd_hal2_reg_t rx_stat[2]; /* Status registers */
287 snd_hal2_reg_t rx_cr[2]; /* Control registers */
288 snd_hal2_reg_t rx_ud[4]; /* User data window */
289 snd_hal2_reg_t rx_st[24]; /* Channel status data */
290
291 snd_hal2_reg_t tx_stat[1]; /* Status register */
292 snd_hal2_reg_t tx_cr[3]; /* Control registers */
293 snd_hal2_reg_t tx_ud[4]; /* User data window */
294 snd_hal2_reg_t tx_st[24]; /* Channel status data */
295};
296
297typedef struct _snd_hal2_vol_regs snd_hal2_vol_regs_t;
298
299struct _snd_hal2_vol_regs {
300 snd_hal2_reg_t right; /* 0x00 Right volume */
301 snd_hal2_reg_t left; /* 0x04 Left volume */
302};
303
304typedef struct _snd_hal2_syn_regs snd_hal2_syn_regs_t;
305
306struct _snd_hal2_syn_regs {
307 snd_hal2_reg_t _unused0[2];
308 snd_hal2_reg_t page; /* DOC Page register */
309 snd_hal2_reg_t regsel; /* DOC Register selection */
310 snd_hal2_reg_t dlow; /* DOC Data low */
311 snd_hal2_reg_t dhigh; /* DOC Data high */
312 snd_hal2_reg_t irq; /* IRQ Status */
313 snd_hal2_reg_t dram; /* DRAM Access */
314};
315
316struct _snd_hal2_card;
317typedef struct _snd_hal2_card snd_hal2_card_t;
318
319/* HAL2 specific structure */
320
321typedef struct _snd_hal2_ring snd_hal2_ring_t;
322
323struct _snd_hal2_ring {
324 volatile struct hpc_dma_desc desc;
325 unsigned long _padding; /* 8 byte aligned */
326};
327
328typedef struct _snd_hal2_pbus snd_hal2_pbus_t;
329
330struct _snd_hal2_pbus {
331 struct hpc3_pbus_dmacregs *pbus;
332 int pbusnr;
333 unsigned long fifobeg;
334 unsigned long fifoend;
335 unsigned long highwater;
336
337 unsigned long ctrl; /* Current state of pbus->pbdma_ctrl */
338};
339
340typedef struct _snd_hal2_codec snd_hal2_codec_t;
341
342struct _snd_hal2_codec {
343 snd_dma_t *dmaptr; /* DMA1 pointer */
344 snd_hal2_ring_t *ringbuf; /* DMA descirptors */
345 snd_hal2_pbus_t pbus;
346 unsigned short blocks;
347};
348
349struct _snd_hal2 {
350 snd_irq_t *irqptr; /* IRQ pointer */
351 snd_hal2_ctl_regs_t *ctl_regs; /* HAL2 ctl registers */
352 snd_hal2_aes_regs_t *aes_regs; /* HAL2 vol registers */
353 snd_hal2_vol_regs_t *vol_regs; /* HAL2 aes registers */
354 snd_hal2_syn_regs_t *syn_regs; /* HAL2 syn registers */
355
356 unsigned int master; /* Master frequency */
357 unsigned short mod; /* MOD value */
358 unsigned short inc; /* INC value */
359
360 snd_hal2_codec_t dac;
361 snd_hal2_codec_t adc;
362};
363
364/* main structure for HAL2 card */
365
366struct _snd_hal2_card {
367 snd_card_t *card;
368 snd_pcm_t *pcm;
369 snd_rawmidi_t *midi_uart;
370
371 snd_pcm_substream_t *playback_substream;
372 snd_pcm_substream_t *capture_substream;
373 snd_pcm1_substream_t *playback_substream1;
374 snd_pcm1_substream_t *capture_substream1;
375
376 struct _snd_hal2 hal2; /* HAL2 specific variables */
377
378 int usecount;
379};
380
381extern void snd_hal2_isr_write(snd_hal2_card_t *hal2, unsigned short val);
382extern unsigned short snd_hal2_isr_look(snd_hal2_card_t *hal2);
383extern unsigned short snd_hal2_rev_look(snd_hal2_card_t *hal2);
384
385extern void snd_hal2_i_write16(snd_hal2_card_t *hal2, unsigned short addr, unsigned short val);
386extern void snd_hal2_i_write32(snd_hal2_card_t *hal2, unsigned short addr, unsigned long val);
387
388extern unsigned short snd_hal2_i_look16(snd_hal2_card_t *hal2, unsigned short addr);
389extern unsigned long snd_hal2_i_look32(snd_hal2_card_t *hal2, unsigned short addr);
390
391extern snd_pcm_t *snd_hal2_pcm_new_device(snd_hal2_card_t *hal2);
392extern void snd_hal2_dump_regs(snd_hal2_card_t *hal2);
393extern snd_pcm_t *snd_hal2_new_device(snd_card_t *card,
394 snd_irq_t *irqnum,
395 snd_dma_t *dma1ptr,
396 snd_dma_t *dma2ptr,
397 snd_hal2_ctl_regs_t *ctl_regs,
398 snd_hal2_aes_regs_t *aes_regs,
399 snd_hal2_vol_regs_t *vol_regs,
400 snd_hal2_syn_regs_t *syn_regs);
401extern void snd_hal2_interrupt(snd_hal2_card_t * hal2);
402
403extern snd_pcm_t *snd_hal2_pcm(snd_hal2_card_t *hal2);
404
405#endif /* __HAL2_H */
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