source: GPL/alsa-kernel/include/sound/cs4231.h@ 1

Last change on this file since 1 was 1, checked in by vladest, 20 years ago

initial import
File size: 14.4 KB
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1#ifndef __CS4231_H
2#define __CS4231_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Definitions for CS4231 & InterWave chips & compatible chips
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include "control.h"
26#include "pcm.h"
27#include "timer.h"
28
29/* IO ports */
30
31#define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
32
33#define c_d_c_CS4231REGSEL 0
34#define c_d_c_CS4231REG 1
35#define c_d_c_CS4231STATUS 2
36#define c_d_c_CS4231PIO 3
37
38/* codec registers */
39
40#define CS4231_LEFT_INPUT 0x00 /* left input control */
41#define CS4231_RIGHT_INPUT 0x01 /* right input control */
42#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
43#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
44#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
45#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
46#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
47#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
48#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
49#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
50#define CS4231_PIN_CTRL 0x0a /* pin control */
51#define CS4231_TEST_INIT 0x0b /* test and initialization */
52#define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
53#define CS4231_LOOPBACK 0x0d /* loopback control */
54#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
55#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
56#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
57#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
58#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
59#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
60#define CS4231_TIMER_LOW 0x14 /* timer low byte */
61#define CS4231_TIMER_HIGH 0x15 /* timer high byte */
62#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
63#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
64#define CS4236_EXT_REG 0x17 /* extended register access */
65#define CS4231_IRQ_STATUS 0x18 /* irq status register */
66#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
67#define CS4231_VERSION 0x19 /* CS4231(A) - version values */
68#define CS4231_MONO_CTRL 0x1a /* mono input/output control */
69#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
70#define CS4235_LEFT_MASTER 0x1b /* left master output control */
71#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
72#define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
73#define CS4235_RIGHT_MASTER 0x1d /* right master output control */
74#define CS4231_REC_UPR_CNT 0x1e /* record upper count */
75#define CS4231_REC_LWR_CNT 0x1f /* record lower count */
76
77/* definitions for codec register select port - CODECP( REGSEL ) */
78
79#define CS4231_INIT 0x80 /* CODEC is initializing */
80#define CS4231_MCE 0x40 /* mode change enable */
81#define CS4231_TRD 0x20 /* transfer request disable */
82
83/* definitions for codec status register - CODECP( STATUS ) */
84
85#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
86
87/* definitions for codec irq status */
88
89#define CS4231_PLAYBACK_IRQ 0x10
90#define CS4231_RECORD_IRQ 0x20
91#define CS4231_TIMER_IRQ 0x40
92#define CS4231_ALL_IRQS 0x70
93#define CS4231_REC_UNDERRUN 0x08
94#define CS4231_REC_OVERRUN 0x04
95#define CS4231_PLY_OVERRUN 0x02
96#define CS4231_PLY_UNDERRUN 0x01
97
98/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
99
100#define CS4231_ENABLE_MIC_GAIN 0x20
101
102#define CS4231_MIXS_LINE 0x00
103#define CS4231_MIXS_AUX1 0x40
104#define CS4231_MIXS_MIC 0x80
105#define CS4231_MIXS_ALL 0xc0
106
107/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
108
109#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
110#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
111#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
112#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
113#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
114#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
115#define CS4231_STEREO 0x10 /* stereo mode */
116/* bits 3-1 define frequency divisor */
117#define CS4231_XTAL1 0x00 /* 24.576 crystal */
118#define CS4231_XTAL2 0x01 /* 16.9344 crystal */
119
120/* definitions for interface control register - CS4231_IFACE_CTRL */
121
122#define CS4231_RECORD_PIO 0x80 /* record PIO enable */
123#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
124#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
125#define CS4231_AUTOCALIB 0x08 /* auto calibrate */
126#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
127#define CS4231_RECORD_ENABLE 0x02 /* record enable */
128#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
129
130/* definitions for pin control register - CS4231_PIN_CTRL */
131
132#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
133#define CS4231_XCTL1 0x40 /* external control #1 */
134#define CS4231_XCTL0 0x80 /* external control #0 */
135
136/* definitions for test and init register - CS4231_TEST_INIT */
137
138#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
139#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
140
141/* definitions for misc control register - CS4231_MISC_INFO */
142
143#define CS4231_MODE2 0x40 /* MODE 2 */
144#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
145#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
146
147/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
148
149#define CS4231_DACZ 0x01 /* zero DAC when underrun */
150#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
151#define CS4231_OLB 0x80 /* output level bit */
152
153/* definitions for Extended Registers - CS4236+ */
154
155#define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))
156#define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)
157
158#define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */
159#define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */
160#define CS4236_LEFT_MIC 0x28 /* left MIC volume */
161#define CS4236_RIGHT_MIC 0x38 /* right MIC volume */
162#define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */
163#define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */
164#define CS4236_LEFT_FM 0x68 /* left FM volume */
165#define CS4236_RIGHT_FM 0x78 /* right FM volume */
166#define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */
167#define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */
168#define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */
169#define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */
170#define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */
171#define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */
172#define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */
173#define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */
174#define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */
175#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */
176#define CS4236_VERSION 0x9c /* chip version and ID */
177
178/* defines for codec.mode */
179
180#define CS4231_MODE_NONE 0x0000
181#define CS4231_MODE_PLAY 0x0001
182#define CS4231_MODE_RECORD 0x0002
183#define CS4231_MODE_TIMER 0x0004
184#define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
185
186/* defines for codec.hardware */
187
188#define CS4231_HW_DETECT 0x0000 /* let CS4231 driver detect chip */
189#define CS4231_HW_DETECT3 0x0001 /* allow mode 3 */
190#define CS4231_HW_TYPE_MASK 0xff00 /* type mask */
191#define CS4231_HW_CS4231_MASK 0x0100 /* CS4231 serie */
192#define CS4231_HW_CS4231 0x0100 /* CS4231 chip */
193#define CS4231_HW_CS4231A 0x0101 /* CS4231A chip */
194#define CS4231_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */
195#define CS4231_HW_CS4232 0x0200 /* CS4232 */
196#define CS4231_HW_CS4232A 0x0201 /* CS4232A */
197#define CS4231_HW_CS4236 0x0202 /* CS4236 */
198#define CS4231_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */
199#define CS4231_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */
200#define CS4231_HW_CS4236B 0x0401 /* CS4236B */
201#define CS4231_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */
202#define CS4231_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */
203#define CS4231_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */
204/* compatible, but clones */
205#define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */
206#define CS4231_HW_OPL3SA2 0x1001 /* OPL3-SA2 chip */
207
208/* defines for codec.hwshare */
209#define CS4231_HWSHARE_IRQ (1<<0)
210#define CS4231_HWSHARE_DMA1 (1<<1)
211#define CS4231_HWSHARE_DMA2 (1<<2)
212
213typedef struct _snd_cs4231 cs4231_t;
214
215struct _snd_cs4231 {
216 unsigned long port; /* base i/o port */
217 struct resource *res_port;
218 unsigned long cport; /* control base i/o port (CS4236) */
219 struct resource *res_cport;
220 int irq; /* IRQ line */
221 int dma1; /* playback DMA */
222 int dma2; /* record DMA */
223 unsigned short version; /* version of CODEC chip */
224 unsigned short mode; /* see to CS4231_MODE_XXXX */
225 unsigned short hardware; /* see to CS4231_HW_XXXX */
226 unsigned short hwshare; /* shared resources */
227 unsigned short single_dma:1; /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
228
229 snd_card_t *card;
230 snd_pcm_t *pcm;
231 snd_pcm_substream_t *playback_substream;
232 snd_pcm_substream_t *capture_substream;
233 snd_timer_t *timer;
234
235 unsigned char image[32]; /* registers image */
236 unsigned char eimage[32]; /* extended registers image */
237 unsigned char cimage[16]; /* control registers image */
238 int mce_bit;
239 int calibrate_mute;
240 int sw_3d_bit;
241 unsigned int p_dma_size;
242 unsigned int c_dma_size;
243
244 spinlock_t reg_lock;
245 struct semaphore mce_mutex;
246 struct semaphore open_mutex;
247
248 int (*rate_constraint) (snd_pcm_runtime_t *runtime);
249 void (*set_playback_format) (cs4231_t *chip, snd_pcm_hw_params_t *hw_params, unsigned char pdfr);
250 void (*set_capture_format) (cs4231_t *chip, snd_pcm_hw_params_t *hw_params, unsigned char cdfr);
251#ifdef CONFIG_PM
252 void (*suspend) (cs4231_t *chip);
253 void (*resume) (cs4231_t *chip);
254#endif
255 void *dma_private_data;
256 int (*claim_dma) (cs4231_t *chip, void *dma_private_data, int dma);
257 int (*release_dma) (cs4231_t *chip, void *dma_private_data, int dma);
258};
259
260/* exported functions */
261
262void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char val);
263unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg);
264void snd_cs4231_outm(cs4231_t *chip, unsigned char reg, unsigned char mask, unsigned char val);
265void snd_cs4236_ext_out(cs4231_t *chip, unsigned char reg, unsigned char val);
266unsigned char snd_cs4236_ext_in(cs4231_t *chip, unsigned char reg);
267void snd_cs4231_mce_up(cs4231_t *chip);
268void snd_cs4231_mce_down(cs4231_t *chip);
269
270void snd_cs4231_interrupt(int irq, void *dev_id, struct pt_regs *regs);
271
272const char *snd_cs4231_chip_id(cs4231_t *chip);
273
274int snd_cs4231_create(snd_card_t * card,
275 unsigned long port,
276 unsigned long cport,
277 int irq, int dma1, int dma2,
278 unsigned short hardware,
279 unsigned short hwshare,
280 cs4231_t ** rchip);
281int snd_cs4231_pcm(cs4231_t * chip, int device, snd_pcm_t **rpcm);
282int snd_cs4231_timer(cs4231_t * chip, int device, snd_timer_t **rtimer);
283int snd_cs4231_mixer(cs4231_t * chip);
284
285int snd_cs4236_create(snd_card_t * card,
286 unsigned long port,
287 unsigned long cport,
288 int irq, int dma1, int dma2,
289 unsigned short hardware,
290 unsigned short hwshare,
291 cs4231_t ** rchip);
292int snd_cs4236_pcm(cs4231_t * chip, int device, snd_pcm_t **rpcm);
293int snd_cs4236_mixer(cs4231_t * chip);
294
295/*
296 * mixer library
297 */
298
299#ifdef TARGET_OS2
300#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
301{ SNDRV_CTL_ELEM_IFACE_MIXER, 0,0, xname, xindex, \
302 0, 0, snd_cs4231_info_single, \
303 snd_cs4231_get_single, snd_cs4231_put_single, \
304 reg | (shift << 8) | (mask << 16) | (invert << 24) }
305#else
306#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
307{ iface: SNDRV_CTL_ELEM_IFACE_MIXER, name: xname, index: xindex, \
308 info: snd_cs4231_info_single, \
309 get: snd_cs4231_get_single, put: snd_cs4231_put_single, \
310 private_value: reg | (shift << 8) | (mask << 16) | (invert << 24) }
311#endif
312
313int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
314int snd_cs4231_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
315int snd_cs4231_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
316
317#ifdef TARGET_OS2
318#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
319{ SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, xindex, \
320 0, 0, snd_cs4231_info_double, \
321 snd_cs4231_get_double, snd_cs4231_put_double, \
322 left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
323#else
324#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
325{ iface: SNDRV_CTL_ELEM_IFACE_MIXER, name: xname, index: xindex, \
326 info: snd_cs4231_info_double, \
327 get: snd_cs4231_get_double, put: snd_cs4231_put_double, \
328 private_value: left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
329#endif
330
331int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
332int snd_cs4231_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
333int snd_cs4231_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
334
335#ifdef CONFIG_SND_DEBUG
336void snd_cs4231_debug(cs4231_t *chip);
337#endif
338
339#endif /* __CS4231_H */
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