source: GPL/alsa-kernel/include/sound/ad1848.h@ 1

Last change on this file since 1 was 1, checked in by vladest, 20 years ago

initial import
File size: 8.0 KB
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1#ifndef __AD1848_H
2#define __AD1848_H
3
4/*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Definitions for AD1847/AD1848/CS4248 chips
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include "control.h"
26#include "pcm.h"
27
28/* IO ports */
29
30#define AD1848P( codec, x ) ( (chip) -> port + c_d_c_AD1848##x )
31
32#define c_d_c_AD1848REGSEL 0
33#define c_d_c_AD1848REG 1
34#define c_d_c_AD1848STATUS 2
35#define c_d_c_AD1848PIO 3
36
37/* codec registers */
38
39#define AD1848_LEFT_INPUT 0x00 /* left input control */
40#define AD1848_RIGHT_INPUT 0x01 /* right input control */
41#define AD1848_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
42#define AD1848_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
43#define AD1848_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
44#define AD1848_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
45#define AD1848_LEFT_OUTPUT 0x06 /* left output control register */
46#define AD1848_RIGHT_OUTPUT 0x07 /* right output control register */
47#define AD1848_DATA_FORMAT 0x08 /* clock and data format - playback/capture - bits 7-0 MCE */
48#define AD1848_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
49#define AD1848_PIN_CTRL 0x0a /* pin control */
50#define AD1848_TEST_INIT 0x0b /* test and initialization */
51#define AD1848_MISC_INFO 0x0c /* miscellaneaous information */
52#define AD1848_LOOPBACK 0x0d /* loopback control */
53#define AD1848_DATA_UPR_CNT 0x0e /* playback/capture upper base count */
54#define AD1848_DATA_LWR_CNT 0x0f /* playback/capture lower base count */
55
56/* definitions for codec register select port - CODECP( REGSEL ) */
57
58#define AD1848_INIT 0x80 /* CODEC is initializing */
59#define AD1848_MCE 0x40 /* mode change enable */
60#define AD1848_TRD 0x20 /* transfer request disable */
61
62/* definitions for codec status register - CODECP( STATUS ) */
63
64#define AD1848_GLOBALIRQ 0x01 /* IRQ is active */
65
66/* definitions for AD1848_LEFT_INPUT and AD1848_RIGHT_INPUT registers */
67
68#define AD1848_ENABLE_MIC_GAIN 0x20
69
70#define AD1848_MIXS_LINE1 0x00
71#define AD1848_MIXS_AUX1 0x40
72#define AD1848_MIXS_LINE2 0x80
73#define AD1848_MIXS_ALL 0xc0
74
75/* definitions for clock and data format register - AD1848_PLAYBK_FORMAT */
76
77#define AD1848_LINEAR_8 0x00 /* 8-bit unsigned data */
78#define AD1848_ALAW_8 0x60 /* 8-bit A-law companded */
79#define AD1848_ULAW_8 0x20 /* 8-bit U-law companded */
80#define AD1848_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
81#define AD1848_STEREO 0x10 /* stereo mode */
82/* bits 3-1 define frequency divisor */
83#define AD1848_XTAL1 0x00 /* 24.576 crystal */
84#define AD1848_XTAL2 0x01 /* 16.9344 crystal */
85
86/* definitions for interface control register - AD1848_IFACE_CTRL */
87
88#define AD1848_CAPTURE_PIO 0x80 /* capture PIO enable */
89#define AD1848_PLAYBACK_PIO 0x40 /* playback PIO enable */
90#define AD1848_CALIB_MODE 0x18 /* calibration mode bits */
91#define AD1848_AUTOCALIB 0x08 /* auto calibrate */
92#define AD1848_SINGLE_DMA 0x04 /* use single DMA channel */
93#define AD1848_CAPTURE_ENABLE 0x02 /* capture enable */
94#define AD1848_PLAYBACK_ENABLE 0x01 /* playback enable */
95
96/* definitions for pin control register - AD1848_PIN_CTRL */
97
98#define AD1848_IRQ_ENABLE 0x02 /* enable IRQ */
99#define AD1848_XCTL1 0x40 /* external control #1 */
100#define AD1848_XCTL0 0x80 /* external control #0 */
101
102/* definitions for test and init register - AD1848_TEST_INIT */
103
104#define AD1848_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
105#define AD1848_DMA_REQUEST 0x10 /* DMA request in progress */
106
107/* defines for codec.mode */
108
109#define AD1848_MODE_NONE 0x0000
110#define AD1848_MODE_PLAY 0x0001
111#define AD1848_MODE_CAPTURE 0x0002
112#define AD1848_MODE_TIMER 0x0004
113#define AD1848_MODE_OPEN (AD1848_MODE_PLAY|AD1848_MODE_CAPTURE|AD1848_MODE_TIMER)
114
115/* defines for codec.hardware */
116
117#define AD1848_HW_DETECT 0x0000 /* let AD1848 driver detect chip */
118#define AD1848_HW_AD1847 0x0001 /* AD1847 chip */
119#define AD1848_HW_AD1848 0x0002 /* AD1848 chip */
120#define AD1848_HW_CS4248 0x0003 /* CS4248 chip */
121#define AD1848_HW_CMI8330 0x0004 /* CMI8330 chip */
122
123struct _snd_ad1848 {
124 unsigned long port; /* i/o port */
125 struct resource *res_port;
126 int irq; /* IRQ line */
127 int dma; /* data DMA */
128 unsigned short version; /* version of CODEC chip */
129 unsigned short mode; /* see to AD1848_MODE_XXXX */
130 unsigned short hardware; /* see to AD1848_HW_XXXX */
131 unsigned short single_dma:1; /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
132
133 snd_pcm_t *pcm;
134 snd_pcm_substream_t *playback_substream;
135 snd_pcm_substream_t *capture_substream;
136 snd_card_t *card;
137
138 unsigned char image[32]; /* SGalaxy needs an access to extended registers */
139 int mce_bit;
140 int calibrate_mute;
141 int dma_size;
142 int thinkpad_flag; /* Thinkpad CS4248 needs some extra help */
143
144 spinlock_t reg_lock;
145 struct semaphore open_mutex;
146};
147
148typedef struct _snd_ad1848 ad1848_t;
149
150/* exported functions */
151
152void snd_ad1848_out(ad1848_t *chip, unsigned char reg, unsigned char value);
153
154int snd_ad1848_create(snd_card_t * card,
155 unsigned long port,
156 int irq, int dma,
157 unsigned short hardware,
158 ad1848_t ** chip);
159
160int snd_ad1848_pcm(ad1848_t * chip, int device, snd_pcm_t **rpcm);
161int snd_ad1848_mixer(ad1848_t * chip);
162void snd_ad1848_interrupt(int irq, void *dev_id, struct pt_regs *regs);
163
164#ifdef TARGET_OS2
165#define AD1848_SINGLE(xname, xindex, reg, shift, mask, invert) \
166{ SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, xindex, \
167 0, 0, snd_ad1848_info_single, \
168 snd_ad1848_get_single, snd_ad1848_put_single, \
169 reg | (shift << 8) | (mask << 16) | (invert << 24) }
170#else
171#define AD1848_SINGLE(xname, xindex, reg, shift, mask, invert) \
172{ iface: SNDRV_CTL_ELEM_IFACE_MIXER, name: xname, index: xindex, \
173 info: snd_ad1848_info_single, \
174 get: snd_ad1848_get_single, put: snd_ad1848_put_single, \
175 private_value: reg | (shift << 8) | (mask << 16) | (invert << 24) }
176#endif
177
178int snd_ad1848_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
179int snd_ad1848_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
180int snd_ad1848_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
181
182#ifdef TARGET_OS2
183#define AD1848_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
184{ SNDRV_CTL_ELEM_IFACE_MIXER, 0, 0, xname, xindex, \
185 0, 0, snd_ad1848_info_double, \
186 snd_ad1848_get_double, snd_ad1848_put_double, \
187 left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
188#else
189#define AD1848_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
190{ iface: SNDRV_CTL_ELEM_IFACE_MIXER, name: xname, index: xindex, \
191 info: snd_ad1848_info_double, \
192 get: snd_ad1848_get_double, put: snd_ad1848_put_double, \
193 private_value: left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
194#endif
195
196int snd_ad1848_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
197int snd_ad1848_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
198int snd_ad1848_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
199
200#ifdef CONFIG_SND_DEBUG
201void snd_ad1848_debug(ad1848_t *chip);
202#endif
203
204#endif /* __AD1848_H */
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