| 1 | /*
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| 2 | ** THIS SOFTWARE IS SUBJECT TO COPYRIGHT PROTECTION AND IS OFFERED ONLY
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| 3 | ** PURSUANT TO THE 3DFX GLIDE GENERAL PUBLIC LICENSE. THERE IS NO RIGHT
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| 4 | ** TO USE THE GLIDE TRADEMARK WITHOUT PRIOR WRITTEN PERMISSION OF 3DFX
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| 5 | ** INTERACTIVE, INC. A COPY OF THIS LICENSE MAY BE OBTAINED FROM THE
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| 6 | ** DISTRIBUTOR OR BY CONTACTING 3DFX INTERACTIVE INC(info@3dfx.com).
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| 7 | ** THIS PROGRAM IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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| 8 | ** EXPRESSED OR IMPLIED. SEE THE 3DFX GLIDE GENERAL PUBLIC LICENSE FOR A
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| 9 | ** FULL TEXT OF THE NON-WARRANTY PROVISIONS.
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| 10 | **
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| 11 | ** USE, DUPLICATION OR DISCLOSURE BY THE GOVERNMENT IS SUBJECT TO
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| 12 | ** RESTRICTIONS AS SET FORTH IN SUBDIVISION (C)(1)(II) OF THE RIGHTS IN
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| 13 | ** TECHNICAL DATA AND COMPUTER SOFTWARE CLAUSE AT DFARS 252.227-7013,
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| 14 | ** AND/OR IN SIMILAR OR SUCCESSOR CLAUSES IN THE FAR, DOD OR NASA FAR
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| 15 | ** SUPPLEMENT. UNPUBLISHED RIGHTS RESERVED UNDER THE COPYRIGHT LAWS OF
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| 16 | ** THE UNITED STATES.
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| 17 | **
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| 18 | ** COPYRIGHT 3DFX INTERACTIVE, INC. 1999, ALL RIGHTS RESERVED
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| 19 | **
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| 20 | **
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| 21 | ** $Revision: 1.1 $
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| 22 | ** $Date: 2000-02-25 00:33:56 $
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| 23 | **
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| 24 | */
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| 25 |
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| 26 | #ifndef _FXPCI_H_
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| 27 | #define _FXPCI_H_
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| 28 |
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| 29 | #ifdef __cplusplus
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| 30 | extern "C" {
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| 31 | #endif
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| 32 |
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| 33 | #define _3DFX_PCI_ID 0x121A
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| 34 |
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| 35 | /* jeske - 10/14/98
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| 36 | * This old assumption dosn't work anymore, because now a device_number
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| 37 | * is defined as:
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| 38 | *
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| 39 | * device_number[0:4] = slot
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| 40 | * device_number[5:12] = bus
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| 41 | * device_number[13:15] = function
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| 42 | *
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| 43 | * OLD ASSUMPTION:
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| 44 | * 16 Busses ( of possible 256, I am making the
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| 45 | * assumption that busses are numbered
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| 46 | * in increasing order and that no
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| 47 | * PC will have more than 16 busses )
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| 48 | * 32 Slots Per Bus
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| 49 | *
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| 50 | * Device Number = Bus Number * 32 + Slot Number <== wrong, see above....
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| 51 | */
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| 52 | # define MAX_PCI_DEVICES 512
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| 53 |
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| 54 | /* baseAddr0, baseAddr1, ioBaseAddr, romBaseAddr */
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| 55 | #define MAX_PCI_BASEADDRESSES 4
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| 56 |
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| 57 | typedef int PciMemType;
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| 58 | #define PciMemTypeUncacheable 0
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| 59 | #define PciMemTypeWriteCombining 1
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| 60 | #define PciMemTypeWriteThrough 4
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| 61 | #define PciMemTypeWriteProtected 5
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| 62 | #define PciMemTypeWriteback 6
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| 63 |
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| 64 | typedef enum {
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| 65 | READ_ONLY,
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| 66 | WRITE_ONLY,
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| 67 | READ_WRITE
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| 68 | } PciIOFlag;
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| 69 |
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| 70 | typedef struct {
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| 71 | FxU32 regAddress;
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| 72 | FxU32 sizeInBytes;
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| 73 | PciIOFlag rwFlag;
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| 74 | } PciRegister;
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| 75 |
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| 76 | #ifndef KERNEL
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| 77 | extern PciRegister PCI_VENDOR_ID;
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| 78 | extern PciRegister PCI_DEVICE_ID;
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| 79 | extern PciRegister PCI_COMMAND;
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| 80 | extern PciRegister PCI_STATUS;
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| 81 | extern PciRegister PCI_REVISION_ID;
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| 82 | extern PciRegister PCI_CLASS_CODE;
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| 83 | extern PciRegister PCI_CACHE_LINE_SIZE;
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| 84 | extern PciRegister PCI_LATENCY_TIMER;
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| 85 | extern PciRegister PCI_HEADER_TYPE;
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| 86 | extern PciRegister PCI_BIST;
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| 87 | extern PciRegister PCI_BASE_ADDRESS_0;
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| 88 | extern PciRegister PCI_BASE_ADDRESS_1;
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| 89 | extern PciRegister PCI_IO_BASE_ADDRESS;
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| 90 | extern PciRegister PCI_SUBVENDOR_ID;
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| 91 | extern PciRegister PCI_SUBSYSTEM_ID;
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| 92 | extern PciRegister PCI_ROM_BASE_ADDRESS;
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| 93 | extern PciRegister PCI_CAP_PTR;
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| 94 | extern PciRegister PCI_INTERRUPT_LINE;
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| 95 | extern PciRegister PCI_INTERRUPT_PIN;
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| 96 | extern PciRegister PCI_MIN_GNT;
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| 97 | extern PciRegister PCI_MAX_LAT;
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| 98 | extern PciRegister PCI_FAB_ID;
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| 99 | extern PciRegister PCI_CONFIG_STATUS;
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| 100 | extern PciRegister PCI_CONFIG_SCRATCH;
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| 101 | extern PciRegister PCI_AGP_CAP_ID;
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| 102 | extern PciRegister PCI_AGP_STATUS;
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| 103 | extern PciRegister PCI_AGP_CMD;
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| 104 | extern PciRegister PCI_ACPI_CAP_ID;
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| 105 | extern PciRegister PCI_CNTRL_STATUS;
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| 106 |
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| 107 | extern PciRegister PCI_SST1_INIT_ENABLE; // 0x40
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| 108 | extern PciRegister PCI_SST1_BUS_SNOOP_0; // 0x44
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| 109 | extern PciRegister PCI_SST1_BUS_SNOOP_1; // 0x48
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| 110 | extern PciRegister PCI_SST1_CFG_STATUS; // 0x4C
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| 111 |
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| 112 | #endif /* #ifndef KERNEL */
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| 113 |
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| 114 | /* a structure that contains callback procs */
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| 115 | typedef struct {
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| 116 | FxBool doHW;
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| 117 | FxU8 (*pioInByte) (FxU16 port);
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| 118 | FxU16 (*pioInWord) (FxU16 port);
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| 119 | FxU32 (*pioInLong) (FxU16 port);
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| 120 | void (*pioOutByte) (FxU16 port,FxU8 data);
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| 121 | void (*pioOutWord) (FxU16 port,FxU16 data);
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| 122 | void (*pioOutLong) (FxU16 port,FxU32 data);
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| 123 | } PciHwcCallbacks;
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| 124 |
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| 125 | FX_ENTRY const char * FX_CALL
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| 126 | pciGetErrorString( void );
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| 127 |
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| 128 | FX_ENTRY FxU32 FX_CALL
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| 129 | pciGetErrorCode( void );
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| 130 |
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| 131 | FX_ENTRY FxU8 FX_CALL
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| 132 | pioInByte ( unsigned short port ); /* inp */
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| 133 |
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| 134 | FX_ENTRY FxU16 FX_CALL
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| 135 | pioInWord ( unsigned short port ); /* inpw */
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| 136 |
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| 137 | FX_ENTRY FxU32 FX_CALL
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| 138 | pioInLong ( unsigned short port ); /* inpd */
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| 139 |
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| 140 | FX_ENTRY FxBool FX_CALL
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| 141 | pioOutByte ( unsigned short port, FxU8 data ); /* outp */
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| 142 |
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| 143 | FX_ENTRY FxBool FX_CALL
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| 144 | pioOutWord ( unsigned short port, FxU16 data ); /* outpw */
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| 145 |
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| 146 | FX_ENTRY FxBool FX_CALL
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| 147 | pioOutLong ( unsigned short port, FxU32 data ); /* outpd */
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| 148 |
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| 149 |
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| 150 | FX_ENTRY FxBool FX_CALL
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| 151 | pciOpen( void );
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| 152 |
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| 153 | FX_ENTRY FxBool FX_CALL
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| 154 | pciOpenEx( PciHwcCallbacks * );
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| 155 |
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| 156 | FX_ENTRY FxBool FX_CALL
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| 157 | pciClose( void );
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| 158 |
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| 159 | FX_ENTRY FxBool FX_CALL
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| 160 | pciDeviceExists( FxU32 device_number );
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| 161 |
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| 162 | FX_ENTRY FxBool FX_CALL
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| 163 | pciGetConfigData( PciRegister reg, FxU32 device_number, FxU32 *data );
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| 164 |
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| 165 | FX_ENTRY FxBool FX_CALL
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| 166 | pciSetConfigData( PciRegister reg, FxU32 device_number, FxU32 *data );
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| 167 |
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| 168 | /* NB: This routine makes the implicit assumption that the device was
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| 169 | * on bus0 which would not work across pci bridges or on agp devices.
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| 170 | */
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| 171 | FX_ENTRY FxBool FX_CALL
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| 172 | pciMapPhysicalToLinear(FxU32 *linear_addr, FxU32 physical_addr,FxU32 *length);
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| 173 |
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| 174 | FX_ENTRY FxBool FX_CALL
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| 175 | pciMapPhysicalDeviceToLinear(FxU32 *linear_addr,
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| 176 | FxU32 busNumber, FxU32 physical_addr,
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| 177 | FxU32 *length);
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| 178 |
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| 179 | FX_ENTRY void FX_CALL
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| 180 | pciUnmapPhysical( FxU32 linear_addr, FxU32 length );
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| 181 |
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| 182 | const char *
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| 183 | pciGetVendorName( FxU16 vendor_id );
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| 184 | const char *
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| 185 | pciGetClassName( FxU32 class_code , FxU32 deviceID);
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| 186 |
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| 187 | FX_ENTRY FxBool FX_CALL
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| 188 | pciFindCard(FxU32 vendorID, FxU32 deviceID, FxU32 *devNum);
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| 189 |
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| 190 | FX_ENTRY FxBool FX_CALL
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| 191 | pciFindCardMulti(FxU32 vID, FxU32 dID, FxU32 *devNum, FxU32 cardNum);
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| 192 |
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| 193 | FX_ENTRY FxU32 * FX_CALL
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| 194 | pciMapCard(FxU32 vID, FxU32 dID, FxI32 len, FxU32 *devNo, FxU32 addrNo);
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| 195 |
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| 196 | FX_ENTRY FxU32 * FX_CALL
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| 197 | pciMapCardMulti(FxU32 vID,FxU32 dID,FxI32 l,FxU32 *dNo,FxU32 cNo,FxU32 aNo);
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| 198 |
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| 199 | FX_ENTRY FxBool FX_CALL
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| 200 | pciFindMTRRMatch(FxU32 pBaseAddrs, FxU32 psz, PciMemType type, FxU32 *mtrrNum);
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| 201 |
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| 202 | FX_ENTRY FxBool FX_CALL
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| 203 | pciFindFreeMTRR(FxU32 *mtrrNum);
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| 204 |
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| 205 | FX_ENTRY FxBool FX_CALL
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| 206 | pciSetMTRR(FxU32 mtrrNo, FxU32 pBaseAddr, FxU32 psz, PciMemType type);
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| 207 |
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| 208 | FX_ENTRY FxBool FX_CALL
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| 209 | pciSetMTRRAmdK6(FxU32 mtrrNo, FxU32 pBaseAddr, FxU32 psz, PciMemType type);
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| 210 |
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| 211 | FX_ENTRY FxBool FX_CALL
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| 212 | pciSetPassThroughBase(FxU32* pBaseAddr, FxU32 baseAddrLen);
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| 213 |
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| 214 | FX_ENTRY FxBool FX_CALL
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| 215 | pciOutputDebugString(const char* debugMsg);
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| 216 |
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| 217 | FX_ENTRY FxBool FX_CALL
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| 218 | pciLinearRangeSetPermission(const FxU32 addrBase, const FxU32 addrLen, const FxBool writeableP);
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| 219 |
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| 220 | #define PCI_ERR_NOERR 0
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| 221 | #define PCI_ERR_WINRTINIT 1
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| 222 | #define PCI_ERR_MEMMAPVXD 2
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| 223 | #define PCI_ERR_MAPMEMDRV 3
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| 224 | #define PCI_ERR_GENPORT 4
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| 225 | #define PCI_ERR_NO_BUS 5
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| 226 | #define PCI_ERR_NOTOPEN 6
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| 227 | #define PCI_ERR_NOTOPEN2 7
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| 228 | #define PCI_ERR_NOTOPEN3 8
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| 229 | #define PCI_ERR_OUTOFRANGE 9
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| 230 | #define PCI_ERR_NODEV 10
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| 231 | #define PCI_ERR_NODEV2 11
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| 232 | #define PCI_ERR_WRITEONLY 12
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| 233 | #define PCI_ERR_READONLY 13
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| 234 | #define PCI_ERR_PHARLAP 14
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| 235 | #define PCI_ERR_WRONGVXD 15
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| 236 | #define PCI_ERR_MEMMAP 16
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| 237 | #define PCI_ERR_MAPMEM 17
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| 238 | #define PCI_ERR_WINRT 18
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| 239 | #define PCI_ERR_VXDINUSE 19
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| 240 | #define PCI_ERR_NO_IO_PERM 20
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| 241 | #define PCI_ERR_NO_MEM_PERM 21
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| 242 |
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| 243 | #ifdef __cplusplus
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| 244 | }
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| 245 | #endif
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| 246 |
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| 247 | #endif /* _FXPCI_H_ */
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