source: trunk/src/opengl/glide/swlibs/pcilib/fxos2.cpp

Last change on this file was 3093, checked in by sandervl, 25 years ago

added missing ports for voodoo1
File size: 20.8 KB
Line 
1/*
2** THIS SOFTWARE IS SUBJECT TO COPYRIGHT PROTECTION AND IS OFFERED ONLY
3** PURSUANT TO THE 3DFX GLIDE GENERAL PUBLIC LICENSE. THERE IS NO RIGHT
4** TO USE THE GLIDE TRADEMARK WITHOUT PRIOR WRITTEN PERMISSION OF 3DFX
5** INTERACTIVE, INC. A COPY OF THIS LICENSE MAY BE OBTAINED FROM THE
6** DISTRIBUTOR OR BY CONTACTING 3DFX INTERACTIVE INC(info@3dfx.com).
7** THIS PROGRAM IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
8** EXPRESSED OR IMPLIED. SEE THE 3DFX GLIDE GENERAL PUBLIC LICENSE FOR A
9** FULL TEXT OF THE NON-WARRANTY PROVISIONS.
10**
11** USE, DUPLICATION OR DISCLOSURE BY THE GOVERNMENT IS SUBJECT TO
12** RESTRICTIONS AS SET FORTH IN SUBDIVISION (C)(1)(II) OF THE RIGHTS IN
13** TECHNICAL DATA AND COMPUTER SOFTWARE CLAUSE AT DFARS 252.227-7013,
14** AND/OR IN SIMILAR OR SUCCESSOR CLAUSES IN THE FAR, DOD OR NASA FAR
15** SUPPLEMENT. UNPUBLISHED RIGHTS RESERVED UNDER THE COPYRIGHT LAWS OF
16** THE UNITED STATES.
17**
18** COPYRIGHT 3DFX INTERACTIVE, INC. 1999, ALL RIGHTS RESERVED
19*/
20
21#define INCL_DOS
22#define INCL_DOSDEVIOCTL
23#define INCL_DOSPROCESS
24#define INCL_DOSERRORS
25#define INCL_DOSMODULEMGR
26#define INCL_DOSDEVICES
27#include <os2wrap.h>
28
29#include <stdarg.h>
30#include <stdio.h>
31#include <stdlib.h>
32#include <types.h>
33////#include <unistd.h>
34#include <io.h>
35#include <ctype.h>
36#include <string.h>
37#include <fcntl.h>
38
39#include "3dfx.h"
40#include "fxpci.h"
41#include "pcilib.h"
42#include "fxos2.h"
43
44#ifdef __WIN32OS2__
45#define FX_CSTYLE __stdcall
46#include <misc.h>
47#else
48#define FX_CSTYLE _System
49#endif
50
51#pragma pack(1)
52
53#ifdef DEBUG
54#define DEBUGMSG(x) printf x
55#else
56#define DEBUGMSG(x)
57#endif
58
59#define PCI_VENDOR_ID_OS2 0x0
60#define PCI_DEVICE_ID_OS2 0x2
61#define PCI_COMMAND_OS2 0x4
62#define PCI_REVISION_ID_OS2 0x8
63#define PCI_BASE_ADDRESS_0_OS2 0x10
64#define PCI_BASE_ADDRESS_1_OS2 0x14
65#define SST1_PCI_INIT_ENABLE_OS2 0x40
66#define SST1_PCI_BUS_SNOOP0_OS2 0x44
67#define SST1_PCI_BUS_SNOOP1_OS2 0x48
68#define SST1_PCI_SPECIAL1_OS2 0x40
69#define SST1_PCI_SPECIAL2_OS2 0x44
70#define SST1_PCI_SPECIAL3_OS2 0x48
71#define SST1_PCI_SPECIAL4_OS2 0x54
72#define SST1_PCI_VCLK_ENABLE 0xc0
73#define SST1_PCI_VCLK_DISABLE 0xe0
74
75
76#define PCI_VENDOR_ID_3DFX 0x121a
77#define PCI_DEVICE_ID_3DFX_VOODOO 1
78#define PCI_DEVICE_ID_3DFX_VOODOO2 2
79#define PCI_DEVICE_ID_3DFX_BANSHEE 3
80#define PCI_DEVICE_ID_3DFX_VOODOO3 5
81#define PCI_VENDOR_ID_ALLIANCE 0x1142
82#define PCI_DEVICE_ID_ALLIANCE_AT3D 0x643d
83
84static const char* pciIdentifyOS2(void);
85static FxBool pciOutputStringOS2(const char *msg);
86static FxBool pciInitializeOS2(void);
87static FxBool pciShutdownOS2(void);
88static FxBool pciMapLinearOS2(FxU32, FxU32 physical_addr, FxU32 *linear_addr,
89 FxU32 *length);
90static FxBool pciUnmapLinearOS2(FxU32 linear_addr, FxU32 length);
91static FxBool pciSetPermissionOS2(const FxU32, const FxU32, const FxBool);
92static FxU8 pciPortInByteOS2(unsigned short port);
93static FxU16 pciPortInWordOS2(unsigned short port);
94static FxU32 pciPortInLongOS2(unsigned short port);
95static FxBool pciPortOutByteOS2(unsigned short port, FxU8 data);
96static FxBool pciPortOutWordOS2(unsigned short port, FxU16 data);
97static FxBool pciPortOutLongOS2(unsigned short port, FxU32 data);
98static FxBool pciMsrGetOS2(MSRInfo *, MSRInfo *);
99static FxBool pciMsrSetOS2(MSRInfo *, MSRInfo *);
100static FxBool pciSetPassThroughBaseOS2(FxU32 *, FxU32);
101
102const FxPlatformIOProcs ioProcsOS2 = {
103 pciInitializeOS2,
104 pciShutdownOS2,
105 pciIdentifyOS2,
106
107 pciPortInByteOS2,
108 pciPortInWordOS2,
109 pciPortInLongOS2,
110
111 pciPortOutByteOS2,
112 pciPortOutWordOS2,
113 pciPortOutLongOS2,
114
115 pciMapLinearOS2,
116 pciUnmapLinearOS2,
117 pciSetPermissionOS2,
118
119 pciMsrGetOS2,
120 pciMsrSetOS2,
121
122 pciOutputStringOS2,
123 pciSetPassThroughBaseOS2
124};
125
126static int linuxDevFd=-1;
127
128typedef struct pioData_t {
129 short port;
130 short size;
131 int device;
132 void *value;
133} ;
134
135struct cardInfo_t {
136 int vendor;
137 int type;
138 ULONG addr0;
139 ULONG addr1;
140 PULONG laddr0;
141 PULONG laddr1;
142 unsigned char bus;
143 unsigned char dev;
144};
145
146struct pci_dev
147{
148 unsigned char bus;
149 unsigned char devfn;
150};
151
152typedef struct pioData_t pioData;
153typedef struct cardInfo_t cardInfo;
154
155#define MAXCARDS 16
156
157static HFILE hOemHlp;
158static HFILE hTestCfg;
159static HFILE hScreenDD;
160
161static cardInfo cards[MAXCARDS];
162static int numCards = 0;
163
164static UINT os2_pci_query( HFILE hOemHlp, USHORT usDeviceID, USHORT usVendorID, UCHAR ucIndex, PUCHAR pucBus, PUCHAR pucDevFn )
165{
166 ULONG cbParmLenMax, cbDataLenMax;
167 APIRET rc;
168 struct
169 {
170 UCHAR ucSubFunction;
171 USHORT usDeviceID;
172 USHORT usVendorID;
173 UCHAR ucIndex;
174 } pcifindreq;
175 struct
176 {
177 UCHAR ucRC;
178 UCHAR ucBus;
179 UCHAR ucDevFunc;
180 } pcifindrep;
181
182 pcifindreq.ucSubFunction = 1; // find pci device
183 pcifindreq.usDeviceID = usDeviceID; // pci device
184 pcifindreq.usVendorID = usVendorID; // pci vendor
185 pcifindreq.ucIndex = ucIndex; // entry
186
187 memset( &pcifindrep, 0, sizeof(pcifindrep) );
188
189 cbParmLenMax = sizeof(pcifindreq);
190 cbDataLenMax = sizeof(pcifindrep);
191
192 rc = DosDevIOCtl( hOemHlp, IOCTL_OEMHLP, OEMHLP_PCI,
193 &pcifindreq, cbParmLenMax, &cbParmLenMax,
194 &pcifindrep, cbDataLenMax, &cbDataLenMax);
195
196 if ( pcifindrep.ucRC == 0 )
197 {
198 *pucBus = pcifindrep.ucBus;
199 *pucDevFn = pcifindrep.ucDevFunc;
200 return TRUE;
201 }
202
203 return FALSE;
204}
205
206static void os2_pci_read( HFILE hOemHlp, UCHAR ucBus, UCHAR ucDevFn, UCHAR ucIndex, PULONG pulData, UCHAR ucSize )
207{
208 ULONG cbParmLenMax, cbDataLenMax;
209 APIRET rc;
210 struct
211 {
212 UCHAR ucSubFunction;
213 UCHAR ucBus;
214 UCHAR ucDevFunc;
215 UCHAR ucCfgReg;
216 UCHAR ucSize;
217 } pcireadreq;
218 struct
219 {
220 UCHAR ucRC;
221 ULONG ulData;
222 } pcireadrep;
223
224 pcireadreq.ucSubFunction = 3; // read pci device
225 pcireadreq.ucBus = ucBus;
226 pcireadreq.ucDevFunc = ucDevFn;
227 pcireadreq.ucCfgReg = ucIndex;
228 pcireadreq.ucSize = ucSize;
229
230 rc = DosDevIOCtl( hOemHlp, IOCTL_OEMHLP, OEMHLP_PCI,
231 &pcireadreq, sizeof(pcireadreq), &cbParmLenMax,
232 &pcireadrep, sizeof(pcireadrep), &cbDataLenMax);
233
234 *pulData = pcireadrep.ulData;
235}
236
237static void os2_pci_write( HFILE hOemHlp, UCHAR ucBus, UCHAR ucDevFn, UCHAR ucIndex, ULONG ulData, UCHAR ucSize )
238{
239 ULONG cbParmLenMax, cbDataLenMax;
240 APIRET rc;
241 struct
242 {
243 UCHAR ucSubFunction;
244 UCHAR ucBus;
245 UCHAR ucDevFunc;
246 UCHAR ucCfgReg;
247 UCHAR ucSize;
248 ULONG ulData;
249 } pciwritereq;
250 struct
251 {
252 UCHAR ucRC;
253 ULONG ulData;
254 } pciwriterep;
255
256 pciwritereq.ucSubFunction = 4; // write pci device
257 pciwritereq.ucBus = ucBus;
258 pciwritereq.ucDevFunc = ucDevFn;
259 pciwritereq.ucCfgReg = ucIndex;
260 pciwritereq.ucSize = ucSize;
261 pciwritereq.ulData = ulData;
262
263 rc = DosDevIOCtl( hOemHlp, IOCTL_OEMHLP, OEMHLP_PCI,
264 &pciwritereq, sizeof(pciwritereq), &cbParmLenMax,
265 &pciwriterep, sizeof(pciwriterep), &cbDataLenMax);
266}
267
268static struct pci_dev *pci_find_device(int vendor, int device, char index, struct pci_dev *dev)
269{
270 UINT bFound;
271
272 bFound = os2_pci_query( hOemHlp, device, vendor, index, &dev->bus, &dev->devfn );
273
274 return bFound ? dev : 0;
275}
276
277static void pci_read_config_dword(unsigned int bus, unsigned int devfn, char index, PULONG pulDest)
278{
279 os2_pci_read( hOemHlp, bus, devfn, index, pulDest, 4 );
280}
281
282static void pci_read_config_word(unsigned int bus, unsigned int devfn, char index, PUSHORT pusDest)
283{
284 ULONG ulDest;
285 os2_pci_read( hOemHlp, bus, devfn, index, &ulDest, 4 );
286 *pusDest = (USHORT)ulDest;
287}
288
289static void pci_read_config_byte(unsigned int bus, unsigned int devfn, char index, PUCHAR pucDest)
290{
291 ULONG ulDest;
292 os2_pci_read( hOemHlp, bus, devfn, index, &ulDest, 4 );
293 *pucDest = (UCHAR)ulDest;
294}
295
296static void pci_write_config_dword(unsigned int bus, unsigned int devfn, char index, ULONG ulDest)
297{
298 os2_pci_write( hOemHlp, bus, devfn, index, ulDest, 4 );
299}
300
301static FxU32 mmap_allocate( ULONG ulAddr )
302{
303 ULONG cbParmLenMax;
304 APIRET rc;
305 struct
306 {
307 ULONG ulPacketLength;
308 ULONG ulPhysicalAddress;
309 ULONG ulMemorySize;
310 ULONG ulLinearAddress;
311 ULONG ulLinearFlags;
312 } memmapreq;
313
314 memmapreq.ulPacketLength = sizeof(memmapreq);
315 memmapreq.ulPhysicalAddress = ulAddr;
316 memmapreq.ulMemorySize = 0x1000000;
317 memmapreq.ulLinearAddress = 0;
318 memmapreq.ulLinearFlags = 0x410;
319
320 cbParmLenMax = sizeof(memmapreq);
321
322 rc = DosDevIOCtl( hScreenDD, SCREENDD_CATEGORY, SCREENDD_GETLINEARACCESS,
323 &memmapreq, cbParmLenMax, &cbParmLenMax,
324 0, 0, 0);
325
326 return memmapreq.ulLinearAddress;
327}
328
329int _System io_init1(void)
330{
331 return 0;
332}
333
334int _System io_exit1(void)
335{
336 return 0;
337}
338
339char _System c_inb1 ( short sPort )
340{
341 ULONG cbParmLenMax, cbDataLenMax;
342 APIRET rc;
343 struct
344 {
345 USHORT usPort;
346 USHORT usSize;
347 } ioreq;
348 struct
349 {
350 LONG lValue;
351 } iorep;
352
353 ioreq.usPort = (USHORT) sPort;
354 ioreq.usSize = sizeof(CHAR);
355
356 memset( &iorep, 0, sizeof(iorep) );
357
358 cbParmLenMax = sizeof(ioreq);
359 cbDataLenMax = sizeof(iorep);
360
361 rc = DosDevIOCtl( hTestCfg, IOCTL_TESTCFG_SYS, TESTCFG_SYS_ISSUEINIOINSTR,
362 &ioreq, cbParmLenMax, &cbParmLenMax,
363 &iorep, cbDataLenMax, &cbDataLenMax);
364
365 return (CHAR) iorep.lValue;
366}
367
368short _System c_inw1 ( short sPort )
369{
370 ULONG cbParmLenMax, cbDataLenMax;
371 APIRET rc;
372 struct
373 {
374 USHORT usPort;
375 USHORT usSize;
376 } ioreq;
377 struct
378 {
379 LONG lValue;
380 } iorep;
381
382 ioreq.usPort = (USHORT) sPort;
383 ioreq.usSize = sizeof(SHORT);
384
385 memset( &iorep, 0, sizeof(iorep) );
386
387 cbParmLenMax = sizeof(ioreq);
388 cbDataLenMax = sizeof(iorep);
389
390 rc = DosDevIOCtl( hTestCfg, IOCTL_TESTCFG_SYS, TESTCFG_SYS_ISSUEINIOINSTR,
391 &ioreq, cbParmLenMax, &cbParmLenMax,
392 &iorep, cbDataLenMax, &cbDataLenMax);
393
394 return (SHORT) iorep.lValue;
395}
396
397long _System c_inl1 ( short sPort )
398{
399 ULONG cbParmLenMax, cbDataLenMax;
400 APIRET rc;
401 struct
402 {
403 USHORT usPort;
404 USHORT usSize;
405 } ioreq;
406 struct
407 {
408 LONG lValue;
409 } iorep;
410
411 ioreq.usPort = (USHORT) sPort;
412 ioreq.usSize = sizeof(LONG);
413
414 memset( &iorep, 0, sizeof(iorep) );
415
416 cbParmLenMax = sizeof(ioreq);
417 cbDataLenMax = sizeof(iorep);
418
419 rc = DosDevIOCtl( hTestCfg, IOCTL_TESTCFG_SYS, TESTCFG_SYS_ISSUEINIOINSTR,
420 &ioreq, cbParmLenMax, &cbParmLenMax,
421 &iorep, cbDataLenMax, &cbDataLenMax);
422
423 return iorep.lValue;
424}
425
426void _System c_outb1 ( short sPort, char cValue )
427{
428 ULONG cbParmLenMax, cbDataLenMax;
429 APIRET rc;
430 struct
431 {
432 USHORT usPort;
433 USHORT usSize;
434 } ioreq;
435 struct
436 {
437 LONG lValue;
438 } iorep;
439
440 ioreq.usPort = (USHORT) sPort;
441 ioreq.usSize = sizeof(CHAR);
442
443 iorep.lValue = (LONG) cValue;
444
445 cbParmLenMax = sizeof(ioreq);
446 cbDataLenMax = sizeof(iorep);
447
448 rc = DosDevIOCtl( hTestCfg, IOCTL_TESTCFG_SYS, TESTCFG_SYS_ISSUEOUTIOINSTR,
449 &ioreq, cbParmLenMax, &cbParmLenMax,
450 &iorep, cbDataLenMax, &cbDataLenMax);
451}
452
453void _System c_outw1 ( short sPort, short sValue )
454{
455 ULONG cbParmLenMax, cbDataLenMax;
456 APIRET rc;
457 struct
458 {
459 USHORT usPort;
460 USHORT usSize;
461 } ioreq;
462 struct
463 {
464 LONG lValue;
465 } iorep;
466
467 ioreq.usPort = (USHORT) sPort;
468 ioreq.usSize = sizeof(SHORT);
469
470 iorep.lValue = (LONG) sValue;
471
472 cbParmLenMax = sizeof(ioreq);
473 cbDataLenMax = sizeof(iorep);
474
475 rc = DosDevIOCtl( hTestCfg, IOCTL_TESTCFG_SYS, TESTCFG_SYS_ISSUEOUTIOINSTR,
476 &ioreq, cbParmLenMax, &cbParmLenMax,
477 &iorep, cbDataLenMax, &cbDataLenMax);
478}
479
480void _System c_outl1 ( short sPort, long lValue )
481{
482 ULONG cbParmLenMax, cbDataLenMax;
483 APIRET rc;
484 struct
485 {
486 USHORT usPort;
487 USHORT usSize;
488 } ioreq;
489 struct
490 {
491 LONG lValue;
492 } iorep;
493
494 ioreq.usPort = (USHORT) sPort;
495 ioreq.usSize = sizeof(LONG);
496
497 iorep.lValue = (LONG) lValue;
498
499 cbParmLenMax = sizeof(ioreq);
500 cbDataLenMax = sizeof(iorep);
501
502 rc = DosDevIOCtl( hTestCfg, IOCTL_TESTCFG_SYS, TESTCFG_SYS_ISSUEOUTIOINSTR,
503 &ioreq, cbParmLenMax, &cbParmLenMax,
504 &iorep, cbDataLenMax, &cbDataLenMax);
505}
506
507static void findCardType(int vendor, int device)
508{
509 struct pci_dev dev = {0};
510 char index = 0;
511
512 while (numCards < MAXCARDS && pci_find_device(vendor, device, index, &dev)) {
513 pci_read_config_dword(dev.bus, dev.devfn, PCI_BASE_ADDRESS_0_OS2, &cards[numCards].addr0);
514 pci_read_config_dword(dev.bus, dev.devfn, PCI_BASE_ADDRESS_1_OS2, &cards[numCards].addr1);
515 cards[numCards].bus = dev.bus;
516 cards[numCards].dev = dev.devfn;
517 cards[numCards].addr0 &= ~0xF;
518 cards[numCards].addr1 &= ~0xF;
519 cards[numCards].vendor = vendor;
520 cards[numCards].type = device;
521
522 DEBUGMSG(("3dfx: board vendor %x type %x located at %x/%x bus %x dev %x\n",
523 vendor, device, cards[numCards].addr0, cards[numCards].addr1, cards[numCards].bus, cards[numCards].dev));
524
525 ++numCards;
526 ++index;
527 }
528}
529
530static int findCards(void)
531{
532 numCards = 0;
533 findCardType(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO);
534 findCardType(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2);
535 findCardType(PCI_VENDOR_ID_ALLIANCE, 0x643d);
536 findCardType(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE);
537 findCardType(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3);
538 return numCards;
539}
540
541FxBool
542pciPlatformInit(void)
543{
544 gCurPlatformIO = &ioProcsOS2;
545 return FXTRUE;
546}
547
548FxBool
549hasDev3DfxOS2(void)
550{
551 if (numCards==0) return FXFALSE;
552 return FXTRUE;
553}
554
555static int doQueryFetchOS2(pioData *desc)
556{
557 int retval;
558 UCHAR retchar;
559 USHORT retword;
560 ULONG retlong;
561
562 if (desc->device < 0 || desc->device >= numCards)
563 return -1;
564 switch (desc->port) {
565 case PCI_VENDOR_ID_OS2:
566 if (desc->size != 2)
567 return -1;
568 memcpy(desc->value, &cards[desc->device].vendor, desc->size);
569 return 0;
570 case PCI_DEVICE_ID_OS2:
571 if (desc->size != 2)
572 return -1;
573 memcpy(desc->value, &cards[desc->device].type, desc->size);
574 return 0;
575 case PCI_BASE_ADDRESS_0_OS2:
576 if (desc->size != 4)
577 return -1;
578 memcpy(desc->value, &cards[desc->device].addr0, desc->size);
579 return 0;
580 case PCI_BASE_ADDRESS_1_OS2:
581 if (desc->size != 4)
582 return -1;
583 memcpy(desc->value, &cards[desc->device].addr1, desc->size);
584 return 0;
585 case SST1_PCI_SPECIAL1_OS2:
586 if (desc->size != 4)
587 return -1;
588 break;
589 case PCI_REVISION_ID_OS2:
590 if (desc->size != 1)
591 return -1;
592 break;
593 case SST1_PCI_SPECIAL4_OS2:
594 if (desc->size != 4)
595 return -1;
596 break;
597
598 default:
599 return -1;
600 }
601 switch (desc->size) {
602 case 1:
603 pci_read_config_byte(cards[desc->device].bus, cards[desc->device].dev, desc->port, &retchar);
604 memcpy(desc->value, &retchar, 1);
605 break;
606 case 2:
607 pci_read_config_word(cards[desc->device].bus, cards[desc->device].dev, desc->port, &retword);
608 memcpy(desc->value, &retword, 2);
609 break;
610 case 4:
611 pci_read_config_dword(cards[desc->device].bus, cards[desc->device].dev, desc->port, &retlong);
612 memcpy(desc->value, &retlong, 4);
613 break;
614 default:
615 return -1;
616 }
617 return 0;
618}
619
620FxU32
621pciFetchRegisterOS2( FxU32 cmd, FxU32 size, FxU32 device)
622{
623 pioData desc;
624 char cval;
625 short sval;
626 int ival;
627
628 if (numCards==0) return -1;
629 desc.port=cmd;
630 desc.size=size;
631 desc.device=device;
632 switch (size) {
633 case 1:
634 desc.value=&cval;
635 break;
636 case 2:
637 desc.value=&sval;
638 break;
639 case 4:
640 desc.value=&ival;
641 break;
642 default:
643 return 0;
644 }
645 if (doQueryFetchOS2(&desc)==-1)
646 return 0;
647 switch (size) {
648 case 1:
649 return cval;
650 case 2:
651 return sval;
652 case 4:
653 return ival;
654 default:
655 return 0;
656 }
657}
658
659static int doQueryUpdateOS2(pioData *desc)
660{
661 ULONG retval;
662 ULONG preval;
663 int mask;
664 UCHAR retchar;
665 USHORT retword;
666 ULONG retlong;
667
668 if (desc->device < 0 || desc->device >= numCards)
669 return -1;
670 switch (desc->port) {
671 case PCI_COMMAND_OS2:
672 if (desc->size != 2)
673 return -1;
674 break;
675 case SST1_PCI_SPECIAL1_OS2:
676 if (desc->size != 4)
677 return -1;
678 break;
679 case SST1_PCI_SPECIAL2_OS2:
680 if (desc->size != 4)
681 return -1;
682 break;
683 case SST1_PCI_SPECIAL3_OS2:
684 if (desc->size != 4)
685 return -1;
686 break;
687 case SST1_PCI_SPECIAL4_OS2:
688 if (desc->size != 4)
689 return -1;
690 break;
691
692 case SST1_PCI_VCLK_ENABLE:
693 if (desc->size != 4)
694 return -1;
695 break;
696
697 case SST1_PCI_VCLK_DISABLE:
698 if (desc->size != 4)
699 return -1;
700 break;
701
702 default:
703 return -1;
704 }
705 pci_read_config_dword(cards[desc->device].bus, cards[desc->device].dev, desc->port & ~0x3, &retval);
706 switch (desc->size) {
707 case 1:
708 memcpy(&retchar, desc->value, 1);
709 preval = retchar << (8 * (desc->port & 0x3));
710 mask = 0xFF << (8 * (desc->port & 0x3));
711 break;
712 case 2:
713 memcpy(&retword, desc->value, 2);
714 preval = retword << (8 * (desc->port & 0x3));
715 mask = 0xFFFF << (8 * (desc->port & 0x3));
716 break;
717 case 4:
718 memcpy(&retlong, desc->value, 4);
719 preval = retlong;
720 mask = ~0;
721 break;
722 default:
723 return -1;
724 }
725 retval = (retval & ~mask) | preval;
726 pci_write_config_dword(cards[desc->device].bus, cards[desc->device].dev, desc->port, retval);
727 return 0;
728}
729
730FxBool
731pciUpdateRegisterOS2(FxU32 cmd, FxU32 data, FxU32 size, FxU32 device) {
732 pioData desc;
733
734 if (numCards==0) return -1;
735 desc.port=cmd;
736 desc.size=size;
737 desc.device=device;
738 desc.value=&data;
739 if (doQueryUpdateOS2(&desc)==-1)
740 return FXFALSE;
741 return FXTRUE;
742}
743
744int
745getNumDevicesOS2(void)
746{
747 if (numCards==0) return -1;
748 return numCards;
749}
750
751static const char*
752pciIdentifyOS2(void)
753{
754 return "fxPCI for OS2";
755}
756
757static FxBool
758pciOutputStringOS2(const char *msg)
759{
760 printf(msg);
761 return FXTRUE;
762}
763
764static FxBool
765pciInitializeOS2(void)
766{
767 ULONG ulAction;
768 APIRET rc;
769
770 io_init1();
771
772tryopen1:
773 rc = DosOpen("OEMHLP$", &hOemHlp, &ulAction, 0, FILE_NORMAL, OPEN_ACTION_OPEN_IF_EXISTS, OPEN_ACCESS_READWRITE|OPEN_SHARE_DENYREADWRITE, 0L);
774 if(rc == ERROR_TOO_MANY_OPEN_FILES) {
775 ULONG CurMaxFH;
776 LONG ReqCount = 32;
777
778 rc = DosSetRelMaxFH(&ReqCount, &CurMaxFH);
779 if(rc) {
780 dprintf(("DosSetRelMaxFH returned %d", rc));
781 pciErrorCode = PCI_ERR_NO_IO_PERM;
782 return FXFALSE;
783 }
784 dprintf(("DosOpen failed -> increased nr open files to %d", CurMaxFH));
785 goto tryopen1;
786 }
787 else
788 if(rc) {
789 pciErrorCode = PCI_ERR_NO_IO_PERM;
790 return FXFALSE;
791 }
792tryopen2:
793 rc = DosOpen("TESTCFG$", &hTestCfg, &ulAction, 0, FILE_NORMAL, OPEN_ACTION_OPEN_IF_EXISTS, OPEN_ACCESS_READWRITE|OPEN_SHARE_DENYNONE, 0L );
794 if(rc == ERROR_TOO_MANY_OPEN_FILES) {
795 ULONG CurMaxFH;
796 LONG ReqCount = 32;
797
798 rc = DosSetRelMaxFH(&ReqCount, &CurMaxFH);
799 if(rc) {
800 dprintf(("DosSetRelMaxFH returned %d", rc));
801 pciErrorCode = PCI_ERR_NO_IO_PERM;
802 return FXFALSE;
803 }
804 dprintf(("DosOpen failed -> increased nr open files to %d", CurMaxFH));
805 goto tryopen2;
806 }
807 else
808 if(rc) {
809 pciErrorCode = PCI_ERR_NO_IO_PERM;
810 return FXFALSE;
811 }
812tryopen3:
813 rc = DosOpen("SCREEN$", &hScreenDD, &ulAction, 0, FILE_NORMAL, OPEN_ACTION_OPEN_IF_EXISTS, OPEN_ACCESS_READWRITE|OPEN_SHARE_DENYNONE, 0L );
814 if(rc == ERROR_TOO_MANY_OPEN_FILES) {
815 ULONG CurMaxFH;
816 LONG ReqCount = 32;
817
818 rc = DosSetRelMaxFH(&ReqCount, &CurMaxFH);
819 if(rc) {
820 dprintf(("DosSetRelMaxFH returned %d", rc));
821 pciErrorCode = PCI_ERR_NO_IO_PERM;
822 return FXFALSE;
823 }
824 dprintf(("DosOpen failed -> increased nr open files to %d", CurMaxFH));
825 goto tryopen3;
826 }
827 else
828 if(rc) {
829 pciErrorCode = PCI_ERR_NO_IO_PERM;
830 return FXFALSE;
831 }
832 findCards();
833 if (numCards==0) {
834 pciErrorCode = PCI_ERR_NO_IO_PERM;
835 return FXFALSE;
836 }
837 return FXTRUE;
838}
839
840static FxBool
841pciShutdownOS2(void)
842{
843 DosClose( hTestCfg );
844 DosClose( hScreenDD );
845 DosClose( hOemHlp );
846 io_exit1();
847 return FXTRUE;
848}
849
850static FxBool
851pciMapLinearOS2(FxU32 bus, FxU32 physical_addr, FxU32 *linear_addr, FxU32 *length)
852{
853 *linear_addr = mmap_allocate(physical_addr);
854 return FXTRUE;
855}
856
857static FxBool
858pciUnmapLinearOS2(FxU32 linear_addr, FxU32 length)
859{
860 return FXTRUE;
861}
862
863static FxBool
864pciSetPermissionOS2(const FxU32 addrBase, const FxU32 addrLen, const FxBool writePermP)
865{
866 return FXTRUE;
867}
868
869static FxU8
870pciPortInByteOS2(unsigned short port)
871{
872 return c_inb1(port);
873}
874
875static FxU16
876pciPortInWordOS2(unsigned short port)
877{
878 return c_inw1(port);
879}
880
881static FxU32
882pciPortInLongOS2(unsigned short port)
883{
884 return c_inl1(port);
885}
886
887static FxBool
888pciPortOutByteOS2(unsigned short port, FxU8 data)
889{
890 c_outb1(port,data);
891 return FXTRUE;
892}
893
894static FxBool
895pciPortOutWordOS2(unsigned short port, FxU16 data)
896{
897 c_outw1(port,data);
898 return FXTRUE;
899}
900
901static FxBool
902pciPortOutLongOS2(unsigned short port, FxU32 data)
903{
904 c_outl1(port,data);
905 return FXTRUE;
906}
907
908static FxBool
909pciMsrGetOS2(MSRInfo *in, MSRInfo *out)
910{
911 return FXTRUE;
912}
913
914static FxBool
915pciMsrSetOS2(MSRInfo *in, MSRInfo *out)
916{
917 return FXTRUE;
918}
919
920static FxBool
921pciSetPassThroughBaseOS2(FxU32 *baseAddr, FxU32 baseAddrLen)
922{
923 return FXTRUE;
924}
925
926FxBool FX_CSTYLE pciFindFreeMTRR(FxU32 *mtrrNum)
927{
928 return FXFALSE;
929}
930
931FxBool FX_CSTYLE pciSetMTRR(FxU32 mtrrNum, FxU32 physBaseAddr, FxU32 physSize, PciMemType type)
932{
933 return FXTRUE;
934}
935
936FxBool FX_CSTYLE pciFindMTRRMatch(FxU32 physBaseAddress, FxU32 physSize, PciMemType type, FxU32 *mtrrNum)
937{
938 return FXFALSE;
939}
940
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