source: trunk/src/opengl/glide/cvg/init/sst1init.h

Last change on this file was 2888, checked in by sandervl, 26 years ago

Created Voodoo 2 dir
File size: 57.2 KB
Line 
1/*-*-c++-*-*/
2/*
3** THIS SOFTWARE IS SUBJECT TO COPYRIGHT PROTECTION AND IS OFFERED ONLY
4** PURSUANT TO THE 3DFX GLIDE GENERAL PUBLIC LICENSE. THERE IS NO RIGHT
5** TO USE THE GLIDE TRADEMARK WITHOUT PRIOR WRITTEN PERMISSION OF 3DFX
6** INTERACTIVE, INC. A COPY OF THIS LICENSE MAY BE OBTAINED FROM THE
7** DISTRIBUTOR OR BY CONTACTING 3DFX INTERACTIVE INC(info@3dfx.com).
8** THIS PROGRAM IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
9** EXPRESSED OR IMPLIED. SEE THE 3DFX GLIDE GENERAL PUBLIC LICENSE FOR A
10** FULL TEXT OF THE NON-WARRANTY PROVISIONS.
11**
12** USE, DUPLICATION OR DISCLOSURE BY THE GOVERNMENT IS SUBJECT TO
13** RESTRICTIONS AS SET FORTH IN SUBDIVISION (C)(1)(II) OF THE RIGHTS IN
14** TECHNICAL DATA AND COMPUTER SOFTWARE CLAUSE AT DFARS 252.227-7013,
15** AND/OR IN SIMILAR OR SUCCESSOR CLAUSES IN THE FAR, DOD OR NASA FAR
16** SUPPLEMENT. UNPUBLISHED RIGHTS RESERVED UNDER THE COPYRIGHT LAWS OF
17** THE UNITED STATES.
18**
19** COPYRIGHT 3DFX INTERACTIVE, INC. 1999, ALL RIGHTS RESERVED
20**
21** $Revision: 1.1 $
22** $Date: 2000-02-25 00:37:55 $
23**
24*/
25
26#ifndef __SST1INIT_H__
27#define __SST1INIT_H__
28
29/*
30** $Revision: 1.1 $
31** $Date: 2000-02-25 00:37:55 $
32**
33** SST-1 Initialization routine protypes
34**
35** If all initialization routines are called, it is assumed they are called
36** in the following order:
37** 1. sst1InitMapBoard();
38** 2. sst1InitRegisters();
39** 3. sst1InitGamma();
40** 4. sst1InitVideoBuffers();
41** 5. sst1InitSli(); [Optional]
42** 6. sst1InitCmdFifo();
43**
44** sst1InitShutdown() is called at the end of an application to turn off
45** the SST-1 graphics subsystem
46**
47*/
48
49/* sst1init.h assumes "glide.h" and "sst.h" are already included */
50
51/* Init code debug print routine */
52#define INIT_OUTPUT
53#define INIT_PRINTF(a) sst1InitPrintf a
54#define INIT_INFO(A)
55
56#ifndef DIRECTX
57#undef GETENV
58#undef ATOI
59#undef ATOF
60#undef SSCANF
61#undef POW
62#define GETENV(A) sst1InitGetenv(A)
63#define ATOI(A) atoi(A)
64#define ATOF(A) atof(A)
65#define SSCANF( A, B, C ) sscanf( A, B, C )
66#define POW( A, B ) pow( A, B )
67#define FTOL( X ) ((FxU32)(X))
68
69// Video resolution declarations
70#include "sst1vid.h"
71
72// Info Structure declaration
73#include "cvginfo.h"
74
75#else /* DIRECTX */
76#include "ddglobal.h"
77#pragma optimize ("",off) /* ddglobal.h tuns this on for retail builds */
78#undef INIT_PRINTF
79#undef INIT_INFO
80#undef GETENV
81#undef ATOI
82#undef ATOF
83#undef FTOL
84#undef ITOF_INV
85#undef SSCANF
86#undef POW
87/* #define INIT_PRINTF(a) */
88#ifdef FXTRACE
89 #define INIT_PRINTF DDPRINTF
90#else
91 #define INIT_PRINTF 1 ? (void) 0 : (void)
92#endif
93#define INIT_INFO(A)
94#define GETENV(A) ddgetenv(A)
95#define ATOI(A) ddatoi(A)
96#define ATOF(A) ddatof(A)
97#define FTOL(A) ddftol(A)
98#define ITOF_INV(A) dd_itof_inv(A)
99#define SSCANF( A, B, C ) ddsscanf( A, B, C )
100#define POW( A, B ) ddpow( A, B )
101
102#endif /* DIRECTX */
103
104/* Defines to writing to/reading from SST-1 */
105#if 0
106#define IGET(A) A
107#define ISET(A,D) A = (D)
108#else
109#define IGET(A) sst1InitRead32((FxU32 *) &(A))
110#define ISET(A,D) sst1InitWrite32((FxU32 *) &(A), D)
111#endif
112
113/*
114** P6 Fence
115**
116** Here's the stuff to do P6 Fencing. This is required for the
117** certain things on the P6
118*/
119#ifdef __cplusplus
120extern "C" {
121#endif
122
123#ifdef SST1INIT_ALLOCATE
124 FxU32 p6FenceVar;
125#else
126 extern FxU32 p6FenceVar;
127#endif
128
129#if defined(__OS2__)
130
131extern void p6Fence(void);
132#define P6FENCE p6Fence()
133
134#elif defined(__WATCOMC__)
135void
136p6Fence(void);
137# pragma aux p6Fence = \
138 "xchg eax, p6FenceVar" \
139 modify [eax];
140# define P6FENCE p6Fence()
141#elif defined(__MSC__)
142# define P6FENCE {_asm xchg eax, p6FenceVar}
143#elif defined(macintosh) && __POWERPC__ && defined(__MWERKS__)
144# define P6FENCE __eieio()
145#elif defined(__GNUC__) && defined(__i386__)
146# define P6FENCE asm("xchg %%eax,%0" : /*outputs*/ : "m" (p6FenceVar) : \
147 "eax");
148#else
149# error "P6 Fencing in-line assembler code needs to be added for this compiler"
150#endif
151
152#ifdef __cplusplus
153}
154#endif
155
156#ifndef _FXPCI_H_
157#include <fxpci.h>
158#endif
159#include <sst1_pci.h>
160
161/*--------------------------------------------------------*/
162/* Following defines need to go in "cvgdefs.h" eventually */
163#define SST_CMDFIFO_ADDR BIT(21)
164
165/*--------- SST PCI Configuration Command bits --------------*/
166#define SST_PCIMEM_ACCESS_EN BIT(1)
167
168/*------- SST PCI Configuration Register defaults -----------*/
169#define SST_PCI_INIT_ENABLE_DEFAULT 0x0
170#define SST_PCI_BUS_SNOOP_DEFAULT 0x0
171
172/*--- SST PCI Init Enable Configuration Register defaults ---*/
173#define SST_SLI_OWNPCI SST_SCANLINE_SLV_OWNPCI
174#define SST_SLI_MASTER_OWNPCI 0x0
175#define SST_SLI_SLAVE_OWNPCI SST_SCANLINE_SLV_OWNPCI
176#define SST_CHUCK_REVISION_ID_SHIFT 12
177#define SST_CHUCK_REVISION_ID (0xF<<SST_CHUCK_REVISION_ID_SHIFT)
178#define SST_CHUCK_MFTG_ID_SHIFT 16
179#define SST_CHUCK_MFTG_ID (0xF<<SST_CHUCK_MFTG_ID_SHIFT)
180#define SST_PCI_INTR_EN BIT(20)
181#define SST_PCI_INTR_TIMEOUT_EN BIT(21)
182#define SST_SLI_SNOOP_EN BIT(23)
183#define SST_SLI_SNOOP_MEMBASE_SHIFT 24
184#define SST_SLI_SNOOP_MEMBASE (0xFF<<SST_SLI_SNOOP_MEMBASE_SHIFT)
185
186/*------- SST Silicon Process Monitor Register Defines ------*/
187#define SST_SIPROCESS_OSC_CNTR 0xFFFF
188#define SST_SIPROCESS_PCI_CNTR_SHIFT 16
189#define SST_SIPROCESS_PCI_CNTR (0xFFF<<SST_SIPROCESS_PCI_CNTR_SHIFT)
190#define SST_SIPROCESS_OSC_CNTR_RESET_N 0
191#define SST_SIPROCESS_OSC_CNTR_RUN BIT(28)
192#define SST_SIPROCESS_OSC_NAND_SEL 0
193#define SST_SIPROCESS_OSC_NOR_SEL BIT(29)
194#define SST_SIPROCESS_OSC_FORCE_ENABLE BIT(30)
195
196/*----------------- SST fbiinit0 bits -----------------------*/
197//#define SST_FBIINIT0_DEFAULT 0x00000410
198// Must include SST_EN_TEX_MEMFIFO and SST_EN_LFB_MEMFIFO in FBIINIT0_DEFAULT
199// or else texture memory detection will hang on some machines (see bug_3.c)
200#define SST_FBIINIT0_DEFAULT (0x00000410 | SST_EN_TEX_MEMFIFO | \
201 SST_EN_LFB_MEMFIFO)
202#define SST_GRX_RESET BIT(1)
203#define SST_PCI_FIFO_RESET BIT(2)
204#define SST_EN_ENDIAN_SWAPPING BIT(3)
205
206/*----------------- SST fbiinit1 bits -----------------------*/
207#define SST_FBIINIT1_DEFAULT 0x00201102
208#define SST_VIDEO_TILES_MASK 0x010000F0
209#define SST_VIDEO_TILES_IN_X_MSB_SHIFT 24
210#define SST_VIDEO_TILES_IN_X_MSB (1<<SST_VIDEO_TILES_IN_X_MSB_SHIFT)
211
212/*----------------- SST fbiinit2 bits -----------------------*/
213#define SST_FBIINIT2_DEFAULT 0x80000040
214#define SST_SWAP_ALGORITHM_SHIFT 9
215#define SST_SWAP_ALGORITHM (0x3<<SST_SWAP_ALGORITHM_SHIFT)
216# define SST_SWAP_VSYNC (0<<SST_SWAP_ALGORITHM_SHIFT)
217# define SST_SWAP_DACDATA0 (1<<SST_SWAP_ALGORITHM_SHIFT)
218# define SST_SWAP_FIFOSTALL (2<<SST_SWAP_ALGORITHM_SHIFT)
219# define SST_SWAP_SLISYNC (3<<SST_SWAP_ALGORITHM_SHIFT)
220#define SST_DRAM_REFRESH_16MS (0x30 << SST_DRAM_REFRESH_CNTR_SHIFT)
221
222/*----------------- SST fbiinit3 bits -----------------------*/
223#define SST_TEXMAP_DISABLE BIT(6)
224#define SST_FBI_MEM_TYPE_SHIFT 8
225#define SST_FBI_MEM_TYPE (0x7<<SST_FBI_MEM_TYPE_SHIFT)
226#define SST_FBI_VGA_PASS_POWERON BIT(12)
227#define SST_FT_CLK_DEL_ADJ_SHIFT 13
228#define SST_FT_CLK_DEL_ADJ (0xF<<SST_FT_CLK_DEL_ADJ_SHIFT)
229#define SST_TF_FIFO_THRESH_SHIFT 17
230#define SST_TF_FIFO_THRESH (0x1F<<SST_TF_FIFO_THRESH_SHIFT)
231#define SST_FBIINIT3_DEFAULT (0x001E4000|SST_TEXMAP_DISABLE)
232
233/*----------------- SST fbiinit4 bits -----------------------*/
234#define SST_FBIINIT4_DEFAULT 0x00000001
235#define SST_PCI_RDWS_1 0x0
236#define SST_PCI_RDWS_2 BIT(0)
237#define SST_EN_LFB_RDAHEAD BIT(1)
238#define SST_MEM_FIFO_LWM_SHIFT 2
239#define SST_MEM_FIFO_LWM (0x3F<<SST_MEM_FIFO_LWM_SHIFT)
240#define SST_MEM_FIFO_ROW_BASE_SHIFT 8
241#define SST_MEM_FIFO_ROW_BASE (0x3FF<<SST_MEM_FIFO_ROW_BASE_SHIFT)
242#define SST_MEM_FIFO_ROW_ROLL_SHIFT 18
243#define SST_MEM_FIFO_ROW_ROLL (0x3FF<<SST_MEM_FIFO_ROW_ROLL_SHIFT)
244
245/*----------------- SST fbiinit5 bits -----------------------*/
246#define SST_DAC_24BPP_PORT BIT(2)
247#define SST_GPIO_0 BIT(3)
248#define SST_GPIO_0_DRIVE0 0x0
249#define SST_GPIO_0_DRIVE1 BIT(3)
250#define SST_GPIO_0_SHIFT 3
251#define SST_GPIO_1 BIT(4)
252#define SST_GPIO_1_DRIVE0 0x0
253#define SST_GPIO_1_DRIVE1 BIT(4)
254#define SST_GPIO_1_SHIFT 4
255#define SST_BUFFER_ALLOC_SHIFT 9
256#define SST_BUFFER_ALLOC (0x3 << SST_BUFFER_ALLOC_SHIFT)
257# define SST_BUFFER_ALLOC_2C0Z (0x0 << SST_BUFFER_ALLOC_SHIFT)
258# define SST_BUFFER_ALLOC_2C1Z (0x0 << SST_BUFFER_ALLOC_SHIFT)
259# define SST_BUFFER_ALLOC_3C0Z (0x1 << SST_BUFFER_ALLOC_SHIFT)
260# define SST_BUFFER_ALLOC_3C1Z (0x2 << SST_BUFFER_ALLOC_SHIFT)
261#define SST_VIDEO_CLK_SLAVE_OE_EN BIT(11)
262#define SST_VID_CLK_2X_OUT_OE_EN BIT(12)
263#define SST_VID_CLK_DAC_DATA16_SEL BIT(13)
264#define SST_SLI_DETECT BIT(14)
265#define SST_HVRETRACE_SYNC_READS BIT(15)
266#define SST_COLOR_BORDER_RIGHT_EN BIT(16)
267#define SST_COLOR_BORDER_LEFT_EN BIT(17)
268#define SST_COLOR_BORDER_BOTTOM_EN BIT(18)
269#define SST_COLOR_BORDER_TOP_EN BIT(19)
270#define SST_SCAN_DOUBLE_HORIZ BIT(20)
271#define SST_SCAN_DOUBLE_VERT BIT(21)
272#define SST_GAMMA_CORRECT_16BPP_EN BIT(22)
273#define SST_INVERT_HSYNC BIT(23)
274#define SST_INVERT_VSYNC BIT(24)
275#define SST_VIDEO_OUT_24BPP_EN BIT(25)
276#define SST_GPIO_1_SEL BIT(27)
277#define SST_FBIINIT5_DEFAULT \
278 (SST_HVRETRACE_SYNC_READS | \
279 SST_GAMMA_CORRECT_16BPP_EN | \
280 SST_GPIO_1_SEL)
281
282/*----------------- SST fbiinit6 bits -----------------------*/
283#define SST_SLI_SWAP_VACTIVE_SHIFT 0
284#define SST_SLI_SWAP_VACTIVE (0x7<<SST_SLI_SWAP_VACTIVE_SHIFT)
285#define SST_SLI_SWAP_VACTIVE_DRAG_SHIFT 3
286#define SST_SLI_SWAP_VACTIVE_DRAG (0x1F<<SST_SLI_SWAP_VACTIVE_DRAG_SHIFT)
287#define SST_SLI_SYNC_MASTER BIT(8)
288#define SST_GPIO_2 (0x3<<9)
289#define SST_GPIO_2_DRIVE0 (0x2<<9)
290#define SST_GPIO_2_DRIVE1 (0x3<<9)
291#define SST_GPIO_2_FLOAT (0x1<<9)
292#define SST_GPIO_2_SHIFT 9
293#define SST_GPIO_3 (0x3<<11)
294#define SST_GPIO_3_DRIVE0 (0x2<<11)
295#define SST_GPIO_3_DRIVE1 (0x3<<11)
296#define SST_GPIO_3_FLOAT (0x1<<11)
297#define SST_GPIO_3_SHIFT 11
298#define SST_SLI_SYNCIN (0x3<<13)
299#define SST_SLI_SYNCIN_DRIVE0 (0x2<<13)
300#define SST_SLI_SYNCIN_DRIVE1 (0x3<<13)
301#define SST_SLI_SYNCIN_FLOAT (0x1<<13)
302#define SST_SLI_SYNCOUT (0x3<<15)
303#define SST_SLI_SYNCOUT_DRIVE0 (0x2<<15)
304#define SST_SLI_SYNCOUT_DRIVE1 (0x3<<15)
305#define SST_SLI_SYNCOUT_FLOAT (0x1<<15)
306#define SST_DAC_RD (0x3<<17)
307#define SST_DAC_RD_DRIVE0 (0x2<<17)
308#define SST_DAC_RD_DRIVE1 (0x3<<17)
309#define SST_DAC_RD_FLOAT (0x1<<17)
310#define SST_DAC_WR (0x3<<19)
311#define SST_DAC_WR_DRIVE0 (0x2<<19)
312#define SST_DAC_WR_DRIVE1 (0x3<<19)
313#define SST_DAC_WR_FLOAT (0x1<<19)
314#define SST_PCI_FIFO_LWM_RDY_SHIFT 21
315#define SST_PCI_FIFO_LWM_RDY (0x7f<<SST_PCI_FIFO_LWM_RDY_SHIFT)
316#define SST_VGA_PASS_N (0x3<<28)
317#define SST_VGA_PASS_N_DRIVE0 (0x2<<28)
318#define SST_VGA_PASS_N_DRIVE1 (0x3<<28)
319#define SST_VIDEO_TILES_IN_X_LSB_SHIFT 30
320#define SST_VIDEO_TILES_IN_X_LSB (1<<SST_VIDEO_TILES_IN_X_LSB_SHIFT)
321#define SST_FBIINIT6_DEFAULT 0x0
322
323/*----------------- SST fbiinit7 bits -----------------------*/
324#define SST_CMDFIFO_EN BIT(8)
325#define SST_CMDFIFO_STORE_OFFSCREEN BIT(9)
326#define SST_CMDFIFO_DISABLE_HOLES BIT(10)
327#define SST_CMDFIFO_RDFETCH_THRESH_SHIFT 11
328#define SST_CMDFIFO_RDFETCH_THRESH (0x1FUL<<SST_CMDFIFO_RDFETCH_THRESH_SHIFT)
329#define SST_CMDFIFO_SYNC_WRITES BIT(16)
330#define SST_CMDFIFO_SYNC_READS BIT(17)
331#define SST_PCI_PACKER_RESET BIT(18)
332#define SST_TMU_CHROMA_REG_WR_EN BIT(19)
333#define SST_CMDFIFO_PCI_TIMEOUT_SHIFT 20
334#define SST_CMDFIFO_PCI_TIMEOUT (0x7FUL<<SST_CMDFIFO_PCI_TIMEOUT_SHIFT)
335#define SST_TEXMEMWR_BURST_EN BIT(27)
336#define SST_FBIINIT7_DEFAULT \
337 (SST_TEXMEMWR_BURST_EN | SST_TMU_CHROMA_REG_WR_EN)
338
339/*----------------- SST trexInit0 bits -----------------------*/
340#define SST_EN_TEX_MEM_REFRESH BIT(0)
341#define SST_TEX_MEM_REFRESH_SHIFT 1
342#define SST_TEX_MEM_REFRESH (0x1FF<<SST_TEX_MEM_REFRESH_SHIFT)
343#define SST_TEX_MEM_PAGE_SIZE_SHIFT 10
344#define SST_TEX_MEM_PAGE_SIZE_8BITS (0x0<<SST_TEX_MEM_PAGE_SIZE_SHIFT)
345#define SST_TEX_MEM_PAGE_SIZE_9BITS (0x1<<SST_TEX_MEM_PAGE_SIZE_SHIFT)
346#define SST_TEX_MEM_PAGE_SIZE_10BITS (0x2<<SST_TEX_MEM_PAGE_SIZE_SHIFT)
347#define SST_TEX_MEM_SECOND_RAS_BIT_SHIFT 12
348#define SST_TEX_MEM_SECOND_RAS_BIT_BIT17 (0x0<<SST_TEX_MEM_SECOND_RAS_BIT_SHIFT)
349#define SST_TEX_MEM_SECOND_RAS_BIT_BIT18 (0x1<<SST_TEX_MEM_SECOND_RAS_BIT_SHIFT)
350#define SST_EN_TEX_MEM_SECOND_RAS BIT(14)
351#define SST_TEX_MEM_TYPE_SHIFT 15
352#define SST_TEX_MEM_TYPE_EDO (0x0<<SST_TEX_MEM_TYPE_SHIFT)
353#define SST_TEX_MEM_TYPE_SYNC (0x1<<SST_TEX_MEM_TYPE_SHIFT)
354#define SST_TEX_MEM_DATA_SIZE_16BIT 0x0
355#define SST_TEX_MEM_DATA_SIZE_8BIT BIT(18)
356#define SST_TEX_MEM_DO_EXTRA_CAS BIT(19)
357#define SST_TEX_MEM2 BIT(20)
358
359#define SST_TREXINIT0_DEFAULT \
360 ( (SST_EN_TEX_MEM_REFRESH) \
361 | (0x020 << SST_TEX_MEM_REFRESH_SHIFT) \
362 | (SST_TEX_MEM_PAGE_SIZE_9BITS) \
363 | (SST_TEX_MEM_SECOND_RAS_BIT_BIT18) \
364 | (SST_EN_TEX_MEM_SECOND_RAS) \
365 | (SST_TEX_MEM_TYPE_EDO) \
366 | (SST_TEX_MEM_DATA_SIZE_16BIT) \
367 | (0 & SST_TEX_MEM_DO_EXTRA_CAS) \
368 | (0 & SST_TEX_MEM2) )
369
370#define SST_TREX0INIT0_DEFAULT SST_TREXINIT0_DEFAULT
371#define SST_TREX1INIT0_DEFAULT SST_TREXINIT0_DEFAULT
372#define SST_TREX2INIT0_DEFAULT SST_TREXINIT0_DEFAULT
373
374/*----------------- SST trexInit1 bits -----------------------*/
375#define SST_TEX_SCANLINE_INTERLEAVE_MASTER 0x0
376#define SST_TEX_SCANLINE_INTERLEAVE_SLAVE BIT(0)
377#define SST_EN_TEX_SCANLINE_INTERLEAVE BIT(1)
378#define SST_TEX_FT_FIFO_SIL_SHIFT 2
379#define SST_TEX_FT_FIFO_SIL (0x1F<<SST_TEX_FT_FIFO_SIL_SHIFT)
380#define SST_TEX_TT_FIFO_SIL_SHIFT 7
381#define SST_TEX_TT_FIFO_SIL (0xF<<SST_TEX_TT_FIFO_SIL_SHIFT)
382#define SST_TEX_TF_CLK_DEL_ADJ_SHIFT 12
383#define SST_TEX_TF_CLK_DEL_ADJ (0xF<<SST_TEX_TF_CLK_DEL_ADJ_SHIFT)
384#define SST_TEX_RG_TTCII_INH BIT(16)
385#define SST_TEX_USE_RG_TTCII_INH BIT(17)
386#define SST_TEX_SEND_CONFIG BIT(18)
387#define SST_TEX_RESET_FIFO BIT(19)
388#define SST_TEX_RESET_GRX BIT(20)
389#define SST_TEX_PALETTE_DEL_SHIFT 21
390#define SST_TEX_PALETTE_DEL (0x3<<SST_TEX_PALETTE_DEL_SHIFT)
391#define SST_TEX_SEND_CONFIG_SEL_SHIFT 23
392#define SST_TEX_SEND_CONFIG_SEL (0x7<<SST_TEX_SEND_CONFIG_SEL_SHIFT)
393
394/* After things stabilize, the fifo stall inputs levels should be backed off
395
396 from the max. conservative values that are being used now for better
397 performance.
398 SST_TEX_FT_FIFO_SIL = ??
399 SST_TEX_TT_FIFO_SIL = ?? (effects multi-trex only)
400 */
401
402/* for trex ver. 1 bringup, SST_TEX_PALETTE_DEL should be set to it's max
403 (== 3) for <50 MHz bringup */
404
405#define SST_TREXINIT1_DEFAULT \
406 ( (SST_TEX_SCANLINE_INTERLEAVE_MASTER) \
407 | (0 & SST_EN_TEX_SCANLINE_INTERLEAVE) \
408 | (0x8 << SST_TEX_FT_FIFO_SIL_SHIFT) \
409 | (0x8 << SST_TEX_TT_FIFO_SIL_SHIFT) \
410 | (0xf << SST_TEX_TF_CLK_DEL_ADJ_SHIFT) \
411 | (0 & SST_TEX_RG_TTCII_INH) \
412 | (0 & SST_TEX_USE_RG_TTCII_INH) \
413 | (0 & SST_TEX_SEND_CONFIG) \
414 | (0 & SST_TEX_RESET_FIFO) \
415 | (0 & SST_TEX_RESET_GRX) \
416 | (0 << SST_TEX_PALETTE_DEL_SHIFT) \
417 | (0 << SST_TEX_SEND_CONFIG_SEL_SHIFT) )
418
419#define SST_TREX0INIT1_DEFAULT SST_TREXINIT1_DEFAULT
420#define SST_TREX1INIT1_DEFAULT SST_TREXINIT1_DEFAULT
421#define SST_TREX2INIT1_DEFAULT SST_TREXINIT1_DEFAULT
422
423/*----------------- SST clutData bits -----------------------*/
424#define SST_CLUTDATA_INDEX_SHIFT 24
425#define SST_CLUTDATA_RED_SHIFT 16
426#define SST_CLUTDATA_GREEN_SHIFT 8
427#define SST_CLUTDATA_BLUE_SHIFT 0
428
429/*----------------- SST video setup shifts ------------------*/
430#define SST_VIDEO_HSYNC_OFF_SHIFT 16
431#define SST_VIDEO_HSYNC_ON_SHIFT 0
432#define SST_VIDEO_VSYNC_OFF_SHIFT 16
433#define SST_VIDEO_VSYNC_ON_SHIFT 0
434#define SST_VIDEO_HBACKPORCH_SHIFT 0
435#define SST_VIDEO_VBACKPORCH_SHIFT 16
436#define SST_VIDEO_XDIM_SHIFT 0
437#define SST_VIDEO_YDIM_SHIFT 16
438
439/*----------------- SST dacData constants -------------------*/
440#define SST_DACREG_WMA 0x0
441#define SST_DACREG_LUT 0x1
442#define SST_DACREG_RMR 0x2
443#define SST_DACREG_RMA 0x3
444#define SST_DACREG_ICS_PLLADDR_WR 0x4 /* ICS only */
445#define SST_DACREG_ICS_PLLADDR_RD 0x7 /* ICS only */
446#define SST_DACREG_ICS_PLLADDR_DATA 0x5 /* ICS only */
447#define SST_DACREG_ICS_CMD 0x6 /* ICS only */
448#define SST_DACREG_ICS_COLORMODE_16BPP 0x50 /* ICS only */
449#define SST_DACREG_ICS_COLORMODE_24BPP 0x70 /* ICS only */
450#define SST_DACREG_ICS_PLLADDR_VCLK0 0x0 /* ICS only */
451#define SST_DACREG_ICS_PLLADDR_VCLK1 0x1 /* ICS only */
452#define SST_DACREG_ICS_PLLADDR_VCLK7 0x7 /* ICS only */
453#define SST_DACREG_ICS_PLLADDR_VCLK1_DEFAULT 0x55 /* ICS only */
454#define SST_DACREG_ICS_PLLADDR_VCLK7_DEFAULT 0x71 /* ICS only */
455#define SST_DACREG_ICS_PLLADDR_GCLK0 0xa /* ICS only */
456#define SST_DACREG_ICS_PLLADDR_GCLK1 0xb /* ICS only */
457#define SST_DACREG_ICS_PLLADDR_GCLK1_DEFAULT 0x79 /* ICS only */
458#define SST_DACREG_ICS_PLLADDR_CTRL 0xe /* ICS only */
459#define SST_DACREG_ICS_PLLCTRL_CLK1SEL BIT(4)
460#define SST_DACREG_ICS_PLLCTRL_CLK0SEL BIT(5)
461#define SST_DACREG_ICS_PLLCTRL_CLK0FREQ 0x7
462#define SST_DACREG_INDEXADDR SST_DACREG_WMA
463#define SST_DACREG_INDEXDATA SST_DACREG_RMR
464#define SST_DACREG_INDEX_RMR 0x0
465#define SST_DACREG_INDEX_CR0 0x1
466#define SST_DACREG_INDEX_MIR 0x2
467#define SST_DACREG_INDEX_MIR_ATT_DEFAULT 0x84 /* AT&T */
468#define SST_DACREG_INDEX_MIR_TI_DEFAULT 0x97 /* TI */
469#define SST_DACREG_INDEX_DIR 0x3
470#define SST_DACREG_INDEX_DIR_ATT_DEFAULT 0x9 /* AT&T */
471#define SST_DACREG_INDEX_DIR_TI_DEFAULT 0x9 /* TI */
472#define SST_DACREG_INDEX_TST 0x4
473#define SST_DACREG_INDEX_CR1 0x5
474#define SST_DACREG_INDEX_CC 0x6
475#define SST_DACREG_INDEX_AA0 0xff /* can't access */
476#define SST_DACREG_INDEX_AA1 0xff /* can't access */
477#define SST_DACREG_INDEX_AB0 0xff /* can't access */
478#define SST_DACREG_INDEX_AB1 0xff /* can't access */
479#define SST_DACREG_INDEX_AB2 0xff /* can't access */
480#define SST_DACREG_INDEX_AC0 0x48
481#define SST_DACREG_INDEX_AC1 0x49
482#define SST_DACREG_INDEX_AC2 0x4a
483#define SST_DACREG_INDEX_AD0 0x4c
484#define SST_DACREG_INDEX_AD1 0x4d
485#define SST_DACREG_INDEX_AD2 0x4e
486#define SST_DACREG_INDEX_BA0 0xff /* can't access */
487#define SST_DACREG_INDEX_BA1 0xff /* can't access */
488#define SST_DACREG_INDEX_BB0 0xff /* can't access */
489#define SST_DACREG_INDEX_BB1 0xff /* can't access */
490#define SST_DACREG_INDEX_BB2 0xff /* can't access */
491#define SST_DACREG_INDEX_BC0 0xff /* can't access */
492#define SST_DACREG_INDEX_BC1 0xff /* can't access */
493#define SST_DACREG_INDEX_BC2 0xff /* can't access */
494#define SST_DACREG_INDEX_BD0 0x6c
495#define SST_DACREG_INDEX_BD1 0x6d
496#define SST_DACREG_INDEX_BD2 0x6e
497
498#define SST_DACREG_CR0_INDEXED_ADDRESSING BIT(0)
499#define SST_DACREG_CR0_8BITDAC BIT(1)
500#define SST_DACREG_CR0_SLEEP BIT(3)
501#define SST_DACREG_CR0_COLOR_MODE_SHIFT 4
502#define SST_DACREG_CR0_COLOR_MODE (0xF<<SST_DACREG_CR0_COLOR_MODE_SHIFT)
503#define SST_DACREG_CR0_COLOR_MODE_16BPP (0x3<<SST_DACREG_CR0_COLOR_MODE_SHIFT)
504#define SST_DACREG_CR0_COLOR_MODE_24BPP (0x5<<SST_DACREG_CR0_COLOR_MODE_SHIFT)
505
506#define SST_DACREG_CR1_BLANK_PEDASTAL_EN BIT(4)
507
508#define SST_DACREG_CC_BCLK_SEL_SHIFT 0
509#define SST_DACREG_CC_BCLK_SELECT_BD BIT(3)
510#define SST_DACREG_CC_ACLK_SEL_SHIFT 4
511#define SST_DACREG_CC_ACLK_SELECT_AD BIT(7)
512
513#define SST_DACREG_CLKREG_MSHIFT 0
514#define SST_DACREG_CLKREG_PSHIFT 6
515#define SST_DACREG_CLKREG_NSHIFT 0
516#define SST_DACREG_CLKREG_LSHIFT 4
517#define SST_DACREG_CLKREG_IBSHIFT 0
518
519#define SST_FBI_DACTYPE_ATT 0
520#define SST_FBI_DACTYPE_ICS 1
521#define SST_FBI_DACTYPE_TI 2
522
523/* Definitions for parsing voodoo.ini file */
524#define DACRDWR_TYPE_WR 0
525#define DACRDWR_TYPE_RDMODWR 1
526#define DACRDWR_TYPE_RDNOCHECK 2
527#define DACRDWR_TYPE_RDCHECK 3
528#define DACRDWR_TYPE_RDPUSH 4
529#define DACRDWR_TYPE_WRMOD_POP 5
530
531/* Other useful defines */
532#define PCICFG_WR(ADDR, DATA) \
533 n = DATA; \
534 if(pciSetConfigData(ADDR, sst1InitDeviceNumber, &n) == FXFALSE) \
535 return(FXFALSE)
536#define PCICFG_RD(ADDR, DATA) \
537 if(pciGetConfigData(ADDR, sst1InitDeviceNumber, &DATA) == FXFALSE) \
538 return(FXFALSE)
539#define DAC_INDEXWRADDR(ADDR) \
540 sst1InitDacWr(sstbase, SST_DACREG_INDEXADDR, ADDR)
541#define DAC_INDEXWR(DATA) \
542 sst1InitDacWr(sstbase, SST_DACREG_INDEXDATA, (DATA))
543#define DAC_INDEXRD() \
544 sst1InitDacRd(sstbase, SST_DACREG_INDEXDATA)
545
546/*-----------------------------------------------------------*/
547
548/*
549** SST-1 Initialization typedefs
550**
551*/
552
553#ifdef __cplusplus
554extern "C" {
555#endif
556
557typedef struct {
558 float freq;
559 FxU32 clkTiming_M;
560 FxU32 clkTiming_P;
561 FxU32 clkTiming_N;
562 FxU32 clkTiming_L;
563 FxU32 clkTiming_IB;
564} sst1ClkTimingStruct;
565
566typedef struct {
567 unsigned char type;
568 unsigned char addr;
569 FxU32 data;
570 FxU32 mask;
571 void *nextRdWr;
572} sst1InitDacRdWrStruct;
573
574typedef struct {
575 FxU32 width;
576 FxU32 height;
577 FxU32 refresh;
578 FxU32 video16BPP;
579 sst1InitDacRdWrStruct *setVideoRdWr;
580 void *nextSetVideo;
581} sst1InitDacSetVideoStruct;
582
583typedef struct {
584 FxU32 frequency;
585 sst1InitDacRdWrStruct *setMemClkRdWr;
586 void *nextSetMemClk;
587} sst1InitDacSetMemClkStruct;
588
589typedef struct {
590 FxU32 video16BPP;
591 sst1InitDacRdWrStruct *setVideoModeRdWr;
592 void *nextSetVideoMode;
593} sst1InitDacSetVideoModeStruct;
594
595typedef struct {
596 char dacManufacturer[100];
597 char dacDevice[100];
598 sst1InitDacRdWrStruct *detect;
599 sst1InitDacSetVideoStruct *setVideo;
600 sst1InitDacSetMemClkStruct *setMemClk;
601 sst1InitDacSetVideoModeStruct *setVideoMode;
602 void *nextDac;
603} sst1InitDacStruct;
604
605#define kMaxEnvVarLen 100
606#define kMaxEnvValLen 256
607typedef struct {
608 char envVariable[kMaxEnvVarLen];
609 char envValue[kMaxEnvValLen];
610 void *nextVar;
611} sst1InitEnvVarStruct;
612
613FX_ENTRY FxU32 * FX_CALL sst1InitMapBoard(FxU32);
614FX_ENTRY FxU32 * FX_CALL sst1InitMapBoardDirect(FxU32, FxBool);
615FX_ENTRY FxU32 FX_CALL sst1InitNumBoardsInSystem(void);
616FX_ENTRY FxBool FX_CALL sst1InitRegisters(FxU32 *);
617FX_ENTRY FxBool FX_CALL sst1InitGamma(FxU32 *, double);
618FX_ENTRY FxBool FX_CALL sst1InitGammaRGB(FxU32 *, double, double, double);
619FX_ENTRY FxBool FX_CALL sst1InitGammaTable(FxU32 *, FxU32, FxU32 *, FxU32 *, FxU32 *);
620// Note: sst1InitVideo() is for compatibility with SST-1 only, and should
621// not be used for Voodoo2. Use sst1InitVideoBuffers() instead
622FX_ENTRY FxBool FX_CALL sst1InitVideo(FxU32 *, GrScreenResolution_t,
623 GrScreenRefresh_t, void *);
624FX_ENTRY FxBool FX_CALL sst1InitVideoBuffers(FxU32 *,
625 GrScreenResolution_t,
626 GrScreenRefresh_t,
627 FxU32,
628 FxU32,
629 sst1VideoTimingStruct *,
630 FxBool);
631FX_ENTRY FxBool FX_CALL sst1InitAllocBuffers(FxU32 *, FxU32, FxU32);
632FX_ENTRY FxBool FX_CALL sst1InitVideoShutdown(FxU32 *, FxBool);
633FX_ENTRY FxBool FX_CALL sst1InitShutdown(FxU32 *);
634FX_ENTRY FxBool FX_CALL sst1InitShutdownSli(FxU32 *);
635FX_ENTRY FxBool FX_CALL sst1InitSli(FxU32 *, FxU32 *);
636FX_ENTRY FxBool FX_CALL sst1InitGetDeviceInfo(FxU32 *, sst1DeviceInfoStruct *);
637FX_ENTRY FxBool FX_CALL sst1InitVideoBorder(FxU32 *, FxU32, FxU32);
638
639/* Miscellaneous routines */
640FX_ENTRY void FX_CALL sst1InitWrite32(FxU32 *, FxU32);
641FX_ENTRY FxU32 FX_CALL sst1InitRead32(FxU32 *);
642FX_ENTRY FxBool FX_CALL sst1InitIdle(FxU32 *);
643FX_ENTRY FxBool FX_CALL sst1InitIdleWithTimeout(FxU32 *, FxU32);
644FX_ENTRY FxBool FX_CALL sst1InitIdleNoNOP(FxU32 *);
645FX_ENTRY FxBool FX_CALL sst1InitIdleFBI(FxU32 *);
646FX_ENTRY FxBool FX_CALL sst1InitIdleFBINoNOP(FxU32 *);
647FX_ENTRY FxU32 FX_CALL sst1InitReturnStatus(FxU32 *);
648FX_ENTRY FxU32 FX_CALL sst1InitDacRd(FxU32 *, FxU32);
649FX_ENTRY void FX_CALL sst1InitDacWr(FxU32 *, FxU32, FxU32);
650FxBool sst1InitExecuteDacRdWr(FxU32 *, sst1InitDacRdWrStruct *);
651FX_ENTRY void FX_CALL sst1InitSetResolution(FxU32 *, sst1VideoTimingStruct *,
652 FxU32);
653FX_ENTRY FxBool FX_CALL sst1InitDacIndexedEnable(FxU32 *, FxU32);
654FX_ENTRY FxBool FX_CALL sst1InitGrxClk(FxU32 *);
655FX_ENTRY FxBool FX_CALL sst1InitCalcGrxClk(FxU32 *);
656FX_ENTRY FxBool FX_CALL sst1InitDacDetect(FxU32 *);
657FxBool sst1InitDacDetectATT(FxU32 *);
658FxBool sst1InitDacDetectTI(FxU32 *);
659FxBool sst1InitDacDetectICS(FxU32 *);
660FxBool sst1InitDacDetectINI(FxU32 *);
661FX_ENTRY FxBool FX_CALL sst1InitSetGrxClk(FxU32 *, sst1ClkTimingStruct *);
662FX_ENTRY FxBool FX_CALL sst1InitComputeClkParams(float, sst1ClkTimingStruct *);
663FxBool sst1InitComputeClkParamsATT(float, sst1ClkTimingStruct *);
664FxBool sst1InitComputeClkParamsTI(float, sst1ClkTimingStruct *);
665FxBool sst1InitSetGrxClkATT(FxU32 *, sst1ClkTimingStruct *);
666FxBool sst1InitSetGrxClkICS(FxU32 *, sst1ClkTimingStruct *);
667FxBool sst1InitSetGrxClkINI(FxU32 *, sst1ClkTimingStruct *);
668FX_ENTRY FxBool FX_CALL sst1InitSetVidClk(FxU32 *, float);
669FxBool sst1InitSetVidClkATT(FxU32 *, sst1ClkTimingStruct *);
670FxBool sst1InitSetVidClkICS(FxU32 *, sst1ClkTimingStruct *);
671FxBool sst1InitSetVidClkINI(FxU32 *, FxU32, FxU32, FxU32, FxU32);
672FxBool sst1InitSetVidMode(FxU32 *, FxU32);
673FxBool sst1InitSetVidModeATT(FxU32 *, FxU32);
674FxBool sst1InitSetVidModeICS(FxU32 *, FxU32);
675FxBool sst1InitSetVidModeINI(FxU32 *, FxU32);
676FX_ENTRY FxBool FX_CALL sst1InitCheckBoard(FxU32 *);
677FX_ENTRY FxBool FX_CALL sst1InitGetFbiInfo(FxU32 *, sst1DeviceInfoStruct *);
678FX_ENTRY FxBool FX_CALL sst1InitGetTmuInfo(FxU32 *, sst1DeviceInfoStruct *);
679FX_ENTRY void FX_CALL sst1InitRenderingRegisters(FxU32 *);
680FX_ENTRY FxBool FX_CALL sst1InitGetTmuMemory(FxU32 *sstbase,
681 sst1DeviceInfoStruct *info, FxU32 tmu, FxU32 *TmuMemorySize);
682FX_ENTRY FxBool FX_CALL sst1InitClearSwapPending(FxU32 *);
683FX_ENTRY FxBool FX_CALL sst1InitVgaPassCtrl(FxU32 *, FxU32);
684FX_ENTRY FxBool FX_CALL sst1InitResetFbi(FxU32 *);
685FX_ENTRY FxBool FX_CALL sst1InitResetTmus(FxU32 *);
686FX_ENTRY FxU32 FX_CALL sst1InitSliDetect(FxU32 *);
687FX_ENTRY FxU32 FX_CALL sst1InitSliPaired(FxU32 *);
688FX_ENTRY FxBool FX_CALL sst1InitVoodooFile(void);
689FX_ENTRY char * FX_CALL sst1InitGetenv(char *);
690FX_ENTRY FxU32 * FX_CALL sst1InitGetBaseAddr(FxU32);
691FxBool sst1InitFillDeviceInfo(FxU32 *, sst1DeviceInfoStruct *);
692void sst1InitIdleLoop(FxU32 *, FxBool);
693int sst1InitIdleWithTimeoutLoop(FxU32 *, FxBool, FxU32);
694void sst1InitPciFifoIdleLoop(FxU32 *);
695void sst1InitClearBoardInfo(void);
696FX_ENTRY FxBool FX_CALL sst1InitCaching(FxU32* sstBase, FxBool enableP);
697FX_ENTRY void FX_CALL sst1InitPrintInitRegs(FxU32 *);
698FX_ENTRY sst1VideoTimingStruct* FX_CALL
699sst1InitFindVideoTimingStruct(GrScreenResolution_t, GrScreenRefresh_t);
700FX_ENTRY FxU32 FX_CALL sst1InitMeasureSiProcess(FxU32 *, FxU32);
701
702FX_ENTRY FxBool FX_CALL sst1InitCmdFifo(FxU32 *, FxBool, FxU32 *, FxU32 *,
703 FxU32 *, FxSet32Proc);
704FX_ENTRY FxBool FX_CALL sst1InitCmdFifoDirect(FxU32 *, FxU32, FxU32, FxU32,
705 FxBool, FxBool, FxSet32Proc);
706FX_ENTRY FxBool FX_CALL sst1InitLfbLock(FxU32 *);
707FX_ENTRY FxBool FX_CALL sst1InitLfbLockDirect(FxU32 *);
708FX_ENTRY FxBool FX_CALL sst1InitLfbUnlock(FxU32 *);
709FX_ENTRY FxBool FX_CALL sst1InitLfbUnlockDirect(FxU32 *);
710FxU32 sst1InitConvertRefreshRate( FxU32 );
711FX_ENTRY FxBool FX_CALL sst1InitMonitorDetect(FxU32 *);
712FX_ENTRY FxBool FX_CALL sst1InitCalcTClkDelay(FxU32 *, FxU32, FxU32);
713FX_ENTRY FxBool FX_CALL sst1InitSetClkDelays(FxU32 *);
714void sst1InitCheckTmuMemConst(FxU32 *, FxU32, FxU32);
715void sst1InitDrawRectUsingTris(FxU32 *, FxU32, FxU32, FxU32);
716
717#ifdef __cplusplus
718}
719#endif
720
721/* Info/Print routines */
722#ifdef INIT_OUTPUT
723
724#ifdef __cplusplus
725extern "C" {
726#endif
727FX_ENTRY void FX_CALL sst1InitPrintf(const char *, ...);
728#ifdef __cplusplus
729}
730#endif
731
732#ifndef _FILE_DEFINED
733#include <stdio.h>
734#endif
735
736#ifdef __cplusplus
737extern "C" {
738#endif
739
740#ifdef SST1INIT_ALLOCATE
741 FILE *sst1InitMsgFile = NULL;/*stdout;*/
742#else
743extern FILE *sst1InitMsgFile;
744#endif
745
746#ifdef __cplusplus
747}
748#endif
749
750#endif
751
752/* Maximum number of SST-1 boards supported in system */
753#define SST1INIT_MAX_BOARDS 16
754
755/* Maximum number of read pushes in "voodoo.ini" file */
756#define DACRDWR_MAX_PUSH 16
757
758#ifdef __cplusplus
759extern "C" {
760#endif
761
762#ifdef SST1INIT_ALLOCATE
763 static char headersIdent[] = "@#%Voodoo2 InitHeaders $Revision: 1.1 $";
764 FxBool sst1InitUseVoodooFile = FXFALSE;
765 sst1InitEnvVarStruct *envVarsBase = (sst1InitEnvVarStruct *) NULL;
766 sst1InitDacStruct *dacStructBase = (sst1InitDacStruct *) NULL;
767 sst1InitDacStruct *iniDac = (sst1InitDacStruct *) NULL;
768 sst1InitDacSetVideoStruct *iniVideo = (sst1InitDacSetVideoStruct *) NULL;
769 sst1InitDacSetMemClkStruct *iniMemClk = (sst1InitDacSetMemClkStruct *) NULL;
770 FxU32 iniStack[DACRDWR_MAX_PUSH];
771 int iniStackPtr = 0;
772 sst1DeviceInfoStruct *sst1CurrentBoard;
773 FxU32 sst1InitDeviceNumber;
774 sst1DeviceInfoStruct sst1BoardInfo[SST1INIT_MAX_BOARDS];
775 FxU32 boardsInSystem;
776 FxU32 boardsInSystemReally;
777 FxU32 initIdleEnabled = 1;
778
779
780 const PciRegister SST1_PCI_CFG_SCRATCH = { 0x50, 4, READ_WRITE };
781 const PciRegister SST1_PCI_SIPROCESS = { 0x54, 4, READ_WRITE };
782#else
783 extern FxBool sst1InitUseVoodooFile;
784 extern sst1InitEnvVarStruct *envVarsBase;
785 extern sst1InitDacStruct *dacStructBase;
786 extern sst1InitDacStruct *iniDac;
787 extern sst1InitDacSetVideoStruct *iniVideo;
788 extern sst1InitDacSetMemClkStruct *iniMemClk;
789 extern FxU32 iniStack[];
790 extern int iniStackPtr;
791 extern sst1DeviceInfoStruct *sst1CurrentBoard;
792 extern FxU32 sst1InitDeviceNumber;
793 extern sst1DeviceInfoStruct sst1BoardInfo[SST1INIT_MAX_BOARDS];
794 extern FxU32 boardsInSystem;
795 extern FxU32 boardsInSystemReally;
796 extern FxU32 initIdleEnabled;
797
798 extern PciRegister SST1_PCI_CFG_SCRATCH;
799 extern PciRegister SST1_PCI_SIPROCESS;
800#endif /* SST1INIT_ALLOCATE */
801
802#ifdef __3Dfx_PCI_CFG__
803/* This is really ugly, but it makes us happy w/ the top of the tree
804 * pci library which is happier than Gary's library.
805 */
806#define SST1_PCI_INIT_ENABLE PCI_SST1_INIT_ENABLE
807#define SST1_PCI_BUS_SNOOP0 PCI_SST1_BUS_SNOOP_0
808#define SST1_PCI_BUS_SNOOP1 PCI_SST1_BUS_SNOOP_1
809#define SST1_PCI_CFG_STATUS PCI_SST1_CFG_STATUS
810#else /* !__3Dfx_PCI_CFG__ */
811#define SST1_PCI_BUS_SNOOP0 SST1_PCI_BUS_SNOOP_0
812#define SST1_PCI_BUS_SNOOP1 SST1_PCI_BUS_SNOOP_1
813#endif /* !__3Dfx_PCI_CFG__ */
814
815#ifdef __cplusplus
816}
817#endif
818
819#ifdef SST1INIT_VIDEO_ALLOCATE
820/* SST1INIT_VIDEO_ALLOCATE is only #defined in video.c
821
822 Define useful clock and video timings
823 Clocks generated are follows:
824 Clock Freq. (MHz) =
825 [14.318 * (clkTiming_M+2)] / [(clkTiming_N+2) * (2^clkTiming_P)]
826
827 Solving for clkTiming_M yields:
828 clkTiming_M =
829 [ [(Clock Freq (Mhz)) * (clkTiming_N+2) * (2^clkTiming_P)] / 14.318 ] - 2
830
831 NOTE: [14.318 * (clkTiming_M+2)] / (clkTiming_N+2) should be between
832 120 and 240
833 NOTE: Max. M is 127
834 NOTE: Max. N is 31
835 NOTE: Max. P is 3
836 NOTE: Max. L is 15
837 NOTE: Max. IB is 15
838*/
839
840sst1VideoTimingStruct SST_VREZ_320X200_70 = {
841 96, /* hSyncOn */
842 704, /* hSyncOff */
843 2, /* vSyncOn */
844 447, /* vSyncOff */
845 48, /* hBackPorch */
846 35, /* vBackPorch */
847 320, /* xDimension */
848 200, /* yDimension */
849 70, /* refreshRate */
850 0x3, /* miscCtrl */
851 35, /* memOffset */
852 10, /* tilesInX */
853 25, /* vFifoThreshold */
854 FXTRUE, /* video16BPPIsOK */
855 FXTRUE, /* video24BPPIsOK */
856 25.175F, /* clkFreq16bpp */
857 50.350F /* clkFreq24bpp */
858};
859
860sst1VideoTimingStruct SST_VREZ_320X200_75 = {
861 99, /* hSyncOn */
862 733, /* hSyncOff */
863 3, /* vSyncOn */
864 429, /* vSyncOff */
865 52, /* hBackPorch */
866 25, /* vBackPorch */
867 320, /* xDimension */
868 200, /* yDimension */
869 75, /* refreshRate */
870 0x3, /* miscCtrl */
871 35, /* memOffset */
872 10, /* tilesInX */
873 25, /* vFifoThreshold */
874 FXTRUE, /* video16BPPIsOK */
875 FXTRUE, /* video24BPPIsOK */
876 27.0F, /* clkFreq16bpp */
877 54.0F /* clkFreq24bpp */
878};
879
880sst1VideoTimingStruct SST_VREZ_320X200_85 = {
881 63, /* hSyncOn */
882 767, /* hSyncOff */
883 3, /* vSyncOn */
884 442, /* vSyncOff */
885 94, /* hBackPorch */
886 41, /* vBackPorch */
887 320, /* xDimension */
888 200, /* yDimension */
889 85, /* refreshRate */
890 0x3, /* miscCtrl */
891 35, /* memOffset */
892 10, /* tilesInX */
893 23, /* vFifoThreshold */
894 FXTRUE, /* video16BPPIsOK */
895 FXTRUE, /* video24BPPIsOK */
896 31.5F, /* clkFreq16bpp */
897 63.0F /* clkFreq24bpp */
898};
899
900sst1VideoTimingStruct SST_VREZ_320X200_120 = {
901 67, /* hSyncOn */
902 798, /* hSyncOff */
903 3, /* vSyncOn */
904 424, /* vSyncOff */
905 94, /* hBackPorch */
906 16, /* vBackPorch */
907 320, /* xDimension */
908 200, /* yDimension */
909 120, /* refreshRate */
910 0x3, /* miscCtrl */
911 35, /* memOffset */
912 10, /* tilesInX */
913 23, /* vFifoThreshold */
914 FXTRUE, /* video16BPPIsOK */
915 FXTRUE, /* video24BPPIsOK */
916 44.47F, /* clkFreq16bpp */
917 88.94F /* clkFreq24bpp */
918};
919
920sst1VideoTimingStruct SST_VREZ_320X240_60 = {
921 96, /* hSyncOn */
922 704, /* hSyncOff */
923 2, /* vSyncOn */
924 523, /* vSyncOff */
925 38, /* hBackPorch */
926 25, /* vBackPorch */
927 320, /* xDimension */
928 240, /* yDimension */
929 60, /* refreshRate */
930 0x3, /* miscCtrl */
931 40, /* memOffset */
932 10, /* tilesInX */
933 25, /* vFifoThreshold */
934 FXTRUE, /* video16BPPIsOK */
935 FXTRUE, /* video24BPPIsOK */
936 25.175F, /* clkFreq16bpp */
937 50.350F /* clkFreq24bpp */
938};
939
940sst1VideoTimingStruct SST_VREZ_320X240_75 = {
941 63, /* hSyncOn */
942 775, /* hSyncOff */
943 3, /* vSyncOn */
944 497, /* vSyncOff */
945 118, /* hBackPorch */
946 16, /* vBackPorch */
947 320, /* xDimension */
948 240, /* yDimension */
949 75, /* refreshRate */
950 0x3, /* miscCtrl */
951 40, /* memOffset */
952 10, /* tilesInX */
953 25, /* vFifoThreshold */
954 FXTRUE, /* video16BPPIsOK */
955 FXTRUE, /* video24BPPIsOK */
956 31.5F, /* clkFreq16bpp */
957 63.0F /* clkFreq24bpp */
958};
959
960sst1VideoTimingStruct SST_VREZ_320X240_85 = {
961 55, /* hSyncOn */
962 776, /* hSyncOff */
963 3, /* vSyncOn */
964 506, /* vSyncOff */
965 78, /* hBackPorch */
966 25, /* vBackPorch */
967 320, /* xDimension */
968 240, /* yDimension */
969 85, /* refreshRate */
970 0x3, /* miscCtrl */
971 40, /* memOffset */
972 10, /* tilesInX */
973 23, /* vFifoThreshold */
974 FXTRUE, /* video16BPPIsOK */
975 FXTRUE, /* video24BPPIsOK */
976 36.0F, /* clkFreq16bpp */
977 72.0F /* clkFreq24bpp */
978};
979
980sst1VideoTimingStruct SST_VREZ_320X240_120 = {
981 45, /* hSyncOn */
982 785, /* hSyncOff */
983 3, /* vSyncOn */
984 506, /* vSyncOff */
985 100, /* hBackPorch */
986 18, /* vBackPorch */
987 320, /* xDimension */
988 240, /* yDimension */
989 120, /* refreshRate */
990 0x3, /* miscCtrl */
991 40, /* memOffset */
992 10, /* tilesInX */
993 23, /* vFifoThreshold */
994 FXTRUE, /* video16BPPIsOK */
995 FXTRUE, /* video24BPPIsOK */
996 50.82F, /* clkFreq16bpp */
997 101.64F /* clkFreq24bpp */
998};
999
1000sst1VideoTimingStruct SST_VREZ_400X300_60 = {
1001 39, /* hSyncOn */
1002 471, /* hSyncOff */
1003 3, /* vSyncOn */
1004 619, /* vSyncOff */
1005 54, /* hBackPorch */
1006 18, /* vBackPorch */
1007 400, /* xDimension */
1008 300, /* yDimension */
1009 60, /* refreshRate */
1010 0x2, /* miscCtrl */
1011 70, /* memOffset */
1012 14, /* tilesInX */
1013 23, /* vFifoThreshold */
1014 FXTRUE, /* video16BPPIsOK */
1015 FXTRUE, /* video24BPPIsOK */
1016 19.108F, /* clkFreq16bpp */
1017 38.216F /* clkFreq24bpp */
1018};
1019
1020sst1VideoTimingStruct SST_VREZ_400X300_75 = {
1021 39, /* hSyncOn */
1022 487, /* hSyncOff */
1023 3, /* vSyncOn */
1024 624, /* vSyncOff */
1025 62, /* hBackPorch */
1026 23, /* vBackPorch */
1027 400, /* xDimension */
1028 300, /* yDimension */
1029 75, /* refreshRate */
1030 0x2, /* miscCtrl */
1031 70, /* memOffset */
1032 14, /* tilesInX */
1033 23, /* vFifoThreshold */
1034 FXTRUE, /* video16BPPIsOK */
1035 FXTRUE, /* video24BPPIsOK */
1036 24.829F, /* clkFreq16bpp */
1037 49.658F /* clkFreq24bpp */
1038};
1039
1040sst1VideoTimingStruct SST_VREZ_400X300_85 = {
1041 39, /* hSyncOn */
1042 487, /* hSyncOff */
1043 3, /* vSyncOn */
1044 627, /* vSyncOff */
1045 62, /* hBackPorch */
1046 26, /* vBackPorch */
1047 400, /* xDimension */
1048 300, /* yDimension */
1049 85, /* refreshRate */
1050 0x2, /* miscCtrl */
1051 70, /* memOffset */
1052 14, /* tilesInX */
1053 23, /* vFifoThreshold */
1054 FXTRUE, /* video16BPPIsOK */
1055 FXTRUE, /* video24BPPIsOK */
1056 28.274F, /* clkFreq16bpp */
1057 56.548F /* clkFreq24bpp */
1058};
1059
1060sst1VideoTimingStruct SST_VREZ_400X300_120 = {
1061 39, /* hSyncOn */
1062 503, /* hSyncOff */
1063 3, /* vSyncOn */
1064 640, /* vSyncOff */
1065 70, /* hBackPorch */
1066 39, /* vBackPorch */
1067 400, /* xDimension */
1068 300, /* yDimension */
1069 120, /* refreshRate */
1070 0x2, /* miscCtrl */
1071 70, /* memOffset */
1072 14, /* tilesInX */
1073 23, /* vFifoThreshold */
1074 FXTRUE, /* video16BPPIsOK */
1075 FXTRUE, /* video24BPPIsOK */
1076 41.975F, /* clkFreq16bpp */
1077 83.950F /* clkFreq24bpp */
1078};
1079
1080/* 512x256@60 only syncs to Arcade-style monitors */
1081sst1VideoTimingStruct SST_VREZ_512X256_60 = {
1082 41, /* hSyncOn */
1083 626, /* hSyncOff */
1084 4, /* vSyncOn */
1085 286, /* vSyncOff */
1086 65, /* hBackPorch */
1087 24, /* vBackPorch */
1088 512, /* xDimension */
1089 256, /* yDimension */
1090 60, /* refreshRate */
1091 0, /* miscCtrl */
1092 64, /* memOffset */
1093 16, /* tilesInX */
1094 25, /* vFifoThreshold */
1095 FXFALSE, /* video16BPPIsOK */
1096 FXTRUE, /* video24BPPIsOK */
1097 23.334F, /* clkFreq16bpp */
1098 23.334F /* clkFreq24bpp */
1099};
1100
1101#if 0
1102// For Arcade monitors...
1103sst1VideoTimingStruct SST_VREZ_512X384_60 = {
1104 23, /* hSyncOn */
1105 640, /* hSyncOff */
1106 3, /* vSyncOn */
1107 411, /* vSyncOff */
1108 90, /* hBackPorch */
1109 24, /* vBackPorch */
1110 512, /* xDimension */
1111 384, /* yDimension */
1112 60, /* refreshRate */
1113 0, /* miscCtrl */
1114 96, /* memOffset */
1115 16, /* tilesInX */
1116 23, /* vFifoThreshold */
1117 FXFALSE, /* video16BPPIsOK */
1118 FXTRUE, /* video24BPPIsOK */
1119 33.0F, /* clkFreq16bpp */
1120 33.0F /* clkFreq24bpp */
1121};
1122#else
1123// For PC monitors...
1124sst1VideoTimingStruct SST_VREZ_512X384_60 = {
1125 55, /* hSyncOn */
1126 615, /* hSyncOff */
1127 3, /* vSyncOn */
1128 792, /* vSyncOff */
1129 78, /* hBackPorch */
1130 23, /* vBackPorch */
1131 512, /* xDimension */
1132 384, /* yDimension */
1133 60, /* refreshRate */
1134 0x2, /* miscCtrl */
1135 96, /* memOffset */
1136 16, /* tilesInX */
1137 23, /* vFifoThreshold */
1138 FXTRUE, /* video16BPPIsOK */
1139 FXTRUE, /* video24BPPIsOK */
1140 32.054F, /* clkFreq16bpp */
1141 64.108F /* clkFreq24bpp */
1142};
1143#endif
1144
1145sst1VideoTimingStruct SST_VREZ_512X384_72 = {
1146 51, /* hSyncOn */
1147 591, /* hSyncOff */
1148 3, /* vSyncOn */
1149 430, /* vSyncOff */
1150 55, /* hBackPorch */
1151 25, /* vBackPorch */
1152 512, /* xDimension */
1153 384, /* yDimension */
1154 72, /* refreshRate */
1155 0, /* miscCtrl */
1156 96, /* memOffset */
1157 16, /* tilesInX */
1158 23, /* vFifoThreshold */
1159 FXTRUE, /* video16BPPIsOK */
1160 FXTRUE, /* video24BPPIsOK */
1161 20.093F, /* clkFreq16bpp */
1162 40.186F /* clkFreq24bpp */
1163};
1164
1165sst1VideoTimingStruct SST_VREZ_512X384_75 = {
1166 55, /* hSyncOn */
1167 631, /* hSyncOff */
1168 3, /* vSyncOn */
1169 799, /* vSyncOff */
1170 86, /* hBackPorch */
1171 30, /* vBackPorch */
1172 512, /* xDimension */
1173 384, /* yDimension */
1174 75, /* refreshRate */
1175 0x2, /* miscCtrl */
1176 96, /* memOffset */
1177 16, /* tilesInX */
1178 23, /* vFifoThreshold */
1179 FXTRUE, /* video16BPPIsOK */
1180 FXTRUE, /* video24BPPIsOK */
1181 41.383F, /* clkFreq16bpp */
1182 82.766F /* clkFreq24bpp */
1183};
1184
1185sst1VideoTimingStruct SST_VREZ_512X384_75_NOSCANDOUBLE = {
1186 47, /* hSyncOn */
1187 591, /* hSyncOff */
1188 3, /* vSyncOn */
1189 399, /* vSyncOff */
1190 62, /* hBackPorch */
1191 14, /* vBackPorch */
1192 512, /* xDimension */
1193 384, /* yDimension */
1194 75, /* refreshRate */
1195 0, /* miscCtrl */
1196 96, /* memOffset */
1197 16, /* tilesInX */
1198 23, /* vFifoThreshold */
1199 FXTRUE, /* video16BPPIsOK */
1200 FXTRUE, /* video24BPPIsOK */
1201 19.296F, /* clkFreq16bpp */
1202 38.592F /* clkFreq24bpp */
1203};
1204
1205sst1VideoTimingStruct SST_VREZ_512X384_85 = {
1206 55, /* hSyncOn */
1207 631, /* hSyncOff */
1208 3, /* vSyncOn */
1209 804, /* vSyncOff */
1210 86, /* hBackPorch */
1211 35, /* vBackPorch */
1212 512, /* xDimension */
1213 384, /* yDimension */
1214 85, /* refreshRate */
1215 0x2, /* miscCtrl */
1216 96, /* memOffset */
1217 16, /* tilesInX */
1218 23, /* vFifoThreshold */
1219 FXTRUE, /* video16BPPIsOK */
1220 FXTRUE, /* video24BPPIsOK */
1221 47.193F, /* clkFreq16bpp */
1222 94.386F /* clkFreq24bpp */
1223};
1224
1225sst1VideoTimingStruct SST_VREZ_512X384_85_NOSCANDOUBLE = {
1226 55, /* hSyncOn */
1227 599, /* hSyncOff */
1228 3, /* vSyncOn */
1229 401, /* vSyncOff */
1230 70, /* hBackPorch */
1231 16, /* vBackPorch */
1232 512, /* xDimension */
1233 384, /* yDimension */
1234 85, /* refreshRate */
1235 0, /* miscCtrl */
1236 96, /* memOffset */
1237 16, /* tilesInX */
1238 23, /* vFifoThreshold */
1239 FXTRUE, /* video16BPPIsOK */
1240 FXTRUE, /* video24BPPIsOK */
1241 22.527F, /* clkFreq16bpp */
1242 45.054F /* clkFreq24bpp */
1243};
1244
1245sst1VideoTimingStruct SST_VREZ_512X384_120 = {
1246 25, /* hSyncOn */
1247 650, /* hSyncOff */
1248 3, /* vSyncOn */
1249 409, /* vSyncOff */
1250 110, /* hBackPorch */
1251 25, /* vBackPorch */
1252 512, /* xDimension */
1253 384, /* yDimension */
1254 120, /* refreshRate */
1255 0, /* miscCtrl */
1256 96, /* memOffset */
1257 16, /* tilesInX */
1258 25, /* vFifoThreshold */
1259 FXTRUE, /* video16BPPIsOK */
1260 FXTRUE, /* video24BPPIsOK */
1261 33.5F, /* clkFreq16bpp */
1262 67.0F /* clkFreq24bpp */
1263};
1264
1265/* Verified 10/21/96 */
1266sst1VideoTimingStruct SST_VREZ_640X400_70 = {
1267 96, /* hSyncOn */
1268 704, /* hSyncOff */
1269 2, /* vSyncOn */
1270 447, /* vSyncOff */
1271 48, /* hBackPorch */
1272 35, /* vBackPorch */
1273 640, /* xDimension */
1274 400, /* yDimension */
1275 70, /* refreshRate */
1276 0, /* miscCtrl */
1277 130, /* memOffset */
1278 20, /* tilesInX */
1279 25, /* vFifoThreshold */
1280 FXTRUE, /* video16BPPIsOK */
1281 FXTRUE, /* video24BPPIsOK */
1282 25.175F, /* clkFreq16bpp */
1283 50.350F /* clkFreq24bpp */
1284};
1285
1286/* Verified 10/21/96 */
1287sst1VideoTimingStruct SST_VREZ_640X400_75 = {
1288 99, /* hSyncOn */
1289 733, /* hSyncOff */
1290 3, /* vSyncOn */
1291 429, /* vSyncOff */
1292 52, /* hBackPorch */
1293 25, /* vBackPorch */
1294 640, /* xDimension */
1295 400, /* yDimension */
1296 75, /* refreshRate */
1297 0, /* miscCtrl */
1298 130, /* memOffset */
1299 20, /* tilesInX */
1300 25, /* vFifoThreshold */
1301 FXTRUE, /* video16BPPIsOK */
1302 FXTRUE, /* video24BPPIsOK */
1303 27.0F, /* clkFreq16bpp */
1304 54.0F /* clkFreq24bpp */
1305};
1306
1307/* VESA Standard */
1308/* Verified 10/21/96 */
1309sst1VideoTimingStruct SST_VREZ_640X400_85 = {
1310 63, /* hSyncOn */
1311 767, /* hSyncOff */
1312 3, /* vSyncOn */
1313 442, /* vSyncOff */
1314 94, /* hBackPorch */
1315 41, /* vBackPorch */
1316 640, /* xDimension */
1317 400, /* yDimension */
1318 85, /* refreshRate */
1319 0, /* miscCtrl */
1320 130, /* memOffset */
1321 20, /* tilesInX */
1322 23, /* vFifoThreshold */
1323 FXTRUE, /* video16BPPIsOK */
1324 FXTRUE, /* video24BPPIsOK */
1325 31.5F, /* clkFreq16bpp */
1326 63.0F /* clkFreq24bpp */
1327};
1328
1329/* Verified 10/21/96 */
1330sst1VideoTimingStruct SST_VREZ_640X400_120 = {
1331 67, /* hSyncOn */
1332 798, /* hSyncOff */
1333 3, /* vSyncOn */
1334 424, /* vSyncOff */
1335 94, /* hBackPorch */
1336 16, /* vBackPorch */
1337 640, /* xDimension */
1338 400, /* yDimension */
1339 120, /* refreshRate */
1340 0, /* miscCtrl */
1341 130, /* memOffset */
1342 20, /* tilesInX */
1343 23, /* vFifoThreshold */
1344 FXTRUE, /* video16BPPIsOK */
1345 FXTRUE, /* video24BPPIsOK */
1346 44.47F, /* clkFreq16bpp */
1347 88.94F /* clkFreq24bpp */
1348};
1349
1350/* VESA Standard */
1351/* Verified 10/21/96 */
1352sst1VideoTimingStruct SST_VREZ_640X480_60 = {
1353 96, /* hSyncOn */
1354
1355 704, /* hSyncOff */
1356 2, /* vSyncOn */
1357 523, /* vSyncOff */
1358 38, /* hBackPorch */
1359 25, /* vBackPorch */
1360 640, /* xDimension */
1361 480, /* yDimension */
1362 60, /* refreshRate */
1363 0, /* miscCtrl */
1364 150, /* memOffset */
1365 20, /* tilesInX */
1366 25, /* vFifoThreshold */
1367 FXTRUE, /* video16BPPIsOK */
1368 FXTRUE, /* video24BPPIsOK */
1369 25.175F, /* clkFreq16bpp */
1370 50.350F /* clkFreq24bpp */
1371};
1372
1373/* VESA Standard */
1374/* Verified 10/21/96 */
1375sst1VideoTimingStruct SST_VREZ_640X480_75 = {
1376 63, /* hSyncOn */
1377 775, /* hSyncOff */
1378 3, /* vSyncOn */
1379 497, /* vSyncOff */
1380 118, /* hBackPorch */
1381 16, /* vBackPorch */
1382 640, /* xDimension */
1383 480, /* yDimension */
1384 75, /* refreshRate */
1385 0, /* miscCtrl */
1386 150, /* memOffset */
1387 20, /* tilesInX */
1388 25, /* vFifoThreshold */
1389 FXTRUE, /* video16BPPIsOK */
1390 FXTRUE, /* video24BPPIsOK */
1391 31.5F, /* clkFreq16bpp */
1392 63.0F /* clkFreq24bpp */
1393};
1394
1395/* VESA Standard */
1396/* Verified 10/21/96 */
1397sst1VideoTimingStruct SST_VREZ_640X480_85 = {
1398 55, /* hSyncOn */
1399 776, /* hSyncOff */
1400 3, /* vSyncOn */
1401 506, /* vSyncOff */
1402 78, /* hBackPorch */
1403 25, /* vBackPorch */
1404 640, /* xDimension */
1405 480, /* yDimension */
1406 85, /* refreshRate */
1407 0, /* miscCtrl */
1408 150, /* memOffset */
1409 20, /* tilesInX */
1410 23, /* vFifoThreshold */
1411 FXTRUE, /* video16BPPIsOK */
1412 FXTRUE, /* video24BPPIsOK */
1413 36.0F, /* clkFreq16bpp */
1414 72.0F /* clkFreq24bpp */
1415};
1416
1417/* Verified 10/21/96 */
1418sst1VideoTimingStruct SST_VREZ_640X480_120 = {
1419 45, /* hSyncOn */
1420 785, /* hSyncOff */
1421 3, /* vSyncOn */
1422 506, /* vSyncOff */
1423 100, /* hBackPorch */
1424 18, /* vBackPorch */
1425 640, /* xDimension */
1426 480, /* yDimension */
1427 120, /* refreshRate */
1428 0, /* miscCtrl */
1429 150, /* memOffset */
1430 20, /* tilesInX */
1431 23, /* vFifoThreshold */
1432 FXTRUE, /* video16BPPIsOK */
1433 FXTRUE, /* video24BPPIsOK */
1434 50.82F, /* clkFreq16bpp */
1435 101.64F /* clkFreq24bpp */
1436};
1437
1438/* VESA Standard */
1439/* Verified 10/21/96 */
1440// 800x600 requires 832x608 amount of memory usage...
1441sst1VideoTimingStruct SST_VREZ_800X600_60 = {
1442 127, /* hSyncOn */
1443 927, /* hSyncOff */
1444 4, /* vSyncOn */
1445 624, /* vSyncOff */
1446 86, /* hBackPorch */
1447 23, /* vBackPorch */
1448 800, /* xDimension */
1449 600, /* yDimension */
1450 60, /* refreshRate */
1451 0, /* miscCtrl */
1452 247, /* memOffset */
1453 26, /* tilesInX */
1454 23, /* vFifoThreshold */
1455 FXTRUE, /* video16BPPIsOK */
1456 FXTRUE, /* video24BPPIsOK */
1457 40.0F, /* clkFreq16bpp */
1458 80.0F /* clkFreq24bpp */
1459};
1460
1461/* VESA Standard */
1462/* Verified 10/21/96 */
1463sst1VideoTimingStruct SST_VREZ_800X600_75 = {
1464 79, /* hSyncOn */
1465 975, /* hSyncOff */
1466 3, /* vSyncOn */
1467 622, /* vSyncOff */
1468 158, /* hBackPorch */
1469 21, /* vBackPorch */
1470 800, /* xDimension */
1471 600, /* yDimension */
1472 75, /* refreshRate */
1473 0, /* miscCtrl */
1474 247, /* memOffset */
1475 26, /* tilesInX */
1476 21, /* vFifoThreshold */
1477 FXTRUE, /* video16BPPIsOK */
1478 FXTRUE, /* video24BPPIsOK */
1479 49.5F, /* clkFreq16bpp */
1480 99.0F /* clkFreq24bpp */
1481};
1482
1483/* VESA Standard */
1484/* Verified 10/21/96 */
1485sst1VideoTimingStruct SST_VREZ_800X600_85 = {
1486 63, /* hSyncOn */
1487 983, /* hSyncOff */
1488 3, /* vSyncOn */
1489 628, /* vSyncOff */
1490 150, /* hBackPorch */
1491 27, /* vBackPorch */
1492 800, /* xDimension */
1493 600, /* yDimension */
1494 85, /* refreshRate */
1495 0, /* miscCtrl */
1496 247, /* memOffset */
1497 26, /* tilesInX */
1498 19, /* vFifoThreshold */
1499 FXTRUE, /* video16BPPIsOK */
1500 FXTRUE, /* video24BPPIsOK */
1501 56.25F, /* clkFreq16bpp */
1502 112.5F /* clkFreq24bpp */
1503};
1504
1505sst1VideoTimingStruct SST_VREZ_800X600_120 = {
1506 87, /* hSyncOn */
1507 999, /* hSyncOff */
1508 3, /* vSyncOn */
1509 640, /* vSyncOff */
1510 142, /* hBackPorch */
1511 39, /* vBackPorch */
1512 800, /* xDimension */
1513 600, /* yDimension */
1514 120, /* refreshRate */
1515 0, /* miscCtrl */
1516 247, /* memOffset */
1517 26, /* tilesInX */
1518 17, /* vFifoThreshold */
1519 FXTRUE, /* video16BPPIsOK */
1520 FXFALSE, /* video24BPPIsOK */
1521 83.950F, /* clkFreq16bpp */
1522 83.950F /* clkFreq24bpp -- unsupported */
1523};
1524
1525// 856x480 requires 896x480 amount of memory usage...
1526sst1VideoTimingStruct SST_VREZ_856X480_60 = {
1527 136, /* hSyncOn */
1528 1008, /* hSyncOff */
1529 2, /* vSyncOn */
1530 523, /* vSyncOff */
1531 100, /* hBackPorch */
1532 23, /* vBackPorch */
1533 856, /* xDimension */
1534 480, /* yDimension */
1535 60, /* refreshRate */
1536 0, /* miscCtrl */
1537 210, /* memOffset */
1538 28, /* tilesInX */
1539 16, /* vFifoThreshold */
1540 FXTRUE, /* video16BPPIsOK */
1541 FXTRUE, /* video24BPPIsOK */
1542 36.0F, /* clkFreq16bpp */
1543 72.0F /* clkFreq24bpp */
1544};
1545
1546// 960x720 requires 960x736 amount of memory usage...
1547sst1VideoTimingStruct SST_VREZ_960X720_60 = {
1548 103, /* hSyncOn */
1549 1151, /* hSyncOff */
1550 3, /* vSyncOn */
1551 743, /* vSyncOff */
1552 142, /* hBackPorch */
1553 22, /* vBackPorch */
1554 960, /* xDimension */
1555 720, /* yDimension */
1556 60, /* refreshRate */
1557 0, /* miscCtrl */
1558 345, /* memOffset */
1559 30, /* tilesInX */
1560 19, /* vFifoThreshold */
1561 FXTRUE, /* video16BPPIsOK */
1562 FXTRUE, /* video24BPPIsOK */
1563 56.219F, /* clkFreq16bpp */
1564 112.437F /* clkFreq24bpp */
1565};
1566
1567sst1VideoTimingStruct SST_VREZ_960X720_75 = {
1568 103, /* hSyncOn */
1569 1183, /* hSyncOff */
1570 3, /* vSyncOn */
1571 749, /* vSyncOff */
1572 158, /* hBackPorch */
1573 28, /* vBackPorch */
1574 960, /* xDimension */
1575 720, /* yDimension */
1576 75, /* refreshRate */
1577 0, /* miscCtrl */
1578 345, /* memOffset */
1579 30, /* tilesInX */
1580 19, /* vFifoThreshold */
1581 FXTRUE, /* video16BPPIsOK */
1582 FXFALSE, /* video24BPPIsOK */
1583 72.643F, /* clkFreq16bpp */
1584 72.643F /* clkFreq24bpp -- unsupported */
1585};
1586
1587sst1VideoTimingStruct SST_VREZ_960X720_85 = {
1588 103, /* hSyncOn */
1589 1199, /* hSyncOff */
1590 3, /* vSyncOn */
1591 753, /* vSyncOff */
1592 166, /* hBackPorch */
1593 32, /* vBackPorch */
1594 960, /* xDimension */
1595 720, /* yDimension */
1596 85, /* refreshRate */
1597 0, /* miscCtrl */
1598 345, /* memOffset */
1599 30, /* tilesInX */
1600 19, /* vFifoThreshold */
1601 FXTRUE, /* video16BPPIsOK */
1602 FXFALSE, /* video24BPPIsOK */
1603 83.795F, /* clkFreq16bpp */
1604 83.795F /* clkFreq24bpp -- unsupported */
1605};
1606
1607sst1VideoTimingStruct SST_VREZ_1024X768_60 = {
1608 136, /* hSyncOn */
1609 1208, /* hSyncOff */
1610 6, /* vSyncOn */
1611 800, /* vSyncOff */
1612 160, /* hBackPorch */
1613 29, /* vBackPorch */
1614 1024, /* xDimension */
1615 768, /* yDimension */
1616 60, /* refreshRate */
1617 0, /* miscCtrl */
1618 384, /* memOffset */
1619 32, /* tilesInX */
1620 16, /* vFifoThreshold */
1621 FXTRUE, /* video16BPPIsOK */
1622 FXFALSE, /* video24BPPIsOK */
1623 65.0F, /* clkFreq16bpp */
1624 130.0F /* clkFreq24bpp */
1625};
1626
1627sst1VideoTimingStruct SST_VREZ_1024X768_75 = {
1628 96, /* hSyncOn */
1629 1216, /* hSyncOff */
1630 3, /* vSyncOn */
1631 797, /* vSyncOff */
1632 176, /* hBackPorch */
1633 28, /* vBackPorch */
1634 1024, /* xDimension */
1635 768, /* yDimension */
1636 75, /* refreshRate */
1637 0, /* miscCtrl */
1638 384, /* memOffset */
1639 32, /* tilesInX */
1640 16, /* vFifoThreshold */
1641 FXTRUE, /* video16BPPIsOK */
1642 FXFALSE, /* video24BPPIsOK */
1643 78.75F, /* clkFreq16bpp */
1644 78.75F /* clkFreq24bpp -- unsupported */
1645};
1646
1647sst1VideoTimingStruct SST_VREZ_1024X768_85 = {
1648 96, /* hSyncOn */
1649 1280, /* hSyncOff */
1650 3, /* vSyncOn */
1651 805, /* vSyncOff */
1652 208, /* hBackPorch */
1653 36, /* vBackPorch */
1654 1024, /* xDimension */
1655 768, /* yDimension */
1656 85, /* refreshRate */
1657 0, /* miscCtrl */
1658 384, /* memOffset */
1659 32, /* tilesInX */
1660 16, /* vFifoThreshold */
1661 FXTRUE, /* video16BPPIsOK */
1662 FXFALSE, /* video24BPPIsOK */
1663 94.5F, /* clkFreq16bpp */
1664 94.5F /* clkFreq24bpp -- unsupported */
1665};
1666
1667#else /* SST1INIT_VIDEO_ALLOCATE */
1668
1669
1670#ifdef __cplusplus
1671extern "C" {
1672#endif
1673
1674extern sst1VideoTimingStruct SST_VREZ_640X480_60;
1675extern sst1VideoTimingStruct SST_VREZ_800X600_60;
1676
1677#ifdef __cplusplus
1678}
1679#endif
1680
1681#endif /* SST1INIT_VIDEO_ALLOCATE */
1682
1683#endif /* !__SST1INIT_H__ */
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