Changeset 609 for branches/GNU/src/binutils/include/opcode

Timestamp:

Aug 16, 2003, 6:59:22 PM (22 years ago)

Author:

bird

Message:

binutils v2.14 - offical sources.

Location:

branches/GNU/src/binutils/include/opcode

Files:

• ChangeLog (modified) (26 diffs, 1 prop)
• a29k.h (modified) (3 diffs, 1 prop)
• alpha.h (modified) (1 diff, 1 prop)
• arc.h (modified) (3 diffs, 1 prop)
• avr.h (modified) (4 diffs, 1 prop)
• cgen.h (modified) (17 diffs, 1 prop)
• convex.h (modified) (26 diffs, 1 prop)
• cris.h (modified) (2 diffs, 1 prop)
• d10v.h (modified) (3 diffs, 1 prop)
• d30v.h (modified) (1 diff, 1 prop)
• h8300.h (modified) (18 diffs, 1 prop)
• hppa.h (modified) (15 diffs, 1 prop)
• i386.h (modified) (19 diffs, 1 prop)
• i860.h (modified) (1 diff, 1 prop)
• ia64.h (modified) (6 diffs, 1 prop)
• m68hc11.h (modified) (6 diffs, 1 prop)
• m88k.h (modified) (8 diffs, 1 prop)
• mips.h (modified) (16 diffs, 1 prop)
• ns32k.h (modified) (6 diffs, 1 prop)
• pj.h (modified) (2 diffs, 1 prop)
• ppc.h (modified) (5 diffs, 1 prop)
• sparc.h (modified) (2 diffs, 1 prop)
• tic54x.h (modified) (3 diffs, 1 prop)
• v850.h (modified) (2 diffs, 1 prop)

branches/GNU/src/binutils/include/opcode/ChangeLog

@@ -1 @@
-2001-06-11  Alan Modra  <amodra@bigpond.net.au>
-
-        Merge from mainline.
-        2001-05-23  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+2003-05-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+        * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000
+
+2003-04-07  Michael Snyder  <msnyder@redhat.com>
+
+        * h8300.h (ldc/stc): Fix up src/dst swaps.
+
+2003-04-09  J. Grant  <jg-binutils@jguk.org>
+
+        * mips.h: Correct comment typo.
+
+2003-03-21  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+        * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val.
+        (S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH.
+        (s390_opcode): Remove architecture. Add modes and min_cpu.
+
+2003-03-17 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
+
+        * h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line
+        processing.
+
+2003-02-21  Noida D.Venkatasubramanian  <dvenkat@noida.hcltech.com>
+
+        * h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32.
+
+2003-01-23  Alan Modra  <amodra@bigpond.net.au>
+
+        * m68hc11.h (cpu6812s): Define.
+
+2003-01-07  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h: Fix missing space in comment.
+        (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
+        (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
+        by four bits.
+
+2003-01-02  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h: Update copyright years to include 2002 (which had
+        been missed previously) and 2003.  Make comments about "+A",
+        "+B", and "+C" operand types more descriptive.
+
+2002-12-31  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h: Note that the "+D" operand type name is now used.
+
+2002-12-30  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h: Document "+" as the start of two-character operand
+        type names, and add new "K", "+A", "+B", and "+C" operand types.
+        (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
+        (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
+        defines.
+
+2002-12-24    Dmitry Diky <diwil@mail.ru>
+
+        * msp430.h: New file.  Defines msp430 opcodes.
+
+2002-12-30 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
+
+        * h8300.h: Added some more pseudo opcodes for system call
+        processing.
+
+2002-12-19  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3)
+        (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2)
+        (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1)
+        (OP_OP_SDC2, OP_OP_SDC3): Define.
+
+2002-12-16  Alan Modra  <amodra@bigpond.net.au>
+
+        * hppa.h (completer_chars): #if 0 out.
+
+        * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and
+        "default_args".
+        (struct not_wot): Constify "args".
+        (struct not): Constify "name".
+        (numopcodes): Delete.
+        (endop): Delete.
+
+2002-12-13  Alan Modra  <amodra@bigpond.net.au>
+
+        * pj.h (pj_opc_info_t): Add union.
+
+2002-12-04  David Mosberger  <davidm@hpl.hp.com>
+
+        * ia64.h: Fix copyright message.
+        (IA64_OPND_AR_CSD): New operand kind.
+
+2002-12-03  Richard Henderson  <rth@redhat.com>
+
+        * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
+
+2002-12-03  Alan Modra  <amodra@bigpond.net.au>
+
+        * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
+        Constify "leaf" and "multi".
+
+2002-11-19  Klee Dienes  <kdienes@apple.com>
+
+        * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size'
+        fields.
+        (h8_opcodes). Modify initializer and initializer macros to no
+        longer initialize the removed fields.
+        
+2002-11-19  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+        * tic4x.h (c4x_insts): Fixed LDHI constraint
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+        * h8300.h (h8_opcode): Remove 'length' field.
+        (h8_opcodes): Mark as 'const' (both the declaration and
+        definition).  Modify initializer and initializer macros to no
+        longer initialize the length field.
+
+2002-11-18  Klee Dienes  <kdienes@apple.com>
+
+        * arc.h (arc_ext_opcodes): Declare as extern.
+        (arc_ext_operands): Declare as extern.
+        * i860.h (i860_opcodes): Declare as const.
+
+2002-11-18  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+        * tic4x.h: File reordering. Added enhanced opcodes.
+
+2002-11-16  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+        * tic4x.h: Major rewrite of entire file. Define instruction
+          classes, and put each instruction into a class.
+
+2002-11-11  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+        * tic4x.h: Added new opcodes and corrected some bugs.  Add support
+        for new DSP types.
+
+2002-10-14  Alan Modra  <amodra@bigpond.net.au>
+
+        * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.
+
+2002-09-30  Gavin Romig-Koch  <gavin@redhat.com>
+            Ken Raeburn  <raeburn@cygnus.com>
+            Aldy Hernandez  <aldyh@redhat.com>
+            Eric Christopher  <echristo@redhat.com>
+            Richard Sandiford  <rsandifo@redhat.com>
+
+        * mips.h: Update comment for new opcodes.
+        (OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
+        (OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
+        (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
+        (CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
+        (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
+        Don't match CPU_R4111 with INSN_4100.
+
+2002-08-19  Elena Zannoni <ezannoni@redhat.com>
+ 
+        From matthew green  <mrg@redhat.com>
+
+        * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
+        instructions.
+        (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
+        PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
+        e500x2 Integer select, branch locking, performance monitor,
+        cache locking and machine check APUs, respectively.
+        (PPC_OPCODE_EFS): New opcode type for efs* instructions.
+        (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
+
+2002-08-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+        * m68hc11.h (M6812_OP_PAGE): Define to identify call operand.
+        (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE,
+        M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12
+        memory banks.
+        (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value.
+
+2002-07-09  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+        * mips.h (INSN_MIPS16): New define.
+
+2002-07-08  Alan Modra  <amodra@bigpond.net.au>
+
+        * i386.h: Remove IgnoreSize from movsx and movzx.
+
+2002-06-08  Alan Modra  <amodra@bigpond.net.au>
+
+        * a29k.h: Replace CONST with const.
+        (CONST): Don't define.
+        * convex.h: Replace CONST with const.
+        (CONST): Don't define.
+        * dlx.h: Replace CONST with const.
+        * or32.h (CONST): Don't define.
+
+2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
+
+        * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
+        (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
+        (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
+        (INSN_MDMX): New constants, for MDMX support.
+        (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.
+
+2002-05-28  Kuang Hwa Lin <kuang@sbcglobal.net>
+
+        * dlx.h: New file.
+
+2002-05-25  Alan Modra  <amodra@bigpond.net.au>
+
+        * ia64.h: Use #include "" instead of <> for local header files.
+        * sparc.h: Likewise.
+
+2002-05-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+        * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases.
+
+2002-05-17  Andrey Volkov  <avolkov@sources.redhat.com>
+
+        * h8300.h: Corrected defs of all control regs 
+        and eepmov instr.
+                      
+2002-04-11  Alan Modra  <amodra@bigpond.net.au>
+
+        * i386.h: Add intel mode cmpsd and movsd.
+        Put them before SSE2 insns, so that rep prefix works.
+
+2002-03-15  Chris G. Demetriou  <cgd@broadcom.com>
+
+        * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D
+        instructions.
+        (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks
+        may be passed along with the ISA bitmask.
+
+2002-03-05  Paul Koning  <pkoning@equallogic.com>
+
+        * pdp11.h: Add format codes for float instruction formats.
+
+2002-02-25  Alan Modra  <amodra@bigpond.net.au>
+
+        * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.
+
+Mon Feb 18 17:31:48 CET 2002  Jan Hubicka  <jh@suse.cz>
+
+        * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
+
+Mon Feb 11 12:53:19 CET 2002  Jan Hubicka  <jh@suse.cz>
+
+        * i386.h (push,pop): Allow 16bit operands in 64bit mode.
+        (xchg): Fix.
+        (in, out): Disable 64bit operands.
+        (call, jmp): Avoid REX prefixes.
+        (jcxz): Prohibit in 64bit mode
+        (jrcxz, loop): Add 64bit variants.
+        (movq): Fix patterns.
+        (movmskps, pextrw, pinstrw): Add 64bit variants.
+
+2002-01-31  Ivan Guzvinec  <ivang@opencores.org>
+
+        * or32.h: New file.
+
+2002-01-22  Graydon Hoare  <graydon@redhat.com>
+
+        * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure.
+        (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field.
+
+2002-01-21  Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at>
+
+        * h8300.h: Comment typo fix.
+
+2002-01-03  matthew green  <mrg@redhat.com>
+
+        * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific.
+        (PPC_OPCODE_BOOKE64): Likewise.
+
+Mon Dec 31 16:45:41 2001  Jeffrey A Law  (law@cygnus.com)
+
+        * hppa.h (call, ret): Move to end of table.
+        (addb, addib): PA2.0 variants should have been PA2.0W.
+        (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler
+        happy.
+        (fldw, fldd, fstw, fstd, bb): Likewise.
+        (short loads/stores): Tweak format specifier slightly to keep
+        disassembler happy.
+        (indexed loads/stores): Likewise.
+        (absolute loads/stores): Likewise.
+
+2001-12-04  Alexandre Oliva  <aoliva@redhat.com>
+
+        * d10v.h (OPERAND_NOSP): New macro.
+
+2001-11-29  Alexandre Oliva  <aoliva@redhat.com>
+
+        * d10v.h (OPERAND_SP): New macro.
+
+2001-11-15  Alan Modra  <amodra@bigpond.net.au>
+
+        * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param.
+
+2001-11-11  Timothy Wall  <twall@alum.mit.edu>
+
+        * tic54x.h: Revise opcode layout; don't really need a separate
+        structure for parallel opcodes.
+
+2001-11-13  Zack Weinberg <zack@codesourcery.com>
+            Alan Modra  <amodra@bigpond.net.au>
+
+        * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
+        accept WordReg.
+
+2001-11-04  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h (OPCODE_IS_MEMBER): Remove extra space.
+
+2001-10-30  Hans-Peter Nilsson  <hp@bitrange.com>
+
+        * mmix.h: New file.
+
+2001-10-18  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
+        of the expression, to make source code merging easier.
+
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h: Sort coprocessor instruction argument characters
+        in comment, add a few more words of description for "H".
+
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+        * mips.h (INSN_SB1): New cpu-specific instruction bit.
+        (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
+        if cpu is CPU_SB1.
+
+2001-10-17  matthew green  <mrg@redhat.com>
+
+        * ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
+
+2001-10-12  matthew green  <mrg@redhat.com>
+
+        * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New
+        opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403
+        instructions, respectively.
+
+2001-09-27  Nick Clifton  <nickc@cambridge.redhat.com>
+
+        * v850.h: Remove spurious comment.
+
+2001-09-21  Nick Clifton  <nickc@cambridge.redhat.com>
+
+        * h8300.h: Fix compile time warning messages
+
+2001-09-04  Richard Henderson  <rth@redhat.com>
+
+        * alpha.h (struct alpha_operand): Pack elements into bitfields.
+
+2001-08-31  Eric Christopher  <echristo@redhat.com>
+
+        * mips.h: Remove CPU_MIPS32_4K.
+
+2001-08-27  Torbjorn Granlund  <tege@swox.com>
+
+        * ppc.h (PPC_OPERAND_DS): Define.
+
+2001-08-25  Andreas Jaeger  <aj@suse.de>
+
+        * d30v.h: Fix declaration of reg_name_cnt.
+
+        * d10v.h: Fix declaration of d10v_reg_name_cnt.
+
+        * arc.h: Add prototypes from opcodes/arc-opc.c.
+
+2001-08-16  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+        * mips.h (INSN_10000): Define.
+        (OPCODE_IS_MEMBER): Check for INSN_10000.
+
+2001-08-10  Alan Modra  <amodra@one.net.au>
+
+        * ppc.h: Revert 2001-08-08.
+
+2001-08-10  Richard Sandiford  <rsandifo@redhat.com>
+
+        * mips.h (INSN_GP32): Remove.
+        (OPCODE_IS_MEMBER): Remove gp32 parameter.
+        (M_MOVE): New macro identifier.
+
+2001-08-08  Alan Modra  <amodra@one.net.au>
+
+        1999-10-25  Torbjorn Granlund  <tege@swox.com>
+        * ppc.h (struct powerpc_operand): New field `reloc'.
+
+2001-08-01  Aldy Hernandez  <aldyh@redhat.com>
+
+        * mips.h (INSN_ISA_MASK): Nuke bits 12-15.
+
+2001-07-12  Jeff Johnston  <jjohnstn@redhat.com>
+
+        * cgen.h (CGEN_INSN): Add regex support.
+        (build_insn_regex): Declare.
+
+2001-07-11  Frank Ch. Eigler  <fche@redhat.com>
+
+        * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
+        (cgen_cpu_desc): Ditto.
+
+2001-07-07  Ben Elliston  <bje@redhat.com>
+
+        * m88k.h: Clean up and reformat. Remove unused code.
+
+2001-06-14  Geoffrey Keating  <geoffk@redhat.com>
+
+        * cgen.h (cgen_keyword): Add nonalpha_chars field.
+
+2001-05-23  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
         * mips.h (CPU_R12000): Define.
 
-        2001-05-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+2001-05-23  John Healy  <jhealy@redhat.com>
+
+        * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
+
+2001-05-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
         * mips.h (INSN_ISA_MASK): Define.
-
-        2001-03-21  Kazu Hirata  <kazu@hxi.com>
-        * h8300.h: Fix formatting.
-
-        2001-02-28  Igor Shevlyakov  <igor@windriver.com>
-        * m68k.h: new defines for Coldfire V4. Update mcf to know
-        about mcf5407.
-
-        2001-02-10  Nick Clifton  <nickc@redhat.com>
-        * mips.h: Remove extraneous whitespace.  Formating change to allow
-        for future contribution.
-
-2001-06-07  Alan Modra  <amodra@bigpond.net.au>
-
-        * Many files: Update copyright notices.
 
 2001-05-12  Alan Modra  <amodra@one.net.au>
@@ -34 +435 @@
         and pextrw to swap reg/rm assignments.
 
+2001-04-05  Hans-Peter Nilsson  <hp@axis.com>
+
+        * cris.h (enum cris_insn_version_usage): Correct comment for
+        cris_ver_v3p.
+
 2001-03-24  Alan Modra  <alan@linuxcare.com.au>
 
@@ -39 +445 @@
         Add InvMem to first operand of "maskmovdqu".
 
+2001-03-22  Hans-Peter Nilsson  <hp@axis.com>
+
+        * cris.h (ADD_PC_INCR_OPCODE): New macro.
+
+2001-03-21  Kazu Hirata  <kazu@hxi.com>
+
+        * h8300.h: Fix formatting.
+
 2001-03-22  Alan Modra  <alan@linuxcare.com.au>
 
@@ -47 +461 @@
         * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define.
 
-Mon Feb 12 17:39:31 CET 2001  Jan Hubicka  <jh@suse.cz>
+2001-02-28  Igor Shevlyakov  <igor@windriver.com>
+
+        * m68k.h: new defines for Coldfire V4. Update mcf to know
+        about mcf5407.
+
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+        * pdp11.h: New file.
+
+2001-02-12  Jan Hubicka  <jh@suse.cz>
 
         * i386.h (i386_optab): SSE integer converison instructions have
         64bit versions on x86-64.
+
+2001-02-10  Nick Clifton  <nickc@redhat.com>
+
+        * mips.h: Remove extraneous whitespace.  Formating change to allow
+        for future contribution.
+
+2001-02-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+        * s390.h: New file.
+
+2001-02-02  Patrick Macdonald  <patrickm@redhat.com>
+
+        * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
+        (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
+        (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
 
 2001-01-24  Karsten Keil  <kkeil@suse.de>
@@ -63 +501 @@
         Remove duplicate "ldw j(s,b),x".  Sort some entries.
 
-Sat Jan 13 09:56:32 MET 2001  Jan Hubicka  <jh@suse.cz>
+2001-01-13  Jan Hubicka  <jh@suse.cz>
 
         * i386.h (i386_optab): Fix pusha and ret templates.
@@ -118 +556 @@
         * i386.h (i386_optab): Replace "Imm" with "EncImm".
         (i386_regtab): Add flags field.
-        
+
 2000-12-12  Nick Clifton  <nickc@redhat.com>
 
@@ -143 +581 @@
         (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
         ISA_MIPS32): New constants, defined to be the mask of INSN_*
-        constants available at that ISA level. 
+        constants available at that ISA level.
         (CPU_UNKNOWN): New constant to indicate unknown CPU.
         (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
@@ -151 +589 @@
 
         * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
-        definitions. 
+        definitions.
 
         * mips.h (CPU_SB1): New constant.
@@ -165 +603 @@
 
 2000-09-13  Anders Norlander  <anorland@acc.umu.se>
-        
+
         * mips.h: Use defines instead of hard-coded processor numbers.
         (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010,
-        CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, 
+        CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650,
         CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K,
         CPU_4KC, CPU_4KM, CPU_4KP): Define..
         (OPCODE_IS_MEMBER): Use new defines.
-        (OP_MASK_SEL, OP_SH_SEL): Define.
+        (OP_MASK_SEL, OP_SH_SEL): Define.
         (OP_MASK_CODE20, OP_SH_CODE20): Define.
-        Add 'P' to used characters.
-        Use 'H' for coprocessor select field.
+        Add 'P' to used characters.
+        Use 'H' for coprocessor select field.
         Use 'm' for 20 bit breakpoint code.
-        Document new arg characters and add to used characters.
-        (INSN_MIPS32): New define for MIPS32 extensions.
-        (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
+        Document new arg characters and add to used characters.
+        (INSN_MIPS32): New define for MIPS32 extensions.
+        (OPCODE_IS_MEMBER): Recognize MIPS32 instructions.
 
 2000-09-05  Alan Modra  <alan@linuxcare.com.au>
@@ -359 +797 @@
         (CGEN_CPU_TABLE): flags: new field.
         Add prototypes for new functions.
-        
+
 2000-02-24  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
@@ -477 +915 @@
 
         * hppa.h (pa_opcodes): Use 'fX' for first register operand
-        in xmpyu.  
+        in xmpyu.
 
         * hppa.h (pa_opcodes): Fix mask for probe and probei.
@@ -563 +1001 @@
         * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
 
-        * hppa.h (pa_opcodes):  Change xmpyu, fmpyfadd, 
+        * hppa.h (pa_opcodes):  Change xmpyu, fmpyfadd,
         and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
 
@@ -591 +1029 @@
 
         * hppa.h (pa_opcodes): Move integer arithmetic instructions after
-        integer logical instructions.  
+        integer logical instructions.
 
 1999-05-28  Linus Nordberg  <linus.nordberg@canit.se>
@@ -608 +1046 @@
 Wed May 26 16:57:44 1999  Jeffrey A Law  (law@cygnus.com)
 
-        * hppa.h (pa_opcodes): Add second entry for "comb", "comib", 
+        * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
         "addb", and "addib" to be used by the disassembler.
 
@@ -719 +1157 @@
 
 Mon Feb  1 21:09:14 1999  Catherine Moore  <clm@cygnus.com>
- 
+
         * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf):  Define.
         (x_FP, d_FP, dls_FP, sldx_FP):  Define.
@@ -742 +1180 @@
         CGEN_MODE_UINT.
 
-Sat Jan 16 01:29:25 1999  Jeffrey A Law  (law@cygnus.com)
+1999-01-16  Jeffrey A Law  (law@cygnus.com)
 
         * hppa.h (bv): Fix mask.
@@ -760 +1198 @@
 
         The following is part of a change made by Edith Epstein
-        <eepstein@sophia.cygnus.com> as part of a project to merge in
-        changes by HP; HP did not create ChangeLog entries.
+        <eepstein@sophia.cygnus.com> as part of a project to merge in
+        changes by HP; HP did not create ChangeLog entries.
 
         * hppa.h (completer_chars): list of chars to not put a space
-        after.
+        after.
 
 Sun Dec  6 13:21:34 1998  Ian Lance Taylor  <ian@cygnus.com>
 
         * i386.h (i386_optab): Permit w suffix on processor control and
-        status word instructions.
+        status word instructions.
 
 1998-11-30  Doug Evans  <devans@casey.cygnus.com>
@@ -830 +1268 @@
 
         * hppa.h: Add "fid".
-        
+
 Sun Oct  4 21:00:00 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
@@ -884 +1322 @@
         * mn10300.h: Add "machine" field for instructions.
         (MN103, AM30): Define machine types.
-        
+
 Fri Jun 19 16:09:09 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
@@ -1489 +1927 @@
 
         * alpha.h: Don't include "bfd.h"; private relocation types are now
-        negative to minimize problems with shared libraries.  Organize
-        instruction subsets by AMASK extensions and PALcode
-        implementation.
+        negative to minimize problems with shared libraries.  Organize
+        instruction subsets by AMASK extensions and PALcode
+        implementation.
         (struct alpha_operand): Move flags slot for better packing.
 
@@ -1544 +1982 @@
 
         * v850.h (v850_operands): Add insert and extract fields, pointers
-        to functions used to handle unusual operand encoding.
+        to functions used to handle unusual operand encoding.
         (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
-        V850_OPERAND_SIGNED): Defined.
+        V850_OPERAND_SIGNED): Defined.
 
 Wed Aug 21 17:45:10 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
@@ -1560 +1998 @@
 
         * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
-        OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
-        OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
-        OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
-        OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
-        Defined.
+        OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
+        OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
+        OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
+        OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
+        Defined.
 
 Fri Aug 16 00:15:15 1996  Jeffrey A Law  (law@cygnus.com)
@@ -1574 +2012 @@
 
         * d10v.h: Add some additional defines to support the
-        assembler in determining which operations can be done in parallel.
+        assembler in determining which operations can be done in parallel.
 
 Tue Aug  6 11:13:22 1996  Jeffrey A Law  (law@cygnus.com)
@@ -1590 +2028 @@
 
         * d10v.h: Changes for divs, parallel-only instructions, and
-        signed numbers.
+        signed numbers.
 
 Mon Jul 22 11:21:15 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
@@ -1612 +2050 @@
 Wed Jul  3 14:30:12 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
 
-        * m68k.h (mcf5200): New macro.
+        * m68k.h (mcf5200): New macro.
         Document names of coldfire control registers.
 
@@ -1762 +2200 @@
 
         * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
-        instructions.
+        instructions.
 
 Mon Oct 16 10:28:15 1995  Michael Meissner  <meissner@tiktok.cygnus.com>

branches/GNU/src/binutils/include/opcode/a29k.h

@@ -1 +1 @@
 /* Table of opcodes for the AMD 29000 family.
-   Copyright 1990, 1991, 1993, 1994 Free Software Foundation, Inc.
+   Copyright 1990, 1991, 1993, 1994, 2002 Free Software Foundation, Inc.
 
 This file is part of GDB and GAS.
@@ -63 +63 @@
 };
 
-#ifndef CONST
-#define CONST
-#endif /* CONST */
-
-static CONST struct a29k_opcode a29k_opcodes[] =
+static const struct a29k_opcode a29k_opcodes[] =
 {
 
@@ -283 +279 @@
 };
 
-CONST unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1);
+const unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1);

branches/GNU/src/binutils/include/opcode/alpha.h

@@ -83 +83 @@
 {
   /* The number of bits in the operand.  */
-  int bits;
+  unsigned int bits : 5;
 
   /* How far the operand is left shifted in the instruction.  */
-  int shift;
+  unsigned int shift : 5;
 
   /* The default relocation type for this operand.  */
-  int default_reloc;
+  signed int default_reloc : 16;
 
   /* One bit syntax flags.  */
-  unsigned flags;
+  unsigned int flags : 16;
 
   /* Insertion function.  This is used by the assembler.  To insert an

branches/GNU/src/binutils/include/opcode/arc.h

@@ -99 +99 @@
 /* this is an "insert at front" linked list per Metaware spec
    that new definitions override older ones.  */
-struct arc_opcode *arc_ext_opcodes;
+extern struct arc_opcode *arc_ext_opcodes;
 
 struct arc_operand_value {
@@ -118 +118 @@
   struct arc_ext_operand_value *next;
   struct arc_operand_value operand;
-} *arc_ext_operands;
+};
+
+extern struct arc_ext_operand_value *arc_ext_operands;
 
 struct arc_operand {
@@ -314 +316 @@
 int arc_opcode_supported PARAMS ((const struct arc_opcode *));
 int arc_opval_supported PARAMS ((const struct arc_operand_value *));
+int arc_limm_fixup_adjust PARAMS ((arc_insn));
+int arc_insn_is_j PARAMS ((arc_insn));
+int arc_insn_not_jl PARAMS ((arc_insn));
+int arc_operand_type PARAMS ((int));
+struct arc_operand_value *get_ext_suffix PARAMS ((char *));
+int arc_get_noshortcut_flag PARAMS ((void));

branches/GNU/src/binutils/include/opcode/avr.h

@@ -26 +26 @@
 #define AVR_ISA_MUL   0x0040 /* device has new core (MUL, MOVW, ...) */
 #define AVR_ISA_ELPM  0x0080 /* device has >64K program memory (ELPM) */
-#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] (none yet) */
+#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */
 #define AVR_ISA_SPM   0x0200 /* device can program itself */
+#define AVR_ISA_BRK   0x0400 /* device has BREAK (on-chip debug) */
 #define AVR_ISA_EIND  0x0800 /* device has >128K program memory (none yet) */
 
 #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
 #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
-#define AVR_ISA_M83  (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
+#define AVR_ISA_M8   (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
 #define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA)
 #define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM)
 #define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM)
 #define AVR_ISA_94K  (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX)
+#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK)
+#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
 
 #define AVR_ISA_ALL   0xFFFF
@@ -87 +90 @@
    the disassembler will only see the first match.
 
-   Remaining undefined opcodes (1700 total - some of them might work
+   Remaining undefined opcodes (1699 total - some of them might work
    as normal instructions if not all of the bits are decoded):
 
@@ -101 +104 @@
    "10010101001x1000"    (2) 0x95[23]8
    "1001010101xx1000"    (4) 0x95[4-7]8
-   "1001010110x11000"    (2) 0x95[9b]8
+   "1001010110111000"    (1) 0x95b8
    "1001010111111000"    (1) 0x95f8 (`espm' removed in databook update)
    "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f]
@@ -140 +143 @@
 AVR_INSN (reti, "",    "1001010100011000", 1, AVR_ISA_1200, 0x9518)
 AVR_INSN (sleep,"",    "1001010110001000", 1, AVR_ISA_1200, 0x9588)
+AVR_INSN (break,"",    "1001010110011000", 1, AVR_ISA_BRK,  0x9598)
 AVR_INSN (wdr,  "",    "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
 AVR_INSN (spm,  "",    "1001010111101000", 1, AVR_ISA_SPM,  0x95e8)

branches/GNU/src/binutils/include/opcode/cgen.h

@@ -1 +1 @@
 /* Header file for targets using CGEN: Cpu tools GENerator.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
+Free Software Foundation, Inc.
 
 This file is part of GDB, the GNU debugger, and the GNU Binutils.
@@ -27 +28 @@
    Or perhaps one could duplicate its definition in another file.
    Until such time, this file conditionally compiles definitions that require
-   bfd_vma using BFD_VERSION.  */
+   bfd_vma using __BFD_H_SEEN__.  */
 
 /* Enums must be defined before they can be used.
@@ -203 +204 @@
   /* one of enum mach_attr */
   int num;
+  /* parameter from mach->cpu */
+  unsigned int insn_chunk_bitsize;
 } CGEN_MACH;
 
@@ -281 +284 @@
    The result is an error message or NULL if success.  */
 
-#ifdef BFD_VERSION
+#ifdef __BFD_H_SEEN__
 typedef const char * (cgen_insert_fn)
      PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_,
@@ -302 +305 @@
    The result is the length of the insn in bits or zero if not recognized.  */
 
-#ifdef BFD_VERSION
+#ifdef __BFD_H_SEEN__
 typedef int (cgen_extract_fn)
      PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_,
@@ -321 +324 @@
    LEN is the length of the insn, in bits.  */
 
-#ifdef BFD_VERSION
+#ifdef __BFD_H_SEEN__
 typedef void (cgen_print_fn)
      PARAMS ((CGEN_CPU_DESC, PTR info_, const CGEN_INSN *insn_,
@@ -387 +390 @@
 };
 
-#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily.  */
+#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily.  */
 typedef const char * (cgen_parse_operand_fn)
      PARAMS ((CGEN_CPU_DESC,
@@ -522 +525 @@
   /* Pointer to null keyword "" entry if present.  */
   const CGEN_KEYWORD_ENTRY *null_entry;
+
+  /* String containing non-alphanumeric characters used
+     in keywords.  
+     At present, the highest number of entries used is 1.  */
+  char nonalpha_chars[8];
 } CGEN_KEYWORD;
 
@@ -567 +575 @@
 extern const char *cgen_parse_keyword
      PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *));
-#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily.  */
+#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily.  */
 extern const char *cgen_parse_signed_integer
      PARAMS ((CGEN_CPU_DESC, const char **, int, long *));
@@ -613 +621 @@
 #define CGEN_OPERAND_NIL CGEN_OPERAND_MAX
 
+/* A tree of these structs represents the multi-ifield
+   structure of an operand's hw-index value, if it exists.  */
+
+struct cgen_ifld;
+
+typedef struct cgen_maybe_multi_ifield
+{
+  int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry);
+                n: indexed by array of more cgen_maybe_multi_ifields.  */
+  union
+  {
+    const PTR p;
+    const struct cgen_maybe_multi_ifield * multi;
+    const struct cgen_ifld * leaf;
+  } val;
+}
+CGEN_MAYBE_MULTI_IFLD;
+
 /* This struct defines each entry in the operand table.  */
 
@@ -641 +667 @@
   unsigned char length;
 
+  /* The (possibly-multi) ifield used as an index for this operand, if it
+     is indexed by a field at all. This substitutes / extends the start and
+     length fields above, but unsure at this time whether they are used
+     anywhere.  */
+  CGEN_MAYBE_MULTI_IFLD index_fields;
 #if 0 /* ??? Interesting idea but relocs tend to get too complicated,
          and ABI dependent, for simple table lookups to work.  */
@@ -749 +780 @@
 
 /* This should be at least as large as necessary for any target. */
-#define CGEN_MAX_SYNTAX_BYTES 40
+#define CGEN_MAX_SYNTAX_ELEMENTS 48
 
 /* A target may know its own precise maximum.  Assert that it falls below
    the above limit. */
-#ifdef CGEN_ACTUAL_MAX_SYNTAX_BYTES
-#if CGEN_ACTUAL_MAX_SYNTAX_BYTES > CGEN_MAX_SYNTAX_BYTES
-#error "CGEN_ACTUAL_MAX_SYNTAX_BYTES too high - enlarge CGEN_MAX_SYNTAX_BYTES"
-#endif
-#endif
-
-#if !defined(MAX_OPERANDS) || MAX_OPERANDS <= 127
-typedef unsigned char CGEN_SYNTAX_CHAR_TYPE;
-#else
+#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS
+#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS
+#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS"
+#endif
+#endif
+
 typedef unsigned short CGEN_SYNTAX_CHAR_TYPE;
-#endif
 
 typedef struct
 {
-  CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_BYTES];
+  CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS];
 } CGEN_SYNTAX;
 
@@ -1021 +1048 @@
   const CGEN_OPCODE *opcode;
   const CGEN_OPINST *opinst;
+
+  /* Regex to disambiguate overloaded opcodes */
+  void *rx;
+#define CGEN_INSN_RX(insn) ((insn)->rx)
+#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5)
 };
 
@@ -1183 +1215 @@
   unsigned int word_bitsize;
 
+  /* Instruction chunk size (in bits), for purposes of endianness
+     conversion.  */
+  unsigned int insn_chunk_bitsize;
+
   /* Indicator if sizes are unknown.
      This is used by default_insn_bitsize,base_insn_bitsize if there is a
@@ -1237 +1273 @@
      PARAMS ((CGEN_CPU_DESC, int opindex_, const char **,
               CGEN_FIELDS *fields_));
-#ifdef BFD_VERSION
+#ifdef __BFD_H_SEEN__
   const char * (*insert_operand)
      PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_,
@@ -1270 +1306 @@
   void (*set_int_operand)
        PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_));
-#ifdef BFD_VERSION
+#ifdef __BFD_H_SEEN__
   bfd_vma (*get_vma_operand)
        PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_));
@@ -1376 +1412 @@
 extern void CGEN_SYM (init_opcode_table) PARAMS ((CGEN_CPU_DESC cd_));
 
+/* build the insn selection regex.
+   called by init_opcode_table */
+
+extern char * CGEN_SYM(build_insn_regex) PARAMS ((CGEN_INSN *insn_));
+
 /* Initialize the ibld table for use.
    Called by init_asm/init_dis.  */

branches/GNU/src/binutils/include/opcode/convex.h

@@ -1 +1 @@
 /* Information for instruction disassembly on the Convex.
-   Copyright 1989, 1993 Free Software Foundation, Inc.
+   Copyright 1989, 1993, 2002 Free Software Foundation, Inc.
 
 This file is part of GDB.
@@ -17 +17 @@
 along with this program; if not, write to the Free Software
 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#ifndef CONST
-#define CONST
-#endif  /* CONST */
 
 #define xxx 0
@@ -68 +64 @@
 #define TID 21
 
-CONST char *op[] = {
+const char *op[] = {
   "",
   "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7",
@@ -93 +89 @@
 };
 
-CONST struct formstr format0[] = {
+const struct formstr format0[] = {
   {0,0,rrr,V,S,S},      /* mov */
   {0,0,rrr,S,S,V},      /* mov */
@@ -160 +156 @@
 };
 
-CONST struct formstr format1[] = {
+const struct formstr format1[] = {
   {11,0,xxx,0,0,0},     /* exit */
   {12,0,a3,0,0,0},      /* jmp */
@@ -227 +223 @@
 };
 
-CONST struct formstr format2[] = {
+const struct formstr format2[] = {
   {28,5,rr,A,A,0},      /* cvtw.b */
   {28,6,rr,A,A,0},      /* cvtw.h */
@@ -358 +354 @@
 };
 
-CONST struct formstr format3[] = {
+const struct formstr format3[] = {
   {32,3,rr,V,V,0},      /* cvtd.s */
   {31,4,rr,V,V,0},      /* cvts.d */
@@ -425 +421 @@
 };
 
-CONST struct formstr format4[] = {
+const struct formstr format4[] = {
   {46,0,nops,0,0,0},    /* nop */
   {47,0,pcrel,0,0,0},   /* br */
@@ -436 +432 @@
 };
 
-CONST struct formstr format5[] = {
+const struct formstr format5[] = {
   {51,5,rr,V,V,0},      /* ldvi.b */
   {51,6,rr,V,V,0},      /* ldvi.h */
@@ -455 +451 @@
 };
 
-CONST struct formstr format6[] = {
+const struct formstr format6[] = {
   {53,0,r,A,0,0},       /* ldsdr */
   {54,0,r,A,0,0},       /* ldkdr */
@@ -522 +518 @@
 };
 
-CONST struct formstr format7[] = {
+const struct formstr format7[] = {
   {84,5,r,V,0,0},       /* sum.b */
   {84,6,r,V,0,0},       /* sum.h */
@@ -557 +553 @@
 };
 
-CONST struct formstr formatx[] = {
-  {0,0,0,0,0,0},
-};
-
-CONST struct formstr format1a[] = {
+const struct formstr formatx[] = {
+  {0,0,0,0,0,0},
+};
+
+const struct formstr format1a[] = {
   {91,0,imr,A,0,0},     /* halt */
   {92,0,a4,0,0,0},      /* sysc */
@@ -596 +592 @@
 };
 
-CONST struct formstr format1b[] = {
+const struct formstr format1b[] = {
   {18,4,imr,S,0,0},     /* ld.d */
   {18,10,imr,S,0,0},    /* ld.u */
@@ -631 +627 @@
 };
 
-CONST struct formstr e0_format0[] = {
+const struct formstr e0_format0[] = {
   {10,3,rrr,S,V,V},     /* sub.s */
   {10,4,rrr,S,V,V},     /* sub.d */
@@ -698 +694 @@
 };
 
-CONST struct formstr e0_format1[] = {
+const struct formstr e0_format1[] = {
   {0,0,0,0,0,0},
   {94,0,a3,0,0,0},      /* tst */
@@ -765 +761 @@
 };
 
-CONST struct formstr e0_format2[] = {
+const struct formstr e0_format2[] = {
   {28,5,rr,V,V,0},      /* cvtw.b */
   {28,6,rr,V,V,0},      /* cvtw.h */
@@ -896 +892 @@
 };
 
-CONST struct formstr e0_format3[] = {
+const struct formstr e0_format3[] = {
   {32,11,rr,V,V,0},     /* cvtd.s.f */
   {31,12,rr,V,V,0},     /* cvts.d.f */
@@ -963 +959 @@
 };
 
-CONST struct formstr e0_format4[] = {
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-};
-
-CONST struct formstr e0_format5[] = {
+const struct formstr e0_format4[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e0_format5[] = {
   {51,13,rr,V,V,0},     /* ldvi.b.f */
   {51,14,rr,V,V,0},     /* ldvi.h.f */
@@ -993 +989 @@
 };
 
-CONST struct formstr e0_format6[] = {
+const struct formstr e0_format6[] = {
   {0,0,rxl,S,CIR,0},    /* mov */
   {0,0,lr,CIR,S,0},     /* mov */
@@ -1060 +1056 @@
 };
 
-CONST struct formstr e0_format7[] = {
+const struct formstr e0_format7[] = {
   {84,13,r,V,0,0},      /* sum.b.f */
   {84,14,r,V,0,0},      /* sum.h.f */
@@ -1095 +1091 @@
 };
 
-CONST struct formstr e1_format0[] = {
+const struct formstr e1_format0[] = {
   {0,0,0,0,0,0},
   {0,0,0,0,0,0},
@@ -1162 +1158 @@
 };
 
-CONST struct formstr e1_format1[] = {
+const struct formstr e1_format1[] = {
   {0,0,0,0,0,0},
   {0,0,0,0,0,0},
@@ -1229 +1225 @@
 };
 
-CONST struct formstr e1_format2[] = {
+const struct formstr e1_format2[] = {
   {0,0,0,0,0,0},
   {0,0,0,0,0,0},
@@ -1360 +1356 @@
 };
 
-CONST struct formstr e1_format3[] = {
+const struct formstr e1_format3[] = {
   {32,18,rr,V,V,0},     /* cvtd.s.t */
   {31,19,rr,V,V,0},     /* cvts.d.t */
@@ -1427 +1423 @@
 };
 
-CONST struct formstr e1_format4[] = {
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-};
-
-CONST struct formstr e1_format5[] = {
+const struct formstr e1_format4[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e1_format5[] = {
   {51,20,rr,V,V,0},     /* ldvi.b.t */
   {51,21,rr,V,V,0},     /* ldvi.h.t */
@@ -1457 +1453 @@
 };
 
-CONST struct formstr e1_format6[] = {
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-  {0,0,0,0,0,0},
-};
-
-CONST struct formstr e1_format7[] = {
+const struct formstr e1_format6[] = {
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+  {0,0,0,0,0,0},
+};
+
+const struct formstr e1_format7[] = {
   {84,20,r,V,0,0},      /* sum.b.t */
   {84,21,r,V,0,0},      /* sum.h.t */

branches/GNU/src/binutils/include/opcode/cris.h

@@ -51 +51 @@
   cris_ver_v0_3,
 
-  /* Only for v3 or higher (ETRAX 1..4 and beyond).  */
+  /* Only for v3 or higher (ETRAX 4 and beyond).  */
   cris_ver_v3p,
 
@@ -161 +161 @@
 #define JUMP_PC_INCR_OPCODE \
  (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
+#define ADD_PC_INCR_OPCODE \
+ (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC)
 
 /* Nop.  */

branches/GNU/src/binutils/include/opcode/d10v.h

@@ -1 +1 @@
 /* d10v.h -- Header file for D10V opcode table
-   Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
    Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
 
@@ -182 +182 @@
 #define RESTRICTED_NUM3 (0x80000)
 
+/* Pre-decrement is only supported for SP.  */
+#define OPERAND_SP      (0x100000)
+
+/* Post-decrement is not supported for SP.  Like OPERAND_EVEN, and
+   unlike OPERAND_SP, this flag doesn't prevent the instruction from
+   matching, it only fails validation later on.  */
+#define OPERAND_NOSP    (0x200000)
+
 /* Structure to hold information about predefined registers.  */
 struct pd_reg
@@ -191 +199 @@
 
 extern const struct pd_reg d10v_predefined_registers[];
-int d10v_reg_name_cnt();
+int d10v_reg_name_cnt PARAMS ((void));
 
 /* an expressionS only has one register type, so we fake it */

branches/GNU/src/binutils/include/opcode/d30v.h

@@ -33 +33 @@
 
 extern const struct pd_reg pre_defined_registers[];
-int reg_name_cnt();
+int reg_name_cnt PARAMS ((void));
 
 /* the number of control registers */

branches/GNU/src/binutils/include/opcode/h8300.h

@@ -1 +1 @@
 /* Opcode table for the H8/300
-   Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000
+   Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2003
    Free Software Foundation, Inc.
    Written by Steve Chamberlain <sac@cygnus.com>.
@@ -22 +22 @@
 
 /* Instructions are stored as a sequence of nibbles.
-   If the nibble has value 15 or less then the representation is complete.
+   If the nibble has value 15 or less than the representation is complete.
    Otherwise, we record what it contains with several flags.  */
 
@@ -49 +49 @@
 #define L_P             0x08
 #define L_24            0x10
-#define MEMRELAX        0x20                    /* move insn which may relax */ 
+#define MEMRELAX        0x20                    /* Move insn which may relax.  */ 
 #define SRC             0x40
 #define DST             0x80
@@ -67 +67 @@
 #define DISPREG         0x100000
 #define IGNORE          0x200000
-#define E               0x400000                /* FIXME: end of nibble sequence? */
+#define E               0x400000                /* FIXME: end of nibble sequence?  */
 #define L_2             0x800000
-#define B30             0x1000000               /* bit 3 must be low */
-#define B31             0x2000000               /* bit 3 must be high */
+#define B30             0x1000000               /* Bit 3 must be low.  */
+#define B31             0x2000000               /* Bit 3 must be high.  */
 #define CCR             0x4000000
 #define ABS             0x8000000
@@ -78 +78 @@
 #define MEMIND          0x80000000
 
-#define IMM3            IMM|L_3
-#define IMM2            IMM|L_2
-
-#define SIZE            (L_2|L_3|L_8|L_16|L_32|L_P|L_24)
-#define MODE            (REG|IMM|DISP|IND|INC|DEC|CCR|ABS|MEMIND|EXR)
-
-#define RD8             (DST|L_8|REG)
-#define RD16            (DST|L_16|REG)
-#define RD32            (DST|L_32|REG)
-#define RS8             (SRC|L_8|REG)
-#define RS16            (SRC|L_16|REG)
-#define RS32            (SRC|L_32|REG)
-
-#define RSP             (SRC|L_P|REG)
-#define RDP             (DST|L_P|REG)
-
-#define IMM8            (IMM|SRC|L_8)
-#define IMM16           (IMM|SRC|L_16)
-#define IMM32           (IMM|SRC|L_32)
-
-#define ABS8SRC         (SRC|ABS|L_8|ABS8MEM)
-#define ABS8DST         (DST|ABS|L_8|ABS8MEM)
-
-#define DISP8           (PCREL|L_8)
-#define DISP16          (PCREL|L_16)
-
-#define DISP8SRC        (DISP|L_8|SRC)
-#define DISP16SRC       (DISP|L_16|SRC)
-
-#define DISP8DST        (DISP|L_8|DST)
-#define DISP16DST       (DISP|L_16|DST)
-
-#define ABS16SRC        (SRC|ABS|L_16)
-#define ABS16DST        (DST|ABS|L_16)
-#define ABS24SRC        (SRC|ABS|L_24)
-#define ABS24DST        (DST|ABS|L_24)
-#define ABS32SRC        (SRC|ABS|L_32)
-#define ABS32DST        (DST|ABS|L_32)
-
-#define RDDEC           (DST|DEC)
-#define RSINC           (SRC|INC)
-#define RDINC           (DST|INC)
-
-#define RDIND           (DST|IND)
-#define RSIND           (SRC|IND)
+#define IMM3            IMM | L_3
+#define IMM2            IMM | L_2
+
+#define SIZE            (L_2 | L_3 | L_8 | L_16 | L_32 | L_P | L_24)
+#define MODE            (REG | IMM | DISP | IND | INC | DEC | CCR | ABS | MEMIND | EXR)
+
+#define RD8             (DST | L_8  | REG)
+#define RD16            (DST | L_16 | REG)
+#define RD32            (DST | L_32 | REG)
+#define RS8             (SRC | L_8  | REG)
+#define RS16            (SRC | L_16 | REG)
+#define RS32            (SRC | L_32 | REG)
+
+#define RSP             (SRC | L_P | REG)
+#define RDP             (DST | L_P | REG)
+
+#define IMM8            (IMM | SRC | L_8)
+#define IMM16           (IMM | SRC | L_16)
+#define IMM32           (IMM | SRC | L_32)
+
+#define ABS8SRC         (SRC | ABS | L_8 | ABS8MEM)
+#define ABS8DST         (DST | ABS | L_8 | ABS8MEM)
+
+#define DISP8           (PCREL | L_8)
+#define DISP16          (PCREL | L_16)
+
+#define DISP8SRC        (DISP | L_8  | SRC)
+#define DISP16SRC       (DISP | L_16 | SRC)
+
+#define DISP8DST        (DISP | L_8  | DST)
+#define DISP16DST       (DISP | L_16 | DST)
+
+#define ABS16SRC        (SRC | ABS | L_16)
+#define ABS16DST        (DST | ABS | L_16)
+#define ABS24SRC        (SRC | ABS | L_24)
+#define ABS24DST        (DST | ABS | L_24)
+#define ABS32SRC        (SRC | ABS | L_32)
+#define ABS32DST        (DST | ABS | L_32)
+
+#define RDDEC           (DST | DEC)
+#define RSINC           (SRC | INC)
+#define RDINC           (DST | INC)
+
+#define RDIND           (DST | IND)
+#define RSIND           (SRC | IND)
+
+#define MS32            (SRC | L_32 | MACREG)
+#define MD32            (DST | L_32 | MACREG)
 
 #if 1
-#define OR8 RS8         /* ??? OR as in One Register? */
+#define OR8 RS8         /* ??? OR as in One Register?  */
 #define OR16 RS16
 #define OR32 RS32
@@ -152 +155 @@
   struct arg args;
   struct code data;
-  int length;
-  int noperands;
-  int idx;
-  int size;
 };
 
@@ -161 +160 @@
 
 #define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
-{ code, 1, 2, name,     {{imm,RD8,E}},  {{op00, op01, imm, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\
-{ code, 1, 6, name,     {{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}, 0, 0, 0, 0},\
-{ code, 1, 6, name,     {{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}\
-,{ code, 0, 6, name,    {{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0},\
-{ code, 0, 6, name,     {{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}, 0, 0, 0, 0}
+{ code, 1, 2, name,     {{imm,RD8,E}},  {{op00, op01, imm, RD8, E, 0, 0, 0, 0}}},\
+{ code, 1, 6, name,     {{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}},\
+{ code, 1, 6, name,     {{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}}\
+,{ code, 0, 6, name,    {{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}},\
+{ code, 0, 6, name,     {{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}}
 
 
@@ -173 +172 @@
 
 #define WTWOP(code,name, op1, op2) \
-{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
+{ code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}}
 
 #define BRANCH(code, name, op) \
-{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}, 0, 0, 0, 0} 
+{ code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}}, \
+{ code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}} 
 
 #define SOP(code, x,name) \
@@ -184 +183 @@
 #define NEW_SOP(code, in,x,name) \
 {code, in, x,  name 
-#define EOP  ,0,0,0,0 }
+#define EOP  }
 
 #define TWOOP(code, name, op1, op2,op3) \
-{ code,1, 2,name, {{IMM8, RD8, E}},     {{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}, 0, 0, 0, 0},\
-{ code, 1, 2,name, {{RS8, RD8, E}},     {{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}, 0, 0, 0, 0} 
+{ code,1, 2,name, {{IMM8, RD8, E}},     {{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}},\
+{ code, 1, 2,name, {{RS8, RD8, E}},     {{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}} 
 
 #define UNOP(code,name, op1, op2) \
-{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}, 0, 0, 0, 0}
+{ code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}}
 
 #define UNOP3(code, name, op1, op2, op3) \
-{ O(code,SB), 1, 2, name, {{OR8,  E, 0}}, {{op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}, 0, 0, 0, 0} \
-,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST,  E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}, 0, 0, 0, 0}, \
-{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}, 0, 0, 0, 0}
+{ O(code,SB), 1, 2, name, {{OR8,  E, 0}}, {{op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}}}, \
+{ O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}}, \
+{ O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}} \
+,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST,  E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}}}, \
+{ O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}}, \
+{ O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}}
 
 
@@ -216 +215 @@
 
 
-#define O(op, size) (op*4+size)
+#define O(op, size) (op * 4 + size)
 
 #define O_RECOMPILE 0
@@ -306 +305 @@
 #define O_STMAC 87
 #define O_LAST 88
+/* Change made for System Call processing.  */
+#define O_SYS_CREAT 100
+#define O_SYS_OPEN 101
+#define O_SYS_READ 102
+#define O_SYS_WRITE 103
+#define O_SYS_LSEEK 104
+#define O_SYS_CLOSE 105
+#define O_SYS_STAT 106
+#define O_SYS_FSTAT 107
+/* Space reserved for future file I/O system calls.  */
+#define O_SYS_CMDLINE 120
+/* End of System Call specific Changes.  */
 #define SB 0
 #define SW 1
@@ -311 +322 @@
 #define SN 3
 
-
 /* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
    Methinks the zeroes aren't necessary.  Once confirmed, nuke 'em.  */
 
-struct h8_opcode h8_opcodes[] = 
+const struct h8_opcode h8_opcodes[] = 
 {
   TWOOP(O(O_ADD,SB),"add.b", 0x8, 0x0,0x8),
@@ -334 +344 @@
   NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E}} EOP,
 
-  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
-  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
+  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR|DST,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
+  NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
 
   BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
@@ -392 +402 @@
   NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E }},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP,
 
-  NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP,
+  NEW_SOP(O(O_DIVU,SB),1,13,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_DIVU,SW),0,21,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP,
     
-  NEW_SOP(O(O_DIVS,SB),0,20,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
-  NEW_SOP(O(O_DIVS,SW),0,02,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
-
-  NEW_SOP(O(O_EEPMOV,SB),1,50,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP,
-  NEW_SOP(O(O_EEPMOV,SW),0,50,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP,
+  NEW_SOP(O(O_DIVS,SB),0,13,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
+  NEW_SOP(O(O_DIVS,SW),0,21,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
+
+  NEW_SOP(O(O_EEPMOV,SB),1,4,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP,
+  NEW_SOP(O(O_EEPMOV,SW),0,4,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP,
     
   NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{{OR16,E,0}},{{0x1,0x7,0xD,OR16,E   }}EOP,
@@ -420 +430 @@
   SOP(O(O_JSR,SB),8,"jsr"),{{SRC|MEMIND,E,0}},{{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP,
 
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR,E}},         {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR,E}},          {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR,E}},     {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR,E}},     {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR,E}},        {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR,E}},        {{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP,
-
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR,E}},         {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR,E}},          {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
-  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP,
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR|DST,E}},         {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR|DST,E}},          {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR|DST,E}},     {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR|DST,E}},     {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR|DST,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR|DST,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR|DST,E}},        {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR|DST,E}},        {{PREFIXLDC,0x6,0x9,B30|RSIND,0x0,E}} EOP,
+
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR|DST,E}},         {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR|DST,E}},          {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR|DST,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR|DST,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR|DST,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
+  NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR|DST,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RSIND,0x0,E}} EOP,
 
   SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}},  {{ 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP,
@@ -521 +531 @@
   NEW_SOP(O(O_OR,SL),0,2,"or.l"),{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E}} EOP,
 
-  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
 
   NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{{OR16,E,0}},{{ 0x6,0xD,0x7,OR16,E,0,0,0,0}}EOP,
@@ -545 +555 @@
   SOP(O(O_SLEEP,SN),2,"sleep"),{{E,0,0}},{{ 0x0,0x1,0x8,0x0,E,0,0,0,0}} EOP,
 
-  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
-
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RSIND,E}},        {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,RDDEC,E}},        {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
-
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS16SRC,E}},     {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR,ABS32SRC,E}},     {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
-
-  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
-
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RSIND,E}},        {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,RDDEC,E}},        {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
-
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS16SRC,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
-  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR,ABS32SRC,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR|SRC,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
+
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDIND,E}},        {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDDEC,E}},        {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
+
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS16DST,E}},     {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS32DST,E}},     {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
+
+  NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR|SRC,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
+
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDIND,E}},        {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDDEC,E}},        {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
+
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS16DST,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
+  NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS32DST,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
 
   SOP(O(O_SUB,SB),2,"sub.b"),{{RS8,RD8,E}},{{ 0x1,0x8,RS8,RD8,E,0,0,0,0}}EOP,
@@ -586 +596 @@
   NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E}} EOP,
 
-  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
-  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
+  SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
 
   NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP,
   NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP,
-  NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MACREG,E}},{{0x0,0x3,MACREG,RS32,E}} EOP,
-  NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MACREG,RD32,E}},{{0x0,0x2,MACREG,RD32,E}} EOP,
+  NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MD32,E}},{{0x0,0x3,MD32,RS32,E}} EOP,
+  NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MS32,RD32,E}},{{0x0,0x2,MS32,RD32,E}} EOP,  
   NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP,
   NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP,
-  { 0 }
+  {0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}}
 };
 #else
-extern struct h8_opcode h8_opcodes[];
+extern const struct h8_opcode h8_opcodes[];
 #endif

branches/GNU/src/binutils/include/opcode/hppa.h

@@ -1 +1 @@
 /* Table of opcodes for the PA-RISC.
    Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
-   2001
+   2001, 2002
    Free Software Foundation, Inc.
 
@@ -171 +171 @@
 
    cx   indexed load completer.
+   cX   indexed load completer.  Like cx, but emits a space after
+        in disassembler.
    cm   short load and store completer.
+   cM   short load and store completer.  Like cm, but emits a space
+        after in disassembler.
    cq   long load and store completer (like cm, but inserted into a
         different location in the target instruction).
    cs   store bytes short completer.
+   cA   store bytes short completer.  Like cs, but emits a space
+        after in disassembler.
    ce   long load/store completer for LDW/STW with a different encoding than the
         others
@@ -266 +272 @@
 
 
+#if 0
 /* List of characters not to put a space after.  Note that
    "," is included, as the "spopN" operations use literal
    commas in their completer sections.  */
 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
+#endif
 
 /* The order of the opcodes in this table is significant:
@@ -285 +293 @@
 { "ldi",        0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */
 { "ldi",        0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */
-
-{ "call",       0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
-{ "call",       0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT},
-{ "ret",        0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT},
 
 { "cmpib",      0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},
@@ -302 +306 @@
    assembler.  */
 { "comb",       0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
-{ "addb",       0xa0000000, 0xf4000000, "?Wnx,b,w", pa20, FLAG_STRICT},
+{ "addb",       0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},
 { "addb",       0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */
 /* This entry is for the disassembler only.  It will never be used by
    assembler.  */
 { "addb",       0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},
-{ "addib",      0xa4000000, 0xf4000000, "?Wn5,b,w", pa20, FLAG_STRICT},
+{ "addib",      0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},
 { "addib",      0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
 /* This entry is for the disassembler only.  It will never be used by
@@ -328 +332 @@
 { "ldw",        0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT},
 { "ldw",        0x0c000080, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT},
+{ "ldw",        0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
+{ "ldw",        0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
 { "ldw",        0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
 { "ldw",        0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldw",        0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
-{ "ldw",        0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
 { "ldw",        0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},
 { "ldw",        0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},
@@ -343 +347 @@
 { "ldh",        0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT},
 { "ldh",        0x0c000040, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT},
+{ "ldh",        0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
+{ "ldh",        0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
 { "ldh",        0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
 { "ldh",        0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldh",        0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
-{ "ldh",        0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
 { "ldh",        0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
 { "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},
@@ -352 +356 @@
 { "ldb",        0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT},
 { "ldb",        0x0c000000, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT},
+{ "ldb",        0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
+{ "ldb",        0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
 { "ldb",        0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
 { "ldb",        0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT},
-{ "ldb",        0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT},
-{ "ldb",        0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT},
 { "ldb",        0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
 { "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},
@@ -365 +369 @@
 { "std",        0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},
 { "std",        0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT},
+{ "stw",        0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
+{ "stw",        0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
 { "stw",        0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
 { "stw",        0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "stw",        0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
-{ "stw",        0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
 { "stw",        0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},
 { "stw",        0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},
@@ -378 +382 @@
 { "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},
 { "stw",        0x68000000, 0xfc000000, "x,j(b)", pa10, 0},
+{ "sth",        0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
+{ "sth",        0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
 { "sth",        0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
 { "sth",        0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "sth",        0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
-{ "sth",        0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
 { "sth",        0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
 { "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},
 { "sth",        0x64000000, 0xfc000000, "x,j(b)", pa10, 0},
+{ "stb",        0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
+{ "stb",        0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
 { "stb",        0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
 { "stb",        0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "stb",        0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT},
-{ "stb",        0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
 { "stb",        0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
 { "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},
@@ -396 +400 @@
 { "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},
 { "stwm",       0x6c000000, 0xfc000000, "x,j(b)", pa10, 0},
-{ "ldwx",       0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
-{ "ldwx",       0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, 0},
-{ "ldhx",       0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
-{ "ldhx",       0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, 0},
-{ "ldbx",       0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
-{ "ldbx",       0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, 0},
+{ "ldwx",       0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
+{ "ldwx",       0x0c000080, 0xfc001fc0, "cXx(b),t", pa10, 0},
+{ "ldhx",       0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
+{ "ldhx",       0x0c000040, 0xfc001fc0, "cXx(b),t", pa10, 0},
+{ "ldbx",       0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
+{ "ldbx",       0x0c000000, 0xfc001fc0, "cXx(b),t", pa10, 0},
 { "ldwa",       0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa10, FLAG_STRICT},
 { "ldwa",       0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa10, FLAG_STRICT},
+{ "ldwa",       0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
 { "ldcw",       0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa10, FLAG_STRICT},
 { "ldcw",       0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa10, FLAG_STRICT},
 { "ldcw",       0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa10, FLAG_STRICT},
 { "ldcw",       0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa10, FLAG_STRICT},
+{ "stwa",       0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
 { "stwa",       0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
-{ "stwa",       0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT},
 { "stby",       0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa10, FLAG_STRICT},
 { "stby",       0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa10, FLAG_STRICT},
 { "ldda",       0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
 { "ldda",       0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
+{ "ldda",       0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
 { "ldcd",       0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT},
 { "ldcd",       0x0c000140, 0xfc0013c0, "cxcdx(b),t", pa20, FLAG_STRICT},
@@ -422 +428 @@
 { "stda",       0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},
 { "stda",       0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
-{ "ldwax",      0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, 0},
-{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
-{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, 0},
-{ "ldws",       0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
-{ "ldws",       0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, 0},
-{ "ldhs",       0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
-{ "ldhs",       0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, 0},
-{ "ldbs",       0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
-{ "ldbs",       0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, 0},
-{ "ldwas",      0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, 0},
-{ "ldcws",      0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
-{ "ldcws",      0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, 0},
-{ "stws",       0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
-{ "stws",       0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, 0},
-{ "sths",       0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
-{ "sths",       0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, 0},
-{ "stbs",       0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
-{ "stbs",       0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, 0},
-{ "stwas",      0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, 0},
+{ "ldwax",      0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0},
+{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
+{ "ldcwx",      0x0c0001c0, 0xfc001fc0, "cXx(b),t", pa10, 0},
+{ "ldws",       0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
+{ "ldws",       0x0c001080, 0xfc001fc0, "cM5(b),t", pa10, 0},
+{ "ldhs",       0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
+{ "ldhs",       0x0c001040, 0xfc001fc0, "cM5(b),t", pa10, 0},
+{ "ldbs",       0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
+{ "ldbs",       0x0c001000, 0xfc001fc0, "cM5(b),t", pa10, 0},
+{ "ldwas",      0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0},
+{ "ldcws",      0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
+{ "ldcws",      0x0c0011c0, 0xfc001fc0, "cM5(b),t", pa10, 0},
+{ "stws",       0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
+{ "stws",       0x0c001280, 0xfc001fc0, "cMx,V(b)", pa10, 0},
+{ "sths",       0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
+{ "sths",       0x0c001240, 0xfc001fc0, "cMx,V(b)", pa10, 0},
+{ "stbs",       0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
+{ "stbs",       0x0c001200, 0xfc001fc0, "cMx,V(b)", pa10, 0},
+{ "stwas",      0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
 { "stdby",      0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT},
 { "stdby",      0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT},
-{ "stbys",      0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, 0},
-{ "stbys",      0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, 0},
+{ "stbys",      0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0},
+{ "stbys",      0x0c001300, 0xfc001fc0, "cAx,V(b)", pa10, 0},
 
 /* Immediate instructions.  */
@@ -483 +489 @@
 { "addibt",     0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0},
 { "addibf",     0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0},
+{ "bb",         0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, 
+{ "bb",         0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, 
 { "bb",         0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, 
 { "bb",         0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, 
-{ "bb",         0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, 
-{ "bb",         0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, 
 { "bvb",        0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
 { "clrbts",     0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
@@ -702 +708 @@
 /* Floating Point Coprocessor Instructions.  */
  
-{ "fldw",       0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT},
-{ "fldw",       0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT},
 { "fldw",       0x24000000, 0xfc001380, "cxccx(s,b),fT", pa10, FLAG_STRICT},
 { "fldw",       0x24000000, 0xfc001380, "cxccx(b),fT", pa10, FLAG_STRICT},
 { "fldw",       0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa10, FLAG_STRICT},
 { "fldw",       0x24001000, 0xfc001380, "cmcc5(b),fT", pa10, FLAG_STRICT},
+{ "fldw",       0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT},
+{ "fldw",       0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT},
 { "fldw",       0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT},
 { "fldw",       0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT},
 { "fldw",       0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT},
 { "fldw",       0x58000000, 0xfc000000, "cJd(b),fe", pa20, FLAG_STRICT},
-{ "fldd",       0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT},
-{ "fldd",       0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT},
 { "fldd",       0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa10, FLAG_STRICT},
 { "fldd",       0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa10, FLAG_STRICT},
 { "fldd",       0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa10, FLAG_STRICT},
 { "fldd",       0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa10, FLAG_STRICT},
+{ "fldd",       0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT},
+{ "fldd",       0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT},
 { "fldd",       0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT},
 { "fldd",       0x50000002, 0xfc000002, "cq#(b),fx", pa20, FLAG_STRICT},
-{ "fstw",       0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT},
-{ "fstw",       0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT},
 { "fstw",       0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa10, FLAG_STRICT},
 { "fstw",       0x24000200, 0xfc001380, "cxcCfT,x(b)", pa10, FLAG_STRICT},
 { "fstw",       0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa10, FLAG_STRICT},
 { "fstw",       0x24001200, 0xfc001380, "cmcCfT,5(b)", pa10, FLAG_STRICT},
+{ "fstw",       0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT},
+{ "fstw",       0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT},
 { "fstw",       0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT},
 { "fstw",       0x78000000, 0xfc000000, "cJfe,y(b)", pa20w, FLAG_STRICT},
 { "fstw",       0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT},
 { "fstw",       0x78000000, 0xfc000000, "cJfe,d(b)", pa20, FLAG_STRICT},
-{ "fstd",       0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT},
-{ "fstd",       0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT},
 { "fstd",       0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa10, FLAG_STRICT},
 { "fstd",       0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa10, FLAG_STRICT},
 { "fstd",       0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa10, FLAG_STRICT},
 { "fstd",       0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa10, FLAG_STRICT},
+{ "fstd",       0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT},
+{ "fstd",       0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT},
 { "fstd",       0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT},
 { "fstd",       0x70000002, 0xfc000002, "cqfx,#(b)", pa20, FLAG_STRICT},
-{ "fldwx",      0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10, 0},
-{ "fldwx",      0x24000000, 0xfc001f80, "cxx(b),fT", pa10, 0},
-{ "flddx",      0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, 0},
-{ "flddx",      0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, 0},
+{ "fldwx",      0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0},
+{ "fldwx",      0x24000000, 0xfc001f80, "cXx(b),fT", pa10, 0},
+{ "flddx",      0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0},
+{ "flddx",      0x2c000000, 0xfc001fc0, "cXx(b),ft", pa10, 0},
 { "fstwx",      0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0},
 { "fstwx",      0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0},
@@ -816 +822 @@
 { "spop3",      0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0},
 { "copr",       0x30000000, 0xfc000000, "u,2N", pa10, 0},
-{ "cldwx",      0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0},
-{ "cldwx",      0x24000000, 0xfc001e00, "ucxx(b),t", pa10, 0},
-{ "clddx",      0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0},
-{ "clddx",      0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, 0},
-{ "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0},
-{ "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, 0},
-{ "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0},
-{ "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, 0},
-{ "cldws",      0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0},
-{ "cldws",      0x24001000, 0xfc001e00, "ucm5(b),t", pa10, 0},
-{ "cldds",      0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0},
-{ "cldds",      0x2c001000, 0xfc001e00, "ucm5(b),t", pa10, 0},
-{ "cstws",      0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0},
-{ "cstws",      0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, 0},
-{ "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0},
-{ "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, 0},
-{ "cldw",       0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT},
-{ "cldw",       0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT},
-{ "cldw",       0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT},
-{ "cldw",       0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT},
-{ "cldd",       0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT},
-{ "cldd",       0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT},
-{ "cldd",       0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT},
-{ "cldd",       0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT},
-{ "cstw",       0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT},
-{ "cstw",       0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT},
-{ "cstw",       0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT},
-{ "cstw",       0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT},
-{ "cstd",       0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT},
-{ "cstd",       0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT},
-{ "cstd",       0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT},
-{ "cstd",       0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT},
+{ "cldwx",      0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
+{ "cldwx",      0x24000000, 0xfc001e00, "ucXx(b),t", pa10, 0},
+{ "clddx",      0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
+{ "clddx",      0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, 0},
+{ "cstwx",      0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
+{ "cstwx",      0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, 0},
+{ "cstdx",      0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
+{ "cstdx",      0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, 0},
+{ "cldws",      0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
+{ "cldws",      0x24001000, 0xfc001e00, "ucM5(b),t", pa10, 0},
+{ "cldds",      0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
+{ "cldds",      0x2c001000, 0xfc001e00, "ucM5(b),t", pa10, 0},
+{ "cstws",      0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
+{ "cstws",      0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, 0},
+{ "cstds",      0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
+{ "cstds",      0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, 0},
+{ "cldw",       0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
+{ "cldw",       0x24000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT},
+{ "cldw",       0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
+{ "cldw",       0x24001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT},
+{ "cldd",       0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
+{ "cldd",       0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT},
+{ "cldd",       0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
+{ "cldd",       0x2c001000, 0xfc001e00, "ucM5(b),t", pa20, FLAG_STRICT},
+{ "cstw",       0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
+{ "cstw",       0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT},
+{ "cstw",       0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
+{ "cstw",       0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT},
+{ "cstd",       0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
+{ "cstd",       0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT},
+{ "cstd",       0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
+{ "cstd",       0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT},
+
+/* More pseudo instructions which must follow the main table.  */
+{ "call",       0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
+{ "call",       0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT},
+{ "ret",        0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT},
+
 };
 

branches/GNU/src/binutils/include/opcode/i386.h

@@ -63 +63 @@
 #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf)
 #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
+#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
 #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
 #define sldx_Suf (No_bSuf|No_wSuf|No_qSuf)
@@ -121 +122 @@
 /* Intel Syntax next 5 insns */
 {"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,                   { Reg8|ByteMem, WordReg, 0} },
-{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize,        { Reg16|ShortMem, Reg32, 0} },
+{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,                   { Reg16|ShortMem, Reg32, 0} },
 {"movsx",  2, 0x0fbe, X, Cpu64,  b_Suf|Modrm|Rex64,             { Reg8|ByteMem, Reg64, 0} },
-{"movsx",  2, 0x0fbf, X, Cpu64,  w_Suf|Modrm|IgnoreSize|Rex64,  { Reg16|ShortMem, Reg64, 0} },
+{"movsx",  2, 0x0fbf, X, Cpu64,  w_Suf|Modrm|Rex64,             { Reg16|ShortMem, Reg64, 0} },
 {"movsx",  2,   0x63, X, Cpu64,  l_Suf|Modrm|Rex64,             { Reg32|WordMem, Reg64, 0} },
 
@@ -135 +136 @@
 /* Intel Syntax next 4 insns */
 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,                   { Reg8|ByteMem, WordReg, 0} },
-{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize,        { Reg16|ShortMem, Reg32, 0} },
+{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,                   { Reg16|ShortMem, Reg32, 0} },
 /* These instructions are not particulary usefull, since the zero extend
    32->64 is implicit, but we can encode them.  */
 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64,             { Reg8|ByteMem, Reg64, 0} },
-{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize|Rex64,  { Reg16|ShortMem, Reg64, 0} },
+{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64,             { Reg16|ShortMem, Reg64, 0} },
 
 /* Push instructions.  */
@@ -149 +150 @@
 {"push",   1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
 /* In 64bit mode, the operand size is implicitly 64bit.  */
-{"push",   1,   0x50, X, Cpu64, q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } },
-{"push",   1,   0xff, 6, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } },
-{"push",   1,   0x6a, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
-{"push",   1,   0x68, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm32S, 0, 0} },
-{"push",   1,   0x06, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
-{"push",   1, 0x0fa0, X, Cpu386|Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
+{"push",   1,   0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } },
+{"push",   1,   0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } },
+{"push",   1,   0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
+{"push",   1,   0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
+{"push",   1,   0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
+{"push",   1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
 
 {"pusha",  0,   0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,    { 0, 0, 0 } },
@@ -165 +166 @@
 {"pop",    1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
 /* In 64bit mode, the operand size is implicitly 64bit.  */
-{"pop",    1,   0x58, X, Cpu64,  q_Suf|ShortForm|DefaultSize|NoRex64,   { Reg64, 0, 0 } },
-{"pop",    1,   0x8f, 0, Cpu64,  q_Suf|Modrm|DefaultSize|NoRex64,       { Reg64|WordMem, 0, 0 } },
-{"pop",    1,   0x07, X, Cpu64,  q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
-{"pop",    1, 0x0fa1, X, Cpu64,  q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
+{"pop",    1,   0x58, X, Cpu64,  wq_Suf|ShortForm|DefaultSize|NoRex64,  { WordReg, 0, 0 } },
+{"pop",    1,   0x8f, 0, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64,      { WordReg|WordMem, 0, 0 } },
+{"pop",    1,   0x07, X, Cpu64,  wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
+{"pop",    1, 0x0fa1, X, Cpu64,  wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
 
 {"popa",   0,   0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,            { 0, 0, 0 } },
@@ -177 +178 @@
    In the 64bit code, xchg eax, eax is reused for new nop instruction.
  */
-{"xchg",   2,   0x90, X, CpuNo64, wl_Suf|ShortForm,     { WordReg, Acc, 0 } },
-{"xchg",   2,   0x90, X, CpuNo64, wl_Suf|ShortForm,     { Acc, WordReg, 0 } },
+{"xchg",   2,   0x90, X, 0,      wlq_Suf|ShortForm,     { WordReg, Acc, 0 } },
+{"xchg",   2,   0x90, X, 0,      wlq_Suf|ShortForm,     { Acc, WordReg, 0 } },
 {"xchg",   2,   0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg, Reg|AnyMem, 0 } },
 {"xchg",   2,   0x86, X, 0,      bwlq_Suf|W|Modrm,      { Reg|AnyMem, Reg, 0 } },
 
 /* In/out from ports.  */
-{"in",     2,   0xe4, X, 0,      bwlq_Suf|W,            { Imm8, Acc, 0 } },
-{"in",     2,   0xec, X, 0,      bwlq_Suf|W,            { InOutPortReg, Acc, 0 } },
-{"in",     1,   0xe4, X, 0,      bwlq_Suf|W,            { Imm8, 0, 0 } },
-{"in",     1,   0xec, X, 0,      bwlq_Suf|W,            { InOutPortReg, 0, 0 } },
-{"out",    2,   0xe6, X, 0,      bwlq_Suf|W,            { Acc, Imm8, 0 } },
-{"out",    2,   0xee, X, 0,      bwlq_Suf|W,            { Acc, InOutPortReg, 0 } },
-{"out",    1,   0xe6, X, 0,      bwlq_Suf|W,            { Imm8, 0, 0 } },
-{"out",    1,   0xee, X, 0,      bwlq_Suf|W,            { InOutPortReg, 0, 0 } },
+{"in",     2,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, Acc, 0 } },
+{"in",     2,   0xec, X, 0,      bwl_Suf|W,             { InOutPortReg, Acc, 0 } },
+{"in",     1,   0xe4, X, 0,      bwl_Suf|W,             { Imm8, 0, 0 } },
+{"in",     1,   0xec, X, 0,      bwl_Suf|W,             { InOutPortReg, 0, 0 } },
+{"out",    2,   0xe6, X, 0,      bwl_Suf|W,             { Acc, Imm8, 0 } },
+{"out",    2,   0xee, X, 0,      bwl_Suf|W,             { Acc, InOutPortReg, 0 } },
+{"out",    1,   0xe6, X, 0,      bwl_Suf|W,             { Imm8, 0, 0 } },
+{"out",    1,   0xee, X, 0,      bwl_Suf|W,             { InOutPortReg, 0, 0 } },
 
 /* Load effective address.  */
@@ -211 +212 @@
 {"sahf",   0,   0x9e, X, CpuNo64,NoSuf,                 { 0, 0, 0} },
 {"pushf",  0,   0x9c, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },
-{"pushf",  0,   0x9c, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"pushf",  0,   0x9c, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 {"popf",   0,   0x9d, X, CpuNo64,wlq_Suf|DefaultSize,   { 0, 0, 0} },
-{"popf",   0,   0x9d, X, Cpu64,  q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"popf",   0,   0x9d, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 {"stc",    0,   0xf9, X, 0,      NoSuf,                 { 0, 0, 0} },
 {"std",    0,   0xfd, X, 0,      NoSuf,                 { 0, 0, 0} },
@@ -371 +372 @@
 /* Control transfer instructions.  */
 {"call",   1,   0xe8, X, 0,      wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
-{"call",   1,   0xff, 2, 0,      wlq_Suf|Modrm|DefaultSize,     { WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"call",   1,   0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize,     { WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"call",   1,   0xff, 2, Cpu64,  wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} },
 /* Intel Syntax */
 {"call",   2,   0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
@@ -382 +384 @@
 #define JUMP_PC_RELATIVE 0xeb
 {"jmp",    1,   0xeb, X, 0,      NoSuf|Jump,            { Disp, 0, 0} },
-{"jmp",    1,   0xff, 4, 0,      wlq_Suf|Modrm,         { WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"jmp",    1,   0xff, 4, CpuNo64, wl_Suf|Modrm,         { WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"jmp",    1,   0xff, 4, Cpu64,  wq_Suf|Modrm|NoRex64,  { WordReg|WordMem|JumpAbsolute, 0, 0} },
 /* Intel Syntax */
 {"jmp",    2,   0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
@@ -433 +436 @@
 
 /* jcxz vs. jecxz is chosen on the basis of the address size prefix.  */
-{"jcxz",   1,   0xe3, X, 0,      NoSuf|JumpByte|Size16, { Disp, 0, 0} },
-{"jecxz",  1,   0xe3, X, 0,      NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jcxz",  1,    0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} },
+{"jecxz",  1,   0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jecxz",  1,   0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jrcxz",  1,   0xe3, X, Cpu64,  NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} },
 
 /* The loop instructions also use the address size prefix to select
@@ -440 +445 @@
    instructions emit an address size prefix rather than a data size
    prefix.  */
-{"loop",   1,   0xe2, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
-{"loopz",  1,   0xe1, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
-{"loope",  1,   0xe1, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
-{"loopnz", 1,   0xe0, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
-{"loopne", 1,   0xe0, X, 0,      wlq_Suf|JumpByte,      { Disp, 0, 0} },
+{"loop",   1,   0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loop",   1,   0xe2, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopz",  1,   0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopz",  1,   0xe1, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loope",  1,   0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loope",  1,   0xe1, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopnz", 1,   0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopnz", 1,   0xe0, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopne", 1,   0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopne", 1,   0xe0, X, Cpu64,  lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
 
 /* Set byte on flag instructions.  */
@@ -483 +493 @@
 {"scmp",   0,   0xa6, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 {"scmp",   2,   0xa6, X, 0,      bwlq_Suf|W|IsString,   { AnyMem|EsSeg, AnyMem, 0} },
-{"ins",    0,   0x6c, X, Cpu186, bwlq_Suf|W|IsString,   { 0, 0, 0} },
-{"ins",    2,   0x6c, X, Cpu186, bwlq_Suf|W|IsString,   { InOutPortReg, AnyMem|EsSeg, 0} },
-{"outs",   0,   0x6e, X, Cpu186, bwlq_Suf|W|IsString,   { 0, 0, 0} },
-{"outs",   2,   0x6e, X, Cpu186, bwlq_Suf|W|IsString,   { AnyMem, InOutPortReg, 0} },
+{"ins",    0,   0x6c, X, Cpu186, bwl_Suf|W|IsString,    { 0, 0, 0} },
+{"ins",    2,   0x6c, X, Cpu186, bwl_Suf|W|IsString,    { InOutPortReg, AnyMem|EsSeg, 0} },
+{"outs",   0,   0x6e, X, Cpu186, bwl_Suf|W|IsString,    { 0, 0, 0} },
+{"outs",   2,   0x6e, X, Cpu186, bwl_Suf|W|IsString,    { AnyMem, InOutPortReg, 0} },
 {"lods",   0,   0xac, X, 0,      bwlq_Suf|W|IsString,   { 0, 0, 0} },
 {"lods",   1,   0xac, X, 0,      bwlq_Suf|W|IsString,   { AnyMem, 0, 0} },
@@ -554 +564 @@
 {"sgdt",   1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm,         { WordMem, 0, 0} },
 {"sidt",   1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm,         { WordMem, 0, 0} },
-{"sldt",   1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm,         { WordReg|WordMem, 0, 0} },
-{"smsw",   1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm,         { WordReg|WordMem, 0, 0} },
-{"str",    1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
+{"sldt",   1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
+{"sldt",   1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
+{"smsw",   1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
+{"smsw",   1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
+{"str",    1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm,         { WordReg|InvMem, 0, 0} },
+{"str",    1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
 
 {"verr",   1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
@@ -969 +982 @@
 {"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,            { RegXMM, Reg32|LLongMem, 0 } },
 /* Real MMX instructions.  */
+{"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,            { Reg64|LLongMem, RegMMX, 0 } },
+{"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,            { RegMMX, Reg64|LLongMem, 0 } },
+{"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,            { Reg64|LLongMem, RegXMM, 0 } },
+{"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,            { RegXMM, Reg64|LLongMem, 0 } },
+/* In the 64bit mode the short form mov immediate is redefined to have
+   64bit displacement value.  */
 {"movq",     2, 0x0f6f, X, CpuMMX, FP|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
 {"movq",     2, 0x0f7f, X, CpuMMX, FP|Modrm,            { RegMMX, RegMMX|LongMem, 0 } },
 {"movq",     2, 0xf30f7e,X,CpuSSE2,FP|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
 {"movq",     2, 0x660fd6,X,CpuSSE2,FP|Modrm,            { RegXMM, RegXMM|LLongMem, 0 } },
-/* In the 64bit mode the short form mov immediate is redefined to have
-   64bit displacement value.  */
 {"movq",   2,   0x88, X, Cpu64,  NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
 {"movq",   2,   0xc6, 0, Cpu64,  NoSuf|W|Modrm|Size64,  { Imm32S, Reg64|WordMem, 0 } },
@@ -1138 +1155 @@
 {"movlps",    2, 0x0f12,    X, CpuSSE, FP|Modrm,        { LLongMem, RegXMM, 0 } },
 {"movlps",    2, 0x0f13,    X, CpuSSE, FP|Modrm,        { RegXMM, LLongMem, 0 } },
-{"movmskps",  2, 0x0f50,    X, CpuSSE, FP|Modrm,        { RegXMM|InvMem, Reg32, 0 } },
+{"movmskps",  2, 0x0f50,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"movntps",   2, 0x0f2b,    X, CpuSSE, FP|Modrm,        { RegXMM, LLongMem, 0 } },
 {"movntq",    2, 0x0fe7,    X, CpuSSE, FP|Modrm,        { RegMMX, LLongMem, 0 } },
@@ -1153 +1170 @@
 {"pavgw",     2, 0x0fe3,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },
 {"pavgw",     2, 0x660fe3,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
-{"pextrw",    3, 0x0fc5,    X, CpuSSE, FP|Modrm,        { Imm8, RegMMX|InvMem, Reg32 } },
-{"pextrw",    3, 0x660fc5,  X, CpuSSE2,FP|Modrm,        { Imm8, RegXMM|InvMem, Reg32 } },
-{"pinsrw",    3, 0x0fc4,    X, CpuSSE, FP|Modrm,        { Imm8, Reg32|ShortMem, RegMMX } },
-{"pinsrw",    3, 0x660fc4,  X, CpuSSE2, FP|Modrm,       { Imm8, Reg32|ShortMem, RegXMM } },
+{"pextrw",    3, 0x0fc5,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
+{"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } },
+{"pinsrw",    3, 0x0fc4,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
+{"pinsrw",    3, 0x660fc4,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
 {"pmaxsw",    2, 0x0fee,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },
 {"pmaxsw",    2, 0x660fee,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
@@ -1165 +1182 @@
 {"pminub",    2, 0x0fda,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },
 {"pminub",    2, 0x660fda,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
-{"pmovmskb",  2, 0x0fd7,    X, CpuSSE, FP|Modrm,        { RegMMX|InvMem, Reg32, 0 } },
-{"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,FP|Modrm,        { RegXMM|InvMem, Reg32, 0 } },
+{"pmovmskb",  2, 0x0fd7,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
+{"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"pmulhuw",   2, 0x0fe4,    X, CpuSSE, FP|Modrm,        { RegMMX|LLongMem, RegMMX, 0 } },
 {"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,FP|Modrm,        { RegXMM|LLongMem, RegXMM, 0 } },
@@ -1215 +1232 @@
 {"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
 {"cmppd",     3, 0x660fc2,  X, CpuSSE2, FP|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },
+/* Intel mode string compare.  */
+{"cmpsd",     0, 0xa7,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
+{"cmpsd",     2, 0xa7,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
 {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, FP|Modrm,       { Imm8, RegXMM|LongMem, RegXMM } },
 {"comisd",    2, 0x660f2f,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
@@ -1231 +1251 @@
 {"movlpd",    2, 0x660f12,  X, CpuSSE2, FP|Modrm,       { LLongMem, RegXMM, 0 } },
 {"movlpd",    2, 0x660f13,  X, CpuSSE2, FP|Modrm,       { RegXMM, LLongMem, 0 } },
-{"movmskpd",  2, 0x660f50,  X, CpuSSE2, FP|Modrm,       { RegXMM|InvMem, Reg32, 0 } },
+{"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"movntpd",   2, 0x660f2b,  X, CpuSSE2, FP|Modrm,       { RegXMM, LLongMem, 0 } },
+/* Intel mode string move.  */
+{"movsd",     0, 0xa5,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
+{"movsd",     2, 0xa5,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
 {"movsd",     2, 0xf20f10,  X, CpuSSE2, FP|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
 {"movsd",     2, 0xf20f11,  X, CpuSSE2, FP|Modrm,       { RegXMM, RegXMM|LongMem, 0 } },

branches/GNU/src/binutils/include/opcode/i860.h

@@ -97 +97 @@
    The order of opcodes does not affect the disassembler.  */
 
-static struct i860_opcode i860_opcodes[] =
+static const struct i860_opcode i860_opcodes[] =
 {
 /* REG-Format Instructions.  */

branches/GNU/src/binutils/include/opcode/ia64.h

@@ -1 +1 @@
 /* ia64.h -- Header file for ia64 opcode table
-   Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
-
-   See the file HP-COPYRIGHT for additional information.  */
+   Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc.
+        Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
 
 #ifndef opcode_ia64_h
@@ -9 +8 @@
 #include <sys/types.h>
 
-#include <bfd.h>
+#include "bfd.h"
 
 
@@ -40 +39 @@
 
 /* Changes to this enumeration must be propagated to the operand table in
-   bfd/cpu-ia64-opc.c 
- */ 
+   bfd/cpu-ia64-opc.c
+ */
 enum ia64_opnd
   {
@@ -47 +46 @@
 
     /* constants */
+    IA64_OPND_AR_CSD,   /* application register csd (ar.csd) */
     IA64_OPND_AR_CCV,   /* application register ccv (ar.ccv) */
     IA64_OPND_AR_PFS,   /* application register pfs (ar.pfs) */
@@ -134 +134 @@
     IA64_OPND_TGT25c,   /* signed 25-bit (ip + 16*bits 13-32, 36) */
     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
+    IA64_OPND_LDXMOV,   /* any symbol, generates R_IA64_LDXMOV.  */
 
     IA64_OPND_COUNT     /* # of operand types (MUST BE LAST!) */
@@ -288 +289 @@
     short ent_index;
 
-    /* Opcode dependencies. */ 
+    /* Opcode dependencies. */
     const struct ia64_opcode_dependency *dependencies;
   };

branches/GNU/src/binutils/include/opcode/m68hc11.h

@@ -1 +1 @@
 /* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table
-   Copyright 1999, 2000 Free Software Foundation, Inc.
-   Written by Stephane Carrez (stcarrez@worldnet.fr)
+   Copyright 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
+   Written by Stephane Carrez (stcarrez@nerim.fr)
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -192 +192 @@
 #define M6811_SPIF      0x80    /* SPI Transfer Complete flag */
 #define M6811_WCOL      0x40    /* Write Collision */
-#define M6811_MODF      0x20    /* Mode Fault */
+#define M6811_MODF      0x10    /* Mode Fault */
 
 /* Flags of the ADCTL register.  */
@@ -213 +213 @@
 #define M6811_OC1M7     0x80    /* Output Compare 7 */
 #define M6811_OC1M6     0x40    /*                6 */
-#define M6811_OC1M5     0x40    /*                5 */
-#define M6811_OC1M4     0x40    /*                4 */
+#define M6811_OC1M5     0x20    /*                5 */
+#define M6811_OC1M4     0x10    /*                4 */
 #define M6811_OC1M3     0x08    /*                3 */
 
@@ -342 +342 @@
 #define M6812_OP_D_IDX        0x1000   /* Indirect indexed: [D,r] */
 #define M6812_OP_D_IDX_2      0x2000   /* [N,r] N:16-bits */
-#define M6811_OP_MASK         0x0FFFF
+#define M6812_OP_PAGE         0x4000   /* Page number */
+#define M6811_OP_MASK         0x07FFF
+#define M6811_OP_BRANCH       0x00008000 /* Branch, jsr, call */
 #define M6811_OP_BITMASK      0x00010000 /* Bitmask:             #<val-8>    */
 #define M6811_OP_JUMP_REL     0x00020000 /* Pc-Relative:         <val-8>     */
@@ -377 +379 @@
 #define M6811_OP_LOW_ADDR     0x02000000
 
+#define M68HC12_BANK_VIRT 0x010000
+#define M68HC12_BANK_MASK 0x00003fff
+#define M68HC12_BANK_BASE 0x00008000
+#define M68HC12_BANK_SHIFT 14
+#define M68HC12_BANK_PAGE_MASK 0x0ff
+
+
 /* CPU identification.  */
 #define cpu6811 0x01
 #define cpu6812 0x02
+#define cpu6812s 0x04
 
 /* The opcode table is an array of struct m68hc11_opcode.  */
@@ -416 +426 @@
 
 #endif /* _OPCODE_M68HC11_H */
-

branches/GNU/src/binutils/include/opcode/m88k.h

@@ -1 @@
-/* Table of opcodes for the motorola 88k family.
-   Copyright 1989, 1990, 1991, 1993 Free Software Foundation, Inc.
+/* Table of opcodes for the Motorola M88k family.
+   Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc.
 
 This file is part of GDB and GAS.
@@ -35 +35 @@
  *      are initialized by init_disasm().
  *
- *                              Structure Format
- *
- *       struct INSTAB {
- *          UPINT opcode;
- *          char *mnemonic;
- *          struct OPSPEC op1,op2,op3;
- *          struct SIM_FLAGS flgs;
- *          struct INSTAB *next;
- *       }
- *
- *       struct OPSPEC {
- *          UPINT offset:5;
- *          UPINT width:6;
- *          UPINT type:5;
- *       }
- *
  *                              Revision History
  *
@@ -62 +46 @@
 #include <stdio.h>
 
-
-/*
- * This file contains the structures and constants needed to build the M88000
- * simulator.  It is the main include file, containing all the
- * structures, macros and definitions except for the floating point
- * instruction set.
- */
-
-/*
- * The following flag informs the Simulator as to what type of byte ordering
- * will be used. For instance, a BOFLAG = 1 indicates a DEC VAX and IBM type
- * of ordering shall be used.
-*/
-
-/* # define     BOFLAG   1 */                       /* BYTE ORDERING FLAG */
-
-/* define the number of bits in the primary opcode field of the instruction,
- * the destination field, the source 1 and source 2 fields.
- */
-# define    OP       8                        /* size of opcode field */
-# define    DEST     6                        /* size of destination  */
-# define    SOURCE1  6                        /* size of source1      */
-# define    SOURCE2  6                        /* size of source2      */
-
-# define    REGs    32                        /* number of registers  */
-
-# define    WORD    long
-# define    FLAG    unsigned
-# define    STATE   short
-
-# define    TRUE     1
-# define    FALSE    0
-
-# define    READ     0
-# define    WRITE    1
+/* Define the number of bits in the primary opcode field of the instruction,
+   the destination field, the source 1 and source 2 fields.  */
+
+/* Size of opcode field.  */
+#define OP 8
+
+/* Size of destination.  */
+#define DEST 6
+
+/* Size of source1.  */
+#define SOURCE1 6
+
+/* Size of source2.  */
+#define SOURCE2 6
+
+/* Number of registers.  */
+#define REGs 32
+
+/* Type definitions.  */
+
+typedef unsigned int UINT;
+#define    WORD    long
+#define    FLAG    unsigned
+#define    STATE   short
 
 /* The next four equates define the priorities that the various classes
  * of instructions have regarding writing results back into registers and
- * signalling exceptions.
- */
+ * signalling exceptions.  */
+
 /* PMEM is also defined in <sys/param.h> on Delta 88's.  Sigh!  */
 #undef PMEM
 
-# define    PINT  0   /* Integer Priority */
-# define    PFLT  1   /* Floating Point Priority */
-# define    PMEM  2   /* Memory Priority */
-# define    NA    3   /* Not Applicable, instruction doesnt write to regs */
-# define    HIPRI 3   /* highest of these priorities */
+/* Integer priority.  */
+#define    PINT  0
+
+/* Floating point priority.  */
+#define    PFLT  1
+
+/* Memory priority.  */
+#define    PMEM  2
+
+/* Not applicable, instruction doesn't write to regs.  */
+#define    NA    3
+
+/* Highest of these priorities.  */
+#define    HIPRI 3
 
 /* The instruction registers are an artificial mechanism to speed up
@@ -123 +105 @@
  */
 
-struct IR_FIELDS {
-                    unsigned        op:OP,
-                                    dest: DEST,
-                                    src1: SOURCE1,
-                                    src2: SOURCE2;
-                              int   ltncy,
-                                    extime,
-                                    wb_pri;     /* writeback priority     */
-                    unsigned        imm_flags:2,/* immediate size         */
-                                    rs1_used:1, /* register source 1 used */
-                                    rs2_used:1, /* register source 2 used */
-                                    rsd_used:1, /* register source/dest. used */
-                                    c_flag:1,   /* complement      */
-                                    u_flag:1,   /* upper half word */
-                                    n_flag:1,   /* execute next    */
-                                    wb_flag:1,  /* uses writeback slot */
-                                    dest_64:1,  /* dest size       */
-                                    s1_64:1,    /* source 1 size   */
-                                    s2_64:1,    /* source 2 size   */
-                                    scale_flag:1, /* scaled register */
-                                    brk_flg:1;
-                 };
-
-struct  mem_segs {
-        struct mem_wrd *seg;                    /* pointer (returned by calloc) to segment */
-        unsigned long baseaddr;                 /* base load address from file headers */
-        unsigned long endaddr;                  /* Ending address of segment */
-        int           flags;                    /* segment control flags (none defined 12/5/86) */
+struct IR_FIELDS
+{
+  unsigned op:OP,
+    dest: DEST,
+    src1: SOURCE1,
+    src2: SOURCE2;
+  int ltncy,
+    extime,
+    /* Writeback priority.  */
+    wb_pri;
+  /* Immediate size.  */
+  unsigned        imm_flags:2,
+    /* Register source 1 used.  */
+    rs1_used:1,
+    /* Register source 2 used. */
+    rs2_used:1,
+    /* Register source/dest. used.  */
+    rsd_used:1,
+    /* Complement.  */
+    c_flag:1,
+    /* Upper half word.  */
+    u_flag:1,
+    /* Execute next.  */
+    n_flag:1,
+    /* Uses writeback slot.  */
+    wb_flag:1,
+    /* Dest size.  */
+    dest_64:1,
+    /* Source 1 size.  */
+    s1_64:1,
+    /* Source 2 size.  */
+    s2_64:1,
+    scale_flag:1,
+    /* Scaled register.  */
+    brk_flg:1;
+};
+
+struct  mem_segs
+{
+  /* Pointer (returned by calloc) to segment.  */
+  struct mem_wrd *seg;                  
+
+  /* Base load address from file headers.  */
+  unsigned long baseaddr;                       
+
+  /* Ending address of segment.  */
+  unsigned long endaddr;                
+
+  /* Segment control flags (none defined).  */  
+  int         flags;                    
 };
 
@@ -156 +160 @@
 #define MEMSEGSIZE      (sizeof(struct mem_segs))/* size of mem_segs structure */
 
-
+#if 0
 #define BRK_RD          (0x01)                  /* break on memory read */
 #define BRK_WR          (0x02)                  /* break on memory write */
 #define BRK_EXEC        (0x04)                  /* break on execution */
 #define BRK_CNT         (0x08)                  /* break on terminal count */
-
-
-struct  mem_wrd {
-        struct IR_FIELDS opcode;                /* simulator instruction break down */
-        union {
-                unsigned long  l;               /* memory element break down */
-                unsigned short s[2];
-                unsigned char  c[4];
-        } mem;
-};
-
-#define MEMWRDSIZE      (sizeof(struct mem_wrd))        /* size of each 32 bit memory model */
-
-/* External declarations */
-
-extern  struct mem_segs memory[];
-extern  struct PROCESSOR m78000;
-
-struct  PROCESSOR   {
-             unsigned WORD
-                            ip,          /* execute instruction pointer */
-                            vbr,         /* vector base register */
-                            psr;         /* processor status register */
-
-                    WORD    S1bus, /* source 1 */
-                            S2bus, /* source 2 */
-                            Dbus,  /* destination */
-                            DAbus, /* data address bus */
-                            ALU,
-                            Regs[REGs],       /* data registers */
-                            time_left[REGs],  /* max clocks before reg is available */
-                            wb_pri[REGs],     /* writeback priority of reg */
-                            SFU0_regs[REGs],  /* integer unit control regs */
-                            SFU1_regs[REGs],  /* floating point control regs */
-                            Scoreboard[REGs],
-                            Vbr;
-            unsigned WORD   scoreboard,
-                            Psw,
-                            Tpsw;
-                    FLAG   jump_pending:1;   /* waiting for a jump instr. */
-                    };
-
-# define    i26bit      1    /* size of immediate field */
-# define    i16bit      2
-# define    i10bit      3
-
-/* Definitions for fields in psr */
-
-# define mode  31
-# define rbo   30
-# define ser   29
-# define carry 28
-# define sf7m  11
-# define sf6m  10
-# define sf5m   9
-# define sf4m   8
-# define sf3m   7
-# define sf2m   6
-# define sf1m   5
-# define mam    4
-# define inm    3
-# define exm    2
-# define trm    1
-# define ovfm   0
-
-#define     MODEMASK   (1<<(mode-1))
-# define    SILENT     0   /* simulate without output to crt */
-# define    VERBOSE    1   /* simulate in verbose mode */
-# define    PR_INSTR   2   /* only print instructions */
-
-# define    RESET      16 /* reset phase */
-
-# define    PHASE1     0  /* data path phases */
-# define    PHASE2     1
-
-/* the 1 clock operations */
-
-# define    ADDU        1
-# define    ADDC        2
-# define    ADDUC       3
-# define    ADD         4
-
-# define    SUBU    ADD+1
-# define    SUBB    ADD+2
-# define    SUBUB   ADD+3
-# define    SUB     ADD+4
-
-# define    AND_    ADD+5
-# define    OR      ADD+6
-# define    XOR     ADD+7
-# define    CMP     ADD+8
-
-/* the LOADS */
-
-# define    LDAB    CMP+1
-# define    LDAH    CMP+2
-# define    LDA     CMP+3
-# define    LDAD    CMP+4
-
-# define    LDB   LDAD+1
-# define    LDH   LDAD+2
-# define    LD    LDAD+3
-# define    LDD   LDAD+4
-# define    LDBU  LDAD+5
-# define    LDHU  LDAD+6
-
-/* the STORES */
-
-# define    STB    LDHU+1
-# define    STH    LDHU+2
-# define    ST     LDHU+3
-# define    STD    LDHU+4
-
-/* the exchange */
-
-# define    XMEMBU LDHU+5
-# define    XMEM   LDHU+6
-
-/* the branches */
-# define    JSR    STD+1
-# define    BSR    STD+2
-# define    BR     STD+3
-# define    JMP    STD+4
-# define    BB1    STD+5
-# define    BB0    STD+6
-# define    RTN    STD+7
-# define    BCND   STD+8
-
-/* the TRAPS */
-# define    TB1    BCND+1
-# define    TB0    BCND+2
-# define    TCND   BCND+3
-# define    RTE    BCND+4
-# define    TBND   BCND+5
-
-/* the MISC instructions */
-# define    MUL     TBND + 1
-# define    DIV     MUL  +2
-# define    DIVU    MUL  +3
-# define    MASK    MUL  +4
-# define    FF0     MUL  +5
-# define    FF1     MUL  +6
-# define    CLR     MUL  +7
-# define    SET     MUL  +8
-# define    EXT     MUL  +9
-# define    EXTU    MUL  +10
-# define    MAK     MUL  +11
-# define    ROT     MUL  +12
-
-/* control register manipulations */
-
-# define    LDCR    ROT  +1
-# define    STCR    ROT  +2
-# define    XCR     ROT  +3
-
-# define    FLDCR    ROT  +4
-# define    FSTCR    ROT  +5
-# define    FXCR     ROT  +6
-
-
-# define    NOP     XCR +1
-
-/* floating point instructions */
-
-# define    FADD    NOP +1
-# define    FSUB    NOP +2
-# define    FMUL    NOP +3
-# define    FDIV    NOP +4
-# define    FSQRT   NOP +5
-# define    FCMP    NOP +6
-# define    FIP     NOP +7
-# define    FLT     NOP +8
-# define    INT     NOP +9
-# define    NINT    NOP +10
-# define    TRNC    NOP +11
-# define    FLDC   NOP +12
-# define    FSTC   NOP +13
-# define    FXC    NOP +14
-
-# define UEXT(src,off,wid) ((((unsigned int)(src))>>(off)) & ((1<<(wid)) - 1))
-# define SEXT(src,off,wid) (((((int)(src))<<(32-((off)+(wid)))) >>(32-(wid))) )
-# define MAKE(src,off,wid) \
-  ((((unsigned int)(src)) & ((1<<(wid)) - 1)) << (off))
-
-# define opword(n) (unsigned long) (memaddr->mem.l)
-
-/*  Constants and Masks */
+#endif
+
+struct mem_wrd
+{
+  /* Simulator instruction break down.  */
+  struct IR_FIELDS opcode;
+  union {
+    /* Memory element break down.  */
+    unsigned long  l;
+    unsigned short s[2];
+    unsigned char  c[4];
+  } mem;
+};
+
+/* Size of each 32 bit memory model.  */
+#define MEMWRDSIZE      (sizeof (struct mem_wrd))
+
+extern struct mem_segs memory[];
+extern struct PROCESSOR m78000;
+
+struct PROCESSOR
+{
+  unsigned WORD
+  /* Execute instruction pointer.  */
+  ip, 
+    /* Vector base register.  */
+    vbr,
+    /* Processor status register.  */
+    psr;
+  
+  /* Source 1.  */
+  WORD    S1bus,
+    /* Source 2.  */
+    S2bus,
+    /* Destination.  */
+    Dbus,
+    /* Data address bus.  */
+    DAbus,
+    ALU,
+    /* Data registers.  */
+    Regs[REGs],
+    /* Max clocks before reg is available.  */
+    time_left[REGs],
+    /* Writeback priority of reg.  */
+    wb_pri[REGs], 
+    /* Integer unit control regs.  */
+    SFU0_regs[REGs],
+    /* Floating point control regs.  */
+    SFU1_regs[REGs], 
+    Scoreboard[REGs],
+    Vbr;
+  unsigned WORD   scoreboard,
+    Psw,
+    Tpsw;
+  /* Waiting for a jump instruction.  */
+  FLAG   jump_pending:1;
+};
+
+/* Size of immediate field.  */
+
+#define    i26bit      1
+#define    i16bit      2
+#define    i10bit      3
+
+/* Definitions for fields in psr.  */
+
+#define mode  31
+#define rbo   30
+#define ser   29
+#define carry 28
+#define sf7m  11
+#define sf6m  10
+#define sf5m   9
+#define sf4m   8
+#define sf3m   7
+#define sf2m   6
+#define sf1m   5
+#define mam    4
+#define inm    3
+#define exm    2
+#define trm    1
+#define ovfm   0
+
+/* The 1 clock operations.  */
+
+#define    ADDU        1
+#define    ADDC        2
+#define    ADDUC       3
+#define    ADD         4
+
+#define    SUBU    ADD+1
+#define    SUBB    ADD+2
+#define    SUBUB   ADD+3
+#define    SUB     ADD+4
+
+#define    AND_    ADD+5
+#define    OR      ADD+6
+#define    XOR     ADD+7
+#define    CMP     ADD+8
+
+/* Loads.  */
+
+#define    LDAB    CMP+1
+#define    LDAH    CMP+2
+#define    LDA     CMP+3
+#define    LDAD    CMP+4
+
+#define    LDB   LDAD+1
+#define    LDH   LDAD+2
+#define    LD    LDAD+3
+#define    LDD   LDAD+4
+#define    LDBU  LDAD+5
+#define    LDHU  LDAD+6
+
+/* Stores.  */
+
+#define    STB    LDHU+1
+#define    STH    LDHU+2
+#define    ST     LDHU+3
+#define    STD    LDHU+4
+
+/* Exchange.  */
+
+#define    XMEMBU LDHU+5
+#define    XMEM   LDHU+6
+
+/* Branches.  */
+
+#define    JSR    STD+1
+#define    BSR    STD+2
+#define    BR     STD+3
+#define    JMP    STD+4
+#define    BB1    STD+5
+#define    BB0    STD+6
+#define    RTN    STD+7
+#define    BCND   STD+8
+
+/* Traps.  */
+
+#define    TB1    BCND+1
+#define    TB0    BCND+2
+#define    TCND   BCND+3
+#define    RTE    BCND+4
+#define    TBND   BCND+5
+
+/* Misc.  */
+
+#define    MUL     TBND + 1
+#define    DIV     MUL  +2
+#define    DIVU    MUL  +3
+#define    MASK    MUL  +4
+#define    FF0     MUL  +5
+#define    FF1     MUL  +6
+#define    CLR     MUL  +7
+#define    SET     MUL  +8
+#define    EXT     MUL  +9
+#define    EXTU    MUL  +10
+#define    MAK     MUL  +11
+#define    ROT     MUL  +12
+
+/* Control register manipulations.  */
+
+#define    LDCR    ROT  +1
+#define    STCR    ROT  +2
+#define    XCR     ROT  +3
+
+#define    FLDCR    ROT  +4
+#define    FSTCR    ROT  +5
+#define    FXCR     ROT  +6
+
+#define    NOP     XCR +1
+
+/* Floating point instructions.  */
+
+#define    FADD    NOP +1
+#define    FSUB    NOP +2
+#define    FMUL    NOP +3
+#define    FDIV    NOP +4
+#define    FSQRT   NOP +5
+#define    FCMP    NOP +6
+#define    FIP     NOP +7
+#define    FLT     NOP +8
+#define    INT     NOP +9
+#define    NINT    NOP +10
+#define    TRNC    NOP +11
+#define    FLDC   NOP +12
+#define    FSTC   NOP +13
+#define    FXC    NOP +14
+
+#define UEXT(src,off,wid) \
+  ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
+
+#define SEXT(src,off,wid) \
+  (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
+
+#define MAKE(src,off,wid) \
+  ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
+
+#define opword(n) (unsigned long) (memaddr->mem.l)
+
+/* Constants and masks.  */
 
 #define SFU0       0x80000000
@@ -361 +379 @@
 #define CTRLMASK   0xfc00f800
 
-/* Operands types */
-
-enum operand_type {
+/* Operands types.  */
+
+enum operand_type
+{
   HEX = 1,
   REG = 2,
@@ -369 +388 @@
   IND = 3,
   BF = 4,
-  REGSC = 5    /* scaled register */,
-  CRREG = 6    /* control register */,
-  FCRREG = 7    /* floating point control register */,
+  /* Scaled register.  */
+  REGSC = 5,
+  /* Control register.  */
+  CRREG = 6,
+  /* Floating point control register.  */
+  FCRREG = 7,
   PCREL = 8,
   CONDMASK = 9,
-  XREG = 10, /* extended register */
-  DEC = 11, /* decimal */
-};
-
-/* Hashing Specification */
+  /* Extended register.  */
+  XREG = 10,
+  /* Decimal.  */
+  DEC = 11
+};
+
+/* Hashing specification.  */
 
 #define HASHVAL     79
 
-/* Type definitions */
-
-typedef unsigned int UINT;
-
-/* Structure templates */
-
-#if never
-typedef struct {
-   unsigned int offset:5;
-   unsigned int width:6;
-   unsigned int type:5;
+/* Structure templates.  */
+
+typedef struct
+{
+  unsigned int offset;
+  unsigned int width;
+  enum operand_type type;
 } OPSPEC;
-#endif
-
-typedef struct {
-   unsigned int offset;
-   unsigned int width;
-   enum operand_type type;
-} OPSPEC;
-
-        struct SIM_FLAGS {
-              int  ltncy,   /* latency (max number of clocks needed to execute) */
-                  extime,   /* execution time (min number of clocks needed to execute) */
-                  wb_pri;   /* writeback slot priority */
-   unsigned         op:OP,   /* simulator version of opcode */
-             imm_flags:2,   /* 10,16 or 26 bit immediate flags */
-              rs1_used:1,   /* register source 1 used */
-              rs2_used:1,   /* register source 2 used */
-              rsd_used:1,   /* register source/dest used */
-                c_flag:1,   /* complement */
-                u_flag:1,   /* upper half word */
-                n_flag:1,   /* execute next */
-               wb_flag:1,   /* uses writeback slot */
-               dest_64:1,   /* double precision dest */
-                 s1_64:1,   /* double precision source 1 */
-                 s2_64:1,   /* double precision source 2 */
-            scale_flag:1;   /* register is scaled */
+
+struct SIM_FLAGS
+{
+  int  ltncy,   /* latency (max number of clocks needed to execute).  */
+    extime,   /* execution time (min number of clocks needed to execute).  */
+    wb_pri;   /* writeback slot priority.  */
+  unsigned         op:OP,   /* simulator version of opcode.  */
+    imm_flags:2,   /* 10,16 or 26 bit immediate flags.  */
+    rs1_used:1,   /* register source 1 used.  */
+    rs2_used:1,   /* register source 2 used.  */
+    rsd_used:1,   /* register source/dest used.  */
+    c_flag:1,   /* complement.  */
+    u_flag:1,   /* upper half word.  */
+    n_flag:1,   /* execute next.  */
+    wb_flag:1,   /* uses writeback slot.  */
+    dest_64:1,   /* double precision dest.  */
+    s1_64:1,   /* double precision source 1.  */
+    s2_64:1,   /* double precision source 2.  */
+    scale_flag:1;   /* register is scaled.  */
 };
 
 typedef struct INSTRUCTAB {
-   unsigned int  opcode;
-   char          *mnemonic;
-   OPSPEC        op1,op2,op3;
-   struct SIM_FLAGS flgs;
-   struct INSTRUCTAB    *next;
+  unsigned int  opcode;
+  char          *mnemonic;
+  OPSPEC        op1,op2,op3;
+  struct SIM_FLAGS flgs;
 } INSTAB;
 
@@ -433 +446 @@
 #define NO_OPERAND {0,0,0}
 
-/* Opcode     Mnemonic       Op 1 Spec     Op 2 Spec    Op 3 Spec         Simflags             Next  */
-
-static INSTAB  instructions[] = {
-  {0xf400c800,"jsr         ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,JSR ,          0,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf400cc00,"jsr.n       ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {1,1,NA,JSR ,          0,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xf400c000,"jmp         ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,JMP ,          0,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf400c400,"jmp.n       ",{0,5,REG}   ,NO_OPERAND      ,NO_OPERAND   , {1,1,NA,JMP ,          0,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xc8000000,"bsr         ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {2,2,NA,BSR ,     i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xcc000000,"bsr.n       ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {1,1,NA,BSR ,     i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xc0000000,"br          ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {2,2,NA,BR  ,     i26bit,0,0,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xc4000000,"br.n        ",{0,26,PCREL},NO_OPERAND      ,NO_OPERAND   , {1,1,NA,BR  ,     i26bit,0,0,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xd0000000,"bb0         ",{21,5,HEX}  ,{16,5,REG}   ,{0,16,PCREL},{2,2,NA,BB0,     i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xd4000000,"bb0.n       ",{21,5,HEX}  ,{16,5,REG}   ,{0,16,PCREL},{1,1,NA,BB0,     i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xd8000000,"bb1         ",{21,5,HEX},{16,5,REG}     ,{0,16,PCREL},{2,2,NA,BB1,     i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xdc000000,"bb1.n       ",{21,5,HEX},{16,5,REG}     ,{0,16,PCREL},{1,1,NA,BB1,     i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xf000d000,"tb0         ",{21,5,HEX}  ,{16,5,REG}   ,{0,10,HEX}, {2,2,NA,TB0 ,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf000d800,"tb1         ",{21,5,HEX}  ,{16,5,REG}   ,{0,10,HEX}, {2,2,NA,TB1 ,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xe8000000,"bcnd        ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{2,2,NA,BCND,    i16bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xec000000,"bcnd.n      ",{21,5,CONDMASK},{16,5,REG},{0,16,PCREL},{1,1,NA,BCND,    i16bit,0,1,0,0,0,1,1,0,0,0,0}, NULL },
-  {0xf000e800,"tcnd        ",{21,5,CONDMASK},{16,5,REG},{0,10,HEX}, {2,2,NA,TCND,     i10bit,0,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf8000000,"tbnd        ",{16,5,REG}  ,{0,16,HEX}   ,NO_OPERAND   , {2,2,NA,TBND,     i10bit,1,0,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf400f800,"tbnd        ",{16,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {2,2,NA,TBND,          0,1,1,0,0,0,0,1,0,0,0,0}, NULL },
-  {0xf400fc00,"rte         ",NO_OPERAND     ,NO_OPERAND      ,NO_OPERAND   , {2,2,NA,RTE ,          0,0,0,0,0,0,0,1,0,0,0,0}, NULL },
-  {0x1c000000,"ld.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDB    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001c00,"ld.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDB     ,    0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0x0c000000,"ld.bu       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDBU,   i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4000c00,"ld.bu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDBU        ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0x18000000,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDH    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001800,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDH         ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001a00,"ld.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDH         ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x08000000,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDHU,   i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4000800,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDHU        ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4000a00,"ld.hu       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDHU        ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x14000000,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LD     ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001400,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001600,"ld          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x10000000,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,LDD    ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001000,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LDD         ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001200,"ld.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LDD         ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0xf4001500,"ld.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4001700,"ld.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,LD          ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x2c000000,"st.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STB      ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4002c00,"st.b        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STB           ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0x28000000,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STH      ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4002800,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STH           ,0,1,1,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4002a00,"st.h        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,STH           ,0,1,1,1,0,0,0,1,0,0,0,1}, NULL },
-  {0x24000000,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,ST       ,i16bit,1,0,1,0,0,0,1,0,0,0,0}, NULL },
-  {0xf4002400,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4002600,"st          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-  {0x20000000,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,NA,STD      ,i16bit,0,1,0,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4002000,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,STD           ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4002200,"st.d        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,STD           ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-  {0xf4002500,"st.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4002700,"st.usr      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,NA,ST            ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-/*  m88100 only:
-  {0x00000000,"xmem.bu     ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,XMEMBU ,i16bit,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
- */
-  {0xf4000000,"xmem.bu     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-/*  m88100 only:
-  {0x04000000,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {3,1,PMEM,XMEM   ,i16bit,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
- */
-  {0xf4000400,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4000600,"xmem        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-  {0xf4000500,"xmem.usr    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0xf4000700,"xmem.usr    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{3,1,PMEM,XMEM        ,0,1,1,1,0,0,0,1,0,0,0,1}   ,NULL },
-/* m88100 only:
-  {0xf4003e00,"lda.b       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
- */
-  {0xf4003e00,"lda.x       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
-  {0xf4003a00,"lda.h       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAH,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
-  {0xf4003600,"lda         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDA ,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
-  {0xf4003200,"lda.d       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REGSC},{1,1,PINT,LDAD,        0,1,1,1,0,0,0,0,0,0,0,1}   ,NULL },
-
-  {0x80004000,"ldcr        ",{21,5,REG}  ,{5,6,CRREG}  ,NO_OPERAND    ,{1,1,PINT,LDCR,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x80008000,"stcr        ",{16,5,REG}  ,{5,6,CRREG}  ,NO_OPERAND    ,{1,1,PINT,STCR,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x8000c000,"xcr         ",{21,5,REG}  ,{16,5,REG}   ,{5,6,CRREG},{1,1,PINT,XCR,         0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0xf4006000,"addu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006200,"addu.ci     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006100,"addu.co     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006300,"addu.cio    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADDU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006400,"subu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006600,"subu.ci     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006500,"subu.co     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006700,"subu.cio    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUBU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006800,"divu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {32,32,PINT,DIVU,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4006900,"divu.d      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}, NULL },
-  {0xf4006e00,"muls        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}, NULL },
-  {0xf4006c00,"mulu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,4,PINT,MUL,      0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007000,"add         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007200,"add.ci      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007100,"add.co      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007300,"add.cio     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ADD ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007400,"sub         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007600,"sub.ci      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007500,"sub.co      ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007700,"sub.cio     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SUB ,        0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007800,"divs        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {32,32,PINT,DIV ,      0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4007c00,"cmp         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,CMP,         0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0x60000000,"addu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,ADDU,   i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x64000000,"subu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,SUBU,   i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0x68000000,"divu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {32,32,PINT,DIVU, i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x6c000000,"mulu        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {4,1,PINT,MUL,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x70000000,"add         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,ADD,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x74000000,"sub         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,SUB,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x78000000,"divs        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {32,32,PINT,DIV,  i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x7c000000,"cmp         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,CMP,    i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0xf4004000,"and         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,AND_        ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4004400,"and.c       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,AND_        ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4005800,"or          ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,OR          ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4005c00,"or.c        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,OR          ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4005000,"xor         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,XOR         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4005400,"xor.c       ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,XOR         ,0,1,1,1,1,0,0,0,0,0,0,0}   ,NULL },
-  {0x40000000,"and         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,AND_   ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x44000000,"and.u       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,AND_   ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
-  {0x58000000,"or          ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,OR     ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x5c000000,"or.u        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,OR     ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
-  {0x50000000,"xor         ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,XOR    ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x54000000,"xor.u       ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,XOR    ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
-  {0x48000000,"mask        ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,MASK   ,i16bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0x4c000000,"mask.u      ",{21,5,REG}  ,{16,5,REG}   ,{0,16,HEX}, {1,1,PINT,MASK   ,i16bit,1,0,1,0,1,0,0,0,0,0,0}   ,NULL },
-  {0xf400ec00,"ff0         ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {1,1,PINT,FF0         ,0,0,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf400e800,"ff1         ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {1,1,PINT,FF1         ,0,0,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf0008000,"clr         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,CLR    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf0008800,"set         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,SET    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf0009000,"ext         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,EXT    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf0009800,"extu        ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,EXTU   ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf000a000,"mak         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,MAK    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf000a800,"rot         ",{21,5,REG}  ,{16,5,REG}   ,{0,10,BF} , {1,1,PINT,ROT    ,i10bit,1,0,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4008000,"clr         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,CLR         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4008800,"set         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,SET         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4009000,"ext         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,EXT         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf4009800,"extu        ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,EXTU        ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf400a000,"mak         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,MAK         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-  {0xf400a800,"rot         ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {1,1,PINT,ROT         ,0,1,1,1,0,0,0,0,0,0,0,0}   ,NULL },
-
-  {0x84002800,"fadd.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84002880,"fadd.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
-  {0x84002a00,"fadd.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84002a80,"fadd.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
-  {0x84002820,"fadd.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x840028a0,"fadd.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
-  {0x84002a20,"fadd.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x84002aa0,"fadd.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FADD        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
-  {0x84003000,"fsub.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84003080,"fsub.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
-  {0x84003200,"fsub.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84003280,"fsub.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
-  {0x84003020,"fsub.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x840030a0,"fsub.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
-  {0x84003220,"fsub.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x840032a0,"fsub.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,2,PFLT,FSUB        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
-  {0x84000000,"fmul.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84000080,"fmul.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
-  {0x84000200,"fmul.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84000280,"fmul.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
-  {0x84000020,"fmul.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x840000a0,"fmul.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
-  {0x84000220,"fmul.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x840002a0,"fmul.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {9,2,PFLT,FMUL        ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
-  {0x84007000,"fdiv.sss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {30,30,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84007080,"fdiv.ssd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,0,1,0}   ,NULL },
-  {0x84007200,"fdiv.sds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84007280,"fdiv.sdd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,0,1,1,0}   ,NULL },
-  {0x84007020,"fdiv.dss    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x840070a0,"fdiv.dsd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,0,1,0}   ,NULL },
-  {0x84007220,"fdiv.dds    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x840072a0,"fdiv.ddd    ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {60,60,PFLT,FDIV      ,0,1,1,1,0,0,0,1,1,1,1,0}   ,NULL },
-  {0x84007800,"fsqrt.ss    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84007820,"fsqrt.sd    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84007880,"fsqrt.ds    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x840078a0,"fsqrt.dd    ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84003800,"fcmp.ss     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {5,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84003880,"fcmp.sd     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,0,1,0,0}   ,NULL },
-  {0x84003a00,"fcmp.ds     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84003a80,"fcmp.dd     ",{21,5,REG}  ,{16,5,REG}   ,{0,5,REG} , {6,1,PFLT,FCMP        ,0,1,1,1,0,0,0,1,1,1,0,0}   ,NULL },
-  {0x84002000,"flt.s       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84002020,"flt.d       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,FLT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84004800,"int.s       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,INT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84004880,"int.d       ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,INT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84005000,"nint.s      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,INT         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84005080,"nint.d      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,INT         ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-  {0x84005800,"trnc.s      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {5,1,PFLT,TRNC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x84005880,"trnc.d      ",{21,5,REG}  ,{0,5,REG}    ,NO_OPERAND   , {6,1,PFLT,TRNC        ,0,0,1,1,0,0,0,1,1,0,0,0}   ,NULL },
-
-  {0x80004800,"fldcr       ",{21,5,REG}  ,{5,6,FCRREG} ,NO_OPERAND   , {1,1,PFLT,FLDC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x80008800,"fstcr       ",{16,5,REG}  ,{5,6,FCRREG} ,NO_OPERAND   , {1,1,PFLT,FSTC        ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-  {0x8000c800,"fxcr        ",{21,5,REG}  ,{16,5,REG}   ,{5,6,FCRREG} , {1,1,PFLT,FXC         ,0,0,1,1,0,0,0,1,0,0,0,0}   ,NULL },
-
-/* The following are new for the 88110. */
-
-  {0x8400aaa0,"fadd.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aa80,"fadd.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aac0,"fadd.ddx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aa20,"fadd.dsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aa00,"fadd.dss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aa40,"fadd.dsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ab20,"fadd.dxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ab00,"fadd.dxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ab40,"fadd.dxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a8a0,"fadd.sdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a880,"fadd.sds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a8c0,"fadd.sdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a820,"fadd.ssd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a800,"fadd.sss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a840,"fadd.ssx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a920,"fadd.sxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a900,"fadd.sxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400a940,"fadd.sxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400aca0,"fadd.xdd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ac80,"fadd.xds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400acc0,"fadd.xdx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ac20,"fadd.xsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ac00,"fadd.xss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ac40,"fadd.xsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ad20,"fadd.xxd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ad00,"fadd.xxs    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ad40,"fadd.xxx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400ba80,"fcmp.sdd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ba00,"fcmp.sds    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bb00,"fcmp.sdx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b880,"fcmp.ssd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b800,"fcmp.sss    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b900,"fcmp.ssx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bc80,"fcmp.sxd    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bc00,"fcmp.sxs    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bd00,"fcmp.sxx    ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400baa0,"fcmpu.sdd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400ba20,"fcmpu.sds   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bb20,"fcmpu.sdx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b8a0,"fcmpu.ssd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b820,"fcmpu.sss   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400b920,"fcmpu.ssx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bca0,"fcmpu.sxd   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bc20,"fcmpu.sxs   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400bd20,"fcmpu.sxx   ",{21,5,REG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x84000820,"fcvt.sd     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84000880,"fcvt.ds     ",{21,5,REG} ,{0,5,REG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x84008880,"fcvt.ds     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x840088c0,"fcvt.dx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84008820,"fcvt.sd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84008840,"fcvt.sx     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84008920,"fcvt.xd     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84008900,"fcvt.xs     ",{21,5,XREG} ,{0,5,XREG}  ,NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400f2a0,"fdiv.ddd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f280,"fdiv.dds    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f2c0,"fdiv.ddx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f220,"fdiv.dsd    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f200,"fdiv.dss    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400f240,"fdiv.dsx    ",{21,5,XREG} ,{16,5,XREG}  ,{0,5,XREG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
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-  {0xf0001600,"ld          ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0001200,"ld.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0001a00,"ld.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0001700,"ld.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0001300,"ld.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0001b00,"ld.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400c000,"mov.s       ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400c080,"mov.d       ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84004200,"mov.s       ", {21,5,XREG}, {0,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x84004280,"mov.d       ", {21,5,XREG}, {0,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400c300,"mov         ", {21,5,XREG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf4006d00,"mulu.d      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400d080,"nint.sd     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400d000,"nint.ss     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400d100,"nint.sx     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88002020,"padd.b      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002040,"padd.h      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002060,"padd        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x880021e0,"padds.s     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880021a0,"padds.s.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880021c0,"padds.s.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880020e0,"padds.u     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880020a0,"padds.u.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880020c0,"padds.u.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002160,"padds.us    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002120,"padds.us.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88002140,"padds.us.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88003860,"pcmp        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88000000,"pmul        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88006260,"ppack.16    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006240,"ppack.16.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006460,"ppack.32    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006420,"ppack.32.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006440,"ppack.32.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006160,"ppack.8     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88007200,"prot        ", {21,5,REG}, {16,5,REG}, {5,6,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88007800,"prot        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88003020,"psub.b      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003040,"psub.h      ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003060,"psub        ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x880031e0,"psubs.s     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880031a0,"psubs.s.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880031c0,"psubs.s.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880030e0,"psubs.u     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880030a0,"psubs.u.b   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x880030c0,"psubs.u.h   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003160,"psubs.us    ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003120,"psubs.us.b  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88003140,"psubs.us.h  ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x88006800,"punpk.n     ", {21,5,REG}, {16,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x88006820,"punpk.b     ", {21,5,REG}, {16,5,REG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x34000000,"st          ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x30000000,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x38000000,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,16,HEX}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf4002c80,"st.b.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002880,"st.h.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002480,"st.wt       ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002080,"st.d.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002d80,"st.b.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002980,"st.h.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002580,"st.usr.wt   ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002180,"st.d.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf0002400,"st          ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002000,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002100,"st.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002180,"st.d.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002080,"st.d.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002500,"st.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002580,"st.usr.wt   ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002480,"st.wt       ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002800,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002900,"st.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002980,"st.x.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002880,"st.x.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REG}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf4002f80,"st.b.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002e80,"st.b.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002380,"st.d.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002280,"st.d.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002b80,"st.h.usr.wt ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002a80,"st.h.wt     ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002780,"st.usr.wt   ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf4002680,"st.wt       ", {21,5,REG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0xf0002600,"st          ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002200,"st.d        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002300,"st.d.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002380,"st.d.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002280,"st.d.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002700,"st.usr      ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002780,"st.usr.wt   ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002680,"st.wt       ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002a00,"st.x        ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002b00,"st.x.usr    ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002b80,"st.x.usr.wt ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0xf0002a80,"st.x.wt     ", {21,5,XREG}, {16,5,REG}, {0,5,REGSC}, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-  {0x8400d880,"trnc.sd     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400d800,"trnc.ss     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-  {0x8400d900,"trnc.sx     ", {21,5,REG}, {0,5,XREG}, NO_OPERAND, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, NULL },
-
-};
+extern const INSTAB  instructions[];
 
 /*

branches/GNU/src/binutils/include/opcode/mips.h

@@ -1 +1 @@
 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
@@ -134 +134 @@
 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 #define OP_MASK_CODE19          0x7ffff
+#define OP_SH_ALN               21
+#define OP_MASK_ALN             0x7
+#define OP_SH_VSEL              21
+#define OP_MASK_VSEL            0x1f
+#define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
+                                           but 0x8-0xf don't select bytes.  */
+#define OP_SH_VECBYTE           22
+#define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
+#define OP_SH_VECALIGN          21
+#define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
+#define OP_SH_INSMSB            11
+#define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
+#define OP_SH_EXTMSBD           11
+
+#define OP_OP_COP0              0x10
+#define OP_OP_COP1              0x11
+#define OP_OP_COP2              0x12
+#define OP_OP_COP3              0x13
+#define OP_OP_LWC1              0x31
+#define OP_OP_LWC2              0x32
+#define OP_OP_LWC3              0x33    /* a.k.a. pref */
+#define OP_OP_LDC1              0x35
+#define OP_OP_LDC2              0x36
+#define OP_OP_LDC3              0x37    /* a.k.a. ld */
+#define OP_OP_SWC1              0x39
+#define OP_OP_SWC2              0x3a
+#define OP_OP_SWC3              0x3b
+#define OP_OP_SDC1              0x3d
+#define OP_OP_SDC2              0x3e
+#define OP_OP_SDC3              0x3f    /* a.k.a. sd */
+
+/* Values in the 'VSEL' field.  */
+#define MDMX_FMTSEL_IMM_QH      0x1d
+#define MDMX_FMTSEL_IMM_OB      0x1e
+#define MDMX_FMTSEL_VEC_QH      0x15
+#define MDMX_FMTSEL_VEC_OB      0x16
 
 /* This structure holds information for a particular instruction.  */
@@ -162 +198 @@
 };
 
-/* These are the characters which may appears in the args field of an
+/* These are the characters which may appear in the args field of an
    instruction.  They appear in the order in which the fields appear
    when the instruction is used.  Commas and parentheses in the args
@@ -180 +216 @@
    "j" 16 bit signed immediate (OP_*_DELTA)
    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
+       Also used for immediate operands in vr5400 vector insns.
    "o" 16 bit signed offset (OP_*_DELTA)
    "p" 16 bit PC relative branch target address (OP_*_DELTA)
@@ -196 +233 @@
    "x" accept and ignore register name
    "z" must be zero register
+   "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
+   "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
+        Enforces: 0 <= pos < 32.
+   "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
+        Requires that "+A" occur first to set position.
+        Enforces: 0 < (pos+size) <= 32.
+   "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
+        Requires that "+A" occur first to set position.
+        Enforces: 0 < (pos+size) <= 32.
 
    Floating point instructions:
@@ -210 +256 @@
    "E" 5 bit target register (OP_*_RT)
    "G" 5 bit destination register (OP_*_RD)
+   "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
    "P" 5 bit performance-monitor register (OP_*_PERFREG)
-   "H" 3 bit sel field (OP_*_SEL)
+   "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
+   "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
+   see also "k" above
+   "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
+        for pretty-printing in disassembly only.
 
    Macro instructions:
@@ -221 +272 @@
    "l" 32 bit floating point constant in .lit4
 
+   MDMX instruction operands (note that while these use the FP register
+   fields, they accept both $fN and $vN names for the registers):  
+   "O"  MDMX alignment offset (OP_*_ALN)
+   "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
+   "X"  MDMX destination register (OP_*_FD) 
+   "Y"  MDMX source register (OP_*_FS)
+   "Z"  MDMX source register (OP_*_FT)
+
    Other:
    "()" parens surrounding optional value
    ","  separates operands
+   "[]" brackets around index for vector-op scalar operand specifier (vr5400)
+   "+"  Start of extension sequence.
 
    Characters used so far, for quick reference when adding more:
-   "<>(),"
-   "ABCDEFGHIJLMNPRSTUVW"
-   "abcdfhijklopqrstuvwxz"
+   "%[]<>(),+"
+   "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
+   "abcdefhijklopqrstuvwxz"
+
+   Extension character sequences used so far ("+" followed by the
+   following), for quick reference when adding more:
+   "ABCD"
 */
 
@@ -298 +363 @@
 /* Instruction synchronize shared memory.  */
 #define INSN_SYNC                   0x80000000
+/* Instruction reads MDMX accumulator.  XXX FIXME: No bits left!  */
+#define INSN_READ_MDMX_ACC          0
+/* Instruction writes MDMX accumulator.  XXX FIXME: No bits left!  */
+#define INSN_WRITE_MDMX_ACC         0
 
 /* Instruction is actually a macro.  It should be ignored by the
@@ -305 +374 @@
 /* Masks used to mark instructions to indicate which MIPS ISA level
    they were introduced in.  ISAs, as defined below, are logical
-   ORs of these bits, indicatingthat they support the instructions
+   ORs of these bits, indicating that they support the instructions
    defined at the given level.  */
 
-#define INSN_ISA_MASK             0x0000ffff
-#define INSN_ISA1                 0x00000010
-#define INSN_ISA2                 0x00000020
-#define INSN_ISA3                 0x00000040
-#define INSN_ISA4                 0x00000080
-#define INSN_ISA5                 0x00000100
-#define INSN_ISA32                0x00000200
-#define INSN_ISA64                0x00000400
+#define INSN_ISA_MASK             0x00000fff
+#define INSN_ISA1                 0x00000001
+#define INSN_ISA2                 0x00000002
+#define INSN_ISA3                 0x00000004
+#define INSN_ISA4                 0x00000008
+#define INSN_ISA5                 0x00000010
+#define INSN_ISA32                0x00000020
+#define INSN_ISA64                0x00000040
+#define INSN_ISA32R2              0x00000080
+
+/* Masks used for MIPS-defined ASEs.  */
+#define INSN_ASE_MASK             0x0000f000
+
+/* MIPS 16 ASE */
+#define INSN_MIPS16               0x00002000
+/* MIPS-3D ASE */
+#define INSN_MIPS3D               0x00004000
+/* MDMX ASE */ 
+#define INSN_MDMX                 0x00008000
 
 /* Chip specific instructions.  These are bitmasks.  */
@@ -327 +407 @@
 /* Toshiba R3900 instruction.  */
 #define INSN_3900                 0x00080000
-/* 32-bit code running on a ISA3+ CPU.  */
-#define INSN_GP32                 0x00100000
+/* MIPS R10000 instruction.  */
+#define INSN_10000                0x00100000
+/* Broadcom SB-1 instruction.  */
+#define INSN_SB1                  0x00200000
+/* NEC VR4111/VR4181 instruction.  */
+#define INSN_4111                 0x00400000
+/* NEC VR4120 instruction.  */
+#define INSN_4120                 0x00800000
+/* NEC VR5400 instruction.  */
+#define INSN_5400                 0x01000000
+/* NEC VR5500 instruction.  */
+#define INSN_5500                 0x02000000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
@@ -338 +428 @@
 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
+
 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
+
+#define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
 #define CPU_UNKNOWN     0               /* Gas internal use.  */
-#define CPU_R2000       2000
 #define CPU_R3000       3000
 #define CPU_R3900       3900
@@ -351 +443 @@
 #define CPU_VR4100      4100
 #define CPU_R4111       4111
+#define CPU_VR4120      4120
 #define CPU_R4300       4300
 #define CPU_R4400       4400
@@ -356 +449 @@
 #define CPU_R4650       4650
 #define CPU_R5000       5000
+#define CPU_VR5400      5400
+#define CPU_VR5500      5500
 #define CPU_R6000       6000
 #define CPU_R8000       8000
@@ -362 +457 @@
 #define CPU_MIPS16      16
 #define CPU_MIPS32      32
-#define CPU_MIPS32_4K   3204113         /* 32, 04, octal 'K'.  */
+#define CPU_MIPS32R2    33
 #define CPU_MIPS5       5
 #define CPU_MIPS64      64
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 
-/* Test for membership in an ISA including chip specific ISAs.
-   INSN is pointer to an element of the opcode table; ISA is the
-   specified ISA to test against; and CPU is the CPU specific ISA
-   to test, or zero if no CPU specific ISA test is desired.
-   The gp32 arg is set when you need to force 32-bit register usage on
-   a machine with 64-bit registers; see the documentation under -mgp32
-   in the MIPS gas docs.  */
-
-#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32)                          \
-    ((((insn)->membership & isa) != 0                                   \
-      && ((insn)->membership & INSN_GP32 ? gp32 : 1)                    \
-     )                                                                  \
+/* Test for membership in an ISA including chip specific ISAs.  INSN
+   is pointer to an element of the opcode table; ISA is the specified
+   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
+   test, or zero if no CPU specific ISA test is desired.  */
+
+#define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
+    (((insn)->membership & isa) != 0                                    \
      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
-     || ((cpu == CPU_VR4100 || cpu == CPU_R4111)                        \
-         && ((insn)->membership & INSN_4100) != 0)                      \
-     || (cpu == CPU_R3900  && ((insn)->membership & INSN_3900) != 0))
+     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
+     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
+     || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
+         && ((insn)->membership & INSN_10000) != 0)                     \
+     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
+     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
+     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
+     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
+     || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
+     || 0)      /* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.
@@ -509 +606 @@
   M_LWR_AB,
   M_LWU_AB,
+  M_MOVE,
   M_MUL,
   M_MUL_I,
@@ -521 +619 @@
   M_REMU_3,
   M_REMU_3I,
+  M_DROL,
   M_ROL,
+  M_DROL_I,
   M_ROL_I,
+  M_DROR,
   M_ROR,
+  M_DROR_I,
   M_ROR_I,
   M_S_DA,

branches/GNU/src/binutils/include/opcode/ns32k.h

@@ -1 +1 @@
 /* ns32k-opcode.h -- Opcode table for National Semi 32k processor
-   Copyright 1987, 1991, 1994 Free Software Foundation, Inc.
+   Copyright 1987, 1991, 1994, 2002 Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler.
@@ -38 +38 @@
    The operands in the source instruction are checked for inconsistent
    semantics.
- 
+
         F : 32 bit float        general form
         L : 64 bit float            "
@@ -81 +81 @@
 */
 struct ns32k_opcode {
-  char *name;
+  const char *name;
   unsigned char opcode_id_size; /* not used by the assembler */
   unsigned char opcode_size;
   unsigned long opcode_seed;
-  char *operands;
+  const char *operands;
   unsigned char im_size;        /* not used by dissassembler */
-  char *default_args;           /* default to those args when none given */
+  const char *default_args;     /* default to those args when none given */
   char default_modec;           /* default to this addr-mode when ambigous
                                    ie when the argument of a general addr-mode
@@ -104 +104 @@
                                 /* particular opcode */
 {
-  int obits;            /* number of opcode bits */
-  int ibits;            /* number of instruction bits */
-  ns32k_opcodeT code;   /* op-code (may be > 8 bits!) */
-  char *args;           /* how to compile said opcode */
+  int obits;                    /* number of opcode bits */
+  int ibits;                    /* number of instruction bits */
+  ns32k_opcodeT code;           /* op-code (may be > 8 bits!) */
+  const char *args;             /* how to compile said opcode */
 };
 
 struct not                      /* ns32k opcode text */
 {
-  char *            name;       /* opcode name: lowercase string  [key]  */
-  struct not_wot    detail;     /* rest of opcode table          [datum] */
+  const char *name;             /* opcode name: lowercase string  [key]  */
+  struct not_wot detail;        /* rest of opcode table          [datum] */
 };
 
 /* Instructions look like this:
-    
+
    basic instruction--1, 2, or 3 bytes
    index byte for operand A, if operand A is indexed--1 byte
@@ -131 +131 @@
 
    Each operand has a digit and a letter.
-   
+
    The digit gives the position in the assembly language.  The letter,
    one of the following, tells us what kind of operand it is.  */
@@ -483 +483 @@
 };
 
-static const int numopcodes=sizeof(ns32k_opcodes)/sizeof(ns32k_opcodes[0]);
-
-static const struct ns32k_opcode *const endop = ns32k_opcodes+sizeof(ns32k_opcodes)/sizeof(ns32k_opcodes[0]);
-
 #define MAX_ARGS 4
 #define ARG_LEN 50

branches/GNU/src/binutils/include/opcode/pj.h

@@ -37 +37 @@
 
                   
-typedef struct 
+typedef struct pj_opc_info_t
 {
   short opcode;
@@ -43 +43 @@
   char len;
   unsigned char arg[2];
-  const char *name;
+  union {
+    const char *name;
+    void (*func) PARAMS ((struct pj_opc_info_t *, char *));
+  } u;
 } pj_opc_info_t;

branches/GNU/src/binutils/include/opcode/ppc.h

@@ -1 +1 @@
 /* ppc.h -- Header file for PowerPC opcode table
-   Copyright 1994, 1995, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1999, 2000, 2001, 2002
+   Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
@@ -90 +91 @@
 
 /* Opcode is supported by Altivec Vector Unit */
-#define PPC_OPCODE_ALTIVEC   (01000)
+#define PPC_OPCODE_ALTIVEC (01000)
+
+/* Opcode is supported by PowerPC 403 processor.  */
+#define PPC_OPCODE_403 (02000)
+
+/* Opcode is supported by PowerPC BookE processor.  */
+#define PPC_OPCODE_BOOKE (04000)
+
+/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
+#define PPC_OPCODE_BOOKE64 (010000)
+
+/* Opcode is only supported by Power4 architecture.  */
+#define PPC_OPCODE_POWER4 (020000)
+
+/* Opcode isn't supported by Power4 architecture.  */
+#define PPC_OPCODE_NOPOWER4 (040000)
+
+/* Opcode is only supported by POWERPC Classic architecture.  */
+#define PPC_OPCODE_CLASSIC (0100000)
+
+/* Opcode is only supported by e500x2 Core.  */
+#define PPC_OPCODE_SPE     (0200000)
+
+/* Opcode is supported by e500x2 Integer select APU.  */
+#define PPC_OPCODE_ISEL     (0400000)
+
+/* Opcode is an e500 SPE floating point instruction.  */
+#define PPC_OPCODE_EFS      (01000000)
+
+/* Opcode is supported by branch locking APU.  */
+#define PPC_OPCODE_BRLOCK   (02000000)
+
+/* Opcode is supported by performance monitor APU.  */
+#define PPC_OPCODE_PMR      (04000000)
+
+/* Opcode is supported by cache locking APU.  */
+#define PPC_OPCODE_CACHELCK (010000000)
+
+/* Opcode is supported by machine check APU.  */
+#define PPC_OPCODE_RFMCI    (020000000)
 
 /* A macro to extract the major opcode from an instruction.  */
@@ -123 +163 @@
      can accept any value).  */
   unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
+                                   int dialect,
                                    const char **errmsg));
 
@@ -142 +183 @@
      this operand (i.e., the instruction does not match).  If the
      operand is valid, *INVALID will not be changed.  */
-  long (*extract) PARAMS ((unsigned long instruction, int *invalid));
+  long (*extract) PARAMS ((unsigned long instruction, int dialect,
+                           int *invalid));
 
   /* One bit syntax flags.  */
@@ -231 +273 @@
 #define PPC_OPERAND_VR (010000)
 
+/* This operand is for the DS field in a DS form instruction.  */
+#define PPC_OPERAND_DS (020000)
 
 

branches/GNU/src/binutils/include/opcode/sparc.h

@@ -1 +1 @@
 /* Definitions for opcode table for the sparc.
-   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000
+   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002
    Free Software Foundation, Inc.
 
@@ -21 +21 @@
 Boston, MA 02111-1307, USA.  */
 
-#include <ansidecl.h>
+#include "ansidecl.h"
 
 /* The SPARC opcode table (and other related data) is defined in

branches/GNU/src/binutils/include/opcode/tic54x.h

@@ -20 +20 @@
 02111-1307, USA.  */
 
-#ifndef _TIC54X_H_
-#define _TIC54X_H_
+#ifndef _opcode_tic54x_h_
+#define _opcode_tic54x_h_
 
 typedef struct _symbol
@@ -87 +87 @@
   /* The opcode mnemonic */
   const char *name;
-
   unsigned int words; /* insn size in words */
   int minops, maxops; /* min/max operand count */
@@ -142 +141 @@
 #define FL_SMR      0x200 /* Smem read (for flagging write-only *+ARx */
 
+#define FL_PAR      0x400 /* Parallel instruction. */
+
   unsigned short opcode2, mask2;   /* some insns have an extended opcode */
+
+  const char* parname;
+  enum optype paroperand_types[MAX_OPERANDS];
 
 } template;
 
-typedef struct _partemplate {
-  char *name;
-  char *parname;
-  unsigned int words; /* length in words */
-  int minops, maxops; /* min/max operand count for 2nd part of insn */
-  unsigned short opcode;
-  unsigned short mask;
-  enum optype operand_types[MAX_OPERANDS];
-  enum optype paroperand_types[MAX_OPERANDS];
-} partemplate;
-
 extern const template tic54x_unknown_opcode;
 extern const template tic54x_optab[];
-extern const partemplate tic54x_paroptab[];
+extern const template tic54x_paroptab[];
 extern const symbol mmregs[], regs[];
 extern const symbol condition_codes[], cc2_codes[], status_bits[];
 extern const symbol cc3_codes[];
 extern const char *misc_symbols[];
+struct disassemble_info;
+extern const template* tic54x_get_insn (struct disassemble_info *, 
+                                        bfd_vma, unsigned short, int *);
 
-#endif /* TIC54X_H */
+#endif /* _opcode_tic54x_h_ */

branches/GNU/src/binutils/include/opcode/v850.h

@@ -1 +1 @@
 /* v850.h -- Header file for NEC V850 opcode table
-   Copyright 1996, 1997 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 2001 Free Software Foundation, Inc.
    Written by J.T. Conklin, Cygnus Support
 
@@ -155 +155 @@
 #define V850_NOT_R0             0x80
 
-/* CYGNUS LOCAL v850e */
 /* push/pop type instruction, V850E specific.  */
 #define V850E_PUSH_POP          0x100