Index: trunk/src/gcc/gcc/config/alpha/alpha.h
===================================================================
--- trunk/src/gcc/gcc/config/alpha/alpha.h	(revision 1591)
+++ trunk/src/gcc/gcc/config/alpha/alpha.h	(revision 1594)
@@ -650,4 +650,5 @@
   ((REGNO) >= 32 && (REGNO) <= 62 					\
    ? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode		\
+     || (MODE) == SCmode || (MODE) == DCmode				\
    : 1)
 
Index: trunk/src/gcc/gcc/config/i370/i370.md
===================================================================
--- trunk/src/gcc/gcc/config/i370/i370.md	(revision 1591)
+++ trunk/src/gcc/gcc/config/i370/i370.md	(revision 1594)
@@ -475,8 +475,8 @@
 
 ;
-; cmpstrsi instruction pattern(s).
-;
-
-(define_expand "cmpstrsi"
+; cmpmemsi instruction pattern(s).
+;
+
+(define_expand "cmpmemsi"
   [(set (match_operand:SI 0 "general_operand" "")
 	  (compare (match_operand:BLK 1 "general_operand" "")
@@ -546,5 +546,5 @@
 
         /* Compare! */
-        emit_insn (gen_cmpstrsi_1 (result, reg1, reg2));
+        emit_insn (gen_cmpmemsi_1 (result, reg1, reg2));
     }
   DONE;
@@ -570,5 +570,5 @@
 ; Compare a block that is larger than 255 bytes in length.
 
-(define_insn "cmpstrsi_1"
+(define_insn "cmpmemsi_1"
   [(set (match_operand:SI 0 "register_operand" "+d")
         (compare
Index: trunk/src/gcc/gcc/config/ia64/ia64.c
===================================================================
--- trunk/src/gcc/gcc/config/ia64/ia64.c	(revision 1591)
+++ trunk/src/gcc/gcc/config/ia64/ia64.c	(revision 1594)
@@ -1091,6 +1091,5 @@
 	scratch = no_new_pseudos ? subtarget : gen_reg_rtx (DImode);
 
-      emit_insn (gen_load_symptr (subtarget, plus_constant (sym, hi),
-				  scratch));
+      ia64_expand_load_address (subtarget, plus_constant (sym, hi), scratch);
       emit_insn (gen_adddi3 (temp, subtarget, GEN_INT (lo)));
     }
@@ -7192,9 +7191,10 @@
       if (! INSN_P (insn))
         insn = prev_active_insn (insn);
-      if (GET_CODE (insn) == INSN
-	  && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
-	  && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
-	{
-	  saw_stop = 1;
+      /* Skip over insns that expand to nothing.  */
+      while (GET_CODE (insn) == INSN && get_attr_empty (insn) == EMPTY_YES)
+        {
+	  if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
+	      && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
+	    saw_stop = 1;
 	  insn = prev_active_insn (insn);
 	}
@@ -7413,4 +7413,10 @@
      tree decl;
 {
+  /* We can't perform a sibcall if the current function has the syscall_linkage
+     attribute.  */
+  if (lookup_attribute ("syscall_linkage",
+			TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
+    return false;
+
   /* We must always return with our current GP.  This means we can
      only sibcall to functions defined in the current module.  */
Index: trunk/src/gcc/gcc/config/ia64/ia64.md
===================================================================
--- trunk/src/gcc/gcc/config/ia64/ia64.md	(revision 1591)
+++ trunk/src/gcc/gcc/config/ia64/ia64.md	(revision 1594)
@@ -148,4 +148,8 @@
 
 (define_attr "predicable" "no,yes" (const_string "yes"))
+
+;; Empty.  True iff this insn does not generate any code.
+
+(define_attr "empty" "no,yes" (const_string "no"))
 
 
@@ -5086,5 +5090,6 @@
   ""
   [(set_attr "itanium_class" "ignore")
-   (set_attr "predicable" "no")])
+   (set_attr "predicable" "no")
+   (set_attr "empty" "yes")])
 
 ;; Allocate a new register frame.
@@ -5254,5 +5259,6 @@
   ""
   ""
-  [(set_attr "itanium_class" "nop_x")])
+  [(set_attr "itanium_class" "nop_x")
+   (set_attr "empty" "yes")])
 
 (define_insn "bundle_selector"
@@ -5278,5 +5284,6 @@
   ";;"
   [(set_attr "itanium_class" "stop_bit")
-   (set_attr "predicable" "no")])
+   (set_attr "predicable" "no")
+   (set_attr "empty" "yes")])
 
 (define_expand "trap"
Index: trunk/src/gcc/gcc/config/pa/pa.c
===================================================================
--- trunk/src/gcc/gcc/config/pa/pa.c	(revision 1591)
+++ trunk/src/gcc/gcc/config/pa/pa.c	(revision 1594)
@@ -1406,12 +1406,15 @@
 
   /* Handle secondary reloads for loads/stores of FP registers from
-     REG+D addresses where D does not fit in 5 bits, including
+     REG+D addresses where D does not fit in 5 or 14 bits, including
      (subreg (mem (addr))) cases.  */
   if (fp_reg_operand (operand0, mode)
       && ((GET_CODE (operand1) == MEM
-	   && ! memory_address_p (DFmode, XEXP (operand1, 0)))
+	   && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
+				 XEXP (operand1, 0)))
 	  || ((GET_CODE (operand1) == SUBREG
 	       && GET_CODE (XEXP (operand1, 0)) == MEM
-	       && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
+	       && !memory_address_p ((GET_MODE_SIZE (mode) == 4
+				      ? SFmode : DFmode),
+				     XEXP (XEXP (operand1, 0), 0)))))
       && scratch_reg)
     {
@@ -1442,8 +1445,12 @@
   else if (fp_reg_operand (operand1, mode)
 	   && ((GET_CODE (operand0) == MEM
-		&& ! memory_address_p (DFmode, XEXP (operand0, 0)))
+		&& !memory_address_p ((GET_MODE_SIZE (mode) == 4
+				       ? SFmode : DFmode),
+				      XEXP (operand0, 0)))
 	       || ((GET_CODE (operand0) == SUBREG)
 		   && GET_CODE (XEXP (operand0, 0)) == MEM
-		   && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
+		   && !memory_address_p ((GET_MODE_SIZE (mode) == 4
+					  ? SFmode : DFmode),
+					 XEXP (XEXP (operand0, 0), 0))))
 	   && scratch_reg)
     {
@@ -1711,4 +1718,5 @@
 		  operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
 							mode, temp);
+		  operands[1] = gen_rtx_MEM (mode, operands[1]);
 		  emit_move_sequence (operands, mode, temp);
 		}
@@ -6946,5 +6954,13 @@
      the remaining cases.  */
   if (attr_length_indirect_call (insn) == 8)
-    return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2";
+    {
+      /* The HP linker substitutes a BLE for millicode calls using
+	 the short PIC PCREL form.  Thus, we must use %r31 as the
+	 link register when generating PA 1.x code.  */
+      if (TARGET_PA_20)
+	return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
+      else
+	return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
+    }
 
   /* Long millicode call, but we are not generating PIC or portable runtime
Index: trunk/src/gcc/gcc/config/pa/pa.h
===================================================================
--- trunk/src/gcc/gcc/config/pa/pa.h	(revision 1591)
+++ trunk/src/gcc/gcc/config/pa/pa.h	(revision 1594)
@@ -1272,5 +1272,5 @@
    `S' is the constant 31.
 
-   `T' is for fp loads and stores.  */
+   `T' is for floating-point loads and stores.  */
 #define EXTRA_CONSTRAINT(OP, C)				\
   ((C) == 'Q' ?						\
@@ -1291,20 +1291,22 @@
 	  || memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
 	  || reload_in_progress))			\
-   : ((C) == 'T' ? 					\
-      (GET_CODE (OP) == MEM				\
-       /* Using DFmode forces only short displacements	\
-	  to be recognized as valid in reg+d addresses. \
-	  However, this is not necessary for PA2.0 since\
-	  it has long FP loads/stores.			\
-							\
-	  FIXME: the ELF32 linker clobbers the LSB of	\
-	  the FP register number in {fldw,fstw} insns.	\
-	  Thus, we only allow long FP loads/stores on	\
-	  TARGET_64BIT.  */				\
-       && memory_address_p ((TARGET_PA_20		\
-			     && !TARGET_ELF32		\
-			     ? GET_MODE (OP)		\
-			     : DFmode),			\
-			    XEXP (OP, 0))		\
+   : ((C) == 'T' ?							\
+      (GET_CODE (OP) == MEM						\
+       /* Floating-point loads and stores are used to load		\
+	  integer values as well as floating-point values.		\
+	  They don't have the same set of REG+D address modes		\
+	  as integer loads and stores.  PA 1.x supports only		\
+	  short displacements.  PA 2.0 supports long displacements	\
+	  but the base register needs to be aligned.			\
+									\
+	  The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and		\
+	  DFmode test the validity of an address for use in a           \
+	  floating point load or store.  So, we use SFmode/DFmode       \
+	  to see if the address is valid for a floating-point           \
+	  load/store operation.  */                                     \
+       && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4		\
+			     ? SFmode					\
+			     : DFmode),					\
+			    XEXP (OP, 0))				\
        && !(GET_CODE (XEXP (OP, 0)) == LO_SUM		\
 	    && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
@@ -1407,15 +1409,34 @@
 	base = XEXP (X, 1), index = XEXP (X, 0);	\
       if (base != 0)					\
-	if (GET_CODE (index) == CONST_INT		\
-	    && ((INT_14_BITS (index)			\
-		 && (TARGET_SOFT_FLOAT			\
-		     || (TARGET_PA_20			\
-			 && ((MODE == SFmode		\
-			      && (INTVAL (index) % 4) == 0)\
-			     || (MODE == DFmode		\
-				 && (INTVAL (index) % 8) == 0)))\
-		     || ((MODE) != SFmode && (MODE) != DFmode))) \
-		|| INT_5_BITS (index)))			\
-	  goto ADDR;					\
+	if (GET_CODE (index) == CONST_INT				\
+	    && ((INT_14_BITS (index)					\
+		 && (((MODE) != DImode					\
+		      && (MODE) != SFmode				\
+		      && (MODE) != DFmode)				\
+		     /* The base register for DImode loads and stores	\
+			with long displacements must be aligned because	\
+			the lower three bits in the displacement are	\
+			assumed to be zero.  */				\
+		     || ((MODE) == DImode				\
+			 && (!TARGET_64BIT				\
+			     || (INTVAL (index) % 8) == 0))		\
+		     /* Similarly, the base register for SFmode/DFmode	\
+			loads and stores with long displacements must	\
+			be aligned.					\
+									\
+			FIXME: the ELF32 linker clobbers the LSB of	\
+			the FP register number in PA 2.0 floating-point	\
+			insns with long displacements.  This is because	\
+			R_PARISC_DPREL14WR and other relocations like	\
+			it are not supported.  For now, we reject long	\
+			displacements on this target.  */		\
+		     || (((MODE) == SFmode || (MODE) == DFmode)		\
+			 && (TARGET_SOFT_FLOAT				\
+			     || (TARGET_PA_20				\
+				 && !TARGET_ELF32			\
+				 && (INTVAL (index)			\
+				     % GET_MODE_SIZE (MODE)) == 0)))))	\
+		|| INT_5_BITS (index)))					\
+	  goto ADDR;							\
       if (! TARGET_SOFT_FLOAT				\
 	  && ! TARGET_DISABLE_INDEXING			\
@@ -1520,4 +1541,9 @@
 	newoffset = offset & ~mask;					\
 									\
+      /* Ensure that long displacements are aligned.  */		\
+      if (!VAL_5_BITS_P (newoffset)					\
+	  && GET_MODE_CLASS (MODE) == MODE_FLOAT)			\
+	newoffset &= ~(GET_MODE_SIZE (MODE) -1);			\
+									\
       if (newoffset != 0						\
 	  && VAL_14_BITS_P (newoffset))					\
Index: trunk/src/gcc/gcc/config/pa/pa.md
===================================================================
--- trunk/src/gcc/gcc/config/pa/pa.md	(revision 1591)
+++ trunk/src/gcc/gcc/config/pa/pa.md	(revision 1594)
@@ -2266,7 +2266,7 @@
 (define_insn ""
   [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
-				"=r,r,r,r,r,r,Q,!*q,!f,f,*TR")
+				"=r,r,r,r,r,r,Q,!*q,!r,!f,f,*TR")
 	(match_operand:SI 1 "move_operand"
-				"A,r,J,N,K,RQ,rM,!rM,!fM,*RT,f"))]
+				"A,r,J,N,K,RQ,rM,!rM,!*q,!fM,*RT,f"))]
   "(register_operand (operands[0], SImode)
     || reg_or_0_operand (operands[1], SImode))
@@ -2281,16 +2281,17 @@
    stw%M0 %r1,%0
    mtsar %r1
+   {mfctl|mfctl,w} %%sar,%0
    fcpy,sgl %f1,%0
    fldw%F1 %1,%0
    fstw%F0 %1,%0"
-  [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
+  [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
    (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
-				"=r,r,r,r,r,r,Q,!*q")
+				"=r,r,r,r,r,r,Q,!*q,!r")
 	(match_operand:SI 1 "move_operand"
-				"A,r,J,N,K,RQ,rM,!rM"))]
+				"A,r,J,N,K,RQ,rM,!rM,!*q"))]
   "(register_operand (operands[0], SImode)
     || reg_or_0_operand (operands[1], SImode))
@@ -2304,8 +2305,9 @@
    ldw%M1 %1,%0
    stw%M0 %r1,%0
-   mtsar %r1"
-  [(set_attr "type" "load,move,move,move,move,load,store,move")
+   mtsar %r1
+   {mfctl|mfctl,w} %%sar,%0"
+  [(set_attr "type" "load,move,move,move,move,load,store,move,move")
    (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4")])
 
 (define_insn ""
@@ -2701,6 +2703,8 @@
 
 (define_insn ""
-  [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,!*q,!*f")
-	(match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,!rM,!*fM"))]
+  [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand"
+				"=r,r,r,r,r,Q,!*q,!r,!*f")
+	(match_operand:HI 1 "move_operand"
+				"r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
   "register_operand (operands[0], HImode)
    || reg_or_0_operand (operands[1], HImode)"
@@ -2713,8 +2717,9 @@
    sth%M0 %r1,%0
    mtsar %r1
+   {mfctl|mfctl,w} %sar,%0
    fcpy,sgl %f1,%0"
-  [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
+  [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
    (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4")])
 
 (define_insn ""
@@ -2816,6 +2821,8 @@
 
 (define_insn ""
-  [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,!*q,!*f")
-	(match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,!rM,!*fM"))]
+  [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand"
+				"=r,r,r,r,r,Q,!*q,!r,!*f")
+	(match_operand:QI 1 "move_operand"
+				"r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
   "register_operand (operands[0], QImode)
    || reg_or_0_operand (operands[1], QImode)"
@@ -2828,8 +2835,9 @@
    stb%M0 %r1,%0
    mtsar %r1
+   {mfctl|mfctl,w} %%sar,%0
    fcpy,sgl %f1,%0"
-  [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
+  [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
    (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4")])
 
 (define_insn ""
@@ -3140,7 +3148,7 @@
 (define_insn ""
   [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
-				"=r,r,r,r,r,Q,!*q,!f,f,*TR")
+				"=r,r,r,r,r,Q,!f,f,*TR")
 	(match_operand:DF 1 "move_operand"
-				"r,J,N,K,RQ,rM,!rM,!fM,*RT,f"))]
+				"r,J,N,K,RQ,rM,!fM,*RT,f"))]
   "(register_operand (operands[0], DFmode)
     || reg_or_0_operand (operands[1], DFmode))
@@ -3153,11 +3161,10 @@
    ldd%M1 %1,%0
    std%M0 %r1,%0
-   mtsar %r1
    fcpy,dbl %f1,%0
    fldd%F1 %1,%0
    fstd%F0 %1,%0"
-  [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
+  [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
    (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4")])
 
 (define_insn ""
@@ -3299,7 +3306,7 @@
 (define_insn ""
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
-				"=r,r,r,r,r,r,Q,!*q,!f,f,*TR")
+				"=r,r,r,r,r,r,Q,!*q,!r,!f,f,*TR")
 	(match_operand:DI 1 "move_operand"
-				"A,r,J,N,K,RQ,rM,!rM,!fM,*RT,f"))]
+				"A,r,J,N,K,RQ,rM,!rM,!*q,!fM,*RT,f"))]
   "(register_operand (operands[0], DImode)
     || reg_or_0_operand (operands[1], DImode))
@@ -3314,10 +3321,11 @@
    std%M0 %r1,%0
    mtsar %r1
+   {mfctl|mfctl,w} %%sar,%0
    fcpy,dbl %f1,%0
    fldd%F1 %1,%0
    fstd%F0 %1,%0"
-  [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
+  [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
    (set_attr "pa_combine_type" "addmove")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
 
 (define_insn ""
Index: trunk/src/gcc/gcc/config/s390/s390-protos.h
===================================================================
--- trunk/src/gcc/gcc/config/s390/s390-protos.h	(revision 1591)
+++ trunk/src/gcc/gcc/config/s390/s390-protos.h	(revision 1594)
@@ -70,5 +70,5 @@
 extern void s390_expand_movstr PARAMS ((rtx, rtx, rtx));
 extern void s390_expand_clrstr PARAMS ((rtx, rtx));
-extern void s390_expand_cmpstr PARAMS ((rtx, rtx, rtx, rtx));
+extern void s390_expand_cmpmem PARAMS ((rtx, rtx, rtx, rtx));
 extern rtx s390_return_addr_rtx PARAMS ((int, rtx));
 
Index: trunk/src/gcc/gcc/config/s390/s390.c
===================================================================
--- trunk/src/gcc/gcc/config/s390/s390.c	(revision 1591)
+++ trunk/src/gcc/gcc/config/s390/s390.c	(revision 1594)
@@ -2832,5 +2832,5 @@
 
 void
-s390_expand_cmpstr (target, op0, op1, len)
+s390_expand_cmpmem (target, op0, op1, len)
      rtx target;
      rtx op0;
@@ -2839,7 +2839,7 @@
 {
   rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) = 
-    TARGET_64BIT ? gen_cmpstr_short_64 : gen_cmpstr_short_31;
+    TARGET_64BIT ? gen_cmpmem_short_64 : gen_cmpmem_short_31;
   rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) = 
-    TARGET_64BIT ? gen_cmpstr_long_64 : gen_cmpstr_long_31;
+    TARGET_64BIT ? gen_cmpmem_long_64 : gen_cmpmem_long_31;
   rtx (*gen_result) PARAMS ((rtx)) =
     GET_MODE (target) == DImode ? gen_cmpint_di : gen_cmpint_si;
Index: trunk/src/gcc/gcc/config/s390/s390.md
===================================================================
--- trunk/src/gcc/gcc/config/s390/s390.md	(revision 1591)
+++ trunk/src/gcc/gcc/config/s390/s390.md	(revision 1594)
@@ -1864,8 +1864,8 @@
 
 ;
-; cmpstrM instruction pattern(s).
-;
-
-(define_expand "cmpstrdi"
+; cmpmemM instruction pattern(s).
+;
+
+(define_expand "cmpmemdi"
   [(set (match_operand:DI 0 "register_operand" "")
         (compare:DI (match_operand:BLK 1 "memory_operand" "")
@@ -1874,8 +1874,8 @@
    (use (match_operand:DI 4 "" ""))]
   "TARGET_64BIT"
-  "s390_expand_cmpstr (operands[0], operands[1], 
+  "s390_expand_cmpmem (operands[0], operands[1], 
                        operands[2], operands[3]); DONE;")
 
-(define_expand "cmpstrsi"
+(define_expand "cmpmemsi"
   [(set (match_operand:SI 0 "register_operand" "")
         (compare:SI (match_operand:BLK 1 "memory_operand" "")
@@ -1884,5 +1884,5 @@
    (use (match_operand:SI 4 "" ""))]
   ""
-  "s390_expand_cmpstr (operands[0], operands[1], 
+  "s390_expand_cmpmem (operands[0], operands[1], 
                        operands[2], operands[3]); DONE;")
 
@@ -1890,5 +1890,5 @@
 ; The block length is taken as (operands[2] % 256) + 1.
 
-(define_insn "cmpstr_short_64"
+(define_insn "cmpmem_short_64"
   [(set (reg:CCS 33)
         (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
@@ -1918,5 +1918,5 @@
    (set_attr "length"  "*,14")])
 
-(define_insn "cmpstr_short_31"
+(define_insn "cmpmem_short_31"
   [(set (reg:CCS 33)
         (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
@@ -1948,5 +1948,5 @@
 ; Compare a block of arbitrary length.
 
-(define_insn "cmpstr_long_64"
+(define_insn "cmpmem_long_64"
   [(clobber (match_operand:TI 0 "register_operand" "=d"))
    (clobber (match_operand:TI 1 "register_operand" "=d"))
@@ -1963,5 +1963,5 @@
    (set_attr "length"  "8")])
 
-(define_insn "cmpstr_long_31"
+(define_insn "cmpmem_long_31"
   [(clobber (match_operand:DI 0 "register_operand" "=d"))
    (clobber (match_operand:DI 1 "register_operand" "=d"))
Index: trunk/src/gcc/gcc/config/sh/sh.md
===================================================================
--- trunk/src/gcc/gcc/config/sh/sh.md	(revision 1591)
+++ trunk/src/gcc/gcc/config/sh/sh.md	(revision 1594)
@@ -2183,5 +2183,5 @@
 	parts[1] = gen_reg_rtx (SImode);
 	emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
-	parts[choice-1] = operands[1];
+	emit_move_insn (parts[choice-1], operands[1]);
 	emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
 	emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
Index: trunk/src/gcc/gcc/config/sh/t-linux
===================================================================
--- trunk/src/gcc/gcc/config/sh/t-linux	(revision 1591)
+++ trunk/src/gcc/gcc/config/sh/t-linux	(revision 1594)
@@ -15,6 +15,9 @@
 
 # Override t-slibgcc-elf-ver to export some libgcc symbols with
-# the symbol versions that glibc used.
-SHLIB_MAPFILES =  $(srcdir)/libgcc-std.ver $(srcdir)/config/sh/libgcc-glibc.ver
+# the symbol versions that glibc used.  Also use sh specific
+# libgcc-std.ver to avoid to export some lib1func routines which
+# shoud not be called via PLT.
+SHLIB_MAPFILES =  $(srcdir)/config/sh/libgcc-std.ver \
+	$(srcdir)/config/sh/libgcc-glibc.ver
 
 # Override SHLIB_LINK and SHLIB_INSTALL to use linker script
Index: trunk/src/gcc/gcc/config/sparc/sol2-bi.h
===================================================================
--- trunk/src/gcc/gcc/config/sparc/sol2-bi.h	(revision 1591)
+++ trunk/src/gcc/gcc/config/sparc/sol2-bi.h	(revision 1594)
@@ -19,4 +19,5 @@
 #define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus"
 #endif
+
 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
 #undef CPP_CPU64_DEFAULT_SPEC
@@ -26,4 +27,13 @@
 #undef ASM_CPU64_DEFAULT_SPEC
 #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "a"
+#endif
+
+#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
+#undef CPP_CPU64_DEFAULT_SPEC
+#define CPP_CPU64_DEFAULT_SPEC ""
+#undef ASM_CPU32_DEFAULT_SPEC
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
+#undef ASM_CPU64_DEFAULT_SPEC
+#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
 #endif
 
@@ -46,5 +56,5 @@
 %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
 %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=v9|mcpu=ultrasparc:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
+%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
 "
@@ -52,7 +62,8 @@
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC "\
+%{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "} \
 %{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \
-%{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "} \
-%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}} \
+%{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
+%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}} \
 %{!mcpu*:%(asm_cpu_default)} \
 "
@@ -144,5 +155,5 @@
      %{!YP,*:%{p|pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
        %{!p:%{!pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/sparcv9}}} \
-     -R /usr/ucblib} \
+     -R /usr/ucblib/sparcv9} \
    %{!compat-bsd: \
      %{!YP,*:%{p|pg:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
Index: trunk/src/gcc/gcc/config/sparc/sol2.h
===================================================================
--- trunk/src/gcc/gcc/config/sparc/sol2.h	(revision 1591)
+++ trunk/src/gcc/gcc/config/sparc/sol2.h	(revision 1594)
@@ -40,4 +40,9 @@
 #endif
 
+#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
+#undef ASM_CPU_DEFAULT_SPEC
+#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
+#endif
+
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC "\
@@ -45,4 +50,5 @@
 %{mcpu=v9:-xarch=v8plus} \
 %{mcpu=ultrasparc:-xarch=v8plusa} \
+%{mcpu=ultrasparc3:-xarch=v8plusb} \
 %{!mcpu*:%(asm_cpu_default)} \
 "
Index: trunk/src/gcc/gcc/config/sparc/sparc-protos.h
===================================================================
--- trunk/src/gcc/gcc/config/sparc/sparc-protos.h	(revision 1591)
+++ trunk/src/gcc/gcc/config/sparc/sparc-protos.h	(revision 1594)
@@ -89,4 +89,5 @@
 extern int sparc_splitdi_legitimate PARAMS ((rtx, rtx));
 extern int sparc_absnegfloat_split_legitimate PARAMS ((rtx, rtx));
+extern const char *output_ubranch PARAMS ((rtx, int, rtx));
 extern char *output_cbranch PARAMS ((rtx, rtx, int, int, int, int, rtx));
 extern const char *output_sibcall PARAMS ((rtx, rtx));
Index: trunk/src/gcc/gcc/config/sparc/sparc.c
===================================================================
--- trunk/src/gcc/gcc/config/sparc/sparc.c	(revision 1591)
+++ trunk/src/gcc/gcc/config/sparc/sparc.c	(revision 1594)
@@ -5459,4 +5459,66 @@
 
 
+/* Return the string to output an unconditional branch to LABEL, which is
+   the operand number of the label.
+
+   DEST is the destination insn (i.e. the label), INSN is the source.  */
+
+const char *
+output_ubranch (dest, label, insn)
+     rtx dest;
+     int label;
+     rtx insn;
+{
+  static char string[64];
+  bool noop = false;
+  char *p;
+
+  /* TurboSPARC is reported to have problems with
+     with
+	foo: b,a foo
+     i.e. an empty loop with the annul bit set.  The workaround is to use 
+        foo: b foo; nop
+     instead.  */
+
+  if (! TARGET_V9 && flag_delayed_branch
+      && (INSN_ADDRESSES (INSN_UID (dest))
+	  == INSN_ADDRESSES (INSN_UID (insn))))
+    {
+      strcpy (string, "b\t");
+      noop = true;
+    }
+  else
+    {
+      bool v9_form = false;
+
+      if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
+	{
+	  int delta = (INSN_ADDRESSES (INSN_UID (dest))
+		       - INSN_ADDRESSES (INSN_UID (insn)));
+	  /* Leave some instructions for "slop".  */
+	  if (delta >= -260000 && delta < 260000)
+	    v9_form = true;
+	}
+
+      if (v9_form)
+	strcpy (string, "ba%*,pt\t%%xcc, ");
+      else
+	strcpy (string, "b%*\t");
+    }
+
+  p = strchr (string, '\0');
+  *p++ = '%';
+  *p++ = 'l';
+  *p++ = '0' + label;
+  *p++ = '%';
+  if (noop)
+    *p++ = '#';
+  else
+    *p++ = '(';
+  *p = '\0';
+
+  return string;
+}
+
 /* Return the string to output a conditional branch to LABEL, which is
    the operand number of the label.  OP is the conditional expression.
@@ -5464,11 +5526,11 @@
    floating point) and its mode specifies what kind of comparison we made.
 
+   DEST is the destination insn (i.e. the label), INSN is the source.
+
    REVERSED is nonzero if we should reverse the sense of the comparison.
 
    ANNUL is nonzero if we should generate an annulling branch.
 
-   NOOP is nonzero if we have to follow this branch by a noop.
-
-   INSN, if set, is the insn.  */
+   NOOP is nonzero if we have to follow this branch by a noop.  */
 
 char *
@@ -5508,5 +5570,5 @@
      ba .LC29  */
 
-  far = get_attr_length (insn) >= 3;
+  far = TARGET_V9 && (get_attr_length (insn) >= 3);
   if (reversed ^ far)
     {
@@ -5638,7 +5700,5 @@
     }
 
-  if (! TARGET_V9)
-    labelno = "";
-  else
+  if (TARGET_V9)
     {
       rtx note;
@@ -5690,4 +5750,7 @@
 	}
     }
+  else
+    labelno = "";
+
   if (spaces > 0)
     *p++ = '\t';
@@ -5896,4 +5959,6 @@
    operand number of the reg.  OP is the conditional expression.  The mode
    of REG says what kind of comparison we made.
+
+   DEST is the destination insn (i.e. the label), INSN is the source.
 
    REVERSED is nonzero if we should reverse the sense of the comparison.
Index: trunk/src/gcc/gcc/config/sparc/sparc.md
===================================================================
--- trunk/src/gcc/gcc/config/sparc/sparc.md	(revision 1591)
+++ trunk/src/gcc/gcc/config/sparc/sparc.md	(revision 1594)
@@ -121,4 +121,6 @@
 
 ;; Length (in # of insns).
+;; Beware that setting a length greater or equal to 3 for conditional branches
+;; has a side-effect (see output_cbranch and output_v9branch).
 (define_attr "length" ""
   (cond [(eq_attr "type" "uncond_branch,call,sibcall")
@@ -7238,25 +7240,8 @@
 
 ;; Unconditional and other jump instructions
-;; On the SPARC, by setting the annul bit on an unconditional branch, the
-;; following insn is never executed.  This saves us a nop.  Dbx does not
-;; handle such branches though, so we only use them when optimizing.
 (define_insn "jump"
   [(set (pc) (label_ref (match_operand 0 "" "")))]
   ""
-{
-  /* TurboSPARC is reported to have problems with
-     with
-	foo: b,a foo
-     i.e. an empty loop with the annul bit set.  The workaround is to use 
-        foo: b foo; nop
-     instead.  */
-
-  if (! TARGET_V9 && flag_delayed_branch
-      && (INSN_ADDRESSES (INSN_UID (operands[0]))
-	  == INSN_ADDRESSES (INSN_UID (insn))))
-    return "b\t%l0%#";
-  else
-    return TARGET_V9 ? "ba%*,pt\t%%xcc, %l0%(" : "b%*\t%l0%(";
-}
+  "* return output_ubranch (operands[0], 0, insn);"
   [(set_attr "type" "uncond_branch")])
 
Index: trunk/src/gcc/gcc/cp/ChangeLog
===================================================================
--- trunk/src/gcc/gcc/cp/ChangeLog	(revision 1591)
+++ trunk/src/gcc/gcc/cp/ChangeLog	(revision 1594)
@@ -1,2 +1,32 @@
+2004-09-30  Release Manager
+
+	* GCC 3.3.5 Released.
+
+2004-09-21  Giovanni Bajo  <giovannibajo@gcc.gnu.org>
+
+	* decl.c (reshape_init): Remove unused variable.
+
+2004-09-21  Giovanni Bajo  <giovannibajo@gcc.gnu.org>
+
+	PR c++/14179
+	* decl.c (reshape_init): Extract array handling into...
+	(reshape_init_array): New function. Use integers instead of trees
+	for indices.
+
+2004-09-13  Gabriel Dos Reis  <gdr@integrable-solutions.net>
+
+	PR c++/15857
+	Backport from gcc-3_4-branch
+	2004-08-24  Jason Merrill  <jason@redhat.com>
+	PR c++/15461
+	* semantics.c (nullify_returns_r): Replace a DECL_STMT
+	for the NRV with an INIT_EXPR.
+
+2004-07-24  Kriang Lerdsuwanakij  <lerdsuwa@users.sourceforge.net>
+
+	PR c++/16175
+	* error.c (dump_type) <BOUND_TEMPLATE_TEMPLATE_PARM case>: Output
+	cv qualifier.
+
 2004-05-31  Release Manager
 
Index: trunk/src/gcc/gcc/doc/contrib.texi
===================================================================
--- trunk/src/gcc/gcc/doc/contrib.texi	(revision 1591)
+++ trunk/src/gcc/gcc/doc/contrib.texi	(revision 1594)
@@ -144,5 +144,5 @@
 
 @item
-The @uref{http://www.classpath.org,,GNU Classpath project}
+The @uref{http://www.gnu.org/software/classpath/,,GNU Classpath project}
 for all of their merged runtime code.
 
Index: trunk/src/gcc/gcc/doc/include/gcc-common.texi
===================================================================
--- trunk/src/gcc/gcc/doc/include/gcc-common.texi	(revision 1591)
+++ trunk/src/gcc/gcc/doc/include/gcc-common.texi	(revision 1594)
@@ -5,5 +5,5 @@
 @c Common values used in the GCC manuals:
 
-@set version-GCC 3.3.4
+@set version-GCC 3.3.5
 
 @c DEVELOPMENT is set to indicate an in-development version,
Index: trunk/src/gcc/gcc/doc/md.texi
===================================================================
--- trunk/src/gcc/gcc/doc/md.texi	(revision 1591)
+++ trunk/src/gcc/gcc/doc/md.texi	(revision 1594)
@@ -2710,8 +2710,18 @@
 @cindex @code{cmpstr@var{m}} instruction pattern
 @item @samp{cmpstr@var{m}}
-Block compare instruction, with five operands.  Operand 0 is the output;
+String compare instruction, with five operands.  Operand 0 is the output;
 it has mode @var{m}.  The remaining four operands are like the operands
 of @samp{movstr@var{m}}.  The two memory blocks specified are compared
 byte by byte in lexicographic order.  The effect of the instruction is
+to store a value in operand 0 whose sign indicates the result of the
+comparison.
+
+@cindex @code{cmpmem@var{m}} instruction pattern
+@item @samp{cmpmem@var{m}}
+Block compare instruction, with five operands like the operands
+of @samp{cmpstr@var{m}}.  The two memory blocks specified are compared
+byte by byte in lexicographic order starting at the beginning of each
+block.  Unlike @samp{cmpstr@var{m}} the instruction can prefetch
+any bytes in the two memory blocks.  The effect of the instruction is
 to store a value in operand 0 whose sign indicates the result of the
 comparison.
Index: trunk/src/gcc/gcc/doc/trouble.texi
===================================================================
--- trunk/src/gcc/gcc/doc/trouble.texi	(revision 1591)
+++ trunk/src/gcc/gcc/doc/trouble.texi	(revision 1594)
@@ -944,5 +944,5 @@
 
 @example
-string& tmp = strfunc ();
+const string& tmp = strfunc ();
 charfunc (tmp.c_str ());
 @end example
Index: trunk/src/gcc/gcc/f/BUGS
===================================================================
--- trunk/src/gcc/gcc/f/BUGS	(revision 1591)
+++ trunk/src/gcc/gcc/f/BUGS	(revision 1594)
@@ -3,5 +3,5 @@
 it is normally included within source distributions.
 
-   This file lists known bugs in the GCC-3.3.4 version of the GNU
+   This file lists known bugs in the GCC-3.3.5 version of the GNU
 Fortran compiler.  Copyright (C)
 1995,1996,1997,1998,1999,2000,2001,2002 Free Software Foundation, Inc.
@@ -13,5 +13,5 @@
 
    This section identifies bugs that `g77' _users_ might run into in
-the GCC-3.3.4 version of `g77'.  This includes bugs that are actually
+the GCC-3.3.5 version of `g77'.  This includes bugs that are actually
 in the `gcc' back end (GBE) or in `libf2c', because those sets of code
 are at least somewhat under the control of (and necessarily intertwined
Index: trunk/src/gcc/gcc/f/ChangeLog
===================================================================
--- trunk/src/gcc/gcc/f/ChangeLog	(revision 1591)
+++ trunk/src/gcc/gcc/f/ChangeLog	(revision 1594)
@@ -1,2 +1,6 @@
+2004-09-30  Release Manager
+
+	* GCC 3.3.5 Released.
+
 2004-05-31  Release Manager
 
Index: trunk/src/gcc/gcc/f/NEWS
===================================================================
--- trunk/src/gcc/gcc/f/NEWS	(revision 1591)
+++ trunk/src/gcc/gcc/f/NEWS	(revision 1594)
@@ -3,5 +3,5 @@
 it is normally included within source distributions.
 
-   This file lists news about the GCC-3.3.4 version (and some other
+   This file lists news about the GCC-3.3.5 version (and some other
 versions) of the GNU Fortran compiler.  Copyright (C)
 1995,1996,1997,1998,1999,2000,2001,2002,2003 Free Software Foundation,
@@ -384,6 +384,6 @@
 ========================
 
-There is no `g77' version 0.5.24 at this time, or planned.  0.5.24 is
-the version number designated for bug fixes and, perhaps, some new
+   There is no `g77' version 0.5.24 at this time, or planned.  0.5.24
+is the version number designated for bug fixes and, perhaps, some new
 features added, to 0.5.23.  Version 0.5.23 requires `gcc' 2.8.1, as
 0.5.24 was planned to require.
@@ -607,5 +607,5 @@
 =====================
 
-Information on previous versions is not provided in this
+   Information on previous versions is not provided in this
 `gcc/gcc/f/NEWS' file, to keep it short.  See `gcc/gcc/f/news.texi', or
 any of its other derivations (Info, HTML, dvi forms) for such
Index: trunk/src/gcc/gcc/fixinc/fixincl.x
===================================================================
--- trunk/src/gcc/gcc/fixinc/fixincl.x	(revision 1591)
+++ trunk/src/gcc/gcc/fixinc/fixincl.x	(revision 1594)
@@ -6,5 +6,5 @@
  * directory that GNU C will search.
  *
- * This file contains 164 fixup descriptions.
+ * This file contains 166 fixup descriptions.
  *
  * See README for more information.
@@ -2675,4 +2675,86 @@
 /* * * * * * * * * * * * * * * * * * * * * * * * * *
  *
+ *  Description of Irix___Generic1 fix
+ */
+tSCC zIrix___Generic1Name[] =
+     "irix___generic1";
+
+/*
+ *  File name selection pattern
+ */
+tSCC zIrix___Generic1List[] =
+  "|internal/math_core.h|";
+/*
+ *  Machine/OS name selection pattern
+ */
+tSCC* apzIrix___Generic1Machs[] = {
+        "mips-sgi-irix6.5",
+        (const char*)NULL };
+
+/*
+ *  content selection pattern - do fix if pattern found
+ */
+tSCC zIrix___Generic1Select0[] =
+       "#define ([a-z]+)\\(x\\) *__generic.*";
+
+#define    IRIX___GENERIC1_TEST_CT  1
+static tTestDesc aIrix___Generic1Tests[] = {
+  { TT_EGREP,    zIrix___Generic1Select0, (regex_t*)NULL }, };
+
+/*
+ *  Fix Command Arguments for Irix___Generic1
+ */
+static const char* apzIrix___Generic1Patch[] = {
+    "format",
+    "extern int %1(double);\n\
+extern int %1f(float);\n\
+extern int %1l(long double);\n\
+#define %1(x) (sizeof(x) == sizeof(double) ? _%1(x) \\\n\
+               : sizeof(x) == sizeof(float) ? _%1f(x) \\\n\
+               : _%1l(x))\n",
+    (char*)NULL };
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * *
+ *
+ *  Description of Irix___Generic2 fix
+ */
+tSCC zIrix___Generic2Name[] =
+     "irix___generic2";
+
+/*
+ *  File name selection pattern
+ */
+tSCC zIrix___Generic2List[] =
+  "|internal/math_core.h|";
+/*
+ *  Machine/OS name selection pattern
+ */
+tSCC* apzIrix___Generic2Machs[] = {
+        "mips-sgi-irix6.5",
+        (const char*)NULL };
+
+/*
+ *  content selection pattern - do fix if pattern found
+ */
+tSCC zIrix___Generic2Select0[] =
+       "#define ([a-z]+)\\(x,y\\) *__generic.*";
+
+#define    IRIX___GENERIC2_TEST_CT  1
+static tTestDesc aIrix___Generic2Tests[] = {
+  { TT_EGREP,    zIrix___Generic2Select0, (regex_t*)NULL }, };
+
+/*
+ *  Fix Command Arguments for Irix___Generic2
+ */
+static const char* apzIrix___Generic2Patch[] = {
+    "format",
+    "#define %1(x,y) \\\n\
+  ((sizeof(x)<=4 && sizeof(y)<=4) ? _%1f(x,y) \\\n\
+   : (sizeof(x)<=8 && sizeof(y)<=8) ? _%1(x,y) \\\n\
+   : _%1l(x,y))\n",
+    (char*)NULL };
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * *
+ *
  *  Description of Irix_Asm_Apostrophe fix
  */
@@ -6454,7 +6536,7 @@
  *  List of all fixes
  */
-#define REGEX_COUNT          178
+#define REGEX_COUNT          180
 #define MACH_LIST_SIZE_LIMIT 334
-#define FIX_COUNT            164
+#define FIX_COUNT            166
 
 /*
@@ -6527,4 +6609,6 @@
     IP_MISSING_SEMI_FIXIDX,
     IRIX___RESTRICT_FIXIDX,
+    IRIX___GENERIC1_FIXIDX,
+    IRIX___GENERIC2_FIXIDX,
     IRIX_ASM_APOSTROPHE_FIXIDX,
     IRIX_LIMITS_CONST_FIXIDX,
@@ -6954,4 +7038,14 @@
      aIrix___RestrictTests,   apzIrix___RestrictPatch, 0 },
 
+  {  zIrix___Generic1Name,    zIrix___Generic1List,
+     apzIrix___Generic1Machs,
+     IRIX___GENERIC1_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+     aIrix___Generic1Tests,   apzIrix___Generic1Patch, 0 },
+
+  {  zIrix___Generic2Name,    zIrix___Generic2List,
+     apzIrix___Generic2Machs,
+     IRIX___GENERIC2_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
+     aIrix___Generic2Tests,   apzIrix___Generic2Patch, 0 },
+
   {  zIrix_Asm_ApostropheName,    zIrix_Asm_ApostropheList,
      apzIrix_Asm_ApostropheMachs,
Index: trunk/src/gcc/gcc/fixinc/inclhack.def
===================================================================
--- trunk/src/gcc/gcc/fixinc/inclhack.def	(revision 1591)
+++ trunk/src/gcc/gcc/fixinc/inclhack.def	(revision 1594)
@@ -1551,4 +1551,50 @@
 
 /*
+ * IRIX 6.5.22 <internal/math_core.h> uses the SGI c99 __generic() intrinsic
+ * to define the fpclasify, isfinite, isinf, isnan, isnormal and signbit 
+ * functions.
+ *
+ * This was probably introduced around IRIX 6.5.18
+ */
+fix = {
+    hackname  = irix___generic1;
+    files     = internal/math_core.h;
+    mach      = "mips-sgi-irix6.5";
+    select    = "#define ([a-z]+)\\(x\\) *__generic.*";
+
+    c_fix     = format;
+    c_fix_arg = "extern int %1(double);\n"
+		"extern int %1f(float);\n"
+		"extern int %1l(long double);\n"
+		"#define %1(x) (sizeof(x) == sizeof(double) ? _%1(x) \\\n"
+		"               : sizeof(x) == sizeof(float) ? _%1f(x) \\\n"
+		"               : _%1l(x))\n";
+
+    test_text = 
+      "#define isnan(x) __generic(x,,, _isnan, _isnanf, _isnanl,,,)(x)\n";
+};
+
+
+/* Likewise <internal/math_core.h> on IRIX 6.5.19 and later uses the SGI
+   compiler's __generic intrinsic to define isgreater, isgreaterequal,
+   isless, islessequal, islessgreater and isunordered functions.  */
+fix = {
+    hackname  = irix___generic2;
+    files     = internal/math_core.h;
+    mach      = "mips-sgi-irix6.5";
+    select    = "#define ([a-z]+)\\(x,y\\) *__generic.*";
+
+    c_fix     = format;
+    c_fix_arg = "#define %1(x,y) \\\n"
+		"  ((sizeof(x)<=4 && sizeof(y)<=4) ? _%1f(x,y) \\\n"
+		"   : (sizeof(x)<=8 && sizeof(y)<=8) ? _%1(x,y) \\\n"
+		"   : _%1l(x,y))\n";
+
+    test_text = 
+      "#define isless(x,y)         __generic(x,y,, _isless, _islessf, _islessl,,,)(x,y)";
+};
+
+
+/*
  *  IRIX 5.2's <sys/asm.h> contains an asm comment with a contraction
  *  that causes the assembly preprocessor to complain about an
Index: trunk/src/gcc/gcc/intl/ChangeLog
===================================================================
--- trunk/src/gcc/gcc/intl/ChangeLog	(revision 1591)
+++ trunk/src/gcc/gcc/intl/ChangeLog	(revision 1594)
@@ -1,2 +1,6 @@
+2004-09-30  Release Manager
+
+	* GCC 3.3.5 Released.
+
 2004-05-31  Release Manager
 
Index: trunk/src/gcc/gcc/java/ChangeLog
===================================================================
--- trunk/src/gcc/gcc/java/ChangeLog	(revision 1591)
+++ trunk/src/gcc/gcc/java/ChangeLog	(revision 1594)
@@ -1,2 +1,6 @@
+2004-09-30  Release Manager
+
+	* GCC 3.3.5 Released.
+
 2004-05-31  Release Manager
 
Index: trunk/src/gcc/gcc/po/ChangeLog
===================================================================
--- trunk/src/gcc/gcc/po/ChangeLog	(revision 1591)
+++ trunk/src/gcc/gcc/po/ChangeLog	(revision 1594)
@@ -1,2 +1,6 @@
+2004-09-30  Release Manager
+
+	* GCC 3.3.5 Released.
+
 2004-05-31  Release Manager
 
Index: trunk/src/gcc/gcc/testsuite/ChangeLog
===================================================================
--- trunk/src/gcc/gcc/testsuite/ChangeLog	(revision 1591)
+++ trunk/src/gcc/gcc/testsuite/ChangeLog	(revision 1594)
@@ -1,2 +1,31 @@
+2004-09-30  Release Manager
+
+	* GCC 3.3.5 Released.
+
+2004-08-08  Roger Sayle  <roger@eyesopen.com>
+
+	PR middle-end/16790
+	* gcc.c-torture/execute/pr16790-1.c: New test case.
+
+2004-08-04  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	Backport from mainline:
+	2003-07-11  Jakub Jelinek  <jakub@redhat.com>
+	* gcc.dg/20030711-1.c: New test.
+
+2004-07-24  Kriang Lerdsuwanakij  <lerdsuwa@users.sourceforge.net>
+
+	PR c++/16175
+	* g++.dg/template/ttp10.C: New test.
+
+2004-06-28  Josef Zlomek  <zlomekj@suse.cz>
+
+	PR c/15549
+	Backport from mainline
+	2003-08-19  Mark Mitchell  <mark@codesourcery.com>
+
+		PR c++/11946.C
+		* gcc.dg/c99-bool-1.c: Remove bogus warning.
+
 2004-05-31  Release Manager
 
