| 1 | /* Table of opcodes for the Texas Instruments TMS320C54X
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| 2 | Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
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| 3 | Contributed by Timothy Wall (twall@cygnus.com)
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| 4 |
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| 5 | This program is free software; you can redistribute it and/or modify
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| 6 | it under the terms of the GNU General Public License as published by
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| 7 | the Free Software Foundation; either version 2 of the License, or
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| 8 | (at your option) any later version.
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| 9 |
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| 10 | This program is distributed in the hope that it will be useful,
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| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 13 | GNU General Public License for more details.
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| 14 |
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| 15 | You should have received a copy of the GNU General Public License
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| 16 | along with this program; if not, write to the Free Software
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| 17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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| 18 | 02111-1307, USA. */
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| 19 |
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| 20 | #include "sysdep.h"
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| 21 | #include "dis-asm.h"
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| 22 | #include "opcode/tic54x.h"
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| 23 |
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| 24 | /* these are the only register names not found in mmregs */
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| 25 | const symbol regs[] = {
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| 26 | { "AR0", 16 }, { "ar0", 16 },
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| 27 | { "AR1", 17 }, { "ar1", 17 },
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| 28 | { "AR2", 18 }, { "ar2", 18 },
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| 29 | { "AR3", 19 }, { "ar3", 19 },
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| 30 | { "AR4", 20 }, { "ar4", 20 },
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| 31 | { "AR5", 21 }, { "ar5", 21 },
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| 32 | { "AR6", 22 }, { "ar6", 22 },
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| 33 | { "AR7", 23 }, { "ar7", 23 },
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| 34 | { NULL, 0}
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| 35 | };
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| 36 |
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| 37 | /* status bits, MM registers, condition codes, etc */
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| 38 | /* some symbols are only valid for certain chips... */
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| 39 | const symbol mmregs[] = {
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| 40 | { "IMR", 0 }, { "imr", 0 },
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| 41 | { "IFR", 1 }, { "ifr", 1 },
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| 42 | { "ST0", 6 }, { "st0", 6 },
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| 43 | { "ST1", 7 }, { "st1", 7 },
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| 44 | { "AL", 8 }, { "al", 8 },
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| 45 | { "AH", 9 }, { "ah", 9 },
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| 46 | { "AG", 10 }, { "ag", 10 },
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| 47 | { "BL", 11 }, { "bl", 11 },
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| 48 | { "BH", 12 }, { "bh", 12 },
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| 49 | { "BG", 13 }, { "bg", 13 },
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| 50 | { "T", 14 }, { "t", 14 },
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| 51 | { "TRN", 15 }, { "trn", 15 },
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| 52 | { "AR0", 16 }, { "ar0", 16 },
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| 53 | { "AR1", 17 }, { "ar1", 17 },
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| 54 | { "AR2", 18 }, { "ar2", 18 },
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| 55 | { "AR3", 19 }, { "ar3", 19 },
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| 56 | { "AR4", 20 }, { "ar4", 20 },
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| 57 | { "AR5", 21 }, { "ar5", 21 },
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| 58 | { "AR6", 22 }, { "ar6", 22 },
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| 59 | { "AR7", 23 }, { "ar7", 23 },
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| 60 | { "SP", 24 }, { "sp", 24 },
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| 61 | { "BK", 25 }, { "bk", 25 },
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| 62 | { "BRC", 26 }, { "brc", 26 },
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| 63 | { "RSA", 27 }, { "rsa", 27 },
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| 64 | { "REA", 28 }, { "rea", 28 },
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| 65 | { "PMST",29 }, { "pmst",29 },
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| 66 | { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */
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| 67 | /* optional peripherals */ /* optional peripherals */
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| 68 | { "M1F", 31 }, { "m1f", 31 },
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| 69 | { "DRR0",0x20 }, { "drr0",0x20 },
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| 70 | { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */
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| 71 | { "DXR0",0x21 }, { "dxr0",0x21 },
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| 72 | { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */
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| 73 | { "SPC0",0x22 }, { "spc0",0x22 },
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| 74 | { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */
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| 75 | { "SPCE0",0x23 }, { "spce0",0x23 },
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| 76 | { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */
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| 77 | { "TIM", 0x24 }, { "tim", 0x24 },
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| 78 | { "PRD", 0x25 }, { "prd", 0x25 },
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| 79 | { "TCR", 0x26 }, { "tcr", 0x26 },
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| 80 | { "SWWSR",0x28 }, { "swwsr",0x28 },
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| 81 | { "BSCR",0x29 }, { "bscr",0x29 },
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| 82 | { "HPIC",0x2C }, { "hpic",0x2c },
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| 83 | /* 'c541, 'c545 */ /* 'c541, 'c545 */
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| 84 | { "DRR1",0x30 }, { "drr1",0x30 },
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| 85 | { "DXR1",0x31 }, { "dxr1",0x31 },
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| 86 | { "SPC1",0x32 }, { "spc1",0x32 },
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| 87 | /* 'c542, 'c543 */ /* 'c542, 'c543 */
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| 88 | { "TRCV",0x30 }, { "trcv",0x30 },
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| 89 | { "TDXR",0x31 }, { "tdxr",0x31 },
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| 90 | { "TSPC",0x32 }, { "tspc",0x32 },
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| 91 | { "TCSR",0x33 }, { "tcsr",0x33 },
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| 92 | { "TRTA",0x34 }, { "trta",0x34 },
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| 93 | { "TRAD",0x35 }, { "trad",0x35 },
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| 94 | { "AXR0",0x38 }, { "axr0",0x38 },
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| 95 | { "BKX0",0x39 }, { "bkx0",0x39 },
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| 96 | { "ARR0",0x3A }, { "arr0",0x3a },
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| 97 | { "BKR0",0x3B }, { "bkr0",0x3b },
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| 98 | /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */
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| 99 | { "CLKMD",0x58 }, { "clkmd",0x58 },
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| 100 | /* 'c548 */ /* 'c548 */
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| 101 | { "AXR1",0x3C }, { "axr1",0x3c },
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| 102 | { "BKX1",0x3D }, { "bkx1",0x3d },
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| 103 | { "ARR1",0x3E }, { "arr1",0x3e },
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| 104 | { "BKR1",0x3F }, { "bkr1",0x3f },
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| 105 | { "BDRR1",0x40 }, { "bdrr1",0x40 },
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| 106 | { "BDXR1",0x41 }, { "bdxr1",0x41 },
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| 107 | { "BSPC1",0x42 }, { "bspc1",0x42 },
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| 108 | { "BSPCE1",0x43 }, { "bspce1",0x43 },
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| 109 | { NULL, 0},
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| 110 | };
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| 111 |
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| 112 | const symbol condition_codes[] = {
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| 113 | /* condition codes */
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| 114 | { "UNC", 0 }, { "unc", 0 },
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| 115 | #define CC1 0x40
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| 116 | #define CCB 0x08
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| 117 | #define CCEQ 0x05
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| 118 | #define CCNEQ 0x04
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| 119 | #define CCLT 0x03
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| 120 | #define CCLEQ 0x07
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| 121 | #define CCGT 0x06
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| 122 | #define CCGEQ 0x02
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| 123 | #define CCOV 0x70
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| 124 | #define CCNOV 0x60
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| 125 | #define CCBIO 0x03
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| 126 | #define CCNBIO 0x02
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| 127 | #define CCTC 0x30
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| 128 | #define CCNTC 0x20
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| 129 | #define CCC 0x0C
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| 130 | #define CCNC 0x08
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| 131 | { "aeq", CC1|CCEQ }, { "AEQ", CC1|CCEQ },
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| 132 | { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ },
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| 133 | { "alt", CC1|CCLT }, { "ALT", CC1|CCLT },
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| 134 | { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ },
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| 135 | { "agt", CC1|CCGT }, { "AGT", CC1|CCGT },
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| 136 | { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ },
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| 137 | { "aov", CC1|CCOV }, { "AOV", CC1|CCOV },
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| 138 | { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV },
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| 139 | { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ },
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| 140 | { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ },
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| 141 | { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT },
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| 142 | { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ },
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| 143 | { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT },
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| 144 | { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ },
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| 145 | { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV },
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| 146 | { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV },
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| 147 | { "tc", CCTC }, { "TC", CCTC },
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| 148 | { "ntc", CCNTC }, { "NTC", CCNTC },
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| 149 | { "c", CCC }, { "C", CCC },
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| 150 | { "nc", CCNC }, { "NC", CCNC },
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| 151 | { "bio", CCBIO }, { "BIO", CCBIO },
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| 152 | { "nbio", CCNBIO }, { "NBIO", CCNBIO },
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| 153 | { NULL, 0 }
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| 154 | };
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| 155 |
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| 156 | const symbol cc2_codes[] = {
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| 157 | { "UNC", 0 }, { "unc", 0 },
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| 158 | { "AEQ", 5 }, { "aeq", 5 },
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| 159 | { "ANEQ", 4 }, { "aneq", 4 },
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| 160 | { "AGT", 6 }, { "agt", 6 },
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| 161 | { "ALT", 3 }, { "alt", 3 },
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| 162 | { "ALEQ", 7 }, { "aleq", 7 },
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| 163 | { "AGEQ", 2 }, { "ageq", 2 },
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| 164 | { "BEQ", 13 }, { "beq", 13 },
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| 165 | { "BNEQ", 12 },{ "bneq", 12 },
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| 166 | { "BGT", 14 }, { "bgt", 14 },
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| 167 | { "BLT", 11 }, { "blt", 11 },
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| 168 | { "BLEQ", 15 },{ "bleq", 15 },
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| 169 | { "BGEQ", 10 },{ "bgeq", 10 },
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| 170 | { NULL, 0 },
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| 171 | };
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| 172 |
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| 173 | const symbol cc3_codes[] = {
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| 174 | { "EQ", 0x0000 }, { "eq", 0x0000 },
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| 175 | { "LT", 0x0100 }, { "lt", 0x0100 },
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| 176 | { "GT", 0x0200 }, { "gt", 0x0200 },
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| 177 | { "NEQ", 0x0300 }, { "neq", 0x0300 },
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| 178 | { "0", 0x0000 },
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| 179 | { "1", 0x0100 },
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| 180 | { "2", 0x0200 },
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| 181 | { "3", 0x0300 },
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| 182 | { "00", 0x0000 },
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| 183 | { "01", 0x0100 },
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| 184 | { "10", 0x0200 },
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| 185 | { "11", 0x0300 },
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| 186 | { NULL, 0 },
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| 187 | };
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| 188 |
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| 189 | /* FIXME -- also allow decimal digits */
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| 190 | const symbol status_bits[] = {
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| 191 | /* status register 0 */
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| 192 | { "TC", 12 }, { "tc", 12 },
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| 193 | { "C", 11 }, { "c", 11 },
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| 194 | { "OVA", 10 }, { "ova", 10 },
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| 195 | { "OVB", 9 }, { "ovb", 9 },
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| 196 | /* status register 1 */
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| 197 | { "BRAF",15 }, { "braf",15 },
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| 198 | { "CPL", 14 }, { "cpl", 14 },
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| 199 | { "XF", 13 }, { "xf", 13 },
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| 200 | { "HM", 12 }, { "hm", 12 },
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| 201 | { "INTM",11 }, { "intm",11 },
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| 202 | { "OVM", 9 }, { "ovm", 9 },
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| 203 | { "SXM", 8 }, { "sxm", 8 },
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| 204 | { "C16", 7 }, { "c16", 7 },
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| 205 | { "FRCT", 6 }, { "frct", 6 },
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| 206 | { "CMPT", 5 }, { "cmpt", 5 },
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| 207 | { NULL, 0 },
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| 208 | };
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| 209 |
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| 210 | const char *misc_symbols[] = {
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| 211 | "ARP", "arp",
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| 212 | "DP", "dp",
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| 213 | "ASM", "asm",
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| 214 | "TS", "ts",
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| 215 | NULL
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| 216 | };
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| 217 |
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| 218 | /* Due to the way instructions are hashed and scanned in
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| 219 | gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively
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| 220 | placed
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| 221 |
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| 222 | Items marked with "PREFER" have been moved prior to a more costly
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| 223 | instruction with a similar operand format.
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| 224 |
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| 225 | Mnemonics which can take either a predefined symbol or a memory reference
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| 226 | as an argument are arranged so that the more restrictive (predefined
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| 227 | symbol) version is checked first (marked "SRC").
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| 228 | */
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| 229 | #define ZPAR 0,{OP_None}
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| 230 | #define REST 0,0,ZPAR
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| 231 | #define XREST ZPAR
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| 232 | const template tic54x_unknown_opcode =
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| 233 | { "???", 1,0,0,0x0000, 0x0000, {0}, 0, REST};
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| 234 | const template tic54x_optab[] = {
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| 235 | /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
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| 236 | { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
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| 237 | { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
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| 238 | { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
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| 239 | { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
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| 240 |
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| 241 | { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
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| 242 | { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
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| 243 | { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
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| 244 | { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
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| 245 | { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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| 246 | { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
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| 247 | { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
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| 248 | { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/
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| 249 | { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
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| 250 | FL_EXT|FL_SMR, 0x0C00, 0xFCE0, XREST},
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| 251 | { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
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| 252 | { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST},
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| 253 | { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
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| 254 | { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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| 255 | { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
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| 256 | { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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| 257 | { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},
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| 258 | { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST },
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| 259 | { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
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| 260 | { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
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| 261 | { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST},
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| 262 | { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
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| 263 | { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
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| 264 | { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
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| 265 | { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
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| 266 | { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST},
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| 267 | { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST},
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| 268 | { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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| 269 | B_BRANCH|FL_NR, REST},
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| 270 | { "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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| 271 | B_BRANCH|FL_DELAY|FL_NR, REST},
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| 272 | { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST},
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| 273 | { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
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| 274 | { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST},
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| 275 | { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
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| 276 | { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
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| 277 | { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
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| 278 | { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
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| 279 | { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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| 280 | B_BRANCH|FL_NR, REST},
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| 281 | { "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
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| 282 | B_BRANCH|FL_DELAY|FL_NR, REST},
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|---|
| 283 | { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 284 | { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
|
|---|
| 285 | { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST},
|
|---|
| 286 | { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
|
|---|
| 287 | { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 288 | { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
|
|---|
| 289 | { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
|---|
| 290 | { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
|
|---|
| 291 | { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
|
|---|
| 292 | { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
|
|---|
| 293 | { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST},
|
|---|
| 294 | { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
|
|---|
| 295 | { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
|
|---|
| 296 | { "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */
|
|---|
| 297 | { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST},
|
|---|
| 298 | { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
|
|---|
| 299 | { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
|
|---|
| 300 | { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
|
|---|
| 301 | { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
|
|---|
| 302 | { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST},
|
|---|
| 303 | { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST},
|
|---|
| 304 | { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
|
|---|
| 305 | { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
|
|---|
| 306 | { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
|
|---|
| 307 | { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
|
|---|
| 308 | { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST},
|
|---|
| 309 | { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
|
|---|
| 310 | { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
|
|---|
| 311 | { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/
|
|---|
| 312 | /* alternate syntax */
|
|---|
| 313 | { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
|---|
| 314 | { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/
|
|---|
| 315 | { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/
|
|---|
| 316 | { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/
|
|---|
| 317 | { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */
|
|---|
| 318 | { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/
|
|---|
| 319 | { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/
|
|---|
| 320 | { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/
|
|---|
| 321 | { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
|---|
| 322 | { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST},
|
|---|
| 323 | { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST},
|
|---|
| 324 | { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/
|
|---|
| 325 | { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST},
|
|---|
| 326 | FL_EXT|FL_SMR, 0x0C40, 0xFEE0, XREST},
|
|---|
| 327 | { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST},
|
|---|
| 328 | { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST},
|
|---|
| 329 | { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST},
|
|---|
| 330 | { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
|---|
| 331 | { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
|---|
| 332 | { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/
|
|---|
| 333 | { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
|---|
| 334 | { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
|---|
| 335 | { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
|---|
| 336 | { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 337 | { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 338 | { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
|
|---|
| 339 | { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
|---|
| 340 | { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST},
|
|---|
| 341 | { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
|
|---|
| 342 | { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
|---|
| 343 | { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
|
|---|
| 344 | { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
|---|
| 345 | { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
|
|---|
| 346 | { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
|
|---|
| 347 | { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST},
|
|---|
| 348 | { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST},
|
|---|
| 349 | { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
|---|
| 350 | { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 351 | { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
|---|
| 352 | { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 353 | { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/
|
|---|
| 354 | { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
|
|---|
| 355 | { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 356 | { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST},
|
|---|
| 357 | { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST},
|
|---|
| 358 | { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
|---|
| 359 | { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
|
|---|
| 360 | { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST},
|
|---|
| 361 | { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST},
|
|---|
| 362 | { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
|---|
| 363 | { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/
|
|---|
| 364 | { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
|---|
| 365 | { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
|---|
| 366 | { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
|---|
| 367 | { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST},
|
|---|
| 368 | { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST},
|
|---|
| 369 | { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST},
|
|---|
| 370 | { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST},
|
|---|
| 371 | { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST},
|
|---|
| 372 | { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST},
|
|---|
| 373 | { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST},
|
|---|
| 374 | { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 375 | { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST},
|
|---|
| 376 | { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 377 | { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
|---|
| 378 | { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
|---|
| 379 | { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 380 | { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
|
|---|
| 381 | { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
|
|---|
| 382 | { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
|---|
| 383 | { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST},
|
|---|
| 384 | { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST},
|
|---|
| 385 | { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST},
|
|---|
| 386 | { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST},
|
|---|
| 387 | { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST},
|
|---|
| 388 | { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST},
|
|---|
| 389 | { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
|---|
| 390 | { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
|---|
| 391 | { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
|
|---|
| 392 | B_RET|FL_NR, REST},
|
|---|
| 393 | { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
|
|---|
| 394 | B_RET|FL_DELAY|FL_NR, REST},
|
|---|
| 395 | { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST},
|
|---|
| 396 | { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST},
|
|---|
| 397 | { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
|---|
| 398 | { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
|---|
| 399 | { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
|
|---|
| 400 | { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
|
|---|
| 401 | { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST},
|
|---|
| 402 | { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST},
|
|---|
| 403 | { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST},
|
|---|
| 404 | { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST},
|
|---|
| 405 | { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST},
|
|---|
| 406 | { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST},
|
|---|
| 407 | { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST},
|
|---|
| 408 | { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST},
|
|---|
| 409 | { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST},
|
|---|
| 410 | { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST},
|
|---|
| 411 | { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
|
|---|
| 412 | { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST},
|
|---|
| 413 | { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST},
|
|---|
| 414 | { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
|
|---|
| 415 | { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST},
|
|---|
| 416 | { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
|
|---|
| 417 | { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
|
|---|
| 418 | { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/
|
|---|
| 419 | { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
|
|---|
| 420 | { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
|---|
| 421 | { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
|---|
| 422 | { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
|
|---|
| 423 | { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
|
|---|
| 424 | { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST},
|
|---|
| 425 | { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST},
|
|---|
| 426 | { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST},
|
|---|
| 427 | { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
|
|---|
| 428 | { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
|
|---|
| 429 | { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
|
|---|
| 430 | { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
|
|---|
| 431 | FL_EXT, 0x0C60, 0xFEE0, XREST},
|
|---|
| 432 | { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
|
|---|
| 433 | { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
|
|---|
| 434 | { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
|
|---|
| 435 | { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
|
|---|
| 436 | FL_EXT, 0x0C80, 0xFEE0, XREST },
|
|---|
| 437 | { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST},
|
|---|
| 438 | { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST},
|
|---|
| 439 | { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
|
|---|
| 440 | { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
|
|---|
| 441 | { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
|
|---|
| 442 | { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
|
|---|
| 443 | { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
|
|---|
| 444 | { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
|
|---|
| 445 | { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/
|
|---|
| 446 | { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
|
|---|
| 447 | FL_EXT|FL_SMR, 0x0C20, 0xFCE0, XREST},
|
|---|
| 448 | { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
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| 449 | { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
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| 450 | { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
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| 451 | { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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| 452 | { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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| 453 | { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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| 454 | { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
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| 455 | { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST},
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| 456 | { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST},
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| 457 | { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
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| 458 | { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
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| 459 | { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
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|---|
| 460 | { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
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| 461 | { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST},
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| 462 | { NULL, 0,0,0,0,0, {}, 0, REST},
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| 463 | };
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| 464 |
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| 465 | /* assume all parallel instructions have at least three operands */
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| 466 | const template tic54x_paroptab[] = {
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| 467 | { "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
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| 468 | "mac", {OP_Ymem,OPT|OP_RND},},
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| 469 | { "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
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|---|
| 470 | "macr", {OP_Ymem,OPT|OP_RND},},
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| 471 | { "ld",1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
|
|---|
| 472 | "mas", {OP_Ymem,OPT|OP_RND},},
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|---|
| 473 | { "ld",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST}, FL_PAR,0,0,
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|---|
| 474 | "masr", {OP_Ymem,OPT|OP_RND},},
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|---|
| 475 | { "st",1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
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|---|
| 476 | "add", {OP_Xmem,OP_DST}, },
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|---|
| 477 | { "st",1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
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|---|
| 478 | "ld", {OP_Xmem,OP_DST}, },
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|---|
| 479 | { "st",1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
|---|
| 480 | "ld", {OP_Xmem,OP_T}, },
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|---|
| 481 | { "st",1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
|---|
| 482 | "mac", {OP_Xmem,OP_DST}, },
|
|---|
| 483 | { "st",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
|---|
| 484 | "macr", {OP_Xmem,OP_DST}, },
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|---|
| 485 | { "st",1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
|---|
| 486 | "mas", {OP_Xmem,OP_DST}, },
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|---|
| 487 | { "st",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
|---|
| 488 | "masr", {OP_Xmem,OP_DST}, },
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|---|
| 489 | { "st",1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
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|---|
| 490 | "mpy", {OP_Xmem,OP_DST}, },
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|---|
| 491 | { "st",1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem}, FL_PAR,0,0,
|
|---|
| 492 | "sub", {OP_Xmem,OP_DST}, },
|
|---|
| 493 | { NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST },
|
|---|
| 494 | };
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