source: vendor/binutils/current/opcodes/m32r-opc.c

Last change on this file was 609, checked in by bird, 22 years ago

binutils v2.14 - offical sources.
  • Property cvs2svn:cvs-rev set to 1.1.1.2
  • Property svn:eol-style set to native
  • Property svn:executable set to *
File size: 42.3 KB
Line 
1/* Instruction opcode table for m32r.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include "ansidecl.h"
27#include "bfd.h"
28#include "symcat.h"
29#include "m32r-desc.h"
30#include "m32r-opc.h"
31#include "libiberty.h"
32
33/* The hash functions are recorded here to help keep assembler code out of
34 the disassembler and vice versa. */
35
36static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
37static unsigned int asm_hash_insn PARAMS ((const char *));
38static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
39static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
40
41/* Instruction formats. */
42
43#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
44#define F(f) & m32r_cgen_ifld_table[M32R_##f]
45#else
46#define F(f) & m32r_cgen_ifld_table[M32R_/**/f]
47#endif
48static const CGEN_IFMT ifmt_empty = {
49 0, 0, 0x0, { { 0 } }
50};
51
52static const CGEN_IFMT ifmt_add = {
53 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
54};
55
56static const CGEN_IFMT ifmt_add3 = {
57 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
58};
59
60static const CGEN_IFMT ifmt_and3 = {
61 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
62};
63
64static const CGEN_IFMT ifmt_or3 = {
65 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
66};
67
68static const CGEN_IFMT ifmt_addi = {
69 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
70};
71
72static const CGEN_IFMT ifmt_addv3 = {
73 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
74};
75
76static const CGEN_IFMT ifmt_bc8 = {
77 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
78};
79
80static const CGEN_IFMT ifmt_bc24 = {
81 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
82};
83
84static const CGEN_IFMT ifmt_beq = {
85 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
86};
87
88static const CGEN_IFMT ifmt_beqz = {
89 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
90};
91
92static const CGEN_IFMT ifmt_cmp = {
93 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
94};
95
96static const CGEN_IFMT ifmt_cmpi = {
97 32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
98};
99
100static const CGEN_IFMT ifmt_cmpz = {
101 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
102};
103
104static const CGEN_IFMT ifmt_div = {
105 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
106};
107
108static const CGEN_IFMT ifmt_jc = {
109 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
110};
111
112static const CGEN_IFMT ifmt_ld24 = {
113 32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } }
114};
115
116static const CGEN_IFMT ifmt_ldi16 = {
117 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
118};
119
120static const CGEN_IFMT ifmt_machi_a = {
121 16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } }
122};
123
124static const CGEN_IFMT ifmt_mvfachi = {
125 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
126};
127
128static const CGEN_IFMT ifmt_mvfachi_a = {
129 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
130};
131
132static const CGEN_IFMT ifmt_mvfc = {
133 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
134};
135
136static const CGEN_IFMT ifmt_mvtachi = {
137 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
138};
139
140static const CGEN_IFMT ifmt_mvtachi_a = {
141 16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
142};
143
144static const CGEN_IFMT ifmt_mvtc = {
145 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
146};
147
148static const CGEN_IFMT ifmt_nop = {
149 16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
150};
151
152static const CGEN_IFMT ifmt_rac_dsi = {
153 16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
154};
155
156static const CGEN_IFMT ifmt_seth = {
157 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } }
158};
159
160static const CGEN_IFMT ifmt_slli = {
161 16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } }
162};
163
164static const CGEN_IFMT ifmt_st_d = {
165 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
166};
167
168static const CGEN_IFMT ifmt_trap = {
169 16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } }
170};
171
172static const CGEN_IFMT ifmt_satb = {
173 32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
174};
175
176#undef F
177
178#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
179#define A(a) (1 << CGEN_INSN_##a)
180#else
181#define A(a) (1 << CGEN_INSN_/**/a)
182#endif
183#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
184#define OPERAND(op) M32R_OPERAND_##op
185#else
186#define OPERAND(op) M32R_OPERAND_/**/op
187#endif
188#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
189#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
190
191/* The instruction table. */
192
193static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
194{
195 /* Special null first entry.
196 A `num' value of zero is thus invalid.
197 Also, the special `invalid' insn resides here. */
198 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
199/* add $dr,$sr */
200 {
201 { 0, 0, 0, 0 },
202 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
203 & ifmt_add, { 0xa0 }
204 },
205/* add3 $dr,$sr,$hash$slo16 */
206 {
207 { 0, 0, 0, 0 },
208 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
209 & ifmt_add3, { 0x80a00000 }
210 },
211/* and $dr,$sr */
212 {
213 { 0, 0, 0, 0 },
214 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
215 & ifmt_add, { 0xc0 }
216 },
217/* and3 $dr,$sr,$uimm16 */
218 {
219 { 0, 0, 0, 0 },
220 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
221 & ifmt_and3, { 0x80c00000 }
222 },
223/* or $dr,$sr */
224 {
225 { 0, 0, 0, 0 },
226 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
227 & ifmt_add, { 0xe0 }
228 },
229/* or3 $dr,$sr,$hash$ulo16 */
230 {
231 { 0, 0, 0, 0 },
232 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
233 & ifmt_or3, { 0x80e00000 }
234 },
235/* xor $dr,$sr */
236 {
237 { 0, 0, 0, 0 },
238 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
239 & ifmt_add, { 0xd0 }
240 },
241/* xor3 $dr,$sr,$uimm16 */
242 {
243 { 0, 0, 0, 0 },
244 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
245 & ifmt_and3, { 0x80d00000 }
246 },
247/* addi $dr,$simm8 */
248 {
249 { 0, 0, 0, 0 },
250 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
251 & ifmt_addi, { 0x4000 }
252 },
253/* addv $dr,$sr */
254 {
255 { 0, 0, 0, 0 },
256 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
257 & ifmt_add, { 0x80 }
258 },
259/* addv3 $dr,$sr,$simm16 */
260 {
261 { 0, 0, 0, 0 },
262 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
263 & ifmt_addv3, { 0x80800000 }
264 },
265/* addx $dr,$sr */
266 {
267 { 0, 0, 0, 0 },
268 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
269 & ifmt_add, { 0x90 }
270 },
271/* bc.s $disp8 */
272 {
273 { 0, 0, 0, 0 },
274 { { MNEM, ' ', OP (DISP8), 0 } },
275 & ifmt_bc8, { 0x7c00 }
276 },
277/* bc.l $disp24 */
278 {
279 { 0, 0, 0, 0 },
280 { { MNEM, ' ', OP (DISP24), 0 } },
281 & ifmt_bc24, { 0xfc000000 }
282 },
283/* beq $src1,$src2,$disp16 */
284 {
285 { 0, 0, 0, 0 },
286 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
287 & ifmt_beq, { 0xb0000000 }
288 },
289/* beqz $src2,$disp16 */
290 {
291 { 0, 0, 0, 0 },
292 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
293 & ifmt_beqz, { 0xb0800000 }
294 },
295/* bgez $src2,$disp16 */
296 {
297 { 0, 0, 0, 0 },
298 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
299 & ifmt_beqz, { 0xb0b00000 }
300 },
301/* bgtz $src2,$disp16 */
302 {
303 { 0, 0, 0, 0 },
304 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
305 & ifmt_beqz, { 0xb0d00000 }
306 },
307/* blez $src2,$disp16 */
308 {
309 { 0, 0, 0, 0 },
310 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
311 & ifmt_beqz, { 0xb0c00000 }
312 },
313/* bltz $src2,$disp16 */
314 {
315 { 0, 0, 0, 0 },
316 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
317 & ifmt_beqz, { 0xb0a00000 }
318 },
319/* bnez $src2,$disp16 */
320 {
321 { 0, 0, 0, 0 },
322 { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
323 & ifmt_beqz, { 0xb0900000 }
324 },
325/* bl.s $disp8 */
326 {
327 { 0, 0, 0, 0 },
328 { { MNEM, ' ', OP (DISP8), 0 } },
329 & ifmt_bc8, { 0x7e00 }
330 },
331/* bl.l $disp24 */
332 {
333 { 0, 0, 0, 0 },
334 { { MNEM, ' ', OP (DISP24), 0 } },
335 & ifmt_bc24, { 0xfe000000 }
336 },
337/* bcl.s $disp8 */
338 {
339 { 0, 0, 0, 0 },
340 { { MNEM, ' ', OP (DISP8), 0 } },
341 & ifmt_bc8, { 0x7800 }
342 },
343/* bcl.l $disp24 */
344 {
345 { 0, 0, 0, 0 },
346 { { MNEM, ' ', OP (DISP24), 0 } },
347 & ifmt_bc24, { 0xf8000000 }
348 },
349/* bnc.s $disp8 */
350 {
351 { 0, 0, 0, 0 },
352 { { MNEM, ' ', OP (DISP8), 0 } },
353 & ifmt_bc8, { 0x7d00 }
354 },
355/* bnc.l $disp24 */
356 {
357 { 0, 0, 0, 0 },
358 { { MNEM, ' ', OP (DISP24), 0 } },
359 & ifmt_bc24, { 0xfd000000 }
360 },
361/* bne $src1,$src2,$disp16 */
362 {
363 { 0, 0, 0, 0 },
364 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
365 & ifmt_beq, { 0xb0100000 }
366 },
367/* bra.s $disp8 */
368 {
369 { 0, 0, 0, 0 },
370 { { MNEM, ' ', OP (DISP8), 0 } },
371 & ifmt_bc8, { 0x7f00 }
372 },
373/* bra.l $disp24 */
374 {
375 { 0, 0, 0, 0 },
376 { { MNEM, ' ', OP (DISP24), 0 } },
377 & ifmt_bc24, { 0xff000000 }
378 },
379/* bncl.s $disp8 */
380 {
381 { 0, 0, 0, 0 },
382 { { MNEM, ' ', OP (DISP8), 0 } },
383 & ifmt_bc8, { 0x7900 }
384 },
385/* bncl.l $disp24 */
386 {
387 { 0, 0, 0, 0 },
388 { { MNEM, ' ', OP (DISP24), 0 } },
389 & ifmt_bc24, { 0xf9000000 }
390 },
391/* cmp $src1,$src2 */
392 {
393 { 0, 0, 0, 0 },
394 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
395 & ifmt_cmp, { 0x40 }
396 },
397/* cmpi $src2,$simm16 */
398 {
399 { 0, 0, 0, 0 },
400 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
401 & ifmt_cmpi, { 0x80400000 }
402 },
403/* cmpu $src1,$src2 */
404 {
405 { 0, 0, 0, 0 },
406 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
407 & ifmt_cmp, { 0x50 }
408 },
409/* cmpui $src2,$simm16 */
410 {
411 { 0, 0, 0, 0 },
412 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
413 & ifmt_cmpi, { 0x80500000 }
414 },
415/* cmpeq $src1,$src2 */
416 {
417 { 0, 0, 0, 0 },
418 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
419 & ifmt_cmp, { 0x60 }
420 },
421/* cmpz $src2 */
422 {
423 { 0, 0, 0, 0 },
424 { { MNEM, ' ', OP (SRC2), 0 } },
425 & ifmt_cmpz, { 0x70 }
426 },
427/* div $dr,$sr */
428 {
429 { 0, 0, 0, 0 },
430 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
431 & ifmt_div, { 0x90000000 }
432 },
433/* divu $dr,$sr */
434 {
435 { 0, 0, 0, 0 },
436 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
437 & ifmt_div, { 0x90100000 }
438 },
439/* rem $dr,$sr */
440 {
441 { 0, 0, 0, 0 },
442 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
443 & ifmt_div, { 0x90200000 }
444 },
445/* remu $dr,$sr */
446 {
447 { 0, 0, 0, 0 },
448 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
449 & ifmt_div, { 0x90300000 }
450 },
451/* divh $dr,$sr */
452 {
453 { 0, 0, 0, 0 },
454 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
455 & ifmt_div, { 0x90000010 }
456 },
457/* jc $sr */
458 {
459 { 0, 0, 0, 0 },
460 { { MNEM, ' ', OP (SR), 0 } },
461 & ifmt_jc, { 0x1cc0 }
462 },
463/* jnc $sr */
464 {
465 { 0, 0, 0, 0 },
466 { { MNEM, ' ', OP (SR), 0 } },
467 & ifmt_jc, { 0x1dc0 }
468 },
469/* jl $sr */
470 {
471 { 0, 0, 0, 0 },
472 { { MNEM, ' ', OP (SR), 0 } },
473 & ifmt_jc, { 0x1ec0 }
474 },
475/* jmp $sr */
476 {
477 { 0, 0, 0, 0 },
478 { { MNEM, ' ', OP (SR), 0 } },
479 & ifmt_jc, { 0x1fc0 }
480 },
481/* ld $dr,@$sr */
482 {
483 { 0, 0, 0, 0 },
484 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
485 & ifmt_add, { 0x20c0 }
486 },
487/* ld $dr,@($slo16,$sr) */
488 {
489 { 0, 0, 0, 0 },
490 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
491 & ifmt_add3, { 0xa0c00000 }
492 },
493/* ldb $dr,@$sr */
494 {
495 { 0, 0, 0, 0 },
496 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
497 & ifmt_add, { 0x2080 }
498 },
499/* ldb $dr,@($slo16,$sr) */
500 {
501 { 0, 0, 0, 0 },
502 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
503 & ifmt_add3, { 0xa0800000 }
504 },
505/* ldh $dr,@$sr */
506 {
507 { 0, 0, 0, 0 },
508 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
509 & ifmt_add, { 0x20a0 }
510 },
511/* ldh $dr,@($slo16,$sr) */
512 {
513 { 0, 0, 0, 0 },
514 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
515 & ifmt_add3, { 0xa0a00000 }
516 },
517/* ldub $dr,@$sr */
518 {
519 { 0, 0, 0, 0 },
520 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
521 & ifmt_add, { 0x2090 }
522 },
523/* ldub $dr,@($slo16,$sr) */
524 {
525 { 0, 0, 0, 0 },
526 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
527 & ifmt_add3, { 0xa0900000 }
528 },
529/* lduh $dr,@$sr */
530 {
531 { 0, 0, 0, 0 },
532 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
533 & ifmt_add, { 0x20b0 }
534 },
535/* lduh $dr,@($slo16,$sr) */
536 {
537 { 0, 0, 0, 0 },
538 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
539 & ifmt_add3, { 0xa0b00000 }
540 },
541/* ld $dr,@$sr+ */
542 {
543 { 0, 0, 0, 0 },
544 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
545 & ifmt_add, { 0x20e0 }
546 },
547/* ld24 $dr,$uimm24 */
548 {
549 { 0, 0, 0, 0 },
550 { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
551 & ifmt_ld24, { 0xe0000000 }
552 },
553/* ldi8 $dr,$simm8 */
554 {
555 { 0, 0, 0, 0 },
556 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
557 & ifmt_addi, { 0x6000 }
558 },
559/* ldi16 $dr,$hash$slo16 */
560 {
561 { 0, 0, 0, 0 },
562 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
563 & ifmt_ldi16, { 0x90f00000 }
564 },
565/* lock $dr,@$sr */
566 {
567 { 0, 0, 0, 0 },
568 { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
569 & ifmt_add, { 0x20d0 }
570 },
571/* machi $src1,$src2 */
572 {
573 { 0, 0, 0, 0 },
574 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
575 & ifmt_cmp, { 0x3040 }
576 },
577/* machi $src1,$src2,$acc */
578 {
579 { 0, 0, 0, 0 },
580 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
581 & ifmt_machi_a, { 0x3040 }
582 },
583/* maclo $src1,$src2 */
584 {
585 { 0, 0, 0, 0 },
586 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
587 & ifmt_cmp, { 0x3050 }
588 },
589/* maclo $src1,$src2,$acc */
590 {
591 { 0, 0, 0, 0 },
592 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
593 & ifmt_machi_a, { 0x3050 }
594 },
595/* macwhi $src1,$src2 */
596 {
597 { 0, 0, 0, 0 },
598 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
599 & ifmt_cmp, { 0x3060 }
600 },
601/* macwhi $src1,$src2,$acc */
602 {
603 { 0, 0, 0, 0 },
604 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
605 & ifmt_machi_a, { 0x3060 }
606 },
607/* macwlo $src1,$src2 */
608 {
609 { 0, 0, 0, 0 },
610 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
611 & ifmt_cmp, { 0x3070 }
612 },
613/* macwlo $src1,$src2,$acc */
614 {
615 { 0, 0, 0, 0 },
616 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
617 & ifmt_machi_a, { 0x3070 }
618 },
619/* mul $dr,$sr */
620 {
621 { 0, 0, 0, 0 },
622 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
623 & ifmt_add, { 0x1060 }
624 },
625/* mulhi $src1,$src2 */
626 {
627 { 0, 0, 0, 0 },
628 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
629 & ifmt_cmp, { 0x3000 }
630 },
631/* mulhi $src1,$src2,$acc */
632 {
633 { 0, 0, 0, 0 },
634 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
635 & ifmt_machi_a, { 0x3000 }
636 },
637/* mullo $src1,$src2 */
638 {
639 { 0, 0, 0, 0 },
640 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
641 & ifmt_cmp, { 0x3010 }
642 },
643/* mullo $src1,$src2,$acc */
644 {
645 { 0, 0, 0, 0 },
646 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
647 & ifmt_machi_a, { 0x3010 }
648 },
649/* mulwhi $src1,$src2 */
650 {
651 { 0, 0, 0, 0 },
652 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
653 & ifmt_cmp, { 0x3020 }
654 },
655/* mulwhi $src1,$src2,$acc */
656 {
657 { 0, 0, 0, 0 },
658 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
659 & ifmt_machi_a, { 0x3020 }
660 },
661/* mulwlo $src1,$src2 */
662 {
663 { 0, 0, 0, 0 },
664 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
665 & ifmt_cmp, { 0x3030 }
666 },
667/* mulwlo $src1,$src2,$acc */
668 {
669 { 0, 0, 0, 0 },
670 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
671 & ifmt_machi_a, { 0x3030 }
672 },
673/* mv $dr,$sr */
674 {
675 { 0, 0, 0, 0 },
676 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
677 & ifmt_add, { 0x1080 }
678 },
679/* mvfachi $dr */
680 {
681 { 0, 0, 0, 0 },
682 { { MNEM, ' ', OP (DR), 0 } },
683 & ifmt_mvfachi, { 0x50f0 }
684 },
685/* mvfachi $dr,$accs */
686 {
687 { 0, 0, 0, 0 },
688 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
689 & ifmt_mvfachi_a, { 0x50f0 }
690 },
691/* mvfaclo $dr */
692 {
693 { 0, 0, 0, 0 },
694 { { MNEM, ' ', OP (DR), 0 } },
695 & ifmt_mvfachi, { 0x50f1 }
696 },
697/* mvfaclo $dr,$accs */
698 {
699 { 0, 0, 0, 0 },
700 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
701 & ifmt_mvfachi_a, { 0x50f1 }
702 },
703/* mvfacmi $dr */
704 {
705 { 0, 0, 0, 0 },
706 { { MNEM, ' ', OP (DR), 0 } },
707 & ifmt_mvfachi, { 0x50f2 }
708 },
709/* mvfacmi $dr,$accs */
710 {
711 { 0, 0, 0, 0 },
712 { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
713 & ifmt_mvfachi_a, { 0x50f2 }
714 },
715/* mvfc $dr,$scr */
716 {
717 { 0, 0, 0, 0 },
718 { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
719 & ifmt_mvfc, { 0x1090 }
720 },
721/* mvtachi $src1 */
722 {
723 { 0, 0, 0, 0 },
724 { { MNEM, ' ', OP (SRC1), 0 } },
725 & ifmt_mvtachi, { 0x5070 }
726 },
727/* mvtachi $src1,$accs */
728 {
729 { 0, 0, 0, 0 },
730 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
731 & ifmt_mvtachi_a, { 0x5070 }
732 },
733/* mvtaclo $src1 */
734 {
735 { 0, 0, 0, 0 },
736 { { MNEM, ' ', OP (SRC1), 0 } },
737 & ifmt_mvtachi, { 0x5071 }
738 },
739/* mvtaclo $src1,$accs */
740 {
741 { 0, 0, 0, 0 },
742 { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
743 & ifmt_mvtachi_a, { 0x5071 }
744 },
745/* mvtc $sr,$dcr */
746 {
747 { 0, 0, 0, 0 },
748 { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
749 & ifmt_mvtc, { 0x10a0 }
750 },
751/* neg $dr,$sr */
752 {
753 { 0, 0, 0, 0 },
754 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
755 & ifmt_add, { 0x30 }
756 },
757/* nop */
758 {
759 { 0, 0, 0, 0 },
760 { { MNEM, 0 } },
761 & ifmt_nop, { 0x7000 }
762 },
763/* not $dr,$sr */
764 {
765 { 0, 0, 0, 0 },
766 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
767 & ifmt_add, { 0xb0 }
768 },
769/* rac */
770 {
771 { 0, 0, 0, 0 },
772 { { MNEM, 0 } },
773 & ifmt_nop, { 0x5090 }
774 },
775/* rac $accd,$accs,$imm1 */
776 {
777 { 0, 0, 0, 0 },
778 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
779 & ifmt_rac_dsi, { 0x5090 }
780 },
781/* rach */
782 {
783 { 0, 0, 0, 0 },
784 { { MNEM, 0 } },
785 & ifmt_nop, { 0x5080 }
786 },
787/* rach $accd,$accs,$imm1 */
788 {
789 { 0, 0, 0, 0 },
790 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
791 & ifmt_rac_dsi, { 0x5080 }
792 },
793/* rte */
794 {
795 { 0, 0, 0, 0 },
796 { { MNEM, 0 } },
797 & ifmt_nop, { 0x10d6 }
798 },
799/* seth $dr,$hash$hi16 */
800 {
801 { 0, 0, 0, 0 },
802 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
803 & ifmt_seth, { 0xd0c00000 }
804 },
805/* sll $dr,$sr */
806 {
807 { 0, 0, 0, 0 },
808 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
809 & ifmt_add, { 0x1040 }
810 },
811/* sll3 $dr,$sr,$simm16 */
812 {
813 { 0, 0, 0, 0 },
814 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
815 & ifmt_addv3, { 0x90c00000 }
816 },
817/* slli $dr,$uimm5 */
818 {
819 { 0, 0, 0, 0 },
820 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
821 & ifmt_slli, { 0x5040 }
822 },
823/* sra $dr,$sr */
824 {
825 { 0, 0, 0, 0 },
826 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
827 & ifmt_add, { 0x1020 }
828 },
829/* sra3 $dr,$sr,$simm16 */
830 {
831 { 0, 0, 0, 0 },
832 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
833 & ifmt_addv3, { 0x90a00000 }
834 },
835/* srai $dr,$uimm5 */
836 {
837 { 0, 0, 0, 0 },
838 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
839 & ifmt_slli, { 0x5020 }
840 },
841/* srl $dr,$sr */
842 {
843 { 0, 0, 0, 0 },
844 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
845 & ifmt_add, { 0x1000 }
846 },
847/* srl3 $dr,$sr,$simm16 */
848 {
849 { 0, 0, 0, 0 },
850 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
851 & ifmt_addv3, { 0x90800000 }
852 },
853/* srli $dr,$uimm5 */
854 {
855 { 0, 0, 0, 0 },
856 { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
857 & ifmt_slli, { 0x5000 }
858 },
859/* st $src1,@$src2 */
860 {
861 { 0, 0, 0, 0 },
862 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
863 & ifmt_cmp, { 0x2040 }
864 },
865/* st $src1,@($slo16,$src2) */
866 {
867 { 0, 0, 0, 0 },
868 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
869 & ifmt_st_d, { 0xa0400000 }
870 },
871/* stb $src1,@$src2 */
872 {
873 { 0, 0, 0, 0 },
874 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
875 & ifmt_cmp, { 0x2000 }
876 },
877/* stb $src1,@($slo16,$src2) */
878 {
879 { 0, 0, 0, 0 },
880 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
881 & ifmt_st_d, { 0xa0000000 }
882 },
883/* sth $src1,@$src2 */
884 {
885 { 0, 0, 0, 0 },
886 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
887 & ifmt_cmp, { 0x2020 }
888 },
889/* sth $src1,@($slo16,$src2) */
890 {
891 { 0, 0, 0, 0 },
892 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
893 & ifmt_st_d, { 0xa0200000 }
894 },
895/* st $src1,@+$src2 */
896 {
897 { 0, 0, 0, 0 },
898 { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
899 & ifmt_cmp, { 0x2060 }
900 },
901/* st $src1,@-$src2 */
902 {
903 { 0, 0, 0, 0 },
904 { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
905 & ifmt_cmp, { 0x2070 }
906 },
907/* sub $dr,$sr */
908 {
909 { 0, 0, 0, 0 },
910 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
911 & ifmt_add, { 0x20 }
912 },
913/* subv $dr,$sr */
914 {
915 { 0, 0, 0, 0 },
916 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
917 & ifmt_add, { 0x0 }
918 },
919/* subx $dr,$sr */
920 {
921 { 0, 0, 0, 0 },
922 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
923 & ifmt_add, { 0x10 }
924 },
925/* trap $uimm4 */
926 {
927 { 0, 0, 0, 0 },
928 { { MNEM, ' ', OP (UIMM4), 0 } },
929 & ifmt_trap, { 0x10f0 }
930 },
931/* unlock $src1,@$src2 */
932 {
933 { 0, 0, 0, 0 },
934 { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
935 & ifmt_cmp, { 0x2050 }
936 },
937/* satb $dr,$sr */
938 {
939 { 0, 0, 0, 0 },
940 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
941 & ifmt_satb, { 0x80600300 }
942 },
943/* sath $dr,$sr */
944 {
945 { 0, 0, 0, 0 },
946 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
947 & ifmt_satb, { 0x80600200 }
948 },
949/* sat $dr,$sr */
950 {
951 { 0, 0, 0, 0 },
952 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
953 & ifmt_satb, { 0x80600000 }
954 },
955/* pcmpbz $src2 */
956 {
957 { 0, 0, 0, 0 },
958 { { MNEM, ' ', OP (SRC2), 0 } },
959 & ifmt_cmpz, { 0x370 }
960 },
961/* sadd */
962 {
963 { 0, 0, 0, 0 },
964 { { MNEM, 0 } },
965 & ifmt_nop, { 0x50e4 }
966 },
967/* macwu1 $src1,$src2 */
968 {
969 { 0, 0, 0, 0 },
970 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
971 & ifmt_cmp, { 0x50b0 }
972 },
973/* msblo $src1,$src2 */
974 {
975 { 0, 0, 0, 0 },
976 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
977 & ifmt_cmp, { 0x50d0 }
978 },
979/* mulwu1 $src1,$src2 */
980 {
981 { 0, 0, 0, 0 },
982 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
983 & ifmt_cmp, { 0x50a0 }
984 },
985/* maclh1 $src1,$src2 */
986 {
987 { 0, 0, 0, 0 },
988 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
989 & ifmt_cmp, { 0x50c0 }
990 },
991/* sc */
992 {
993 { 0, 0, 0, 0 },
994 { { MNEM, 0 } },
995 & ifmt_nop, { 0x7401 }
996 },
997/* snc */
998 {
999 { 0, 0, 0, 0 },
1000 { { MNEM, 0 } },
1001 & ifmt_nop, { 0x7501 }
1002 },
1003};
1004
1005#undef A
1006#undef OPERAND
1007#undef MNEM
1008#undef OP
1009
1010/* Formats for ALIAS macro-insns. */
1011
1012#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1013#define F(f) & m32r_cgen_ifld_table[M32R_##f]
1014#else
1015#define F(f) & m32r_cgen_ifld_table[M32R_/**/f]
1016#endif
1017static const CGEN_IFMT ifmt_bc8r = {
1018 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1019};
1020
1021static const CGEN_IFMT ifmt_bc24r = {
1022 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1023};
1024
1025static const CGEN_IFMT ifmt_bl8r = {
1026 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1027};
1028
1029static const CGEN_IFMT ifmt_bl24r = {
1030 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1031};
1032
1033static const CGEN_IFMT ifmt_bcl8r = {
1034 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1035};
1036
1037static const CGEN_IFMT ifmt_bcl24r = {
1038 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1039};
1040
1041static const CGEN_IFMT ifmt_bnc8r = {
1042 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1043};
1044
1045static const CGEN_IFMT ifmt_bnc24r = {
1046 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1047};
1048
1049static const CGEN_IFMT ifmt_bra8r = {
1050 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1051};
1052
1053static const CGEN_IFMT ifmt_bra24r = {
1054 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1055};
1056
1057static const CGEN_IFMT ifmt_bncl8r = {
1058 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
1059};
1060
1061static const CGEN_IFMT ifmt_bncl24r = {
1062 32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
1063};
1064
1065static const CGEN_IFMT ifmt_ld_2 = {
1066 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1067};
1068
1069static const CGEN_IFMT ifmt_ld_d2 = {
1070 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1071};
1072
1073static const CGEN_IFMT ifmt_ldb_2 = {
1074 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1075};
1076
1077static const CGEN_IFMT ifmt_ldb_d2 = {
1078 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1079};
1080
1081static const CGEN_IFMT ifmt_ldh_2 = {
1082 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1083};
1084
1085static const CGEN_IFMT ifmt_ldh_d2 = {
1086 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1087};
1088
1089static const CGEN_IFMT ifmt_ldub_2 = {
1090 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1091};
1092
1093static const CGEN_IFMT ifmt_ldub_d2 = {
1094 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1095};
1096
1097static const CGEN_IFMT ifmt_lduh_2 = {
1098 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1099};
1100
1101static const CGEN_IFMT ifmt_lduh_d2 = {
1102 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1103};
1104
1105static const CGEN_IFMT ifmt_pop = {
1106 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
1107};
1108
1109static const CGEN_IFMT ifmt_ldi8a = {
1110 16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
1111};
1112
1113static const CGEN_IFMT ifmt_ldi16a = {
1114 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
1115};
1116
1117static const CGEN_IFMT ifmt_rac_d = {
1118 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1119};
1120
1121static const CGEN_IFMT ifmt_rac_ds = {
1122 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1123};
1124
1125static const CGEN_IFMT ifmt_rach_d = {
1126 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1127};
1128
1129static const CGEN_IFMT ifmt_rach_ds = {
1130 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
1131};
1132
1133static const CGEN_IFMT ifmt_st_2 = {
1134 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1135};
1136
1137static const CGEN_IFMT ifmt_st_d2 = {
1138 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1139};
1140
1141static const CGEN_IFMT ifmt_stb_2 = {
1142 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1143};
1144
1145static const CGEN_IFMT ifmt_stb_d2 = {
1146 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1147};
1148
1149static const CGEN_IFMT ifmt_sth_2 = {
1150 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1151};
1152
1153static const CGEN_IFMT ifmt_sth_d2 = {
1154 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
1155};
1156
1157static const CGEN_IFMT ifmt_push = {
1158 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
1159};
1160
1161#undef F
1162
1163/* Each non-simple macro entry points to an array of expansion possibilities. */
1164
1165#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1166#define A(a) (1 << CGEN_INSN_##a)
1167#else
1168#define A(a) (1 << CGEN_INSN_/**/a)
1169#endif
1170#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1171#define OPERAND(op) M32R_OPERAND_##op
1172#else
1173#define OPERAND(op) M32R_OPERAND_/**/op
1174#endif
1175#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1176#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1177
1178/* The macro instruction table. */
1179
1180static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
1181{
1182/* bc $disp8 */
1183 {
1184 -1, "bc8r", "bc", 16,
1185 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1186 },
1187/* bc $disp24 */
1188 {
1189 -1, "bc24r", "bc", 32,
1190 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1191 },
1192/* bl $disp8 */
1193 {
1194 -1, "bl8r", "bl", 16,
1195 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1196 },
1197/* bl $disp24 */
1198 {
1199 -1, "bl24r", "bl", 32,
1200 { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1201 },
1202/* bcl $disp8 */
1203 {
1204 -1, "bcl8r", "bcl", 16,
1205 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
1206 },
1207/* bcl $disp24 */
1208 {
1209 -1, "bcl24r", "bcl", 32,
1210 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
1211 },
1212/* bnc $disp8 */
1213 {
1214 -1, "bnc8r", "bnc", 16,
1215 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1216 },
1217/* bnc $disp24 */
1218 {
1219 -1, "bnc24r", "bnc", 32,
1220 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1221 },
1222/* bra $disp8 */
1223 {
1224 -1, "bra8r", "bra", 16,
1225 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1226 },
1227/* bra $disp24 */
1228 {
1229 -1, "bra24r", "bra", 32,
1230 { 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1231 },
1232/* bncl $disp8 */
1233 {
1234 -1, "bncl8r", "bncl", 16,
1235 { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
1236 },
1237/* bncl $disp24 */
1238 {
1239 -1, "bncl24r", "bncl", 32,
1240 { 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
1241 },
1242/* ld $dr,@($sr) */
1243 {
1244 -1, "ld-2", "ld", 16,
1245 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1246 },
1247/* ld $dr,@($sr,$slo16) */
1248 {
1249 -1, "ld-d2", "ld", 32,
1250 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1251 },
1252/* ldb $dr,@($sr) */
1253 {
1254 -1, "ldb-2", "ldb", 16,
1255 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1256 },
1257/* ldb $dr,@($sr,$slo16) */
1258 {
1259 -1, "ldb-d2", "ldb", 32,
1260 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1261 },
1262/* ldh $dr,@($sr) */
1263 {
1264 -1, "ldh-2", "ldh", 16,
1265 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1266 },
1267/* ldh $dr,@($sr,$slo16) */
1268 {
1269 -1, "ldh-d2", "ldh", 32,
1270 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1271 },
1272/* ldub $dr,@($sr) */
1273 {
1274 -1, "ldub-2", "ldub", 16,
1275 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1276 },
1277/* ldub $dr,@($sr,$slo16) */
1278 {
1279 -1, "ldub-d2", "ldub", 32,
1280 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1281 },
1282/* lduh $dr,@($sr) */
1283 {
1284 -1, "lduh-2", "lduh", 16,
1285 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1286 },
1287/* lduh $dr,@($sr,$slo16) */
1288 {
1289 -1, "lduh-d2", "lduh", 32,
1290 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1291 },
1292/* pop $dr */
1293 {
1294 -1, "pop", "pop", 16,
1295 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1296 },
1297/* ldi $dr,$simm8 */
1298 {
1299 -1, "ldi8a", "ldi", 16,
1300 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
1301 },
1302/* ldi $dr,$hash$slo16 */
1303 {
1304 -1, "ldi16a", "ldi", 32,
1305 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1306 },
1307/* rac $accd */
1308 {
1309 -1, "rac-d", "rac", 16,
1310 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
1311 },
1312/* rac $accd,$accs */
1313 {
1314 -1, "rac-ds", "rac", 16,
1315 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
1316 },
1317/* rach $accd */
1318 {
1319 -1, "rach-d", "rach", 16,
1320 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
1321 },
1322/* rach $accd,$accs */
1323 {
1324 -1, "rach-ds", "rach", 16,
1325 { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
1326 },
1327/* st $src1,@($src2) */
1328 {
1329 -1, "st-2", "st", 16,
1330 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1331 },
1332/* st $src1,@($src2,$slo16) */
1333 {
1334 -1, "st-d2", "st", 32,
1335 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1336 },
1337/* stb $src1,@($src2) */
1338 {
1339 -1, "stb-2", "stb", 16,
1340 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1341 },
1342/* stb $src1,@($src2,$slo16) */
1343 {
1344 -1, "stb-d2", "stb", 32,
1345 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1346 },
1347/* sth $src1,@($src2) */
1348 {
1349 -1, "sth-2", "sth", 16,
1350 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
1351 },
1352/* sth $src1,@($src2,$slo16) */
1353 {
1354 -1, "sth-d2", "sth", 32,
1355 { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1356 },
1357/* push $src1 */
1358 {
1359 -1, "push", "push", 16,
1360 { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
1361 },
1362};
1363
1364/* The macro instruction opcode table. */
1365
1366static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
1367{
1368/* bc $disp8 */
1369 {
1370 { 0, 0, 0, 0 },
1371 { { MNEM, ' ', OP (DISP8), 0 } },
1372 & ifmt_bc8r, { 0x7c00 }
1373 },
1374/* bc $disp24 */
1375 {
1376 { 0, 0, 0, 0 },
1377 { { MNEM, ' ', OP (DISP24), 0 } },
1378 & ifmt_bc24r, { 0xfc000000 }
1379 },
1380/* bl $disp8 */
1381 {
1382 { 0, 0, 0, 0 },
1383 { { MNEM, ' ', OP (DISP8), 0 } },
1384 & ifmt_bl8r, { 0x7e00 }
1385 },
1386/* bl $disp24 */
1387 {
1388 { 0, 0, 0, 0 },
1389 { { MNEM, ' ', OP (DISP24), 0 } },
1390 & ifmt_bl24r, { 0xfe000000 }
1391 },
1392/* bcl $disp8 */
1393 {
1394 { 0, 0, 0, 0 },
1395 { { MNEM, ' ', OP (DISP8), 0 } },
1396 & ifmt_bcl8r, { 0x7800 }
1397 },
1398/* bcl $disp24 */
1399 {
1400 { 0, 0, 0, 0 },
1401 { { MNEM, ' ', OP (DISP24), 0 } },
1402 & ifmt_bcl24r, { 0xf8000000 }
1403 },
1404/* bnc $disp8 */
1405 {
1406 { 0, 0, 0, 0 },
1407 { { MNEM, ' ', OP (DISP8), 0 } },
1408 & ifmt_bnc8r, { 0x7d00 }
1409 },
1410/* bnc $disp24 */
1411 {
1412 { 0, 0, 0, 0 },
1413 { { MNEM, ' ', OP (DISP24), 0 } },
1414 & ifmt_bnc24r, { 0xfd000000 }
1415 },
1416/* bra $disp8 */
1417 {
1418 { 0, 0, 0, 0 },
1419 { { MNEM, ' ', OP (DISP8), 0 } },
1420 & ifmt_bra8r, { 0x7f00 }
1421 },
1422/* bra $disp24 */
1423 {
1424 { 0, 0, 0, 0 },
1425 { { MNEM, ' ', OP (DISP24), 0 } },
1426 & ifmt_bra24r, { 0xff000000 }
1427 },
1428/* bncl $disp8 */
1429 {
1430 { 0, 0, 0, 0 },
1431 { { MNEM, ' ', OP (DISP8), 0 } },
1432 & ifmt_bncl8r, { 0x7900 }
1433 },
1434/* bncl $disp24 */
1435 {
1436 { 0, 0, 0, 0 },
1437 { { MNEM, ' ', OP (DISP24), 0 } },
1438 & ifmt_bncl24r, { 0xf9000000 }
1439 },
1440/* ld $dr,@($sr) */
1441 {
1442 { 0, 0, 0, 0 },
1443 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1444 & ifmt_ld_2, { 0x20c0 }
1445 },
1446/* ld $dr,@($sr,$slo16) */
1447 {
1448 { 0, 0, 0, 0 },
1449 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1450 & ifmt_ld_d2, { 0xa0c00000 }
1451 },
1452/* ldb $dr,@($sr) */
1453 {
1454 { 0, 0, 0, 0 },
1455 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1456 & ifmt_ldb_2, { 0x2080 }
1457 },
1458/* ldb $dr,@($sr,$slo16) */
1459 {
1460 { 0, 0, 0, 0 },
1461 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1462 & ifmt_ldb_d2, { 0xa0800000 }
1463 },
1464/* ldh $dr,@($sr) */
1465 {
1466 { 0, 0, 0, 0 },
1467 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1468 & ifmt_ldh_2, { 0x20a0 }
1469 },
1470/* ldh $dr,@($sr,$slo16) */
1471 {
1472 { 0, 0, 0, 0 },
1473 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1474 & ifmt_ldh_d2, { 0xa0a00000 }
1475 },
1476/* ldub $dr,@($sr) */
1477 {
1478 { 0, 0, 0, 0 },
1479 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1480 & ifmt_ldub_2, { 0x2090 }
1481 },
1482/* ldub $dr,@($sr,$slo16) */
1483 {
1484 { 0, 0, 0, 0 },
1485 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1486 & ifmt_ldub_d2, { 0xa0900000 }
1487 },
1488/* lduh $dr,@($sr) */
1489 {
1490 { 0, 0, 0, 0 },
1491 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
1492 & ifmt_lduh_2, { 0x20b0 }
1493 },
1494/* lduh $dr,@($sr,$slo16) */
1495 {
1496 { 0, 0, 0, 0 },
1497 { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
1498 & ifmt_lduh_d2, { 0xa0b00000 }
1499 },
1500/* pop $dr */
1501 {
1502 { 0, 0, 0, 0 },
1503 { { MNEM, ' ', OP (DR), 0 } },
1504 & ifmt_pop, { 0x20ef }
1505 },
1506/* ldi $dr,$simm8 */
1507 {
1508 { 0, 0, 0, 0 },
1509 { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
1510 & ifmt_ldi8a, { 0x6000 }
1511 },
1512/* ldi $dr,$hash$slo16 */
1513 {
1514 { 0, 0, 0, 0 },
1515 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
1516 & ifmt_ldi16a, { 0x90f00000 }
1517 },
1518/* rac $accd */
1519 {
1520 { 0, 0, 0, 0 },
1521 { { MNEM, ' ', OP (ACCD), 0 } },
1522 & ifmt_rac_d, { 0x5090 }
1523 },
1524/* rac $accd,$accs */
1525 {
1526 { 0, 0, 0, 0 },
1527 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1528 & ifmt_rac_ds, { 0x5090 }
1529 },
1530/* rach $accd */
1531 {
1532 { 0, 0, 0, 0 },
1533 { { MNEM, ' ', OP (ACCD), 0 } },
1534 & ifmt_rach_d, { 0x5080 }
1535 },
1536/* rach $accd,$accs */
1537 {
1538 { 0, 0, 0, 0 },
1539 { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
1540 & ifmt_rach_ds, { 0x5080 }
1541 },
1542/* st $src1,@($src2) */
1543 {
1544 { 0, 0, 0, 0 },
1545 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1546 & ifmt_st_2, { 0x2040 }
1547 },
1548/* st $src1,@($src2,$slo16) */
1549 {
1550 { 0, 0, 0, 0 },
1551 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1552 & ifmt_st_d2, { 0xa0400000 }
1553 },
1554/* stb $src1,@($src2) */
1555 {
1556 { 0, 0, 0, 0 },
1557 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1558 & ifmt_stb_2, { 0x2000 }
1559 },
1560/* stb $src1,@($src2,$slo16) */
1561 {
1562 { 0, 0, 0, 0 },
1563 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1564 & ifmt_stb_d2, { 0xa0000000 }
1565 },
1566/* sth $src1,@($src2) */
1567 {
1568 { 0, 0, 0, 0 },
1569 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
1570 & ifmt_sth_2, { 0x2020 }
1571 },
1572/* sth $src1,@($src2,$slo16) */
1573 {
1574 { 0, 0, 0, 0 },
1575 { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
1576 & ifmt_sth_d2, { 0xa0200000 }
1577 },
1578/* push $src1 */
1579 {
1580 { 0, 0, 0, 0 },
1581 { { MNEM, ' ', OP (SRC1), 0 } },
1582 & ifmt_push, { 0x207f }
1583 },
1584};
1585
1586#undef A
1587#undef OPERAND
1588#undef MNEM
1589#undef OP
1590
1591#ifndef CGEN_ASM_HASH_P
1592#define CGEN_ASM_HASH_P(insn) 1
1593#endif
1594
1595#ifndef CGEN_DIS_HASH_P
1596#define CGEN_DIS_HASH_P(insn) 1
1597#endif
1598
1599/* Return non-zero if INSN is to be added to the hash table.
1600 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1601
1602static int
1603asm_hash_insn_p (insn)
1604 const CGEN_INSN *insn ATTRIBUTE_UNUSED;
1605{
1606 return CGEN_ASM_HASH_P (insn);
1607}
1608
1609static int
1610dis_hash_insn_p (insn)
1611 const CGEN_INSN *insn;
1612{
1613 /* If building the hash table and the NO-DIS attribute is present,
1614 ignore. */
1615 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
1616 return 0;
1617 return CGEN_DIS_HASH_P (insn);
1618}
1619
1620#ifndef CGEN_ASM_HASH
1621#define CGEN_ASM_HASH_SIZE 127
1622#ifdef CGEN_MNEMONIC_OPERANDS
1623#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1624#else
1625#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1626#endif
1627#endif
1628
1629/* It doesn't make much sense to provide a default here,
1630 but while this is under development we do.
1631 BUFFER is a pointer to the bytes of the insn, target order.
1632 VALUE is the first base_insn_bitsize bits as an int in host order. */
1633
1634#ifndef CGEN_DIS_HASH
1635#define CGEN_DIS_HASH_SIZE 256
1636#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1637#endif
1638
1639/* The result is the hash value of the insn.
1640 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1641
1642static unsigned int
1643asm_hash_insn (mnem)
1644 const char * mnem;
1645{
1646 return CGEN_ASM_HASH (mnem);
1647}
1648
1649/* BUF is a pointer to the bytes of the insn, target order.
1650 VALUE is the first base_insn_bitsize bits as an int in host order. */
1651
1652static unsigned int
1653dis_hash_insn (buf, value)
1654 const char * buf ATTRIBUTE_UNUSED;
1655 CGEN_INSN_INT value ATTRIBUTE_UNUSED;
1656{
1657 return CGEN_DIS_HASH (buf, value);
1658}
1659
1660static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
1661
1662/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
1663
1664static void
1665set_fields_bitsize (fields, size)
1666 CGEN_FIELDS *fields;
1667 int size;
1668{
1669 CGEN_FIELDS_BITSIZE (fields) = size;
1670}
1671
1672/* Function to call before using the operand instance table.
1673 This plugs the opcode entries and macro instructions into the cpu table. */
1674
1675void
1676m32r_cgen_init_opcode_table (cd)
1677 CGEN_CPU_DESC cd;
1678{
1679 int i;
1680 int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
1681 sizeof (m32r_cgen_macro_insn_table[0]));
1682 const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
1683 const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
1684 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
1685 memset (insns, 0, num_macros * sizeof (CGEN_INSN));
1686 for (i = 0; i < num_macros; ++i)
1687 {
1688 insns[i].base = &ib[i];
1689 insns[i].opcode = &oc[i];
1690 m32r_cgen_build_insn_regex (& insns[i]);
1691 }
1692 cd->macro_insn_table.init_entries = insns;
1693 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
1694 cd->macro_insn_table.num_init_entries = num_macros;
1695
1696 oc = & m32r_cgen_insn_opcode_table[0];
1697 insns = (CGEN_INSN *) cd->insn_table.init_entries;
1698 for (i = 0; i < MAX_INSNS; ++i)
1699 {
1700 insns[i].opcode = &oc[i];
1701 m32r_cgen_build_insn_regex (& insns[i]);
1702 }
1703
1704 cd->sizeof_fields = sizeof (CGEN_FIELDS);
1705 cd->set_fields_bitsize = set_fields_bitsize;
1706
1707 cd->asm_hash_p = asm_hash_insn_p;
1708 cd->asm_hash = asm_hash_insn;
1709 cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
1710
1711 cd->dis_hash_p = dis_hash_insn_p;
1712 cd->dis_hash = dis_hash_insn;
1713 cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
1714}
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