| 1 | /* CPU data header for iq2000.
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| 2 |
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| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN.
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| 4 |
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| 5 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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| 6 |
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| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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| 8 |
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| 9 | This program is free software; you can redistribute it and/or modify
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| 10 | it under the terms of the GNU General Public License as published by
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| 11 | the Free Software Foundation; either version 2, or (at your option)
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| 12 | any later version.
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| 13 |
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| 14 | This program is distributed in the hope that it will be useful,
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| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 17 | GNU General Public License for more details.
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| 18 |
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| 19 | You should have received a copy of the GNU General Public License along
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| 20 | with this program; if not, write to the Free Software Foundation, Inc.,
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| 21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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| 22 |
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| 23 | */
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| 24 |
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| 25 | #ifndef IQ2000_CPU_H
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| 26 | #define IQ2000_CPU_H
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| 27 |
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| 28 | #define CGEN_ARCH iq2000
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| 29 |
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| 30 | /* Given symbol S, return iq2000_cgen_<S>. */
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| 31 | #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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| 32 | #define CGEN_SYM(s) iq2000##_cgen_##s
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| 33 | #else
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| 34 | #define CGEN_SYM(s) iq2000/**/_cgen_/**/s
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| 35 | #endif
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| 36 |
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| 37 |
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| 38 | /* Selected cpu families. */
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| 39 | #define HAVE_CPU_IQ2000BF
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| 40 | #define HAVE_CPU_IQ10BF
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| 41 |
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| 42 | #define CGEN_INSN_LSB0_P 1
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| 43 |
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| 44 | /* Minimum size of any insn (in bytes). */
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| 45 | #define CGEN_MIN_INSN_SIZE 4
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| 46 |
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| 47 | /* Maximum size of any insn (in bytes). */
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| 48 | #define CGEN_MAX_INSN_SIZE 4
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| 49 |
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| 50 | #define CGEN_INT_INSN_P 1
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| 51 |
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| 52 | /* Maximum number of syntax elements in an instruction. */
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| 53 | #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
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| 54 |
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| 55 | /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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| 56 | e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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| 57 | we can't hash on everything up to the space. */
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| 58 | #define CGEN_MNEMONIC_OPERANDS
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| 59 |
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| 60 | /* Maximum number of fields in an instruction. */
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| 61 | #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
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| 62 |
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| 63 | /* Enums. */
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| 64 |
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| 65 | /* Enum declaration for . */
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| 66 | typedef enum gr_names {
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| 67 | H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1, H_GR__1 = 1
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| 68 | , H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3, H_GR__3 = 3
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| 69 | , H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5, H_GR__5 = 5
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| 70 | , H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7, H_GR__7 = 7
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| 71 | , H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9, H_GR__9 = 9
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| 72 | , H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11, H_GR__11 = 11
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| 73 | , H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13, H_GR__13 = 13
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| 74 | , H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15, H_GR__15 = 15
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| 75 | , H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17, H_GR__17 = 17
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| 76 | , H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19, H_GR__19 = 19
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| 77 | , H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21, H_GR__21 = 21
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| 78 | , H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23, H_GR__23 = 23
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| 79 | , H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25, H_GR__25 = 25
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| 80 | , H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27, H_GR__27 = 27
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| 81 | , H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29, H_GR__29 = 29
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| 82 | , H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31, H_GR__31 = 31
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| 83 | } GR_NAMES;
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| 84 |
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| 85 | /* Enum declaration for primary opcodes. */
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| 86 | typedef enum opcodes {
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| 87 | OP_SPECIAL = 0, OP_REGIMM = 1, OP_J = 2, OP_JAL = 3
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| 88 | , OP_BEQ = 4, OP_BNE = 5, OP_BLEZ = 6, OP_BGTZ = 7
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| 89 | , OP_ADDI = 8, OP_ADDIU = 9, OP_SLTI = 10, OP_SLTIU = 11
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| 90 | , OP_ANDI = 12, OP_ORI = 13, OP_XORI = 14, OP_LUI = 15
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| 91 | , OP_COP0 = 16, OP_COP1 = 17, OP_COP2 = 18, OP_COP3 = 19
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| 92 | , OP_BEQL = 20, OP_BNEL = 21, OP_BLEZL = 22, OP_BGTZL = 23
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| 93 | , OP_BMB0 = 24, OP_BMB1 = 25, OP_BMB2 = 26, OP_BMB3 = 27
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| 94 | , OP_BBI = 28, OP_BBV = 29, OP_BBIN = 30, OP_BBVN = 31
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| 95 | , OP_LB = 32, OP_LH = 33, OP_LW = 35, OP_LBU = 36
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| 96 | , OP_LHU = 37, OP_RAM = 39, OP_SB = 40, OP_SH = 41
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| 97 | , OP_SW = 43, OP_ANDOI = 44, OP_BMB = 45, OP_ORUI = 47
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| 98 | , OP_LDW = 48, OP_SDW = 56, OP_ANDOUI = 63
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| 99 | } OPCODES;
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| 100 |
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| 101 | /* Enum declaration for iq10-only primary opcodes. */
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| 102 | typedef enum q10_opcodes {
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| 103 | OP10_BMB = 6, OP10_ORUI = 15, OP10_BMBL = 22, OP10_ANDOUI = 47
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| 104 | , OP10_BBIL = 60, OP10_BBVL = 61, OP10_BBINL = 62, OP10_BBVNL = 63
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| 105 | } Q10_OPCODES;
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| 106 |
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| 107 | /* Enum declaration for branch sub-opcodes. */
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| 108 | typedef enum regimm_functions {
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| 109 | FUNC_BLTZ = 0, FUNC_BGEZ = 1, FUNC_BLTZL = 2, FUNC_BGEZL = 3
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| 110 | , FUNC_BLEZ = 4, FUNC_BGTZ = 5, FUNC_BLEZL = 6, FUNC_BGTZL = 7
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| 111 | , FUNC_BRI = 8, FUNC_BRV = 9, FUNC_BCTX = 12, FUNC_BLTZAL = 16
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| 112 | , FUNC_BGEZAL = 17, FUNC_BLTZALL = 18, FUNC_BGEZALL = 19, FUNC_BLEZAL = 20
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| 113 | , FUNC_BGTZAL = 21, FUNC_BLEZALL = 22, FUNC_BGTZALL = 23
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| 114 | } REGIMM_FUNCTIONS;
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| 115 |
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| 116 | /* Enum declaration for function sub-opcodes. */
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| 117 | typedef enum functions {
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| 118 | FUNC_SLL = 0, FUNC_SLMV = 1, FUNC_SRL = 2, FUNC_SRA = 3
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| 119 | , FUNC_SLLV = 4, FUNC_SRMV = 5, FUNC_SRLV = 6, FUNC_SRAV = 7
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| 120 | , FUNC_JR = 8, FUNC_JALR = 9, FUNC_JCR = 10, FUNC_SYSCALL = 12
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| 121 | , FUNC_BREAK = 13, FUNC_SLEEP = 14, FUNC_ADD = 32, FUNC_ADDU = 33
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| 122 | , FUNC_SUB = 34, FUNC_SUBU = 35, FUNC_AND = 36, FUNC_OR = 37
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| 123 | , FUNC_XOR = 38, FUNC_NOR = 39, FUNC_ADO16 = 41, FUNC_SLT = 42
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| 124 | , FUNC_SLTU = 43, FUNC_MRGB = 45
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| 125 | } FUNCTIONS;
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| 126 |
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| 127 | /* Enum declaration for iq10-only special function sub-opcodes. */
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| 128 | typedef enum q10s_functions {
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| 129 | FUNC10_YIELD = 14, FUNC10_CNT1S = 46
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| 130 | } Q10S_FUNCTIONS;
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| 131 |
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| 132 | /* Enum declaration for iq10 function sub-opcodes. */
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| 133 | typedef enum cop_functions {
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| 134 | FUNC10_CFC = 0, FUNC10_LOCK = 1, FUNC10_CTC = 2, FUNC10_UNLK = 3
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| 135 | , FUNC10_SWRD = 4, FUNC10_SWRDL = 5, FUNC10_SWWR = 6, FUNC10_SWWRU = 7
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| 136 | , FUNC10_RBA = 8, FUNC10_RBAL = 9, FUNC10_RBAR = 10, FUNC10_DWRD = 12
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| 137 | , FUNC10_DWRDL = 13, FUNC10_WBA = 16, FUNC10_WBAU = 17, FUNC10_WBAC = 18
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| 138 | , FUNC10_CRC32 = 20, FUNC10_CRC32B = 21, FUNC10_MCID = 32, FUNC10_DBD = 33
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| 139 | , FUNC10_DBA = 34, FUNC10_DPWT = 35, FUNC10_AVAIL = 36, FUNC10_FREE = 37
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| 140 | , FUNC10_CHKHDR = 38, FUNC10_TSTOD = 39, FUNC10_PKRLA = 40, FUNC10_PKRLAU = 41
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| 141 | , FUNC10_PKRLAH = 42, FUNC10_PKRLAC = 43, FUNC10_CMPHDR = 44, FUNC10_CM64RS = 0
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| 142 | , FUNC10_CM64RD = 1, FUNC10_CM64RI = 4, FUNC10_CM64CLR = 5, FUNC10_CM64SS = 8
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| 143 | , FUNC10_CM64SD = 9, FUNC10_CM64SI = 12, FUNC10_CM64RA = 16, FUNC10_CM64RIA2 = 20
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| 144 | , FUNC10_CM128RIA2 = 21, FUNC10_CM64SA = 24, FUNC10_CM64SIA2 = 28, FUNC10_CM128SIA2 = 29
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| 145 | , FUNC10_CM32RS = 32, FUNC10_CM32RD = 33, FUNC10_CM32XOR = 34, FUNC10_CM32ANDN = 35
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| 146 | , FUNC10_CM32RI = 36, FUNC10_CM128VSA = 38, FUNC10_CM32SS = 40, FUNC10_CM32SD = 41
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| 147 | , FUNC10_CM32OR = 42, FUNC10_CM32AND = 43, FUNC10_CM32SI = 44, FUNC10_CM32RA = 48
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| 148 | , FUNC10_CM32SA = 56
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| 149 | } COP_FUNCTIONS;
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| 150 |
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| 151 | /* Enum declaration for iq10 function sub-opcodes. */
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| 152 | typedef enum cop_cm128_4functions {
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| 153 | FUNC10_CM128RIA3 = 4, FUNC10_CM128SIA3 = 6
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| 154 | } COP_CM128_4FUNCTIONS;
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| 155 |
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| 156 | /* Enum declaration for iq10 function sub-opcodes. */
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| 157 | typedef enum cop_cm128_3functions {
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| 158 | FUNC10_CM128RIA4 = 6, FUNC10_CM128SIA4 = 7
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| 159 | } COP_CM128_3FUNCTIONS;
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| 160 |
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| 161 | /* Enum declaration for iq10 coprocessor sub-opcodes. */
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| 162 | typedef enum cop2_functions {
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| 163 | FUNC10_PKRLI = 0, FUNC10_PKRLIU = 1, FUNC10_PKRLIH = 2, FUNC10_PKRLIC = 3
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| 164 | , FUNC10_RBIR = 1, FUNC10_RBI = 2, FUNC10_RBIL = 3, FUNC10_WBIC = 5
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| 165 | , FUNC10_WBI = 6, FUNC10_WBIU = 7
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| 166 | } COP2_FUNCTIONS;
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| 167 |
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| 168 | /* Enum declaration for iq10 coprocessor cam sub-opcodes. */
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| 169 | typedef enum cop3_cam_functions {
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| 170 | FUNC10_CAM36 = 16, FUNC10_CAM72 = 17, FUNC10_CAM144 = 18, FUNC10_CAM288 = 19
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| 171 | } COP3_CAM_FUNCTIONS;
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| 172 |
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| 173 | /* Attributes. */
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| 174 |
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| 175 | /* Enum declaration for machine type selection. */
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| 176 | typedef enum mach_attr {
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| 177 | MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX
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| 178 | } MACH_ATTR;
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| 179 |
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| 180 | /* Enum declaration for instruction set selection. */
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| 181 | typedef enum isa_attr {
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| 182 | ISA_IQ2000, ISA_MAX
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| 183 | } ISA_ATTR;
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| 184 |
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| 185 | /* Number of architecture variants. */
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| 186 | #define MAX_ISAS 1
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| 187 | #define MAX_MACHS ((int) MACH_MAX)
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| 188 |
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| 189 | /* Ifield support. */
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| 190 |
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| 191 | extern const struct cgen_ifld iq2000_cgen_ifld_table[];
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| 192 |
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| 193 | /* Ifield attribute indices. */
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| 194 |
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| 195 | /* Enum declaration for cgen_ifld attrs. */
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| 196 | typedef enum cgen_ifld_attr {
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| 197 | CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
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| 198 | , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
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| 199 | , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
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| 200 | } CGEN_IFLD_ATTR;
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| 201 |
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| 202 | /* Number of non-boolean elements in cgen_ifld_attr. */
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| 203 | #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
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| 204 |
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| 205 | /* Enum declaration for iq2000 ifield types. */
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| 206 | typedef enum ifield_type {
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| 207 | IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS
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| 208 | , IQ2000_F_RT, IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP
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| 209 | , IQ2000_F_CP_OP_10, IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM
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| 210 | , IQ2000_F_RD_RS, IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG
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| 211 | , IQ2000_F_JTARGQ10, IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT
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| 212 | , IQ2000_F_INDEX, IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL
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| 213 | , IQ2000_F_EXCODE, IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19
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| 214 | , IQ2000_F_5, IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z
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| 215 | , IQ2000_F_CAM_Y, IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z
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| 216 | , IQ2000_F_CM_4Z, IQ2000_F_MAX
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| 217 | } IFIELD_TYPE;
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| 218 |
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| 219 | #define MAX_IFLD ((int) IQ2000_F_MAX)
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| 220 |
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| 221 | /* Hardware attribute indices. */
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| 222 |
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| 223 | /* Enum declaration for cgen_hw attrs. */
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| 224 | typedef enum cgen_hw_attr {
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| 225 | CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
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| 226 | , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
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| 227 | } CGEN_HW_ATTR;
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| 228 |
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| 229 | /* Number of non-boolean elements in cgen_hw_attr. */
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| 230 | #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
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| 231 |
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| 232 | /* Enum declaration for iq2000 hardware types. */
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| 233 | typedef enum cgen_hw_type {
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| 234 | HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
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| 235 | , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX
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| 236 | } CGEN_HW_TYPE;
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| 237 |
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| 238 | #define MAX_HW ((int) HW_MAX)
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| 239 |
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| 240 | /* Operand attribute indices. */
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| 241 |
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| 242 | /* Enum declaration for cgen_operand attrs. */
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| 243 | typedef enum cgen_operand_attr {
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| 244 | CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
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| 245 | , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
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| 246 | , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
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| 247 | } CGEN_OPERAND_ATTR;
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| 248 |
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| 249 | /* Number of non-boolean elements in cgen_operand_attr. */
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| 250 | #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
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| 251 |
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| 252 | /* Enum declaration for iq2000 operand types. */
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| 253 | typedef enum cgen_operand_type {
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| 254 | IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD
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| 255 | , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT
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| 256 | , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG
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| 257 | , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT
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| 258 | , IQ2000_OPERAND_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y
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| 259 | , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z
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| 260 | , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM
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| 261 | , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10
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| 262 | , IQ2000_OPERAND_MAX
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| 263 | } CGEN_OPERAND_TYPE;
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| 264 |
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| 265 | /* Number of operands types. */
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| 266 | #define MAX_OPERANDS 32
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| 267 |
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| 268 | /* Maximum number of operands referenced by any insn. */
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| 269 | #define MAX_OPERAND_INSTANCES 8
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| 270 |
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| 271 | /* Insn attribute indices. */
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| 272 |
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| 273 | /* Enum declaration for cgen_insn attrs. */
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| 274 | typedef enum cgen_insn_attr {
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| 275 | CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
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| 276 | , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
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| 277 | , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY
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| 278 | , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS
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| 279 | , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
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| 280 | , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
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| 281 | } CGEN_INSN_ATTR;
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| 282 |
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| 283 | /* Number of non-boolean elements in cgen_insn_attr. */
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| 284 | #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
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| 285 |
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| 286 | /* cgen.h uses things we just defined. */
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| 287 | #include "opcode/cgen.h"
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| 288 |
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| 289 | /* Attributes. */
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| 290 | extern const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[];
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| 291 | extern const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[];
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| 292 | extern const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[];
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| 293 | extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[];
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| 294 |
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| 295 | /* Hardware decls. */
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| 296 |
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| 297 | extern CGEN_KEYWORD iq2000_cgen_opval_gr_names;
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| 298 |
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| 299 |
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| 300 |
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| 301 |
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| 302 | #endif /* IQ2000_CPU_H */
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