source: vendor/binutils/current/opcodes/dlx-dis.c

Last change on this file was 608, checked in by (none), 22 years ago

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1/* Instruction printing code for the DLX Microprocessor
2 Copyright 2002 Free Software Foundation, Inc.
3 Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002.
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18
19#include "sysdep.h"
20#include "dis-asm.h"
21#include "opcode/dlx.h"
22
23#define R_ERROR 0x1
24#define R_TYPE 0x2
25#define ILD_TYPE 0x3
26#define IST_TYPE 0x4
27#define IAL_TYPE 0x5
28#define IBR_TYPE 0x6
29#define IJ_TYPE 0x7
30#define IJR_TYPE 0x8
31#define NIL 0x9
32
33#define OPC(x) ((x >> 26) & 0x3F)
34#define FUNC(x) (x & 0x7FF)
35
36unsigned char opc, rs1, rs2, rd;
37unsigned long imm26, imm16, func, current_insn_addr;
38
39static unsigned char dlx_get_opcode PARAMS ((unsigned long));
40static unsigned char dlx_get_rs1 PARAMS ((unsigned long));
41static unsigned char dlx_get_rs2 PARAMS ((unsigned long));
42static unsigned char dlx_get_rdR PARAMS ((unsigned long));
43static unsigned long dlx_get_func PARAMS ((unsigned long));
44static unsigned long dlx_get_imm16 PARAMS ((unsigned long));
45static unsigned long dlx_get_imm26 PARAMS ((unsigned long));
46static void operand_deliminator PARAMS ((struct disassemble_info *, char *));
47static unsigned char dlx_r_type PARAMS ((struct disassemble_info *));
48static unsigned char dlx_load_type PARAMS ((struct disassemble_info *));
49static unsigned char dlx_store_type PARAMS ((struct disassemble_info *));
50static unsigned char dlx_aluI_type PARAMS ((struct disassemble_info *));
51static unsigned char dlx_br_type PARAMS ((struct disassemble_info *));
52static unsigned char dlx_jmp_type PARAMS ((struct disassemble_info *));
53static unsigned char dlx_jr_type PARAMS ((struct disassemble_info *));
54
55/* Print one instruction from MEMADDR on INFO->STREAM.
56 Return the size of the instruction (always 4 on dlx). */
57
58static unsigned char
59dlx_get_opcode (opcode)
60 unsigned long opcode;
61{
62 return (unsigned char) ((opcode >> 26) & 0x3F);
63}
64
65static unsigned char
66dlx_get_rs1 (opcode)
67 unsigned long opcode;
68{
69 return (unsigned char) ((opcode >> 21) & 0x1F);
70}
71
72static unsigned char
73dlx_get_rs2 (opcode)
74 unsigned long opcode;
75{
76 return (unsigned char) ((opcode >> 16) & 0x1F);
77}
78
79static unsigned char
80dlx_get_rdR (opcode)
81 unsigned long opcode;
82{
83 return (unsigned char) ((opcode >> 11) & 0x1F);
84}
85
86static unsigned long
87dlx_get_func (opcode)
88 unsigned long opcode;
89{
90 return (unsigned char) (opcode & 0x7FF);
91}
92
93static unsigned long
94dlx_get_imm16 (opcode)
95 unsigned long opcode;
96{
97 return (unsigned long) (opcode & 0xFFFF);
98}
99
100static unsigned long
101dlx_get_imm26 (opcode)
102 unsigned long opcode;
103{
104 return (unsigned long) (opcode & 0x03FFFFFF);
105}
106
107/* Fill the opcode to the max length. */
108static void
109operand_deliminator (info, ptr)
110 struct disassemble_info *info;
111 char *ptr;
112{
113 int difft = 8 - (int) strlen (ptr);
114
115 while (difft > 0)
116 {
117 (*info->fprintf_func) (info->stream, "%c", ' ');
118 difft -= 1;
119 }
120}
121
122/* Process the R-type opcode. */
123static unsigned char
124dlx_r_type (info)
125 struct disassemble_info *info;
126{
127 unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
128 int r_opc_num = (sizeof r_opc) / (sizeof (char));
129 struct _r_opcode
130 {
131 unsigned long func;
132 char *name;
133 }
134 dlx_r_opcode[] =
135 {
136 { NOPF, "nop" }, /* NOP */
137 { ADDF, "add" }, /* Add */
138 { ADDUF, "addu" }, /* Add Unsigned */
139 { SUBF, "sub" }, /* SUB */
140 { SUBUF, "subu" }, /* Sub Unsigned */
141 { MULTF, "mult" }, /* MULTIPLY */
142 { MULTUF, "multu" }, /* MULTIPLY Unsigned */
143 { DIVF, "div" }, /* DIVIDE */
144 { DIVUF, "divu" }, /* DIVIDE Unsigned */
145 { ANDF, "and" }, /* AND */
146 { ORF, "or" }, /* OR */
147 { XORF, "xor" }, /* Exclusive OR */
148 { SLLF, "sll" }, /* SHIFT LEFT LOGICAL */
149 { SRAF, "sra" }, /* SHIFT RIGHT ARITHMETIC */
150 { SRLF, "srl" }, /* SHIFT RIGHT LOGICAL */
151 { SEQF, "seq" }, /* Set if equal */
152 { SNEF, "sne" }, /* Set if not equal */
153 { SLTF, "slt" }, /* Set if less */
154 { SGTF, "sgt" }, /* Set if greater */
155 { SLEF, "sle" }, /* Set if less or equal */
156 { SGEF, "sge" }, /* Set if greater or equal */
157 { SEQUF, "sequ" }, /* Set if equal */
158 { SNEUF, "sneu" }, /* Set if not equal */
159 { SLTUF, "sltu" }, /* Set if less */
160 { SGTUF, "sgtu" }, /* Set if greater */
161 { SLEUF, "sleu" }, /* Set if less or equal */
162 { SGEUF, "sgeu" }, /* Set if greater or equal */
163 { MVTSF, "mvts" }, /* Move to special register */
164 { MVFSF, "mvfs" }, /* Move from special register */
165 { BSWAPF, "bswap" }, /* Byte swap ?? */
166 { LUTF, "lut" } /* ????????? ?? */
167 };
168 int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]);
169 int idx;
170
171 for (idx = 0; idx < r_opc_num; idx++)
172 {
173 if (r_opc[idx] != opc)
174 continue;
175 else
176 break;
177 }
178
179 if (idx == r_opc_num)
180 return NIL;
181
182 for (idx = 0 ; idx < dlx_r_opcode_num; idx++)
183 if (dlx_r_opcode[idx].func == func)
184 {
185 (*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name);
186
187 if (func != NOPF)
188 {
189 /* This is not a nop. */
190 operand_deliminator (info, dlx_r_opcode[idx].name);
191 (*info->fprintf_func) (info->stream, "r%d,", (int)rd);
192 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
193 if (func != MVTSF && func != MVFSF)
194 (*info->fprintf_func) (info->stream, ",r%d", (int)rs2);
195 }
196 return (unsigned char) R_TYPE;
197 }
198
199 return (unsigned char) R_ERROR;
200}
201
202/* Process the memory read opcode. */
203
204static unsigned char
205dlx_load_type (info)
206 struct disassemble_info* info;
207{
208 struct _load_opcode
209 {
210 unsigned long opcode;
211 char *name;
212 }
213 dlx_load_opcode[] =
214 {
215 { OPC(LHIOP), "lhi" }, /* Load HI to register. */
216 { OPC(LBOP), "lb" }, /* load byte sign extended. */
217 { OPC(LBUOP), "lbu" }, /* load byte unsigned. */
218 { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */
219 { OPC(LHOP), "lh" }, /* load halfword sign extended. */
220 { OPC(LHUOP), "lhu" }, /* load halfword unsigned. */
221 { OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */
222 { OPC(LWOP), "lw" }, /* load word. */
223 { OPC(LSWOP), "ldstw" } /* load store word. */
224 };
225 int dlx_load_opcode_num =
226 (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]);
227 int idx;
228
229 for (idx = 0 ; idx < dlx_load_opcode_num; idx++)
230 if (dlx_load_opcode[idx].opcode == opc)
231 {
232 if (opc == OPC (LHIOP))
233 {
234 (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
235 operand_deliminator (info, dlx_load_opcode[idx].name);
236 (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
237 (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
238 }
239 else
240 {
241 (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
242 operand_deliminator (info, dlx_load_opcode[idx].name);
243 (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
244 (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
245 }
246
247 return (unsigned char) ILD_TYPE;
248 }
249
250 return (unsigned char) NIL;
251}
252
253/* Process the memory store opcode. */
254
255static unsigned char
256dlx_store_type (info)
257 struct disassemble_info* info;
258{
259 struct _store_opcode
260 {
261 unsigned long opcode;
262 char *name;
263 }
264 dlx_store_opcode[] =
265 {
266 { OPC(SBOP), "sb" }, /* Store byte. */
267 { OPC(SHOP), "sh" }, /* Store halfword. */
268 { OPC(SWOP), "sw" }, /* Store word. */
269 };
270 int dlx_store_opcode_num =
271 (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]);
272 int idx;
273
274 for (idx = 0 ; idx < dlx_store_opcode_num; idx++)
275 if (dlx_store_opcode[idx].opcode == opc)
276 {
277 (*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name);
278 operand_deliminator (info, dlx_store_opcode[idx].name);
279 (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
280 (*info->fprintf_func) (info->stream, "r%d", (int)rs2);
281 return (unsigned char) IST_TYPE;
282 }
283
284 return (unsigned char) NIL;
285}
286
287/* Process the Arithmetic and Logical I-TYPE opcode. */
288
289static unsigned char
290dlx_aluI_type (info)
291 struct disassemble_info* info;
292{
293 struct _aluI_opcode
294 {
295 unsigned long opcode;
296 char *name;
297 }
298 dlx_aluI_opcode[] =
299 {
300 { OPC(ADDIOP), "addi" }, /* Store byte. */
301 { OPC(ADDUIOP), "addui" }, /* Store halfword. */
302 { OPC(SUBIOP), "subi" }, /* Store word. */
303 { OPC(SUBUIOP), "subui" }, /* Store word. */
304 { OPC(ANDIOP), "andi" }, /* Store word. */
305 { OPC(ORIOP), "ori" }, /* Store word. */
306 { OPC(XORIOP), "xori" }, /* Store word. */
307 { OPC(SLLIOP), "slli" }, /* Store word. */
308 { OPC(SRAIOP), "srai" }, /* Store word. */
309 { OPC(SRLIOP), "srli" }, /* Store word. */
310 { OPC(SEQIOP), "seqi" }, /* Store word. */
311 { OPC(SNEIOP), "snei" }, /* Store word. */
312 { OPC(SLTIOP), "slti" }, /* Store word. */
313 { OPC(SGTIOP), "sgti" }, /* Store word. */
314 { OPC(SLEIOP), "slei" }, /* Store word. */
315 { OPC(SGEIOP), "sgei" }, /* Store word. */
316 { OPC(SEQUIOP), "sequi" }, /* Store word. */
317 { OPC(SNEUIOP), "sneui" }, /* Store word. */
318 { OPC(SLTUIOP), "sltui" }, /* Store word. */
319 { OPC(SGTUIOP), "sgtui" }, /* Store word. */
320 { OPC(SLEUIOP), "sleui" }, /* Store word. */
321 { OPC(SGEUIOP), "sgeui" }, /* Store word. */
322#if 0
323 { OPC(MVTSOP), "mvts" }, /* Store word. */
324 { OPC(MVFSOP), "mvfs" }, /* Store word. */
325#endif
326 };
327 int dlx_aluI_opcode_num =
328 (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]);
329 int idx;
330
331 for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++)
332 if (dlx_aluI_opcode[idx].opcode == opc)
333 {
334 (*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name);
335 operand_deliminator (info, dlx_aluI_opcode[idx].name);
336 (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
337 (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
338 (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
339
340 return (unsigned char) IAL_TYPE;
341 }
342
343 return (unsigned char) NIL;
344}
345
346/* Process the branch instruction. */
347
348static unsigned char
349dlx_br_type (info)
350 struct disassemble_info* info;
351{
352 struct _br_opcode
353 {
354 unsigned long opcode;
355 char *name;
356 }
357 dlx_br_opcode[] =
358 {
359 { OPC(BEQOP), "beqz" }, /* Store byte. */
360 { OPC(BNEOP), "bnez" } /* Store halfword. */
361 };
362 int dlx_br_opcode_num =
363 (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]);
364 int idx;
365
366 for (idx = 0 ; idx < dlx_br_opcode_num; idx++)
367 if (dlx_br_opcode[idx].opcode == opc)
368 {
369 if (imm16 & 0x00008000)
370 imm16 |= 0xFFFF0000;
371
372 imm16 += (current_insn_addr + 4);
373 (*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name);
374 operand_deliminator (info, dlx_br_opcode[idx].name);
375 (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
376 (*info->fprintf_func) (info->stream, "0x%08x", (int)imm16);
377
378 return (unsigned char) IBR_TYPE;
379 }
380
381 return (unsigned char) NIL;
382}
383
384/* Process the jump instruction. */
385
386static unsigned char
387dlx_jmp_type (info)
388 struct disassemble_info* info;
389{
390 struct _jmp_opcode
391 {
392 unsigned long opcode;
393 char *name;
394 }
395 dlx_jmp_opcode[] =
396 {
397 { OPC(JOP), "j" }, /* Store byte. */
398 { OPC(JALOP), "jal" }, /* Store halfword. */
399 { OPC(BREAKOP), "break" }, /* Store halfword. */
400 { OPC(TRAPOP), "trap" }, /* Store halfword. */
401 { OPC(RFEOP), "rfe" } /* Store halfword. */
402 };
403 int dlx_jmp_opcode_num =
404 (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]);
405 int idx;
406
407 for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++)
408 if (dlx_jmp_opcode[idx].opcode == opc)
409 {
410 if (imm26 & 0x02000000)
411 imm26 |= 0xFC000000;
412
413 imm26 += (current_insn_addr + 4);
414
415 (*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name);
416 operand_deliminator (info, dlx_jmp_opcode[idx].name);
417 (*info->fprintf_func) (info->stream, "0x%08x", (int)imm26);
418
419 return (unsigned char) IJ_TYPE;
420 }
421
422 return (unsigned char) NIL;
423}
424
425/* Process the jump register instruction. */
426
427static unsigned char
428dlx_jr_type (info)
429 struct disassemble_info* info;
430{
431 struct _jr_opcode
432 {
433 unsigned long opcode;
434 char *name;
435 }
436 dlx_jr_opcode[] = {
437 { OPC(JROP), "jr" }, /* Store byte. */
438 { OPC(JALROP), "jalr" } /* Store halfword. */
439 };
440 int dlx_jr_opcode_num =
441 (sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]);
442 int idx;
443
444 for (idx = 0 ; idx < dlx_jr_opcode_num; idx++)
445 if (dlx_jr_opcode[idx].opcode == opc)
446 {
447 (*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name);
448 operand_deliminator (info, dlx_jr_opcode[idx].name);
449 (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
450 return (unsigned char) IJR_TYPE;
451 }
452
453 return (unsigned char) NIL;
454}
455
456typedef unsigned char (* dlx_insn) PARAMS ((struct disassemble_info *));
457
458/* This is the main DLX insn handling routine. */
459
460int
461print_insn_dlx (memaddr, info)
462 bfd_vma memaddr;
463 struct disassemble_info* info;
464{
465 bfd_byte buffer[4];
466 int insn_idx;
467 unsigned long insn_word;
468 unsigned char rtn_code;
469 unsigned long dlx_insn_type[] =
470 {
471 (unsigned long) dlx_r_type,
472 (unsigned long) dlx_load_type,
473 (unsigned long) dlx_store_type,
474 (unsigned long) dlx_aluI_type,
475 (unsigned long) dlx_br_type,
476 (unsigned long) dlx_jmp_type,
477 (unsigned long) dlx_jr_type,
478 (unsigned long) NULL
479 };
480 int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1;
481 int status =
482 (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info);
483
484 if (status != 0)
485 {
486 (*info->memory_error_func) (status, memaddr, info);
487 return -1;
488 }
489
490 /* Now decode the insn */
491 insn_word = bfd_getb32 (buffer);
492 opc = dlx_get_opcode (insn_word);
493 rs1 = dlx_get_rs1 (insn_word);
494 rs2 = dlx_get_rs2 (insn_word);
495 rd = dlx_get_rdR (insn_word);
496 func = dlx_get_func (insn_word);
497 imm16= dlx_get_imm16 (insn_word);
498 imm26= dlx_get_imm26 (insn_word);
499
500#if 0
501 printf ("print_insn_big_dlx: opc = 0x%02x\n"
502 " rs1 = 0x%02x\n"
503 " rs2 = 0x%02x\n"
504 " rd = 0x%02x\n"
505 " func = 0x%08x\n"
506 " imm16 = 0x%08x\n"
507 " imm26 = 0x%08x\n",
508 opc, rs1, rs2, rd, func, imm16, imm26);
509#endif
510
511 /* Scan through all the insn type and print the insn out. */
512 rtn_code = 0;
513 current_insn_addr = (unsigned long) memaddr;
514
515 for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++)
516 switch (((dlx_insn) (dlx_insn_type[insn_idx])) (info))
517 {
518 /* Found the correct opcode */
519 case R_TYPE:
520 case ILD_TYPE:
521 case IST_TYPE:
522 case IAL_TYPE:
523 case IBR_TYPE:
524 case IJ_TYPE:
525 case IJR_TYPE:
526 return 4;
527
528 /* Wrong insn type check next one. */
529 default:
530 case NIL:
531 continue;
532
533 /* All rest of the return code are not recongnized, treat it as error */
534 /* we should never get here, I hope! */
535 case R_ERROR:
536 return -1;
537 }
538
539 if (insn_idx == dlx_insn_type_num)
540 /* Well, does not recoganize this opcode. */
541 (*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode");
542
543 return 4;
544}
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