source: vendor/binutils/2.14/include/opcode/arm.h

Last change on this file was 10, checked in by bird, 22 years ago

Initial revision
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Line 
1/* ARM opcode list.
2 Copyright 1989, 1991 Free Software Foundation, Inc.
3
4This file is part of GDB and GAS.
5
6GDB and GAS are free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 1, or (at your option)
9any later version.
10
11GDB and GAS are distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GDB or GAS; see the file COPYING. If not, write to
18the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20/* types of instruction (encoded in bits 26 and 27 of the instruction) */
21
22#define TYPE_ARITHMETIC 0
23#define TYPE_LDR_STR 1
24#define TYPE_BLOCK_BRANCH 2
25#define TYPE_SWI 3
26
27/* bit 25 decides whether an instruction is a block move or a branch */
28#define SUBTYPE_BLOCK 0
29#define SUBTYPE_BRANCH 1
30
31/* codes to distinguish the arithmetic instructions */
32
33#define OPCODE_AND 0
34#define OPCODE_EOR 1
35#define OPCODE_SUB 2
36#define OPCODE_RSB 3
37#define OPCODE_ADD 4
38#define OPCODE_ADC 5
39#define OPCODE_SBC 6
40#define OPCODE_RSC 7
41#define OPCODE_TST 8
42#define OPCODE_TEQ 9
43#define OPCODE_CMP 10
44#define OPCODE_CMN 11
45#define OPCODE_ORR 12
46#define OPCODE_MOV 13
47#define OPCODE_BIC 14
48#define OPCODE_MVN 15
49
50/* condition codes */
51
52#define COND_EQ 0
53#define COND_NE 1
54#define COND_CS 2
55#define COND_CC 3
56#define COND_MI 4
57#define COND_PL 5
58#define COND_VS 6
59#define COND_VC 7
60#define COND_HI 8
61#define COND_LS 9
62#define COND_GE 10
63#define COND_LT 11
64#define COND_GT 12
65#define COND_LE 13
66#define COND_AL 14
67#define COND_NV 15
68
69/* Describes the format of an ARM machine instruction */
70
71struct generic_fmt {
72 unsigned rest :25; /* the rest of the instruction */
73 unsigned subtype :1; /* used to decide between block and branch */
74 unsigned type :2; /* one of TYPE_* */
75 unsigned cond :4; /* one of COND_* defined above */
76};
77
78struct arith_fmt {
79 unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */
80 unsigned dest :4; /* place where the answer goes */
81 unsigned operand1 :4; /* first operand to instruction */
82 unsigned set :1; /* == 1 means set processor flags */
83 unsigned opcode :4; /* one of OPCODE_* defined above */
84 unsigned immed :1; /* operand2 is an immediate value */
85 unsigned type :2; /* == TYPE_ARITHMETIC */
86 unsigned cond :4; /* one of COND_* defined above */
87};
88
89struct ldr_str_fmt {
90 unsigned offset :12; /* #nn or rn or rn shift #m */
91 unsigned reg :4; /* destination for LDR, source for STR */
92 unsigned base :4; /* base register */
93 unsigned is_load :1; /* == 1 for LDR */
94 unsigned writeback :1; /* == 1 means write back (base+offset) into base */
95 unsigned byte :1; /* == 1 means byte access else word */
96 unsigned up :1; /* == 1 means add offset else subtract it */
97 unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */
98 unsigned immed :1; /* == 0 means immediate offset */
99 unsigned type :2; /* == TYPE_LDR_STR */
100 unsigned cond :4; /* one of COND_* defined above */
101};
102
103struct block_fmt {
104 unsigned mask :16; /* register mask */
105 unsigned base :4; /* register used as base of move */
106 unsigned is_load :1; /* == 1 for LDM */
107 unsigned writeback :1; /* == 1 means update base after move */
108 unsigned set :1; /* == 1 means set flags in pc if included in mask */
109 unsigned increment :1; /* == 1 means increment base register */
110 unsigned before :1; /* == 1 means inc/dec before each move */
111 unsigned is_block :1; /* == SUBTYPE_BLOCK */
112 unsigned type :2; /* == TYPE_BLOCK_BRANCH */
113 unsigned cond :4; /* one of COND_* defined above */
114};
115
116struct branch_fmt {
117 unsigned dest :24; /* destination of the branch */
118 unsigned link :1; /* branch with link (function call) */
119 unsigned is_branch :1; /* == SUBTYPE_BRANCH */
120 unsigned type :2; /* == TYPE_BLOCK_BRANCH */
121 unsigned cond :4; /* one of COND_* defined above */
122};
123
124#define ROUND_N 0
125#define ROUND_P 1
126#define ROUND_M 2
127#define ROUND_Z 3
128
129#define FLOAT2_MVF 0
130#define FLOAT2_MNF 1
131#define FLOAT2_ABS 2
132#define FLOAT2_RND 3
133#define FLOAT2_SQT 4
134#define FLOAT2_LOG 5
135#define FLOAT2_LGN 6
136#define FLOAT2_EXP 7
137#define FLOAT2_SIN 8
138#define FLOAT2_COS 9
139#define FLOAT2_TAN 10
140#define FLOAT2_ASN 11
141#define FLOAT2_ACS 12
142#define FLOAT2_ATN 13
143
144#define FLOAT3_ADF 0
145#define FLOAT3_MUF 1
146#define FLOAT3_SUF 2
147#define FLOAT3_RSF 3
148#define FLOAT3_DVF 4
149#define FLOAT3_RDF 5
150#define FLOAT3_POW 6
151#define FLOAT3_RPW 7
152#define FLOAT3_RMF 8
153#define FLOAT3_FML 9
154#define FLOAT3_FDV 10
155#define FLOAT3_FRD 11
156#define FLOAT3_POL 12
157
158struct float2_fmt {
159 unsigned operand2 :3; /* second operand */
160 unsigned immed :1; /* == 1 if second operand is a constant */
161 unsigned pad1 :1; /* == 0 */
162 unsigned rounding :2; /* ROUND_* */
163 unsigned is_double :1; /* == 1 if precision is double (only if not extended) */
164 unsigned pad2 :4; /* == 1 */
165 unsigned dest :3; /* destination */
166 unsigned is_2_op :1; /* == 1 if 2 operand ins */
167 unsigned operand1 :3; /* first operand (only of is_2_op == 0) */
168 unsigned is_extended :1; /* == 1 if precision is extended */
169 unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */
170 unsigned must_be_2 :2; /* == 2 */
171 unsigned type :2; /* == TYPE_SWI */
172 unsigned cond :4; /* COND_* */
173};
174
175struct swi_fmt {
176 unsigned argument :24; /* argument to SWI (syscall number) */
177 unsigned must_be_3 :2; /* == 3 */
178 unsigned type :2; /* == TYPE_SWI */
179 unsigned cond :4; /* one of COND_* defined above */
180};
181
182union insn_fmt {
183 struct generic_fmt generic;
184 struct arith_fmt arith;
185 struct ldr_str_fmt ldr_str;
186 struct block_fmt block;
187 struct branch_fmt branch;
188 struct swi_fmt swi;
189 unsigned long ins;
190};
191
192struct opcode {
193 unsigned long value, mask; /* recognise instruction if (op&mask)==value */
194 char *assembler; /* how to disassemble this instruction */
195};
196
197/* format of the assembler string :
198
199 %% %
200 %<bitfield>d print the bitfield in decimal
201 %<bitfield>x print the bitfield in hex
202 %<bitfield>r print as an ARM register
203 %<bitfield>f print a floating point constant if >7 else an fp register
204 %c print condition code (always bits 28-31)
205 %P print floating point precision in arithmetic insn
206 %Q print floating point precision in ldf/stf insn
207 %R print floating point rounding mode
208 %<bitnum>'c print specified char iff bit is one
209 %<bitnum>`c print specified char iff bit is zero
210 %<bitnum>?ab print a if bit is one else print b
211 %p print 'p' iff bits 12-15 are 15
212 %o print operand2 (immediate or register + shift)
213 %a print address for ldr/str instruction
214 %b print branch destination
215 %A print address for ldc/stc/ldf/stf instruction
216 %m print register mask for ldm/stm instruction
217*/
218
219static struct opcode opcodes[] = {
220 /* ARM instructions */
221 0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r",
222 0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r",
223 0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o",
224 0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o",
225 0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o",
226 0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o",
227 0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o",
228 0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o",
229 0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o",
230 0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o",
231 0x01000000, 0x0de00000, "tst%c%p %16-19r, %o",
232 0x01200000, 0x0de00000, "teq%c%p %16-19r, %o",
233 0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o",
234 0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o",
235 0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o",
236 0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o",
237 0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o",
238 0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o",
239 0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a",
240 0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a",
241 0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m",
242 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^",
243 0x0a000000, 0x0e000000, "b%c%24'l %b",
244 0x0f000000, 0x0f000000, "swi%c %0-23x",
245 /* Floating point coprocessor instructions */
246 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f",
247 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f",
248 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f",
249 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f",
250 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f",
251 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f",
252 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f",
253 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f",
254 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f",
255 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f",
256 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f",
257 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f",
258 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f",
259 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f",
260 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f",
261 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f",
262 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f",
263 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f",
264 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f",
265 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f",
266 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f",
267 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f",
268 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f",
269 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f",
270 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f",
271 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f",
272 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f",
273 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r",
274 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f",
275 0x0e200110, 0x0fff0fff, "wfs%c %12-15r",
276 0x0e300110, 0x0fff0fff, "rfs%c %12-15r",
277 0x0e400110, 0x0fff0fff, "wfc%c %12-15r",
278 0x0e500110, 0x0fff0fff, "rfc%c %12-15r",
279 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f",
280 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f",
281 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f",
282 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f",
283 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A",
284 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A",
285 /* Generic coprocessor instructions */
286 0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}",
287 0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",
288 0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}",
289 0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A",
290 0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A",
291 /* the rest */
292 0x00000000, 0x00000000, "undefined instruction %0-31x",
293};
294#define N_OPCODES (sizeof opcodes / sizeof opcodes[0])
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