source: trunk/src/binutils/opcodes/v850-opc.c@ 610

Last change on this file since 610 was 610, checked in by bird, 22 years ago

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1/* Assemble V850 instructions.
2 Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
3
4This program is free software; you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation; either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program; if not, write to the Free Software
16Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#include "sysdep.h"
19#include "opcode/v850.h"
20#include <stdio.h>
21#include "opintl.h"
22
23/* regular opcode */
24#define OP(x) ((x & 0x3f) << 5)
25#define OP_MASK OP (0x3f)
26
27/* conditional branch opcode */
28#define BOP(x) ((0x0b << 7) | (x & 0x0f))
29#define BOP_MASK ((0x0f << 7) | 0x0f)
30
31/* one-word opcodes */
32#define one(x) ((unsigned int) (x))
33
34/* two-word opcodes */
35#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
36
37static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **));
38static long unsigned extract_d9 PARAMS ((long unsigned, int *));
39static long unsigned insert_d22 PARAMS ((long unsigned, long, const char **));
40static long unsigned extract_d22 PARAMS ((long unsigned, int *));
41static long unsigned insert_d16_15 PARAMS ((long unsigned, long, const char **));
42static long unsigned extract_d16_15 PARAMS ((long unsigned, int *));
43static long unsigned insert_d8_7 PARAMS ((long unsigned, long, const char **));
44static long unsigned extract_d8_7 PARAMS ((long unsigned, int *));
45static long unsigned insert_d8_6 PARAMS ((long unsigned, long, const char **));
46static long unsigned extract_d8_6 PARAMS ((long unsigned, int *));
47static long unsigned insert_d5_4 PARAMS ((long unsigned, long, const char **));
48static long unsigned extract_d5_4 PARAMS ((long unsigned, int *));
49static long unsigned insert_d16_16 PARAMS ((long unsigned, long, const char **));
50static long unsigned extract_d16_16 PARAMS ((long unsigned, int *));
51static long unsigned insert_i9 PARAMS ((long unsigned, long, const char **));
52static long unsigned extract_i9 PARAMS ((long unsigned, int *));
53static long unsigned insert_u9 PARAMS ((long unsigned, long, const char **));
54static long unsigned extract_u9 PARAMS ((long unsigned, int *));
55static long unsigned insert_spe PARAMS ((long unsigned, long, const char **));
56static long unsigned extract_spe PARAMS ((long unsigned, int *));
57static long unsigned insert_i5div PARAMS ((long unsigned, long, const char **));
58static long unsigned extract_i5div PARAMS ((long unsigned, int *));
59
60
61
62/* The functions used to insert and extract complicated operands. */
63
64/* Note: There is a conspiracy between these functions and
65 v850_insert_operand() in gas/config/tc-v850.c. Error messages
66 containing the string 'out of range' will be ignored unless a
67 specific command line option is given to GAS. */
68
69static const char * not_valid = N_ ("displacement value is not in range and is not aligned");
70static const char * out_of_range = N_ ("displacement value is out of range");
71static const char * not_aligned = N_ ("displacement value is not aligned");
72
73static const char * immediate_out_of_range = N_ ("immediate value is out of range");
74
75static unsigned long
76insert_d9 (insn, value, errmsg)
77 unsigned long insn;
78 long value;
79 const char ** errmsg;
80{
81 if (value > 0xff || value < -0x100)
82 {
83 if ((value % 2) != 0)
84 * errmsg = _("branch value not in range and to odd offset");
85 else
86 * errmsg = _("branch value out of range");
87 }
88 else if ((value % 2) != 0)
89 * errmsg = _("branch to odd offset");
90
91 return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3));
92}
93
94static unsigned long
95extract_d9 (insn, invalid)
96 unsigned long insn;
97 int * invalid ATTRIBUTE_UNUSED;
98{
99 unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3);
100
101 if ((insn & 0x8000) != 0)
102 ret -= 0x0200;
103
104 return ret;
105}
106
107static unsigned long
108insert_d22 (insn, value, errmsg)
109 unsigned long insn;
110 long value;
111 const char ** errmsg;
112{
113 if (value > 0x1fffff || value < -0x200000)
114 {
115 if ((value % 2) != 0)
116 * errmsg = _("branch value not in range and to an odd offset");
117 else
118 * errmsg = _("branch value out of range");
119 }
120 else if ((value % 2) != 0)
121 * errmsg = _("branch to odd offset");
122
123 return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16));
124}
125
126static unsigned long
127extract_d22 (insn, invalid)
128 unsigned long insn;
129 int * invalid ATTRIBUTE_UNUSED;
130{
131 signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16);
132
133 return (unsigned long) ((ret << 10) >> 10);
134}
135
136static unsigned long
137insert_d16_15 (insn, value, errmsg)
138 unsigned long insn;
139 long value;
140 const char ** errmsg;
141{
142 if (value > 0x7fff || value < -0x8000)
143 {
144 if ((value % 2) != 0)
145 * errmsg = _(not_valid);
146 else
147 * errmsg = _(out_of_range);
148 }
149 else if ((value % 2) != 0)
150 * errmsg = _(not_aligned);
151
152 return insn | ((value & 0xfffe) << 16);
153}
154
155static unsigned long
156extract_d16_15 (insn, invalid)
157 unsigned long insn;
158 int * invalid ATTRIBUTE_UNUSED;
159{
160 signed long ret = (insn & 0xfffe0000);
161
162 return ret >> 16;
163}
164
165static unsigned long
166insert_d8_7 (insn, value, errmsg)
167 unsigned long insn;
168 long value;
169 const char ** errmsg;
170{
171 if (value > 0xff || value < 0)
172 {
173 if ((value % 2) != 0)
174 * errmsg = _(not_valid);
175 else
176 * errmsg = _(out_of_range);
177 }
178 else if ((value % 2) != 0)
179 * errmsg = _(not_aligned);
180
181 value >>= 1;
182
183 return (insn | (value & 0x7f));
184}
185
186static unsigned long
187extract_d8_7 (insn, invalid)
188 unsigned long insn;
189 int * invalid ATTRIBUTE_UNUSED;
190{
191 unsigned long ret = (insn & 0x7f);
192
193 return ret << 1;
194}
195
196static unsigned long
197insert_d8_6 (insn, value, errmsg)
198 unsigned long insn;
199 long value;
200 const char ** errmsg;
201{
202 if (value > 0xff || value < 0)
203 {
204 if ((value % 4) != 0)
205 *errmsg = _(not_valid);
206 else
207 * errmsg = _(out_of_range);
208 }
209 else if ((value % 4) != 0)
210 * errmsg = _(not_aligned);
211
212 value >>= 1;
213
214 return (insn | (value & 0x7e));
215}
216
217static unsigned long
218extract_d8_6 (insn, invalid)
219 unsigned long insn;
220 int * invalid ATTRIBUTE_UNUSED;
221{
222 unsigned long ret = (insn & 0x7e);
223
224 return ret << 1;
225}
226
227static unsigned long
228insert_d5_4 (insn, value, errmsg)
229 unsigned long insn;
230 long value;
231 const char ** errmsg;
232{
233 if (value > 0x1f || value < 0)
234 {
235 if (value & 1)
236 * errmsg = _(not_valid);
237 else
238 *errmsg = _(out_of_range);
239 }
240 else if (value & 1)
241 * errmsg = _(not_aligned);
242
243 value >>= 1;
244
245 return (insn | (value & 0x0f));
246}
247
248static unsigned long
249extract_d5_4 (insn, invalid)
250 unsigned long insn;
251 int * invalid ATTRIBUTE_UNUSED;
252{
253 unsigned long ret = (insn & 0x0f);
254
255 return ret << 1;
256}
257
258static unsigned long
259insert_d16_16 (insn, value, errmsg)
260 unsigned long insn;
261 signed long value;
262 const char ** errmsg;
263{
264 if (value > 0x7fff || value < -0x8000)
265 * errmsg = _(out_of_range);
266
267 return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5));
268}
269
270static unsigned long
271extract_d16_16 (insn, invalid)
272 unsigned long insn;
273 int * invalid ATTRIBUTE_UNUSED;
274{
275 signed long ret = insn & 0xfffe0000;
276
277 ret >>= 16;
278
279 ret |= ((insn & 0x20) >> 5);
280
281 return ret;
282}
283
284static unsigned long
285insert_i9 (insn, value, errmsg)
286 unsigned long insn;
287 signed long value;
288 const char ** errmsg;
289{
290 if (value > 0xff || value < -0x100)
291 * errmsg = _(immediate_out_of_range);
292
293 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
294}
295
296static unsigned long
297extract_i9 (insn, invalid)
298 unsigned long insn;
299 int * invalid ATTRIBUTE_UNUSED;
300{
301 signed long ret = insn & 0x003c0000;
302
303 ret <<= 10;
304 ret >>= 23;
305
306 ret |= (insn & 0x1f);
307
308 return ret;
309}
310
311static unsigned long
312insert_u9 (insn, v, errmsg)
313 unsigned long insn;
314 long v;
315 const char ** errmsg;
316{
317 unsigned long value = (unsigned long) v;
318 if (value > 0x1ff)
319 * errmsg = _(immediate_out_of_range);
320
321 return insn | ((value & 0x1e0) << 13) | (value & 0x1f);
322}
323
324static unsigned long
325extract_u9 (insn, invalid)
326 unsigned long insn;
327 int * invalid ATTRIBUTE_UNUSED;
328{
329 unsigned long ret = insn & 0x003c0000;
330
331 ret >>= 13;
332
333 ret |= (insn & 0x1f);
334
335 return ret;
336}
337
338static unsigned long
339insert_spe (insn, v, errmsg)
340 unsigned long insn;
341 long v;
342 const char ** errmsg;
343{
344 unsigned long value = (unsigned long) v;
345
346 if (value != 3)
347 * errmsg = _("invalid register for stack adjustment");
348
349 return insn & (~ 0x180000);
350}
351
352static unsigned long
353extract_spe (insn, invalid)
354 unsigned long insn ATTRIBUTE_UNUSED;
355 int * invalid ATTRIBUTE_UNUSED;
356{
357 return 3;
358}
359
360static unsigned long
361insert_i5div (insn, v, errmsg)
362 unsigned long insn;
363 long v;
364 const char ** errmsg;
365{
366 unsigned long value = (unsigned long) v;
367
368 if (value > 0x1ff)
369 {
370 if (value & 1)
371 * errmsg = _("immediate value not in range and not even");
372 else
373 * errmsg = _(immediate_out_of_range);
374 }
375 else if (value & 1)
376 * errmsg = _("immediate value must be even");
377
378 value = 32 - value;
379
380 return insn | ((value & 0x1e) << 17);
381}
382
383static unsigned long
384extract_i5div (insn, invalid)
385 unsigned long insn;
386 int * invalid ATTRIBUTE_UNUSED;
387{
388 unsigned long ret = insn & 0x3c0000;
389
390 ret >>= 17;
391
392 ret = 32 - ret;
393
394 return ret;
395}
396
397
398
399/* Warning: code in gas/config/tc-v850.c examines the contents of this array.
400 If you change any of the values here, be sure to look for side effects in
401 that code. */
402const struct v850_operand v850_operands[] =
403{
404#define UNUSED 0
405 { 0, 0, NULL, NULL, 0 },
406
407/* The R1 field in a format 1, 6, 7, or 9 insn. */
408#define R1 (UNUSED + 1)
409 { 5, 0, NULL, NULL, V850_OPERAND_REG },
410
411/* As above, but register 0 is not allowed. */
412#define R1_NOTR0 (R1 + 1)
413 { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
414
415/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
416#define R2 (R1_NOTR0 + 1)
417 { 5, 11, NULL, NULL, V850_OPERAND_REG },
418
419/* As above, but register 0 is not allowed. */
420#define R2_NOTR0 (R2 + 1)
421 { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
422
423/* The imm5 field in a format 2 insn. */
424#define I5 (R2_NOTR0 + 1)
425 { 5, 0, NULL, NULL, V850_OPERAND_SIGNED },
426
427/* The unsigned imm5 field in a format 2 insn. */
428#define I5U (I5 + 1)
429 { 5, 0, NULL, NULL, 0 },
430
431/* The imm16 field in a format 6 insn. */
432#define I16 (I5U + 1)
433 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
434
435/* The signed disp7 field in a format 4 insn. */
436#define D7 (I16 + 1)
437 { 7, 0, NULL, NULL, 0},
438
439/* The disp16 field in a format 6 insn. */
440#define D16_15 (D7 + 1)
441 { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
442
443/* The 3 bit immediate field in format 8 insn. */
444#define B3 (D16_15 + 1)
445 { 3, 11, NULL, NULL, 0 },
446
447/* The 4 bit condition code in a setf instruction */
448#define CCCC (B3 + 1)
449 { 4, 0, NULL, NULL, V850_OPERAND_CC },
450
451/* The unsigned DISP8 field in a format 4 insn. */
452#define D8_7 (CCCC + 1)
453 { 7, 0, insert_d8_7, extract_d8_7, 0 },
454
455/* The unsigned DISP8 field in a format 4 insn. */
456#define D8_6 (D8_7 + 1)
457 { 6, 1, insert_d8_6, extract_d8_6, 0 },
458
459/* System register operands. */
460#define SR1 (D8_6 + 1)
461 { 5, 0, NULL, NULL, V850_OPERAND_SRG },
462
463/* EP Register. */
464#define EP (SR1 + 1)
465 { 0, 0, NULL, NULL, V850_OPERAND_EP },
466
467/* The imm16 field (unsigned) in a format 6 insn. */
468#define I16U (EP + 1)
469 { 16, 16, NULL, NULL, 0},
470
471/* The R2 field as a system register. */
472#define SR2 (I16U + 1)
473 { 5, 11, NULL, NULL, V850_OPERAND_SRG },
474
475/* The disp16 field in a format 8 insn. */
476#define D16 (SR2 + 1)
477 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
478
479/* The DISP9 field in a format 3 insn, relaxable. */
480#define D9_RELAX (D16 + 1)
481 { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
482
483/* The DISP22 field in a format 4 insn, relaxable.
484 This _must_ follow D9_RELAX; the assembler assumes that the longer
485 version immediately follows the shorter version for relaxing. */
486#define D22 (D9_RELAX + 1)
487 { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
488
489/* The signed disp4 field in a format 4 insn. */
490#define D4 (D22 + 1)
491 { 4, 0, NULL, NULL, 0},
492
493/* The unsigned disp5 field in a format 4 insn. */
494#define D5_4 (D4 + 1)
495 { 4, 0, insert_d5_4, extract_d5_4, 0 },
496
497/* The disp16 field in an format 7 unsigned byte load insn. */
498#define D16_16 (D5_4 + 1)
499 { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 },
500
501/* Third register in conditional moves. */
502#define R3 (D16_16 + 1)
503 { 5, 27, NULL, NULL, V850_OPERAND_REG },
504
505/* Condition code in conditional moves. */
506#define MOVCC (R3 + 1)
507 { 4, 17, NULL, NULL, V850_OPERAND_CC },
508
509/* The imm9 field in a multiply word. */
510#define I9 (MOVCC + 1)
511 { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED },
512
513/* The unsigned imm9 field in a multiply word. */
514#define U9 (I9 + 1)
515 { 9, 0, insert_u9, extract_u9, 0 },
516
517/* A list of registers in a prepare/dispose instruction. */
518#define LIST12 (U9 + 1)
519 { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP },
520
521/* The IMM6 field in a call instruction. */
522#define I6 (LIST12 + 1)
523 { 6, 0, NULL, NULL, 0 },
524
525/* The 16 bit immediate following a 32 bit instruction. */
526#define IMM16 (I6 + 1)
527 { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 },
528
529/* The 32 bit immediate following a 32 bit instruction. */
530#define IMM32 (IMM16 + 1)
531 { 0, 0, NULL, NULL, V850E_IMMEDIATE32 },
532
533/* The imm5 field in a push/pop instruction. */
534#define IMM5 (IMM32 + 1)
535 { 5, 1, NULL, NULL, 0 },
536
537/* Reg2 in dispose instruction. */
538#define R2DISPOSE (IMM5 + 1)
539 { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
540
541/* Stack pointer in prepare instruction. */
542#define SP (R2DISPOSE + 1)
543 { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG },
544
545/* The IMM5 field in a divide N step instruction. */
546#define I5DIV (SP + 1)
547 { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED },
548
549 /* The list of registers in a PUSHMH/POPMH instruction. */
550#define LIST18_H (I5DIV + 1)
551 { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP },
552
553 /* The list of registers in a PUSHML/POPML instruction. */
554#define LIST18_L (LIST18_H + 1)
555 { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */
556} ;
557
558
559
560/* reg-reg instruction format (Format I) */
561#define IF1 {R1, R2}
562
563/* imm-reg instruction format (Format II) */
564#define IF2 {I5, R2}
565
566/* conditional branch instruction format (Format III) */
567#define IF3 {D9_RELAX}
568
569/* 3 operand instruction (Format VI) */
570#define IF6 {I16, R1, R2}
571
572/* 3 operand instruction (Format VI) */
573#define IF6U {I16U, R1, R2}
574
575
576
577
578/* The opcode table.
579
580 The format of the opcode table is:
581
582 NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR
583
584 NAME is the name of the instruction.
585 OPCODE is the instruction opcode.
586 MASK is the opcode mask; this is used to tell the disassembler
587 which bits in the actual opcode must match OPCODE.
588 OPERANDS is the list of operands.
589 MEMOP specifies which operand (if any) is a memory operand.
590 PROCESSORS specifies which CPU(s) support the opcode.
591
592 The disassembler reads the table in order and prints the first
593 instruction which matches, so this table is sorted to put more
594 specific instructions before more general instructions. It is also
595 sorted by major opcode.
596
597 The table is also sorted by name. This is used by the assembler.
598 When parsing an instruction the assembler finds the first occurance
599 of the name of the instruciton in this table and then attempts to
600 match the instruction's arguments with description of the operands
601 associated with the entry it has just found in this table. If the
602 match fails the assembler looks at the next entry in this table.
603 If that entry has the same name as the previous entry, then it
604 tries to match the instruction against that entry and so on. This
605 is how the assembler copes with multiple, different formats of the
606 same instruction. */
607
608const struct v850_opcode v850_opcodes[] =
609{
610{ "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL },
611
612{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL },
613
614/* load/store instructions */
615{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E },
616
617{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E },
618
619{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E },
620{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 },
621
622{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E },
623{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 },
624{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL },
625{ "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL },
626{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL },
627{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL },
628
629{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 },
630{ "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 },
631{ "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 },
632{ "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 },
633{ "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 },
634{ "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 },
635{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 },
636
637{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL },
638{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL },
639{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL },
640{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 },
641{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 },
642{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL },
643{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL },
644{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL },
645
646/* byte swap/extend instructions */
647{ "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
648{ "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
649{ "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
650{ "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
651{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
652{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
653{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
654
655/* jump table instructions */
656{ "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 },
657{ "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 },
658{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
659
660/* arithmetic operation instructions */
661{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL },
662{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
663{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
664
665{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
666{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 },
667{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
668{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 },
669
670{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
671{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
672{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
673{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
674{ "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
675
676{ "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL },
677{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
678{ "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
679{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
680{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
681{ "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
682{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL },
683{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL },
684{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL },
685{ "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL },
686{ "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL },
687{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
688{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
689{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
690{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL },
691{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL },
692
693/* saturated operation instructions */
694{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
695{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
696{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
697{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
698{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
699
700/* logical operation instructions */
701{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL },
702{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL },
703{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL },
704{ "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL },
705{ "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL },
706{ "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL },
707{ "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL },
708{ "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL },
709{ "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
710{ "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
711{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
712{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
713{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL },
714{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
715{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 },
716
717/* branch instructions */
718 /* signed integer */
719{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
720{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
721{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
722{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
723 /* unsigned integer */
724{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
725{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
726{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
727{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
728 /* common */
729{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
730{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
731 /* others */
732{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
733{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
734{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
735{ "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
736{ "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
737{ "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
738{ "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
739{ "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
740{ "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
741{ "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
742
743/* Branch macros.
744
745 We use the short form in the opcode/mask fields. The assembler
746 will twiddle bits as necessary if the long form is needed. */
747
748 /* signed integer */
749{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
750{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
751{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
752{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
753 /* unsigned integer */
754{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
755{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
756{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
757{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
758 /* common */
759{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
760{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
761 /* others */
762{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
763{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
764{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
765{ "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL },
766{ "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
767{ "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
768{ "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
769{ "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
770{ "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL },
771{ "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL },
772
773{ "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL },
774{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL},
775
776/* bit manipulation instructions */
777{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
778{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
779{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
780{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
781{ "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
782{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
783{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
784{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
785
786/* special instructions */
787{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
788{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
789{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
790{ "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
791{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL },
792{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL },
793{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL },
794{ 0, 0, 0, {0}, 0, 0 },
795
796} ;
797
798const int v850_num_opcodes =
799 sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
800
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