source: trunk/src/binutils/opcodes/ppc-opc.c@ 144

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1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
112, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING. If not, write to the Free
20Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2102111-1307, USA. */
22
23#include <stdio.h>
24#include "sysdep.h"
25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38
39
40/* Local insertion and extraction functions. */
41
42static unsigned long insert_bat PARAMS ((unsigned long, long, const char **));
43static long extract_bat PARAMS ((unsigned long, int *));
44static unsigned long insert_bba PARAMS ((unsigned long, long, const char **));
45static long extract_bba PARAMS ((unsigned long, int *));
46static unsigned long insert_bd PARAMS ((unsigned long, long, const char **));
47static long extract_bd PARAMS ((unsigned long, int *));
48static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **));
49static long extract_bdm PARAMS ((unsigned long, int *));
50static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **));
51static long extract_bdp PARAMS ((unsigned long, int *));
52static int valid_bo PARAMS ((long));
53static unsigned long insert_bo PARAMS ((unsigned long, long, const char **));
54static long extract_bo PARAMS ((unsigned long, int *));
55static unsigned long insert_boe PARAMS ((unsigned long, long, const char **));
56static long extract_boe PARAMS ((unsigned long, int *));
57static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
58static long extract_ds PARAMS ((unsigned long, int *));
59static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
60static long extract_li PARAMS ((unsigned long, int *));
61static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
62static long extract_mbe PARAMS ((unsigned long, int *));
63static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **));
64static long extract_mb6 PARAMS ((unsigned long, int *));
65static unsigned long insert_nb PARAMS ((unsigned long, long, const char **));
66static long extract_nb PARAMS ((unsigned long, int *));
67static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **));
68static long extract_nsi PARAMS ((unsigned long, int *));
69static unsigned long insert_ral PARAMS ((unsigned long, long, const char **));
70static unsigned long insert_ram PARAMS ((unsigned long, long, const char **));
71static unsigned long insert_ras PARAMS ((unsigned long, long, const char **));
72static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **));
73static long extract_rbs PARAMS ((unsigned long, int *));
74static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **));
75static long extract_sh6 PARAMS ((unsigned long, int *));
76static unsigned long insert_spr PARAMS ((unsigned long, long, const char **));
77static long extract_spr PARAMS ((unsigned long, int *));
78static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **));
79static long extract_tbr PARAMS ((unsigned long, int *));
80
81
82/* The operands table.
83
84 The fields are bits, shift, insert, extract, flags.
85
86 We used to put parens around the various additions, like the one
87 for BA just below. However, that caused trouble with feeble
88 compilers with a limit on depth of a parenthesized expression, like
89 (reportedly) the compiler in Microsoft Developer Studio 5. So we
90 omit the parens, since the macros are never used in a context where
91 the addition will be ambiguous. */
92
93const struct powerpc_operand powerpc_operands[] =
94{
95 /* The zero index is used to indicate the end of the list of
96 operands. */
97#define UNUSED 0
98 { 0, 0, 0, 0, 0 },
99
100 /* The BA field in an XL form instruction. */
101#define BA UNUSED + 1
102#define BA_MASK (0x1f << 16)
103 { 5, 16, 0, 0, PPC_OPERAND_CR },
104
105 /* The BA field in an XL form instruction when it must be the same
106 as the BT field in the same instruction. */
107#define BAT BA + 1
108 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
109
110 /* The BB field in an XL form instruction. */
111#define BB BAT + 1
112#define BB_MASK (0x1f << 11)
113 { 5, 11, 0, 0, PPC_OPERAND_CR },
114
115 /* The BB field in an XL form instruction when it must be the same
116 as the BA field in the same instruction. */
117#define BBA BB + 1
118 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
119
120 /* The BD field in a B form instruction. The lower two bits are
121 forced to zero. */
122#define BD BBA + 1
123 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
124
125 /* The BD field in a B form instruction when absolute addressing is
126 used. */
127#define BDA BD + 1
128 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
129
130 /* The BD field in a B form instruction when the - modifier is used.
131 This sets the y bit of the BO field appropriately. */
132#define BDM BDA + 1
133 { 16, 0, insert_bdm, extract_bdm,
134 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
135
136 /* The BD field in a B form instruction when the - modifier is used
137 and absolute address is used. */
138#define BDMA BDM + 1
139 { 16, 0, insert_bdm, extract_bdm,
140 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
141
142 /* The BD field in a B form instruction when the + modifier is used.
143 This sets the y bit of the BO field appropriately. */
144#define BDP BDMA + 1
145 { 16, 0, insert_bdp, extract_bdp,
146 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
147
148 /* The BD field in a B form instruction when the + modifier is used
149 and absolute addressing is used. */
150#define BDPA BDP + 1
151 { 16, 0, insert_bdp, extract_bdp,
152 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
153
154 /* The BF field in an X or XL form instruction. */
155#define BF BDPA + 1
156 { 3, 23, 0, 0, PPC_OPERAND_CR },
157
158 /* An optional BF field. This is used for comparison instructions,
159 in which an omitted BF field is taken as zero. */
160#define OBF BF + 1
161 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
162
163 /* The BFA field in an X or XL form instruction. */
164#define BFA OBF + 1
165 { 3, 18, 0, 0, PPC_OPERAND_CR },
166
167 /* The BI field in a B form or XL form instruction. */
168#define BI BFA + 1
169#define BI_MASK (0x1f << 16)
170 { 5, 16, 0, 0, PPC_OPERAND_CR },
171
172 /* The BO field in a B form instruction. Certain values are
173 illegal. */
174#define BO BI + 1
175#define BO_MASK (0x1f << 21)
176 { 5, 21, insert_bo, extract_bo, 0 },
177
178 /* The BO field in a B form instruction when the + or - modifier is
179 used. This is like the BO field, but it must be even. */
180#define BOE BO + 1
181 { 5, 21, insert_boe, extract_boe, 0 },
182
183 /* The BT field in an X or XL form instruction. */
184#define BT BOE + 1
185 { 5, 21, 0, 0, PPC_OPERAND_CR },
186
187 /* The condition register number portion of the BI field in a B form
188 or XL form instruction. This is used for the extended
189 conditional branch mnemonics, which set the lower two bits of the
190 BI field. This field is optional. */
191#define CR BT + 1
192 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
193
194 /* The D field in a D form instruction. This is a displacement off
195 a register, and implies that the next operand is a register in
196 parentheses. */
197#define D CR + 1
198 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
199
200 /* The DS field in a DS form instruction. This is like D, but the
201 lower two bits are forced to zero. */
202#define DS D + 1
203 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
204
205 /* The E field in a wrteei instruction. */
206#define E DS + 1
207 { 1, 15, 0, 0, 0 },
208
209 /* The FL1 field in a POWER SC form instruction. */
210#define FL1 E + 1
211 { 4, 12, 0, 0, 0 },
212
213 /* The FL2 field in a POWER SC form instruction. */
214#define FL2 FL1 + 1
215 { 3, 2, 0, 0, 0 },
216
217 /* The FLM field in an XFL form instruction. */
218#define FLM FL2 + 1
219 { 8, 17, 0, 0, 0 },
220
221 /* The FRA field in an X or A form instruction. */
222#define FRA FLM + 1
223#define FRA_MASK (0x1f << 16)
224 { 5, 16, 0, 0, PPC_OPERAND_FPR },
225
226 /* The FRB field in an X or A form instruction. */
227#define FRB FRA + 1
228#define FRB_MASK (0x1f << 11)
229 { 5, 11, 0, 0, PPC_OPERAND_FPR },
230
231 /* The FRC field in an A form instruction. */
232#define FRC FRB + 1
233#define FRC_MASK (0x1f << 6)
234 { 5, 6, 0, 0, PPC_OPERAND_FPR },
235
236 /* The FRS field in an X form instruction or the FRT field in a D, X
237 or A form instruction. */
238#define FRS FRC + 1
239#define FRT FRS
240 { 5, 21, 0, 0, PPC_OPERAND_FPR },
241
242 /* The FXM field in an XFX instruction. */
243#define FXM FRS + 1
244#define FXM_MASK (0xff << 12)
245 { 8, 12, 0, 0, 0 },
246
247 /* The L field in a D or X form instruction. */
248#define L FXM + 1
249 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
250
251 /* The LEV field in a POWER SC form instruction. */
252#define LEV L + 1
253 { 7, 5, 0, 0, 0 },
254
255 /* The LI field in an I form instruction. The lower two bits are
256 forced to zero. */
257#define LI LEV + 1
258 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
259
260 /* The LI field in an I form instruction when used as an absolute
261 address. */
262#define LIA LI + 1
263 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
264
265 /* The MB field in an M form instruction. */
266#define MB LIA + 1
267#define MB_MASK (0x1f << 6)
268 { 5, 6, 0, 0, 0 },
269
270 /* The ME field in an M form instruction. */
271#define ME MB + 1
272#define ME_MASK (0x1f << 1)
273 { 5, 1, 0, 0, 0 },
274
275 /* The MB and ME fields in an M form instruction expressed a single
276 operand which is a bitmask indicating which bits to select. This
277 is a two operand form using PPC_OPERAND_NEXT. See the
278 description in opcode/ppc.h for what this means. */
279#define MBE ME + 1
280 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
281 { 32, 0, insert_mbe, extract_mbe, 0 },
282
283 /* The MB or ME field in an MD or MDS form instruction. The high
284 bit is wrapped to the low end. */
285#define MB6 MBE + 2
286#define ME6 MB6
287#define MB6_MASK (0x3f << 5)
288 { 6, 5, insert_mb6, extract_mb6, 0 },
289
290 /* The NB field in an X form instruction. The value 32 is stored as
291 0. */
292#define NB MB6 + 1
293 { 6, 11, insert_nb, extract_nb, 0 },
294
295 /* The NSI field in a D form instruction. This is the same as the
296 SI field, only negated. */
297#define NSI NB + 1
298 { 16, 0, insert_nsi, extract_nsi,
299 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
300
301 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
302#define RA NSI + 1
303#define RA_MASK (0x1f << 16)
304 { 5, 16, 0, 0, PPC_OPERAND_GPR },
305
306 /* The RA field in a D or X form instruction which is an updating
307 load, which means that the RA field may not be zero and may not
308 equal the RT field. */
309#define RAL RA + 1
310 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
311
312 /* The RA field in an lmw instruction, which has special value
313 restrictions. */
314#define RAM RAL + 1
315 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
316
317 /* The RA field in a D or X form instruction which is an updating
318 store or an updating floating point load, which means that the RA
319 field may not be zero. */
320#define RAS RAM + 1
321 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
322
323 /* The RB field in an X, XO, M, or MDS form instruction. */
324#define RB RAS + 1
325#define RB_MASK (0x1f << 11)
326 { 5, 11, 0, 0, PPC_OPERAND_GPR },
327
328 /* The RB field in an X form instruction when it must be the same as
329 the RS field in the instruction. This is used for extended
330 mnemonics like mr. */
331#define RBS RB + 1
332 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
333
334 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
335 instruction or the RT field in a D, DS, X, XFX or XO form
336 instruction. */
337#define RS RBS + 1
338#define RT RS
339#define RT_MASK (0x1f << 21)
340 { 5, 21, 0, 0, PPC_OPERAND_GPR },
341
342 /* The SH field in an X or M form instruction. */
343#define SH RS + 1
344#define SH_MASK (0x1f << 11)
345 { 5, 11, 0, 0, 0 },
346
347 /* The SH field in an MD form instruction. This is split. */
348#define SH6 SH + 1
349#define SH6_MASK ((0x1f << 11) | (1 << 1))
350 { 6, 1, insert_sh6, extract_sh6, 0 },
351
352 /* The SI field in a D form instruction. */
353#define SI SH6 + 1
354 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
355
356 /* The SI field in a D form instruction when we accept a wide range
357 of positive values. */
358#define SISIGNOPT SI + 1
359 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
360
361 /* The SPR field in an XFX form instruction. This is flipped--the
362 lower 5 bits are stored in the upper 5 and vice- versa. */
363#define SPR SISIGNOPT + 1
364#define SPR_MASK (0x3ff << 11)
365 { 10, 11, insert_spr, extract_spr, 0 },
366
367 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
368#define SPRBAT SPR + 1
369#define SPRBAT_MASK (0x3 << 17)
370 { 2, 17, 0, 0, 0 },
371
372 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
373#define SPRG SPRBAT + 1
374#define SPRG_MASK (0x3 << 16)
375 { 2, 16, 0, 0, 0 },
376
377 /* The SR field in an X form instruction. */
378#define SR SPRG + 1
379 { 4, 16, 0, 0, 0 },
380
381 /* The SV field in a POWER SC form instruction. */
382#define SV SR + 1
383 { 14, 2, 0, 0, 0 },
384
385 /* The TBR field in an XFX form instruction. This is like the SPR
386 field, but it is optional. */
387#define TBR SV + 1
388 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
389
390 /* The TO field in a D or X form instruction. */
391#define TO TBR + 1
392#define TO_MASK (0x1f << 21)
393 { 5, 21, 0, 0, 0 },
394
395 /* The U field in an X form instruction. */
396#define U TO + 1
397 { 4, 12, 0, 0, 0 },
398
399 /* The UI field in a D form instruction. */
400#define UI U + 1
401 { 16, 0, 0, 0, 0 },
402
403 /* The VA field in a VA, VX or VXR form instruction. */
404#define VA UI + 1
405#define VA_MASK (0x1f << 16)
406 {5, 16, 0, 0, PPC_OPERAND_VR},
407
408 /* The VB field in a VA, VX or VXR form instruction. */
409#define VB VA + 1
410#define VB_MASK (0x1f << 11)
411 {5, 11, 0, 0, PPC_OPERAND_VR},
412
413 /* The VC field in a VA form instruction. */
414#define VC VB + 1
415#define VC_MASK (0x1f << 6)
416 {5, 6, 0, 0, PPC_OPERAND_VR},
417
418 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
419#define VD VC + 1
420#define VS VD
421#define VD_MASK (0x1f << 21)
422 {5, 21, 0, 0, PPC_OPERAND_VR},
423
424 /* The SIMM field in a VX form instruction. */
425#define SIMM VD + 1
426 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
427
428 /* The UIMM field in a VX form instruction. */
429#define UIMM SIMM + 1
430 { 5, 16, 0, 0, 0 },
431
432 /* The SHB field in a VA form instruction. */
433#define SHB UIMM + 1
434 { 4, 6, 0, 0, 0 },
435};
436
437/* The functions used to insert and extract complicated operands. */
438
439/* The BA field in an XL form instruction when it must be the same as
440 the BT field in the same instruction. This operand is marked FAKE.
441 The insertion function just copies the BT field into the BA field,
442 and the extraction function just checks that the fields are the
443 same. */
444
445/*ARGSUSED*/
446static unsigned long
447insert_bat (insn, value, errmsg)
448 unsigned long insn;
449 long value ATTRIBUTE_UNUSED;
450 const char **errmsg ATTRIBUTE_UNUSED;
451{
452 return insn | (((insn >> 21) & 0x1f) << 16);
453}
454
455static long
456extract_bat (insn, invalid)
457 unsigned long insn;
458 int *invalid;
459{
460 if (invalid != (int *) NULL
461 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
462 *invalid = 1;
463 return 0;
464}
465
466/* The BB field in an XL form instruction when it must be the same as
467 the BA field in the same instruction. This operand is marked FAKE.
468 The insertion function just copies the BA field into the BB field,
469 and the extraction function just checks that the fields are the
470 same. */
471
472/*ARGSUSED*/
473static unsigned long
474insert_bba (insn, value, errmsg)
475 unsigned long insn;
476 long value ATTRIBUTE_UNUSED;
477 const char **errmsg ATTRIBUTE_UNUSED;
478{
479 return insn | (((insn >> 16) & 0x1f) << 11);
480}
481
482static long
483extract_bba (insn, invalid)
484 unsigned long insn;
485 int *invalid;
486{
487 if (invalid != (int *) NULL
488 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
489 *invalid = 1;
490 return 0;
491}
492
493/* The BD field in a B form instruction. The lower two bits are
494 forced to zero. */
495
496/*ARGSUSED*/
497static unsigned long
498insert_bd (insn, value, errmsg)
499 unsigned long insn;
500 long value;
501 const char **errmsg ATTRIBUTE_UNUSED;
502{
503 return insn | (value & 0xfffc);
504}
505
506/*ARGSUSED*/
507static long
508extract_bd (insn, invalid)
509 unsigned long insn;
510 int *invalid ATTRIBUTE_UNUSED;
511{
512 if ((insn & 0x8000) != 0)
513 return (insn & 0xfffc) - 0x10000;
514 else
515 return insn & 0xfffc;
516}
517
518/* The BD field in a B form instruction when the - modifier is used.
519 This modifier means that the branch is not expected to be taken.
520 We must set the y bit of the BO field to 1 if the offset is
521 negative. When extracting, we require that the y bit be 1 and that
522 the offset be positive, since if the y bit is 0 we just want to
523 print the normal form of the instruction. */
524
525/*ARGSUSED*/
526static unsigned long
527insert_bdm (insn, value, errmsg)
528 unsigned long insn;
529 long value;
530 const char **errmsg ATTRIBUTE_UNUSED;
531{
532 if ((value & 0x8000) != 0)
533 insn |= 1 << 21;
534 return insn | (value & 0xfffc);
535}
536
537static long
538extract_bdm (insn, invalid)
539 unsigned long insn;
540 int *invalid;
541{
542 if (invalid != (int *) NULL
543 && ((insn & (1 << 21)) == 0
544 || (insn & (1 << 15)) == 0))
545 *invalid = 1;
546 if ((insn & 0x8000) != 0)
547 return (insn & 0xfffc) - 0x10000;
548 else
549 return insn & 0xfffc;
550}
551
552/* The BD field in a B form instruction when the + modifier is used.
553 This is like BDM, above, except that the branch is expected to be
554 taken. */
555
556/*ARGSUSED*/
557static unsigned long
558insert_bdp (insn, value, errmsg)
559 unsigned long insn;
560 long value;
561 const char **errmsg ATTRIBUTE_UNUSED;
562{
563 if ((value & 0x8000) == 0)
564 insn |= 1 << 21;
565 return insn | (value & 0xfffc);
566}
567
568static long
569extract_bdp (insn, invalid)
570 unsigned long insn;
571 int *invalid;
572{
573 if (invalid != (int *) NULL
574 && ((insn & (1 << 21)) == 0
575 || (insn & (1 << 15)) != 0))
576 *invalid = 1;
577 if ((insn & 0x8000) != 0)
578 return (insn & 0xfffc) - 0x10000;
579 else
580 return insn & 0xfffc;
581}
582
583/* Check for legal values of a BO field. */
584
585static int
586valid_bo (value)
587 long value;
588{
589 /* Certain encodings have bits that are required to be zero. These
590 are (z must be zero, y may be anything):
591 001zy
592 011zy
593 1z00y
594 1z01y
595 1z1zz
596 */
597 switch (value & 0x14)
598 {
599 default:
600 case 0:
601 return 1;
602 case 0x4:
603 return (value & 0x2) == 0;
604 case 0x10:
605 return (value & 0x8) == 0;
606 case 0x14:
607 return value == 0x14;
608 }
609}
610
611/* The BO field in a B form instruction. Warn about attempts to set
612 the field to an illegal value. */
613
614static unsigned long
615insert_bo (insn, value, errmsg)
616 unsigned long insn;
617 long value;
618 const char **errmsg;
619{
620 if (errmsg != (const char **) NULL
621 && ! valid_bo (value))
622 *errmsg = _("invalid conditional option");
623 return insn | ((value & 0x1f) << 21);
624}
625
626static long
627extract_bo (insn, invalid)
628 unsigned long insn;
629 int *invalid;
630{
631 long value;
632
633 value = (insn >> 21) & 0x1f;
634 if (invalid != (int *) NULL
635 && ! valid_bo (value))
636 *invalid = 1;
637 return value;
638}
639
640/* The BO field in a B form instruction when the + or - modifier is
641 used. This is like the BO field, but it must be even. When
642 extracting it, we force it to be even. */
643
644static unsigned long
645insert_boe (insn, value, errmsg)
646 unsigned long insn;
647 long value;
648 const char **errmsg;
649{
650 if (errmsg != (const char **) NULL)
651 {
652 if (! valid_bo (value))
653 *errmsg = _("invalid conditional option");
654 else if ((value & 1) != 0)
655 *errmsg = _("attempt to set y bit when using + or - modifier");
656 }
657 return insn | ((value & 0x1f) << 21);
658}
659
660static long
661extract_boe (insn, invalid)
662 unsigned long insn;
663 int *invalid;
664{
665 long value;
666
667 value = (insn >> 21) & 0x1f;
668 if (invalid != (int *) NULL
669 && ! valid_bo (value))
670 *invalid = 1;
671 return value & 0x1e;
672}
673
674/* The DS field in a DS form instruction. This is like D, but the
675 lower two bits are forced to zero. */
676
677/*ARGSUSED*/
678static unsigned long
679insert_ds (insn, value, errmsg)
680 unsigned long insn;
681 long value;
682 const char **errmsg ATTRIBUTE_UNUSED;
683{
684 return insn | (value & 0xfffc);
685}
686
687/*ARGSUSED*/
688static long
689extract_ds (insn, invalid)
690 unsigned long insn;
691 int *invalid ATTRIBUTE_UNUSED;
692{
693 if ((insn & 0x8000) != 0)
694 return (insn & 0xfffc) - 0x10000;
695 else
696 return insn & 0xfffc;
697}
698
699/* The LI field in an I form instruction. The lower two bits are
700 forced to zero. */
701
702/*ARGSUSED*/
703static unsigned long
704insert_li (insn, value, errmsg)
705 unsigned long insn;
706 long value;
707 const char **errmsg;
708{
709 if ((value & 3) != 0 && errmsg != (const char **) NULL)
710 *errmsg = _("ignoring least significant bits in branch offset");
711 return insn | (value & 0x3fffffc);
712}
713
714/*ARGSUSED*/
715static long
716extract_li (insn, invalid)
717 unsigned long insn;
718 int *invalid ATTRIBUTE_UNUSED;
719{
720 if ((insn & 0x2000000) != 0)
721 return (insn & 0x3fffffc) - 0x4000000;
722 else
723 return insn & 0x3fffffc;
724}
725
726/* The MB and ME fields in an M form instruction expressed as a single
727 operand which is itself a bitmask. The extraction function always
728 marks it as invalid, since we never want to recognize an
729 instruction which uses a field of this type. */
730
731static unsigned long
732insert_mbe (insn, value, errmsg)
733 unsigned long insn;
734 long value;
735 const char **errmsg;
736{
737 unsigned long uval, mask;
738 int mb, me, mx, count, last;
739
740 uval = value;
741
742 if (uval == 0)
743 {
744 if (errmsg != (const char **) NULL)
745 *errmsg = _("illegal bitmask");
746 return insn;
747 }
748
749 mb = 0;
750 me = 32;
751 if ((uval & 1) != 0)
752 last = 1;
753 else
754 last = 0;
755 count = 0;
756
757 /* mb: location of last 0->1 transition */
758 /* me: location of last 1->0 transition */
759 /* count: # transitions */
760
761 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
762 {
763 if ((uval & mask) && !last)
764 {
765 ++count;
766 mb = mx;
767 last = 1;
768 }
769 else if (!(uval & mask) && last)
770 {
771 ++count;
772 me = mx;
773 last = 0;
774 }
775 }
776 if (me == 0)
777 me = 32;
778
779 if (count != 2 && (count != 0 || ! last))
780 {
781 if (errmsg != (const char **) NULL)
782 *errmsg = _("illegal bitmask");
783 }
784
785 return insn | (mb << 6) | ((me - 1) << 1);
786}
787
788static long
789extract_mbe (insn, invalid)
790 unsigned long insn;
791 int *invalid;
792{
793 long ret;
794 int mb, me;
795 int i;
796
797 if (invalid != (int *) NULL)
798 *invalid = 1;
799
800 mb = (insn >> 6) & 0x1f;
801 me = (insn >> 1) & 0x1f;
802 if (mb < me + 1)
803 {
804 ret = 0;
805 for (i = mb; i <= me; i++)
806 ret |= (long) 1 << (31 - i);
807 }
808 else if (mb == me + 1)
809 ret = ~0;
810 else /* (mb > me + 1) */
811 {
812 ret = ~ (long) 0;
813 for (i = me + 1; i < mb; i++)
814 ret &= ~ ((long) 1 << (31 - i));
815 }
816 return ret;
817}
818
819/* The MB or ME field in an MD or MDS form instruction. The high bit
820 is wrapped to the low end. */
821
822/*ARGSUSED*/
823static unsigned long
824insert_mb6 (insn, value, errmsg)
825 unsigned long insn;
826 long value;
827 const char **errmsg ATTRIBUTE_UNUSED;
828{
829 return insn | ((value & 0x1f) << 6) | (value & 0x20);
830}
831
832/*ARGSUSED*/
833static long
834extract_mb6 (insn, invalid)
835 unsigned long insn;
836 int *invalid ATTRIBUTE_UNUSED;
837{
838 return ((insn >> 6) & 0x1f) | (insn & 0x20);
839}
840
841/* The NB field in an X form instruction. The value 32 is stored as
842 0. */
843
844static unsigned long
845insert_nb (insn, value, errmsg)
846 unsigned long insn;
847 long value;
848 const char **errmsg;
849{
850 if (value < 0 || value > 32)
851 *errmsg = _("value out of range");
852 if (value == 32)
853 value = 0;
854 return insn | ((value & 0x1f) << 11);
855}
856
857/*ARGSUSED*/
858static long
859extract_nb (insn, invalid)
860 unsigned long insn;
861 int *invalid ATTRIBUTE_UNUSED;
862{
863 long ret;
864
865 ret = (insn >> 11) & 0x1f;
866 if (ret == 0)
867 ret = 32;
868 return ret;
869}
870
871/* The NSI field in a D form instruction. This is the same as the SI
872 field, only negated. The extraction function always marks it as
873 invalid, since we never want to recognize an instruction which uses
874 a field of this type. */
875
876/*ARGSUSED*/
877static unsigned long
878insert_nsi (insn, value, errmsg)
879 unsigned long insn;
880 long value;
881 const char **errmsg ATTRIBUTE_UNUSED;
882{
883 return insn | ((- value) & 0xffff);
884}
885
886static long
887extract_nsi (insn, invalid)
888 unsigned long insn;
889 int *invalid;
890{
891 if (invalid != (int *) NULL)
892 *invalid = 1;
893 if ((insn & 0x8000) != 0)
894 return - ((long)(insn & 0xffff) - 0x10000);
895 else
896 return - (long)(insn & 0xffff);
897}
898
899/* The RA field in a D or X form instruction which is an updating
900 load, which means that the RA field may not be zero and may not
901 equal the RT field. */
902
903static unsigned long
904insert_ral (insn, value, errmsg)
905 unsigned long insn;
906 long value;
907 const char **errmsg;
908{
909 if (value == 0
910 || (unsigned long) value == ((insn >> 21) & 0x1f))
911 *errmsg = "invalid register operand when updating";
912 return insn | ((value & 0x1f) << 16);
913}
914
915/* The RA field in an lmw instruction, which has special value
916 restrictions. */
917
918static unsigned long
919insert_ram (insn, value, errmsg)
920 unsigned long insn;
921 long value;
922 const char **errmsg;
923{
924 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
925 *errmsg = _("index register in load range");
926 return insn | ((value & 0x1f) << 16);
927}
928
929/* The RA field in a D or X form instruction which is an updating
930 store or an updating floating point load, which means that the RA
931 field may not be zero. */
932
933static unsigned long
934insert_ras (insn, value, errmsg)
935 unsigned long insn;
936 long value;
937 const char **errmsg;
938{
939 if (value == 0)
940 *errmsg = _("invalid register operand when updating");
941 return insn | ((value & 0x1f) << 16);
942}
943
944/* The RB field in an X form instruction when it must be the same as
945 the RS field in the instruction. This is used for extended
946 mnemonics like mr. This operand is marked FAKE. The insertion
947 function just copies the BT field into the BA field, and the
948 extraction function just checks that the fields are the same. */
949
950/*ARGSUSED*/
951static unsigned long
952insert_rbs (insn, value, errmsg)
953 unsigned long insn;
954 long value ATTRIBUTE_UNUSED;
955 const char **errmsg ATTRIBUTE_UNUSED;
956{
957 return insn | (((insn >> 21) & 0x1f) << 11);
958}
959
960static long
961extract_rbs (insn, invalid)
962 unsigned long insn;
963 int *invalid;
964{
965 if (invalid != (int *) NULL
966 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
967 *invalid = 1;
968 return 0;
969}
970
971/* The SH field in an MD form instruction. This is split. */
972
973/*ARGSUSED*/
974static unsigned long
975insert_sh6 (insn, value, errmsg)
976 unsigned long insn;
977 long value;
978 const char **errmsg ATTRIBUTE_UNUSED;
979{
980 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
981}
982
983/*ARGSUSED*/
984static long
985extract_sh6 (insn, invalid)
986 unsigned long insn;
987 int *invalid ATTRIBUTE_UNUSED;
988{
989 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
990}
991
992/* The SPR field in an XFX form instruction. This is flipped--the
993 lower 5 bits are stored in the upper 5 and vice- versa. */
994
995static unsigned long
996insert_spr (insn, value, errmsg)
997 unsigned long insn;
998 long value;
999 const char **errmsg ATTRIBUTE_UNUSED;
1000{
1001 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1002}
1003
1004static long
1005extract_spr (insn, invalid)
1006 unsigned long insn;
1007 int *invalid ATTRIBUTE_UNUSED;
1008{
1009 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1010}
1011
1012/* The TBR field in an XFX instruction. This is just like SPR, but it
1013 is optional. When TBR is omitted, it must be inserted as 268 (the
1014 magic number of the TB register). These functions treat 0
1015 (indicating an omitted optional operand) as 268. This means that
1016 ``mftb 4,0'' is not handled correctly. This does not matter very
1017 much, since the architecture manual does not define mftb as
1018 accepting any values other than 268 or 269. */
1019
1020#define TB (268)
1021
1022static unsigned long
1023insert_tbr (insn, value, errmsg)
1024 unsigned long insn;
1025 long value;
1026 const char **errmsg ATTRIBUTE_UNUSED;
1027{
1028 if (value == 0)
1029 value = TB;
1030 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1031}
1032
1033static long
1034extract_tbr (insn, invalid)
1035 unsigned long insn;
1036 int *invalid ATTRIBUTE_UNUSED;
1037{
1038 long ret;
1039
1040 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1041 if (ret == TB)
1042 ret = 0;
1043 return ret;
1044}
1045
1046
1047/* Macros used to form opcodes. */
1048
1049/* The main opcode. */
1050#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1051#define OP_MASK OP (0x3f)
1052
1053/* The main opcode combined with a trap code in the TO field of a D
1054 form instruction. Used for extended mnemonics for the trap
1055 instructions. */
1056#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1057#define OPTO_MASK (OP_MASK | TO_MASK)
1058
1059/* The main opcode combined with a comparison size bit in the L field
1060 of a D form or X form instruction. Used for extended mnemonics for
1061 the comparison instructions. */
1062#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1063#define OPL_MASK OPL (0x3f,1)
1064
1065/* An A form instruction. */
1066#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1067#define A_MASK A (0x3f, 0x1f, 1)
1068
1069/* An A_MASK with the FRB field fixed. */
1070#define AFRB_MASK (A_MASK | FRB_MASK)
1071
1072/* An A_MASK with the FRC field fixed. */
1073#define AFRC_MASK (A_MASK | FRC_MASK)
1074
1075/* An A_MASK with the FRA and FRC fields fixed. */
1076#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1077
1078/* A B form instruction. */
1079#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1080#define B_MASK B (0x3f, 1, 1)
1081
1082/* A B form instruction setting the BO field. */
1083#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1084#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1085
1086/* A BBO_MASK with the y bit of the BO field removed. This permits
1087 matching a conditional branch regardless of the setting of the y
1088 bit. */
1089#define Y_MASK (((unsigned long)1) << 21)
1090#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1091
1092/* A B form instruction setting the BO field and the condition bits of
1093 the BI field. */
1094#define BBOCB(op, bo, cb, aa, lk) \
1095 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1096#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1097
1098/* A BBOCB_MASK with the y bit of the BO field removed. */
1099#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1100
1101/* A BBOYCB_MASK in which the BI field is fixed. */
1102#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1103
1104/* The main opcode mask with the RA field clear. */
1105#define DRA_MASK (OP_MASK | RA_MASK)
1106
1107/* A DS form instruction. */
1108#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1109#define DS_MASK DSO (0x3f, 3)
1110
1111/* An M form instruction. */
1112#define M(op, rc) (OP (op) | ((rc) & 1))
1113#define M_MASK M (0x3f, 1)
1114
1115/* An M form instruction with the ME field specified. */
1116#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1117
1118/* An M_MASK with the MB and ME fields fixed. */
1119#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1120
1121/* An M_MASK with the SH and ME fields fixed. */
1122#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1123
1124/* An MD form instruction. */
1125#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1126#define MD_MASK MD (0x3f, 0x7, 1)
1127
1128/* An MD_MASK with the MB field fixed. */
1129#define MDMB_MASK (MD_MASK | MB6_MASK)
1130
1131/* An MD_MASK with the SH field fixed. */
1132#define MDSH_MASK (MD_MASK | SH6_MASK)
1133
1134/* An MDS form instruction. */
1135#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1136#define MDS_MASK MDS (0x3f, 0xf, 1)
1137
1138/* An MDS_MASK with the MB field fixed. */
1139#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1140
1141/* An SC form instruction. */
1142#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1143#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1144
1145/* An VX form instruction. */
1146#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1147
1148/* The mask for an VX form instruction. */
1149#define VX_MASK VX(0x3f, 0x7ff)
1150
1151/* An VA form instruction. */
1152#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f))
1153
1154/* The mask for an VA form instruction. */
1155#define VXA_MASK VXA(0x3f, 0x7f)
1156
1157/* An VXR form instruction. */
1158#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1159
1160/* The mask for a VXR form instruction. */
1161#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1162
1163/* An X form instruction. */
1164#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1165
1166/* An X form instruction with the RC bit specified. */
1167#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1168
1169/* The mask for an X form instruction. */
1170#define X_MASK XRC (0x3f, 0x3ff, 1)
1171
1172/* An X_MASK with the RA field fixed. */
1173#define XRA_MASK (X_MASK | RA_MASK)
1174
1175/* An X_MASK with the RB field fixed. */
1176#define XRB_MASK (X_MASK | RB_MASK)
1177
1178/* An X_MASK with the RT field fixed. */
1179#define XRT_MASK (X_MASK | RT_MASK)
1180
1181/* An X_MASK with the RA and RB fields fixed. */
1182#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1183
1184/* An X_MASK with the RT and RA fields fixed. */
1185#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1186
1187/* An X form comparison instruction. */
1188#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1189
1190/* The mask for an X form comparison instruction. */
1191#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1192
1193/* The mask for an X form comparison instruction with the L field
1194 fixed. */
1195#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1196
1197/* An X form trap instruction with the TO field specified. */
1198#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1199#define XTO_MASK (X_MASK | TO_MASK)
1200
1201/* An X form tlb instruction with the SH field specified. */
1202#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1203#define XTLB_MASK (X_MASK | SH_MASK)
1204
1205/* An XFL form instruction. */
1206#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1207#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1208
1209/* An XL form instruction with the LK field set to 0. */
1210#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1211
1212/* An XL form instruction which uses the LK field. */
1213#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1214
1215/* The mask for an XL form instruction. */
1216#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1217
1218/* An XL form instruction which explicitly sets the BO field. */
1219#define XLO(op, bo, xop, lk) \
1220 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1221#define XLO_MASK (XL_MASK | BO_MASK)
1222
1223/* An XL form instruction which explicitly sets the y bit of the BO
1224 field. */
1225#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1226#define XLYLK_MASK (XL_MASK | Y_MASK)
1227
1228/* An XL form instruction which sets the BO field and the condition
1229 bits of the BI field. */
1230#define XLOCB(op, bo, cb, xop, lk) \
1231 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1232#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1233
1234/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1235#define XLBB_MASK (XL_MASK | BB_MASK)
1236#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1237#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1238
1239/* An XL_MASK with the BO and BB fields fixed. */
1240#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1241
1242/* An XL_MASK with the BO, BI and BB fields fixed. */
1243#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1244
1245/* An XO form instruction. */
1246#define XO(op, xop, oe, rc) \
1247 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1248#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1249
1250/* An XO_MASK with the RB field fixed. */
1251#define XORB_MASK (XO_MASK | RB_MASK)
1252
1253/* An XS form instruction. */
1254#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1255#define XS_MASK XS (0x3f, 0x1ff, 1)
1256
1257/* A mask for the FXM version of an XFX form instruction. */
1258#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1259
1260/* An XFX form instruction with the FXM field filled in. */
1261#define XFXM(op, xop, fxm) \
1262 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1263
1264/* An XFX form instruction with the SPR field filled in. */
1265#define XSPR(op, xop, spr) \
1266 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1267#define XSPR_MASK (X_MASK | SPR_MASK)
1268
1269/* An XFX form instruction with the SPR field filled in except for the
1270 SPRBAT field. */
1271#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1272
1273/* An XFX form instruction with the SPR field filled in except for the
1274 SPRG field. */
1275#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1276
1277/* An X form instruction with everything filled in except the E field. */
1278#define XE_MASK (0xffff7fff)
1279
1280/* The BO encodings used in extended conditional branch mnemonics. */
1281#define BODNZF (0x0)
1282#define BODNZFP (0x1)
1283#define BODZF (0x2)
1284#define BODZFP (0x3)
1285#define BOF (0x4)
1286#define BOFP (0x5)
1287#define BODNZT (0x8)
1288#define BODNZTP (0x9)
1289#define BODZT (0xa)
1290#define BODZTP (0xb)
1291#define BOT (0xc)
1292#define BOTP (0xd)
1293#define BODNZ (0x10)
1294#define BODNZP (0x11)
1295#define BODZ (0x12)
1296#define BODZP (0x13)
1297#define BOU (0x14)
1298
1299/* The BI condition bit encodings used in extended conditional branch
1300 mnemonics. */
1301#define CBLT (0)
1302#define CBGT (1)
1303#define CBEQ (2)
1304#define CBSO (3)
1305
1306/* The TO encodings used in extended trap mnemonics. */
1307#define TOLGT (0x1)
1308#define TOLLT (0x2)
1309#define TOEQ (0x4)
1310#define TOLGE (0x5)
1311#define TOLNL (0x5)
1312#define TOLLE (0x6)
1313#define TOLNG (0x6)
1314#define TOGT (0x8)
1315#define TOGE (0xc)
1316#define TONL (0xc)
1317#define TOLT (0x10)
1318#define TOLE (0x14)
1319#define TONG (0x14)
1320#define TONE (0x18)
1321#define TOU (0x1f)
1322
1323
1324/* Smaller names for the flags so each entry in the opcodes table will
1325 fit on a single line. */
1326#undef PPC
1327#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1328#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1329#define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
1330#define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
1331#define PPCONLY PPC_OPCODE_PPC
1332#define PPC403 PPC
1333#define PPC405 PPC403
1334#define PPC750 PPC
1335#define PPC860 PPC
1336#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY
1337#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1338#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1339#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1340#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1341#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1342#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1343#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1344#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1345#define MFDEC1 PPC_OPCODE_POWER
1346#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
1347
1348
1349/* The opcode table.
1350
1351 The format of the opcode table is:
1352
1353 NAME OPCODE MASK FLAGS { OPERANDS }
1354
1355 NAME is the name of the instruction.
1356 OPCODE is the instruction opcode.
1357 MASK is the opcode mask; this is used to tell the disassembler
1358 which bits in the actual opcode must match OPCODE.
1359 FLAGS are flags indicated what processors support the instruction.
1360 OPERANDS is the list of operands.
1361
1362 The disassembler reads the table in order and prints the first
1363 instruction which matches, so this table is sorted to put more
1364 specific instructions before more general instructions. It is also
1365 sorted by major opcode. */
1366
1367const struct powerpc_opcode powerpc_opcodes[] = {
1368{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1369{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1370{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1371{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1372{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1373{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1374{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1375{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1376{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1377{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1378{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1379{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1380{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1381{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1382{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1383
1384{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1385{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1386{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1387{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1388{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1389{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1390{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1391{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1392{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1393{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1394{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1395{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1396{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1397{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1398{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1399{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1400{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1401{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1402{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1403{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1404{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1405{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1406{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1407{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1408{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1409{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1410{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1411{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1412{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1413{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1414
1415{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1416{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1417{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1418{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1419{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1420{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1421{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1422{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1423{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1424{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1425{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1426{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1427{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1428{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1429{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1430{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1431{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1432{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1433{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1434{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1435{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1436{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1437{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1438{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1439{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1440{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1441{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1442{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1443{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1444{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1445{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1446{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1447{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1448{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1449{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1450{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1451{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1452{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1453{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1454{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1455{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1456{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1457{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1458{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1459{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1460{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1461{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1462{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1463{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1464{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1465{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1466{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1467{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1468{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1469{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1470{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1471{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1472{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1473{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1474{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1475{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1476{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1477{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1478{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1479{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1480{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1481{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1482{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1483{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1484{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1485{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1486{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1487{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1488{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1489{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1490{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1491{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1492{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1493{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1494{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1495{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1496{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1497{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1498{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1499{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1500{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
1501{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1502{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1503{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1504{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1505{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1506{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1507{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1508{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1509{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1510{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1511{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1512{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1513{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1514{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1515{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1516{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1517{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1518{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1519{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1520{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1521{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1522{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1523{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1524{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1525{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1526{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1527{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1528{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1529{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1530{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1531{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1532{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1533{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1534{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1535{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1536{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1537{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1538{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1539{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1540{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1541{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1542{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1543{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1544{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1545{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1546{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1547{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1548{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1549{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1550{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1551{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1552{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1553{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1554{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1555{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1556{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1557{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1558{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1559{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1560{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1561{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1562{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1563{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1564{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1565{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1566{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1567{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1568{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1569{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1570{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1571{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1572{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1573{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1574{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1575{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1576{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1577{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1578{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1579{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1580{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1581{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1582{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1583{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1584{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1585{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1586{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1587{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1588{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1589{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1590{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1591{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
1592{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
1593{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1594{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
1595{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
1596{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
1597{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
1598{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
1599{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
1600{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
1601{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
1602{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
1603{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
1604{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
1605{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
1606{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
1607{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
1608{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
1609{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
1610{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
1611{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
1612{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1613{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
1614{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
1615{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
1616{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
1617{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1618{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
1619{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1620{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1621{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
1622{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
1623{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
1624{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1625{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
1626{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
1627{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
1628{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
1629{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
1630{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
1631{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
1632{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
1633{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
1634{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
1635{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
1636{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
1637{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
1638{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
1639{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
1640{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
1641{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
1642{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
1643{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
1644{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
1645{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
1646{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
1647{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
1648{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
1649{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
1650{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
1651{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
1652{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
1653{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
1654{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
1655{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
1656
1657{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
1658{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
1659
1660{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
1661{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
1662
1663{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
1664
1665{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
1666{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
1667{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
1668{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
1669
1670{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
1671{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
1672{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
1673{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
1674
1675{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
1676{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
1677{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
1678
1679{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
1680{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
1681{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
1682
1683{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
1684{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
1685{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
1686{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
1687{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
1688{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
1689
1690{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
1691{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
1692{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
1693{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
1694{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
1695
1696{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BDM } },
1697{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BDP } },
1698{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BD } },
1699{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM, { BD } },
1700{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BDM } },
1701{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BDP } },
1702{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BD } },
1703{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM, { BD } },
1704{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDMA } },
1705{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDPA } },
1706{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDA } },
1707{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM, { BDA } },
1708{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDMA } },
1709{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDPA } },
1710{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDA } },
1711{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM, { BDA } },
1712{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPCCOM, { BDM } },
1713{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPCCOM, { BDP } },
1714{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, COM, { BD } },
1715{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPCCOM, { BDM } },
1716{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPCCOM, { BDP } },
1717{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, COM, { BD } },
1718{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPCCOM, { BDMA } },
1719{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPCCOM, { BDPA } },
1720{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, COM, { BDA } },
1721{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPCCOM, { BDMA } },
1722{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPCCOM, { BDPA } },
1723{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, COM, { BDA } },
1724{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1725{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1726{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1727{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1728{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1729{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1730{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1731{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1732{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1733{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1734{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1735{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1736{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1737{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1738{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1739{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1740{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1741{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1742{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1743{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1744{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1745{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1746{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1747{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1748{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1749{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1750{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } },
1751{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1752{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1753{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } },
1754{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1755{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1756{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1757{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1758{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1759{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1760{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1761{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1762{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } },
1763{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1764{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1765{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } },
1766{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1767{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1768{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1769{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1770{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1771{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1772{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1773{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1774{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
1775{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1776{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1777{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
1778{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1779{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1780{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1781{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1782{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1783{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1784{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1785{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1786{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1787{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1788{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1789{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1790{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1791{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1792{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1793{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1794{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1795{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1796{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1797{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1798{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1799{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1800{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1801{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1802{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1803{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1804{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1805{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1806{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1807{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1808{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1809{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1810{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1811{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1812{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1813{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1814{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1815{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1816{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1817{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1818{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1819{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1820{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1821{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1822{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } },
1823{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1824{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1825{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } },
1826{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1827{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1828{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1829{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1830{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1831{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1832{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1833{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1834{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } },
1835{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1836{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1837{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } },
1838{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1839{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1840{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1841{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1842{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1843{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1844{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1845{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1846{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } },
1847{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1848{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1849{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } },
1850{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1851{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1852{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } },
1853{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1854{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1855{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } },
1856{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1857{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1858{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } },
1859{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } },
1860{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } },
1861{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } },
1862{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1863{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1864{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1865{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } },
1866{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } },
1867{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } },
1868{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1869{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1870{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1871{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1872{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1873{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1874{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1875{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1876{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1877{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1878{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1879{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1880{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1881{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1882{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1883{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1884{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1885{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1886{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1887{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1888{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1889{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1890{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1891{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1892{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1893{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1894{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1895{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, PWRCOM, { BI, BD } },
1896{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1897{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1898{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1899{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, PWRCOM, { BI, BD } },
1900{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1901{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1902{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1903{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, PWRCOM, { BI, BDA } },
1904{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1905{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1906{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1907{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, PWRCOM, { BI, BDA } },
1908{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1909{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1910{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1911{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, PWRCOM, { BI, BD } },
1912{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1913{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1914{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1915{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, PWRCOM, { BI, BD } },
1916{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1917{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1918{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1919{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, PWRCOM, { BI, BDA } },
1920{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1921{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1922{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1923{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, PWRCOM, { BI, BDA } },
1924{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1925{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1926{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1927{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1928{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1929{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1930{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1931{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1932{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1933{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1934{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1935{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1936{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } },
1937{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } },
1938{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
1939{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } },
1940{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } },
1941{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
1942{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } },
1943{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } },
1944{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
1945{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } },
1946{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } },
1947{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
1948{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
1949{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
1950{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
1951{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
1952{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
1953{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
1954{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
1955{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
1956{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
1957{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
1958{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
1959{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
1960
1961{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
1962{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
1963{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
1964{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
1965{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
1966
1967{ "b", B(18,0,0), B_MASK, COM, { LI } },
1968{ "bl", B(18,0,1), B_MASK, COM, { LI } },
1969{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
1970{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
1971
1972{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
1973
1974{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1975{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
1976{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1977{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
1978{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1979{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1980{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1981{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1982{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1983{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1984{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1985{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1986{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
1987{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1988{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1989{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
1990{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1991{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1992{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1993{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
1994{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1995{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1996{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
1997{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
1998{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
1999{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2000{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2001{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2002{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2003{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2004{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2005{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2006{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2007{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2008{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2009{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2010{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2011{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2012{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2013{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2014{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2015{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2016{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2017{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2018{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2019{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2020{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2021{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2022{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2023{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2024{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2025{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2026{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2027{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2028{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2029{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2030{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2031{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2032{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2033{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2034{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2035{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2036{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2037{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2038{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2039{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2040{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2041{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2042{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2043{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2044{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2045{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2046{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2047{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2048{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2049{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2050{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2051{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2052{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2053{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2054{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2055{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2056{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2057{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2058{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2059{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2060{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2061{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2062{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2063{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2064{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2065{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2066{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2067{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2068{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2069{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2070{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2071{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2072{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2073{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2074{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2075{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2076{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2077{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2078{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2079{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2080{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2081{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2082{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2083{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2084{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2085{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2086{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2087{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2088{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2089{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2090{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2091{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2092{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2093{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2094{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2095{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2096{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2097{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2098{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2099{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2100{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2101{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2102{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2103{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2104{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2105{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2106{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2107{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2108{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2109{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } },
2110{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2111{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2112{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2113{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2114{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2115{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2116{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2117{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2118{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2119{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2120{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2121{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2122{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2123{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2124{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2125{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2126{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2127{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2128{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2129{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2130
2131{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2132
2133{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2134{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2135
2136{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2137{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
2138
2139{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2140
2141{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2142
2143{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2144{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2145
2146{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2147{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2148
2149{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2150
2151{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2152
2153{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2154{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2155
2156{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2157
2158{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2159{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2160
2161{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2162{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2163{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2164{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2165{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2166{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2167{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2168{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2169{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2170{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2171{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2172{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2173{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2174{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2175{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2176{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2177{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2178{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2179{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2180{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2181{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2182{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2183{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2184{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2185{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2186{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2187{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2188{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2189{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2190{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2191{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2192{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2193{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2194{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2195{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2196{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2197{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2198{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2199{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2200{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2201{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2202{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2203{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2204{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2205{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2206{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2207{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2208{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2209{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2210{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2211{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2212{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2213{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2214{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2215{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2216{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2217{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2218{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2219{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2220{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2221{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2222{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2223{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2224{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2225{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2226{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2227{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2228{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2229{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2230{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2231{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2232{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2233{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2234{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2235{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2236{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2237{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2238{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2239{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2240{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2241{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2242{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2243{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2244{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2245{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2246{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2247{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2248{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2249{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2250{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2251{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2252{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2253{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
2254{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
2255
2256{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2257{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2258
2259{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2260{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2261
2262{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
2263{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2264{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2265{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2266{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
2267{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2268{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2269{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2270
2271{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2272{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2273
2274{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2275{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2276{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2277{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
2278{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
2279{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
2280
2281{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
2282{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
2283{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
2284
2285{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
2286{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
2287
2288{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
2289{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
2290
2291{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
2292{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
2293
2294{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
2295{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
2296
2297{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
2298{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
2299
2300{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2301{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2302{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2303{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
2304{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
2305{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2306
2307{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2308{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
2309
2310{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2311{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2312
2313{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2314{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
2315
2316{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
2317{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2318{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
2319{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
2320
2321{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2322{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
2323
2324{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2325{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2326{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2327{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2328
2329{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
2330{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
2331{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
2332{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
2333{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
2334{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
2335{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
2336{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
2337{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
2338{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
2339{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
2340{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
2341{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
2342{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
2343{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
2344{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
2345{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
2346{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
2347{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
2348{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
2349{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
2350{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
2351{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
2352{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
2353{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
2354{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
2355{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
2356{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
2357{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
2358{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
2359{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
2360
2361{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2362{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2363{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
2364{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2365{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2366{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
2367{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2368{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2369{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
2370{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2371{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2372{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
2373
2374{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2375{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2376
2377{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2378{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2379{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2380{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2381{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2382{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2383{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2384{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2385
2386{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
2387{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
2388
2389{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
2390
2391{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
2392
2393{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
2394
2395{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
2396{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
2397
2398{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
2399{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
2400{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
2401{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
2402
2403{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
2404{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
2405{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
2406{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
2407
2408{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
2409{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
2410
2411{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
2412{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
2413
2414{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
2415{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
2416
2417{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
2418{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
2419{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
2420{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
2421
2422{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
2423{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
2424{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
2425{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
2426{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
2427{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
2428{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
2429{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
2430
2431{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
2432
2433{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
2434
2435{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
2436{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
2437
2438{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
2439{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
2440
2441{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
2442{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
2443
2444{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
2445{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
2446{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
2447{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
2448{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
2449{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
2450{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
2451{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
2452{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
2453{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
2454{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
2455{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
2456{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
2457{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
2458{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
2459
2460{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2461{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2462
2463{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
2464{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
2465
2466{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
2467
2468{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
2469
2470{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
2471
2472{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
2473
2474{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
2475
2476{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
2477{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
2478{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
2479{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
2480
2481{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
2482{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
2483{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
2484{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
2485
2486{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
2487
2488{ "clf", X(31,118), XRB_MASK, POWER, { RT, RA } },
2489
2490{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
2491
2492{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
2493{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
2494{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
2495{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
2496
2497{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
2498
2499{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2500{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2501{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2502{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2503{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2504{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2505{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2506{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2507
2508{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2509{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2510{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2511{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2512{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2513{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2514{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2515{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2516
2517{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
2518{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
2519
2520{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
2521
2522{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
2523
2524{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
2525
2526{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
2527{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
2528
2529{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
2530{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
2531
2532{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
2533{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
2534
2535{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
2536
2537{ "mtmsrd", X(31,178), XRARB_MASK, PPC64, { RS } },
2538
2539{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
2540
2541{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
2542{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
2543
2544{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
2545{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
2546
2547{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2548{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2549{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2550{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2551{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2552{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2553{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2554{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2555
2556{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2557{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2558{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2559{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2560{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2561{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2562{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2563{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2564
2565{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
2566
2567{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
2568
2569{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
2570
2571{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
2572{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
2573
2574{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
2575{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
2576
2577{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2578{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2579{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2580{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2581{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2582{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2583{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2584{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2585
2586{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2587{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2588{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2589{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2590
2591{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
2592{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
2593{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
2594{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
2595{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
2596{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
2597{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
2598{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
2599
2600{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2601{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2602{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2603{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2604{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2605{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2606{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2607{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2608
2609{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
2610{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
2611
2612{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
2613
2614{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
2615
2616{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
2617{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
2618
2619{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
2620{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
2621{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
2622{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
2623
2624{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2625{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2626{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2627{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2628{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
2629{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
2630{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
2631{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
2632
2633{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
2634{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
2635
2636{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
2637
2638{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
2639
2640{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
2641
2642{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
2643{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
2644
2645{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
2646{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
2647
2648{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
2649
2650{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
2651
2652{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
2653{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
2654
2655{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
2656{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
2657{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
2658{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
2659{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
2660{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
2661{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
2662{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
2663{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
2664{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
2665{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
2666{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
2667{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
2668{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
2669{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
2670{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
2671{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
2672{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
2673{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
2674{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
2675{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
2676{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
2677{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
2678{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
2679{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
2680{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
2681{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
2682{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
2683{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
2684{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
2685{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
2686{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
2687{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
2688{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
2689{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
2690
2691{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
2692{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
2693{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
2694{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
2695
2696{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
2697{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
2698{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
2699{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
2700{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
2701{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
2702{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
2703{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
2704{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
2705{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
2706{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
2707{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
2708{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
2709{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
2710{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
2711{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
2712{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
2713{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
2714{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
2715{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
2716{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
2717{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
2718{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
2719{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
2720{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
2721{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
2722{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
2723{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
2724{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
2725{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
2726{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
2727{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
2728{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
2729{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
2730{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
2731{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
2732{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
2733{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
2734{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
2735{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
2736{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
2737{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
2738{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
2739{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2740{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2741{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2742{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
2743{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
2744{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
2745{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
2746{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
2747{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
2748{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
2749{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
2750{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
2751{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
2752{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
2753{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
2754{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
2755{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
2756{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
2757{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
2758{ "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
2759{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
2760{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
2761{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
2762{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
2763{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
2764{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
2765{ "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
2766{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
2767{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
2768{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
2769{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
2770{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
2771{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
2772{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
2773{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
2774{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
2775{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
2776{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
2777{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
2778{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
2779{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
2780{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
2781{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
2782{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
2783{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
2784{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
2785{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
2786{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
2787{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
2788{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
2789{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
2790{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
2791{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
2792{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
2793{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
2794{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
2795{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
2796{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
2797{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
2798{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
2799{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
2800{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
2801{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
2802{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
2803{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
2804{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
2805{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
2806{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
2807{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
2808{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
2809{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
2810{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
2811{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
2812{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
2813{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
2814{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
2815{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
2816{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
2817{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
2818{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
2819{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
2820{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
2821{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
2822{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
2823{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
2824{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
2825{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
2826{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
2827
2828{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
2829
2830{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
2831
2832{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
2833
2834{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
2835{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
2836{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
2837{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
2838
2839{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
2840{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
2841{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
2842{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
2843
2844{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
2845
2846{ "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } },
2847{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } },
2848{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } },
2849
2850{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
2851
2852{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
2853
2854{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
2855
2856{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
2857
2858{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
2859
2860{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
2861
2862{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
2863
2864{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
2865{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
2866
2867{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
2868{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
2869
2870{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
2871
2872{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
2873
2874{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
2875
2876{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
2877{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
2878{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
2879{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
2880
2881{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
2882{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
2883{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
2884{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
2885{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
2886{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
2887{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
2888{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
2889{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
2890{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
2891{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
2892{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
2893{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
2894{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
2895{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
2896{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
2897{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
2898{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
2899{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
2900{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
2901{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
2902{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
2903{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
2904{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
2905{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
2906{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
2907{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
2908{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
2909{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
2910{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
2911{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
2912{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
2913{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
2914{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
2915{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
2916
2917{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
2918{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
2919{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
2920{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
2921
2922{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
2923{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
2924{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
2925{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
2926
2927{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
2928{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
2929{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
2930{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
2931{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
2932{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
2933{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
2934{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
2935{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
2936{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
2937{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
2938{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
2939{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
2940{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
2941{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
2942{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
2943{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
2944{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
2945{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
2946{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
2947{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
2948{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
2949{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
2950{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
2951{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
2952{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
2953{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
2954{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
2955{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
2956{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
2957{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } },
2958{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
2959{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
2960{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
2961{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
2962{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
2963{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
2964{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
2965{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
2966{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
2967{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
2968{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
2969{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
2970{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2971{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2972{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2973{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
2974{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
2975{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
2976{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
2977{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
2978{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
2979{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
2980{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
2981{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
2982{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
2983{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
2984{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
2985{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
2986{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
2987{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
2988{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
2989{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
2990{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
2991{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
2992{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
2993{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
2994{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
2995{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
2996{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
2997{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
2998{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
2999{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
3000{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
3001{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
3002{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
3003{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
3004{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
3005{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
3006{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
3007{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
3008{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
3009{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
3010{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
3011{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
3012{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
3013{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
3014{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
3015{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
3016{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
3017{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
3018{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
3019{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
3020{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
3021{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
3022{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
3023{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
3024{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
3025{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
3026{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
3027{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
3028{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
3029{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
3030
3031{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
3032
3033{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
3034{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
3035
3036{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
3037
3038{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
3039{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
3040{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
3041{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
3042
3043{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3044{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3045{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3046{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3047
3048{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
3049{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
3050{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
3051{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
3052
3053{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
3054
3055{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
3056
3057{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
3058
3059{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
3060
3061{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
3062{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
3063
3064{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
3065{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
3066
3067{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
3068
3069{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
3070{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
3071{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
3072{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
3073
3074{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
3075{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
3076
3077{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
3078{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
3079
3080{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
3081{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
3082
3083{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
3084
3085{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
3086
3087{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
3088
3089{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
3090{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
3091
3092{ "sync", X(31,598), 0xffffffff, PPCCOM, { 0 } },
3093{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
3094
3095{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
3096
3097{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
3098
3099{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
3100
3101{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
3102
3103{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
3104
3105{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
3106{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
3107
3108{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
3109{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
3110
3111{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
3112
3113{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
3114{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
3115
3116{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
3117{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
3118
3119{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
3120
3121{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
3122{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
3123
3124{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
3125{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
3126
3127{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
3128
3129{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
3130{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
3131
3132{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
3133{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
3134
3135{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
3136
3137{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
3138
3139{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
3140{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
3141
3142{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
3143
3144{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
3145{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
3146{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
3147{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
3148
3149{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
3150{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
3151
3152{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
3153
3154{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
3155{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
3156{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
3157{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
3158
3159{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
3160
3161{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
3162{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
3163
3164{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
3165
3166{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
3167{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
3168
3169{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
3170{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
3171
3172{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
3173{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
3174{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
3175{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
3176
3177{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
3178{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
3179{ "tlbre", X(31,946), X_MASK, PPC403, { RT, RA, SH } },
3180
3181{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
3182{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
3183
3184{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
3185{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
3186
3187{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
3188
3189{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
3190
3191{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
3192{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
3193{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
3194
3195{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
3196
3197{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
3198
3199{ "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } },
3200{ "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } },
3201
3202{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
3203
3204{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
3205
3206{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3207{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
3208
3209{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
3210{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
3211{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
3212{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
3213{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
3214{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
3215{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
3216{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
3217{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
3218{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
3219{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
3220{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
3221
3222{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
3223{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
3224
3225{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
3226{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
3227
3228{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
3229
3230{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
3231
3232{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
3233{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
3234
3235{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
3236{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
3237
3238{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
3239
3240{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
3241
3242{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
3243
3244{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
3245
3246{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
3247
3248{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
3249
3250{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
3251
3252{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
3253
3254{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
3255{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
3256
3257{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
3258{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
3259
3260{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
3261
3262{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
3263
3264{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
3265
3266{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
3267
3268{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
3269
3270{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
3271
3272{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
3273
3274{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
3275
3276{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
3277
3278{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
3279
3280{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
3281
3282{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
3283
3284{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
3285
3286{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3287{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3288
3289{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3290{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3291
3292{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3293{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
3294
3295{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3296{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3297
3298{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3299{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3300
3301{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3302{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
3303
3304{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3305{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3306
3307{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3308{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3309
3310{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3311{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3312
3313{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3314{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3315
3316{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
3317
3318{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
3319
3320{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
3321
3322{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
3323
3324{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3325
3326{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
3327{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
3328
3329{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3330{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
3331{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3332{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
3333
3334{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
3335{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
3336{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
3337{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
3338
3339{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3340{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3341{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3342{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3343
3344{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3345{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3346{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3347{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3348
3349{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3350{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3351{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
3352{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
3353
3354{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3355{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
3356
3357{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3358{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
3359
3360{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3361{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3362{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
3363{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
3364
3365{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
3366{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
3367
3368{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3369{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3370{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3371{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3372
3373{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3374{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3375{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3376{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3377
3378{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3379{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3380{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3381{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3382
3383{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3384{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3385{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
3386{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
3387
3388{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
3389
3390{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
3391{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
3392
3393{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
3394{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
3395
3396{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
3397
3398{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
3399{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
3400
3401{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
3402{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
3403
3404{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3405{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
3406
3407{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
3408{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
3409
3410{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
3411{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
3412
3413{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
3414{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
3415
3416{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
3417{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
3418
3419{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
3420{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
3421
3422{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
3423{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
3424
3425{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
3426{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
3427
3428};
3429
3430const int powerpc_num_opcodes =
3431 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
3432
3433
3434/* The macro table. This is only used by the assembler. */
3435
3436/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
3437 when x=0; 32-x when x is between 1 and 31; are negative if x is
3438 negative; and are 32 or more otherwise. This is what you want
3439 when, for instance, you are emulating a right shift by a
3440 rotate-left-and-mask, because the underlying instructions support
3441 shifts of size 0 but not shifts of size 32. By comparison, when
3442 extracting x bits from some word you want to use just 32-x, because
3443 the underlying instructions don't support extracting 0 bits but do
3444 support extracting the whole word (32 bits in this case). */
3445
3446const struct powerpc_macro powerpc_macros[] = {
3447{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
3448{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
3449{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
3450{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
3451{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
3452{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
3453{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
3454{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
3455{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
3456{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
3457{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
3458{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
3459{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
3460{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
3461{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
3462{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
3463
3464{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
3465{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
3466{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
3467{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
3468{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
3469{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
3470{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
3471{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
3472{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3473{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
3474{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
3475{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
3476{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
3477{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
3478{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3479{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3480{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3481{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
3482{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
3483{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
3484{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
3485{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
3486
3487};
3488
3489const int powerpc_num_macros =
3490 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
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