source: trunk/src/binutils/opcodes/ppc-opc.c@ 1227

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1/* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23#include <stdio.h>
24#include "sysdep.h"
25#include "opcode/ppc.h"
26#include "opintl.h"
27
28/* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38
39
40/* Local insertion and extraction functions. */
41
42static unsigned long insert_bat
43 PARAMS ((unsigned long, long, int, const char **));
44static long extract_bat
45 PARAMS ((unsigned long, int, int *));
46static unsigned long insert_bba
47 PARAMS ((unsigned long, long, int, const char **));
48static long extract_bba
49 PARAMS ((unsigned long, int, int *));
50static unsigned long insert_bd
51 PARAMS ((unsigned long, long, int, const char **));
52static long extract_bd
53 PARAMS ((unsigned long, int, int *));
54static unsigned long insert_bdm
55 PARAMS ((unsigned long, long, int, const char **));
56static long extract_bdm
57 PARAMS ((unsigned long, int, int *));
58static unsigned long insert_bdp
59 PARAMS ((unsigned long, long, int, const char **));
60static long extract_bdp
61 PARAMS ((unsigned long, int, int *));
62static int valid_bo
63 PARAMS ((long, int));
64static unsigned long insert_bo
65 PARAMS ((unsigned long, long, int, const char **));
66static long extract_bo
67 PARAMS ((unsigned long, int, int *));
68static unsigned long insert_boe
69 PARAMS ((unsigned long, long, int, const char **));
70static long extract_boe
71 PARAMS ((unsigned long, int, int *));
72static unsigned long insert_ds
73 PARAMS ((unsigned long, long, int, const char **));
74static long extract_ds
75 PARAMS ((unsigned long, int, int *));
76static unsigned long insert_de
77 PARAMS ((unsigned long, long, int, const char **));
78static long extract_de
79 PARAMS ((unsigned long, int, int *));
80static unsigned long insert_des
81 PARAMS ((unsigned long, long, int, const char **));
82static long extract_des
83 PARAMS ((unsigned long, int, int *));
84static unsigned long insert_li
85 PARAMS ((unsigned long, long, int, const char **));
86static long extract_li
87 PARAMS ((unsigned long, int, int *));
88static unsigned long insert_mbe
89 PARAMS ((unsigned long, long, int, const char **));
90static long extract_mbe
91 PARAMS ((unsigned long, int, int *));
92static unsigned long insert_mb6
93 PARAMS ((unsigned long, long, int, const char **));
94static long extract_mb6
95 PARAMS ((unsigned long, int, int *));
96static unsigned long insert_nb
97 PARAMS ((unsigned long, long, int, const char **));
98static long extract_nb
99 PARAMS ((unsigned long, int, int *));
100static unsigned long insert_nsi
101 PARAMS ((unsigned long, long, int, const char **));
102static long extract_nsi
103 PARAMS ((unsigned long, int, int *));
104static unsigned long insert_ral
105 PARAMS ((unsigned long, long, int, const char **));
106static unsigned long insert_ram
107 PARAMS ((unsigned long, long, int, const char **));
108static unsigned long insert_ras
109 PARAMS ((unsigned long, long, int, const char **));
110static unsigned long insert_rbs
111 PARAMS ((unsigned long, long, int, const char **));
112static long extract_rbs
113 PARAMS ((unsigned long, int, int *));
114static unsigned long insert_sh6
115 PARAMS ((unsigned long, long, int, const char **));
116static long extract_sh6
117 PARAMS ((unsigned long, int, int *));
118static unsigned long insert_spr
119 PARAMS ((unsigned long, long, int, const char **));
120static long extract_spr
121 PARAMS ((unsigned long, int, int *));
122static unsigned long insert_tbr
123 PARAMS ((unsigned long, long, int, const char **));
124static long extract_tbr
125 PARAMS ((unsigned long, int, int *));
126static unsigned long insert_ev2
127 PARAMS ((unsigned long, long, int, const char **));
128static long extract_ev2
129 PARAMS ((unsigned long, int, int *));
130static unsigned long insert_ev4
131 PARAMS ((unsigned long, long, int, const char **));
132static long extract_ev4
133 PARAMS ((unsigned long, int, int *));
134static unsigned long insert_ev8
135 PARAMS ((unsigned long, long, int, const char **));
136static long extract_ev8
137 PARAMS ((unsigned long, int, int *));
138
139
140/* The operands table.
141
142 The fields are bits, shift, insert, extract, flags.
143
144 We used to put parens around the various additions, like the one
145 for BA just below. However, that caused trouble with feeble
146 compilers with a limit on depth of a parenthesized expression, like
147 (reportedly) the compiler in Microsoft Developer Studio 5. So we
148 omit the parens, since the macros are never used in a context where
149 the addition will be ambiguous. */
150
151const struct powerpc_operand powerpc_operands[] =
152{
153 /* The zero index is used to indicate the end of the list of
154 operands. */
155#define UNUSED 0
156 { 0, 0, 0, 0, 0 },
157
158 /* The BA field in an XL form instruction. */
159#define BA UNUSED + 1
160#define BA_MASK (0x1f << 16)
161 { 5, 16, 0, 0, PPC_OPERAND_CR },
162
163 /* The BA field in an XL form instruction when it must be the same
164 as the BT field in the same instruction. */
165#define BAT BA + 1
166 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
167
168 /* The BB field in an XL form instruction. */
169#define BB BAT + 1
170#define BB_MASK (0x1f << 11)
171 { 5, 11, 0, 0, PPC_OPERAND_CR },
172
173 /* The BB field in an XL form instruction when it must be the same
174 as the BA field in the same instruction. */
175#define BBA BB + 1
176 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
177
178 /* The BD field in a B form instruction. The lower two bits are
179 forced to zero. */
180#define BD BBA + 1
181 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
182
183 /* The BD field in a B form instruction when absolute addressing is
184 used. */
185#define BDA BD + 1
186 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
187
188 /* The BD field in a B form instruction when the - modifier is used.
189 This sets the y bit of the BO field appropriately. */
190#define BDM BDA + 1
191 { 16, 0, insert_bdm, extract_bdm,
192 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
193
194 /* The BD field in a B form instruction when the - modifier is used
195 and absolute address is used. */
196#define BDMA BDM + 1
197 { 16, 0, insert_bdm, extract_bdm,
198 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
199
200 /* The BD field in a B form instruction when the + modifier is used.
201 This sets the y bit of the BO field appropriately. */
202#define BDP BDMA + 1
203 { 16, 0, insert_bdp, extract_bdp,
204 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
205
206 /* The BD field in a B form instruction when the + modifier is used
207 and absolute addressing is used. */
208#define BDPA BDP + 1
209 { 16, 0, insert_bdp, extract_bdp,
210 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
211
212 /* The BF field in an X or XL form instruction. */
213#define BF BDPA + 1
214 { 3, 23, 0, 0, PPC_OPERAND_CR },
215
216 /* An optional BF field. This is used for comparison instructions,
217 in which an omitted BF field is taken as zero. */
218#define OBF BF + 1
219 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
220
221 /* The BFA field in an X or XL form instruction. */
222#define BFA OBF + 1
223 { 3, 18, 0, 0, PPC_OPERAND_CR },
224
225 /* The BI field in a B form or XL form instruction. */
226#define BI BFA + 1
227#define BI_MASK (0x1f << 16)
228 { 5, 16, 0, 0, PPC_OPERAND_CR },
229
230 /* The BO field in a B form instruction. Certain values are
231 illegal. */
232#define BO BI + 1
233#define BO_MASK (0x1f << 21)
234 { 5, 21, insert_bo, extract_bo, 0 },
235
236 /* The BO field in a B form instruction when the + or - modifier is
237 used. This is like the BO field, but it must be even. */
238#define BOE BO + 1
239 { 5, 21, insert_boe, extract_boe, 0 },
240
241 /* The BT field in an X or XL form instruction. */
242#define BT BOE + 1
243 { 5, 21, 0, 0, PPC_OPERAND_CR },
244
245 /* The condition register number portion of the BI field in a B form
246 or XL form instruction. This is used for the extended
247 conditional branch mnemonics, which set the lower two bits of the
248 BI field. This field is optional. */
249#define CR BT + 1
250 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
251
252 /* The CRB field in an X form instruction. */
253#define CRB CR + 1
254 { 5, 6, 0, 0, 0 },
255
256 /* The CRFD field in an X form instruction. */
257#define CRFD CRB + 1
258 { 3, 23, 0, 0, PPC_OPERAND_CR },
259
260 /* The CRFS field in an X form instruction. */
261#define CRFS CRFD + 1
262 { 3, 0, 0, 0, PPC_OPERAND_CR },
263
264 /* The CT field in an X form instruction. */
265#define CT CRFS + 1
266 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
267
268 /* The D field in a D form instruction. This is a displacement off
269 a register, and implies that the next operand is a register in
270 parentheses. */
271#define D CT + 1
272 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
273
274 /* The DE field in a DE form instruction. This is like D, but is 12
275 bits only. */
276#define DE D + 1
277 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
278
279 /* The DES field in a DES form instruction. This is like DS, but is 14
280 bits only (12 stored.) */
281#define DES DE + 1
282 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
283
284 /* The DS field in a DS form instruction. This is like D, but the
285 lower two bits are forced to zero. */
286#define DS DES + 1
287 { 16, 0, insert_ds, extract_ds,
288 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
289
290 /* The E field in a wrteei instruction. */
291#define E DS + 1
292 { 1, 15, 0, 0, 0 },
293
294 /* The FL1 field in a POWER SC form instruction. */
295#define FL1 E + 1
296 { 4, 12, 0, 0, 0 },
297
298 /* The FL2 field in a POWER SC form instruction. */
299#define FL2 FL1 + 1
300 { 3, 2, 0, 0, 0 },
301
302 /* The FLM field in an XFL form instruction. */
303#define FLM FL2 + 1
304 { 8, 17, 0, 0, 0 },
305
306 /* The FRA field in an X or A form instruction. */
307#define FRA FLM + 1
308#define FRA_MASK (0x1f << 16)
309 { 5, 16, 0, 0, PPC_OPERAND_FPR },
310
311 /* The FRB field in an X or A form instruction. */
312#define FRB FRA + 1
313#define FRB_MASK (0x1f << 11)
314 { 5, 11, 0, 0, PPC_OPERAND_FPR },
315
316 /* The FRC field in an A form instruction. */
317#define FRC FRB + 1
318#define FRC_MASK (0x1f << 6)
319 { 5, 6, 0, 0, PPC_OPERAND_FPR },
320
321 /* The FRS field in an X form instruction or the FRT field in a D, X
322 or A form instruction. */
323#define FRS FRC + 1
324#define FRT FRS
325 { 5, 21, 0, 0, PPC_OPERAND_FPR },
326
327 /* The FXM field in an XFX instruction. */
328#define FXM FRS + 1
329#define FXM_MASK (0xff << 12)
330 { 8, 12, 0, 0, 0 },
331
332 /* The L field in a D or X form instruction. */
333#define L FXM + 1
334 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
335
336 /* The LEV field in a POWER SC form instruction. */
337#define LEV L + 1
338 { 7, 5, 0, 0, 0 },
339
340 /* The LI field in an I form instruction. The lower two bits are
341 forced to zero. */
342#define LI LEV + 1
343 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
344
345 /* The LI field in an I form instruction when used as an absolute
346 address. */
347#define LIA LI + 1
348 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
349
350 /* The LS field in an X (sync) form instruction. */
351#define LS LIA + 1
352 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
353
354 /* The MB field in an M form instruction. */
355#define MB LS + 1
356#define MB_MASK (0x1f << 6)
357 { 5, 6, 0, 0, 0 },
358
359 /* The ME field in an M form instruction. */
360#define ME MB + 1
361#define ME_MASK (0x1f << 1)
362 { 5, 1, 0, 0, 0 },
363
364 /* The MB and ME fields in an M form instruction expressed a single
365 operand which is a bitmask indicating which bits to select. This
366 is a two operand form using PPC_OPERAND_NEXT. See the
367 description in opcode/ppc.h for what this means. */
368#define MBE ME + 1
369 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
370 { 32, 0, insert_mbe, extract_mbe, 0 },
371
372 /* The MB or ME field in an MD or MDS form instruction. The high
373 bit is wrapped to the low end. */
374#define MB6 MBE + 2
375#define ME6 MB6
376#define MB6_MASK (0x3f << 5)
377 { 6, 5, insert_mb6, extract_mb6, 0 },
378
379 /* The MO field in an mbar instruction. */
380#define MO MB6 + 1
381 { 5, 21, 0, 0, 0 },
382
383 /* The NB field in an X form instruction. The value 32 is stored as
384 0. */
385#define NB MO + 1
386 { 6, 11, insert_nb, extract_nb, 0 },
387
388 /* The NSI field in a D form instruction. This is the same as the
389 SI field, only negated. */
390#define NSI NB + 1
391 { 16, 0, insert_nsi, extract_nsi,
392 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
393
394 /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
395#define RA NSI + 1
396#define RA_MASK (0x1f << 16)
397 { 5, 16, 0, 0, PPC_OPERAND_GPR },
398
399 /* The RA field in a D or X form instruction which is an updating
400 load, which means that the RA field may not be zero and may not
401 equal the RT field. */
402#define RAL RA + 1
403 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
404
405 /* The RA field in an lmw instruction, which has special value
406 restrictions. */
407#define RAM RAL + 1
408 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
409
410 /* The RA field in a D or X form instruction which is an updating
411 store or an updating floating point load, which means that the RA
412 field may not be zero. */
413#define RAS RAM + 1
414 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
415
416 /* The RB field in an X, XO, M, or MDS form instruction. */
417#define RB RAS + 1
418#define RB_MASK (0x1f << 11)
419 { 5, 11, 0, 0, PPC_OPERAND_GPR },
420
421 /* The RB field in an X form instruction when it must be the same as
422 the RS field in the instruction. This is used for extended
423 mnemonics like mr. */
424#define RBS RB + 1
425 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
426
427 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
428 instruction or the RT field in a D, DS, X, XFX or XO form
429 instruction. */
430#define RS RBS + 1
431#define RT RS
432#define RT_MASK (0x1f << 21)
433 { 5, 21, 0, 0, PPC_OPERAND_GPR },
434
435 /* The SH field in an X or M form instruction. */
436#define SH RS + 1
437#define SH_MASK (0x1f << 11)
438 { 5, 11, 0, 0, 0 },
439
440 /* The SH field in an MD form instruction. This is split. */
441#define SH6 SH + 1
442#define SH6_MASK ((0x1f << 11) | (1 << 1))
443 { 6, 1, insert_sh6, extract_sh6, 0 },
444
445 /* The SI field in a D form instruction. */
446#define SI SH6 + 1
447 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
448
449 /* The SI field in a D form instruction when we accept a wide range
450 of positive values. */
451#define SISIGNOPT SI + 1
452 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
453
454 /* The SPR field in an XFX form instruction. This is flipped--the
455 lower 5 bits are stored in the upper 5 and vice- versa. */
456#define SPR SISIGNOPT + 1
457#define PMR SPR
458#define SPR_MASK (0x3ff << 11)
459 { 10, 11, insert_spr, extract_spr, 0 },
460
461 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
462#define SPRBAT SPR + 1
463#define SPRBAT_MASK (0x3 << 17)
464 { 2, 17, 0, 0, 0 },
465
466 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
467#define SPRG SPRBAT + 1
468#define SPRG_MASK (0x3 << 16)
469 { 2, 16, 0, 0, 0 },
470
471 /* The SR field in an X form instruction. */
472#define SR SPRG + 1
473 { 4, 16, 0, 0, 0 },
474
475 /* The STRM field in an X AltiVec form instruction. */
476#define STRM SR + 1
477#define STRM_MASK (0x3 << 21)
478 { 2, 21, 0, 0, 0 },
479
480 /* The SV field in a POWER SC form instruction. */
481#define SV STRM + 1
482 { 14, 2, 0, 0, 0 },
483
484 /* The TBR field in an XFX form instruction. This is like the SPR
485 field, but it is optional. */
486#define TBR SV + 1
487 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
488
489 /* The TO field in a D or X form instruction. */
490#define TO TBR + 1
491#define TO_MASK (0x1f << 21)
492 { 5, 21, 0, 0, 0 },
493
494 /* The U field in an X form instruction. */
495#define U TO + 1
496 { 4, 12, 0, 0, 0 },
497
498 /* The UI field in a D form instruction. */
499#define UI U + 1
500 { 16, 0, 0, 0, 0 },
501
502 /* The VA field in a VA, VX or VXR form instruction. */
503#define VA UI + 1
504#define VA_MASK (0x1f << 16)
505 { 5, 16, 0, 0, PPC_OPERAND_VR },
506
507 /* The VB field in a VA, VX or VXR form instruction. */
508#define VB VA + 1
509#define VB_MASK (0x1f << 11)
510 { 5, 11, 0, 0, PPC_OPERAND_VR },
511
512 /* The VC field in a VA form instruction. */
513#define VC VB + 1
514#define VC_MASK (0x1f << 6)
515 { 5, 6, 0, 0, PPC_OPERAND_VR },
516
517 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
518#define VD VC + 1
519#define VS VD
520#define VD_MASK (0x1f << 21)
521 { 5, 21, 0, 0, PPC_OPERAND_VR },
522
523 /* The SIMM field in a VX form instruction. */
524#define SIMM VD + 1
525 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
526
527 /* The UIMM field in a VX form instruction. */
528#define UIMM SIMM + 1
529 { 5, 16, 0, 0, 0 },
530
531 /* The SHB field in a VA form instruction. */
532#define SHB UIMM + 1
533 { 4, 6, 0, 0, 0 },
534
535 /* The other UIMM field in a EVX form instruction. */
536#define EVUIMM SHB + 1
537 { 5, 11, 0, 0, 0 },
538
539 /* The other UIMM field in a half word EVX form instruction. */
540#define EVUIMM_2 EVUIMM + 1
541 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
542
543 /* The other UIMM field in a word EVX form instruction. */
544#define EVUIMM_4 EVUIMM_2 + 1
545 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
546
547 /* The other UIMM field in a double EVX form instruction. */
548#define EVUIMM_8 EVUIMM_4 + 1
549 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
550
551 /* The WS field. */
552#define WS EVUIMM_8 + 1
553#define WS_MASK (0x7 << 11)
554 { 3, 11, 0, 0, 0 },
555
556 /* The L field in an mtmsrd instruction */
557#define MTMSRD_L WS + 1
558 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
559
560};
561
562/* The functions used to insert and extract complicated operands. */
563
564/* The BA field in an XL form instruction when it must be the same as
565 the BT field in the same instruction. This operand is marked FAKE.
566 The insertion function just copies the BT field into the BA field,
567 and the extraction function just checks that the fields are the
568 same. */
569
570/*ARGSUSED*/
571static unsigned long
572insert_bat (insn, value, dialect, errmsg)
573 unsigned long insn;
574 long value ATTRIBUTE_UNUSED;
575 int dialect ATTRIBUTE_UNUSED;
576 const char **errmsg ATTRIBUTE_UNUSED;
577{
578 return insn | (((insn >> 21) & 0x1f) << 16);
579}
580
581static long
582extract_bat (insn, dialect, invalid)
583 unsigned long insn;
584 int dialect ATTRIBUTE_UNUSED;
585 int *invalid;
586{
587 if (invalid != (int *) NULL
588 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
589 *invalid = 1;
590 return 0;
591}
592
593/* The BB field in an XL form instruction when it must be the same as
594 the BA field in the same instruction. This operand is marked FAKE.
595 The insertion function just copies the BA field into the BB field,
596 and the extraction function just checks that the fields are the
597 same. */
598
599/*ARGSUSED*/
600static unsigned long
601insert_bba (insn, value, dialect, errmsg)
602 unsigned long insn;
603 long value ATTRIBUTE_UNUSED;
604 int dialect ATTRIBUTE_UNUSED;
605 const char **errmsg ATTRIBUTE_UNUSED;
606{
607 return insn | (((insn >> 16) & 0x1f) << 11);
608}
609
610static long
611extract_bba (insn, dialect, invalid)
612 unsigned long insn;
613 int dialect ATTRIBUTE_UNUSED;
614 int *invalid;
615{
616 if (invalid != (int *) NULL
617 && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
618 *invalid = 1;
619 return 0;
620}
621
622/* The BD field in a B form instruction. The lower two bits are
623 forced to zero. */
624
625/*ARGSUSED*/
626static unsigned long
627insert_bd (insn, value, dialect, errmsg)
628 unsigned long insn;
629 long value;
630 int dialect ATTRIBUTE_UNUSED;
631 const char **errmsg ATTRIBUTE_UNUSED;
632{
633 return insn | (value & 0xfffc);
634}
635
636/*ARGSUSED*/
637static long
638extract_bd (insn, dialect, invalid)
639 unsigned long insn;
640 int dialect ATTRIBUTE_UNUSED;
641 int *invalid ATTRIBUTE_UNUSED;
642{
643 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
644}
645
646/* The BD field in a B form instruction when the - modifier is used.
647 This modifier means that the branch is not expected to be taken.
648 For chips built to versions of the architecture prior to version 2
649 (ie. not Power4 compatible), we set the y bit of the BO field to 1
650 if the offset is negative. When extracting, we require that the y
651 bit be 1 and that the offset be positive, since if the y bit is 0
652 we just want to print the normal form of the instruction.
653 Power4 compatible targets use two bits, "a", and "t", instead of
654 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
655 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
656 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
657 for branch on CTR. We only handle the taken/not-taken hint here. */
658
659/*ARGSUSED*/
660static unsigned long
661insert_bdm (insn, value, dialect, errmsg)
662 unsigned long insn;
663 long value;
664 int dialect;
665 const char **errmsg ATTRIBUTE_UNUSED;
666{
667 if ((dialect & PPC_OPCODE_POWER4) == 0)
668 {
669 if ((value & 0x8000) != 0)
670 insn |= 1 << 21;
671 }
672 else
673 {
674 if ((insn & (0x14 << 21)) == (0x04 << 21))
675 insn |= 0x02 << 21;
676 else if ((insn & (0x14 << 21)) == (0x10 << 21))
677 insn |= 0x08 << 21;
678 }
679 return insn | (value & 0xfffc);
680}
681
682static long
683extract_bdm (insn, dialect, invalid)
684 unsigned long insn;
685 int dialect;
686 int *invalid;
687{
688 if (invalid != (int *) NULL)
689 {
690 if ((dialect & PPC_OPCODE_POWER4) == 0)
691 {
692 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
693 *invalid = 1;
694 }
695 else
696 {
697 if ((insn & (0x17 << 21)) != (0x06 << 21)
698 && (insn & (0x1d << 21)) != (0x18 << 21))
699 *invalid = 1;
700 }
701 }
702 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
703}
704
705/* The BD field in a B form instruction when the + modifier is used.
706 This is like BDM, above, except that the branch is expected to be
707 taken. */
708
709/*ARGSUSED*/
710static unsigned long
711insert_bdp (insn, value, dialect, errmsg)
712 unsigned long insn;
713 long value;
714 int dialect;
715 const char **errmsg ATTRIBUTE_UNUSED;
716{
717 if ((dialect & PPC_OPCODE_POWER4) == 0)
718 {
719 if ((value & 0x8000) == 0)
720 insn |= 1 << 21;
721 }
722 else
723 {
724 if ((insn & (0x14 << 21)) == (0x04 << 21))
725 insn |= 0x03 << 21;
726 else if ((insn & (0x14 << 21)) == (0x10 << 21))
727 insn |= 0x09 << 21;
728 }
729 return insn | (value & 0xfffc);
730}
731
732static long
733extract_bdp (insn, dialect, invalid)
734 unsigned long insn;
735 int dialect;
736 int *invalid;
737{
738 if (invalid != (int *) NULL)
739 {
740 if ((dialect & PPC_OPCODE_POWER4) == 0)
741 {
742 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
743 *invalid = 1;
744 }
745 else
746 {
747 if ((insn & (0x17 << 21)) != (0x07 << 21)
748 && (insn & (0x1d << 21)) != (0x19 << 21))
749 *invalid = 1;
750 }
751 }
752 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
753}
754
755/* Check for legal values of a BO field. */
756
757static int
758valid_bo (value, dialect)
759 long value;
760 int dialect;
761{
762 if ((dialect & PPC_OPCODE_POWER4) == 0)
763 {
764 /* Certain encodings have bits that are required to be zero.
765 These are (z must be zero, y may be anything):
766 001zy
767 011zy
768 1z00y
769 1z01y
770 1z1zz
771 */
772 switch (value & 0x14)
773 {
774 default:
775 case 0:
776 return 1;
777 case 0x4:
778 return (value & 0x2) == 0;
779 case 0x10:
780 return (value & 0x8) == 0;
781 case 0x14:
782 return value == 0x14;
783 }
784 }
785 else
786 {
787 /* Certain encodings have bits that are required to be zero.
788 These are (z must be zero, a & t may be anything):
789 0000z
790 0001z
791 0100z
792 0101z
793 001at
794 011at
795 1a00t
796 1a01t
797 1z1zz
798 */
799 if ((value & 0x14) == 0)
800 return (value & 0x1) == 0;
801 else if ((value & 0x14) == 0x14)
802 return value == 0x14;
803 else
804 return 1;
805 }
806}
807
808/* The BO field in a B form instruction. Warn about attempts to set
809 the field to an illegal value. */
810
811static unsigned long
812insert_bo (insn, value, dialect, errmsg)
813 unsigned long insn;
814 long value;
815 int dialect;
816 const char **errmsg;
817{
818 if (errmsg != (const char **) NULL
819 && ! valid_bo (value, dialect))
820 *errmsg = _("invalid conditional option");
821 return insn | ((value & 0x1f) << 21);
822}
823
824static long
825extract_bo (insn, dialect, invalid)
826 unsigned long insn;
827 int dialect;
828 int *invalid;
829{
830 long value;
831
832 value = (insn >> 21) & 0x1f;
833 if (invalid != (int *) NULL
834 && ! valid_bo (value, dialect))
835 *invalid = 1;
836 return value;
837}
838
839/* The BO field in a B form instruction when the + or - modifier is
840 used. This is like the BO field, but it must be even. When
841 extracting it, we force it to be even. */
842
843static unsigned long
844insert_boe (insn, value, dialect, errmsg)
845 unsigned long insn;
846 long value;
847 int dialect;
848 const char **errmsg;
849{
850 if (errmsg != (const char **) NULL)
851 {
852 if (! valid_bo (value, dialect))
853 *errmsg = _("invalid conditional option");
854 else if ((value & 1) != 0)
855 *errmsg = _("attempt to set y bit when using + or - modifier");
856 }
857 return insn | ((value & 0x1f) << 21);
858}
859
860static long
861extract_boe (insn, dialect, invalid)
862 unsigned long insn;
863 int dialect;
864 int *invalid;
865{
866 long value;
867
868 value = (insn >> 21) & 0x1f;
869 if (invalid != (int *) NULL
870 && ! valid_bo (value, dialect))
871 *invalid = 1;
872 return value & 0x1e;
873}
874
875static unsigned long
876insert_ev2 (insn, value, dialect, errmsg)
877 unsigned long insn;
878 long value;
879 int dialect ATTRIBUTE_UNUSED;
880 const char ** errmsg ATTRIBUTE_UNUSED;
881{
882 if ((value & 1) != 0 && errmsg != NULL)
883 *errmsg = _("offset not a multiple of 2");
884 if ((value > 62) != 0 && errmsg != NULL)
885 *errmsg = _("offset greater than 62");
886 return insn | ((value & 0x3e) << 10);
887}
888
889static long
890extract_ev2 (insn, dialect, invalid)
891 unsigned long insn;
892 int dialect ATTRIBUTE_UNUSED;
893 int * invalid ATTRIBUTE_UNUSED;
894{
895 return (insn >> 10) & 0x3e;
896}
897
898static unsigned long
899insert_ev4 (insn, value, dialect, errmsg)
900 unsigned long insn;
901 long value;
902 int dialect ATTRIBUTE_UNUSED;
903 const char ** errmsg ATTRIBUTE_UNUSED;
904{
905 if ((value & 3) != 0 && errmsg != NULL)
906 *errmsg = _("offset not a multiple of 4");
907 if ((value > 124) != 0 && errmsg != NULL)
908 *errmsg = _("offset greater than 124");
909 return insn | ((value & 0x7c) << 9);
910}
911
912static long
913extract_ev4 (insn, dialect, invalid)
914 unsigned long insn;
915 int dialect ATTRIBUTE_UNUSED;
916 int * invalid ATTRIBUTE_UNUSED;
917{
918 return (insn >> 9) & 0x7c;
919}
920
921static unsigned long
922insert_ev8 (insn, value, dialect, errmsg)
923 unsigned long insn;
924 long value;
925 int dialect ATTRIBUTE_UNUSED;
926 const char ** errmsg ATTRIBUTE_UNUSED;
927{
928 if ((value & 7) != 0 && errmsg != NULL)
929 *errmsg = _("offset not a multiple of 8");
930 if ((value > 248) != 0 && errmsg != NULL)
931 *errmsg = _("offset greater than 248");
932 return insn | ((value & 0xf8) << 8);
933}
934
935static long
936extract_ev8 (insn, dialect, invalid)
937 unsigned long insn;
938 int dialect ATTRIBUTE_UNUSED;
939 int * invalid ATTRIBUTE_UNUSED;
940{
941 return (insn >> 8) & 0xf8;
942}
943
944/* The DS field in a DS form instruction. This is like D, but the
945 lower two bits are forced to zero. */
946
947/*ARGSUSED*/
948static unsigned long
949insert_ds (insn, value, dialect, errmsg)
950 unsigned long insn;
951 long value;
952 int dialect ATTRIBUTE_UNUSED;
953 const char **errmsg;
954{
955 if ((value & 3) != 0 && errmsg != NULL)
956 *errmsg = _("offset not a multiple of 4");
957 return insn | (value & 0xfffc);
958}
959
960/*ARGSUSED*/
961static long
962extract_ds (insn, dialect, invalid)
963 unsigned long insn;
964 int dialect ATTRIBUTE_UNUSED;
965 int *invalid ATTRIBUTE_UNUSED;
966{
967 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
968}
969
970/* The DE field in a DE form instruction. */
971
972/*ARGSUSED*/
973static unsigned long
974insert_de (insn, value, dialect, errmsg)
975 unsigned long insn;
976 long value;
977 int dialect ATTRIBUTE_UNUSED;
978 const char **errmsg;
979{
980 if ((value > 2047 || value < -2048) && errmsg != NULL)
981 *errmsg = _("offset not between -2048 and 2047");
982 return insn | ((value << 4) & 0xfff0);
983}
984
985/*ARGSUSED*/
986static long
987extract_de (insn, dialect, invalid)
988 unsigned long insn;
989 int dialect ATTRIBUTE_UNUSED;
990 int *invalid ATTRIBUTE_UNUSED;
991{
992 return (insn & 0xfff0) >> 4;
993}
994
995/* The DES field in a DES form instruction. */
996
997/*ARGSUSED*/
998static unsigned long
999insert_des (insn, value, dialect, errmsg)
1000 unsigned long insn;
1001 long value;
1002 int dialect ATTRIBUTE_UNUSED;
1003 const char **errmsg;
1004{
1005 if ((value > 8191 || value < -8192) && errmsg != NULL)
1006 *errmsg = _("offset not between -8192 and 8191");
1007 else if ((value & 3) != 0 && errmsg != NULL)
1008 *errmsg = _("offset not a multiple of 4");
1009 return insn | ((value << 2) & 0xfff0);
1010}
1011
1012/*ARGSUSED*/
1013static long
1014extract_des (insn, dialect, invalid)
1015 unsigned long insn;
1016 int dialect ATTRIBUTE_UNUSED;
1017 int *invalid ATTRIBUTE_UNUSED;
1018{
1019 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
1020}
1021
1022/* The LI field in an I form instruction. The lower two bits are
1023 forced to zero. */
1024
1025/*ARGSUSED*/
1026static unsigned long
1027insert_li (insn, value, dialect, errmsg)
1028 unsigned long insn;
1029 long value;
1030 int dialect ATTRIBUTE_UNUSED;
1031 const char **errmsg;
1032{
1033 if ((value & 3) != 0 && errmsg != (const char **) NULL)
1034 *errmsg = _("ignoring least significant bits in branch offset");
1035 return insn | (value & 0x3fffffc);
1036}
1037
1038/*ARGSUSED*/
1039static long
1040extract_li (insn, dialect, invalid)
1041 unsigned long insn;
1042 int dialect ATTRIBUTE_UNUSED;
1043 int *invalid ATTRIBUTE_UNUSED;
1044{
1045 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1046}
1047
1048/* The MB and ME fields in an M form instruction expressed as a single
1049 operand which is itself a bitmask. The extraction function always
1050 marks it as invalid, since we never want to recognize an
1051 instruction which uses a field of this type. */
1052
1053static unsigned long
1054insert_mbe (insn, value, dialect, errmsg)
1055 unsigned long insn;
1056 long value;
1057 int dialect ATTRIBUTE_UNUSED;
1058 const char **errmsg;
1059{
1060 unsigned long uval, mask;
1061 int mb, me, mx, count, last;
1062
1063 uval = value;
1064
1065 if (uval == 0)
1066 {
1067 if (errmsg != (const char **) NULL)
1068 *errmsg = _("illegal bitmask");
1069 return insn;
1070 }
1071
1072 mb = 0;
1073 me = 32;
1074 if ((uval & 1) != 0)
1075 last = 1;
1076 else
1077 last = 0;
1078 count = 0;
1079
1080 /* mb: location of last 0->1 transition */
1081 /* me: location of last 1->0 transition */
1082 /* count: # transitions */
1083
1084 for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
1085 {
1086 if ((uval & mask) && !last)
1087 {
1088 ++count;
1089 mb = mx;
1090 last = 1;
1091 }
1092 else if (!(uval & mask) && last)
1093 {
1094 ++count;
1095 me = mx;
1096 last = 0;
1097 }
1098 }
1099 if (me == 0)
1100 me = 32;
1101
1102 if (count != 2 && (count != 0 || ! last))
1103 {
1104 if (errmsg != (const char **) NULL)
1105 *errmsg = _("illegal bitmask");
1106 }
1107
1108 return insn | (mb << 6) | ((me - 1) << 1);
1109}
1110
1111static long
1112extract_mbe (insn, dialect, invalid)
1113 unsigned long insn;
1114 int dialect ATTRIBUTE_UNUSED;
1115 int *invalid;
1116{
1117 long ret;
1118 int mb, me;
1119 int i;
1120
1121 if (invalid != (int *) NULL)
1122 *invalid = 1;
1123
1124 mb = (insn >> 6) & 0x1f;
1125 me = (insn >> 1) & 0x1f;
1126 if (mb < me + 1)
1127 {
1128 ret = 0;
1129 for (i = mb; i <= me; i++)
1130 ret |= (long) 1 << (31 - i);
1131 }
1132 else if (mb == me + 1)
1133 ret = ~0;
1134 else /* (mb > me + 1) */
1135 {
1136 ret = ~ (long) 0;
1137 for (i = me + 1; i < mb; i++)
1138 ret &= ~ ((long) 1 << (31 - i));
1139 }
1140 return ret;
1141}
1142
1143/* The MB or ME field in an MD or MDS form instruction. The high bit
1144 is wrapped to the low end. */
1145
1146/*ARGSUSED*/
1147static unsigned long
1148insert_mb6 (insn, value, dialect, errmsg)
1149 unsigned long insn;
1150 long value;
1151 int dialect ATTRIBUTE_UNUSED;
1152 const char **errmsg ATTRIBUTE_UNUSED;
1153{
1154 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1155}
1156
1157/*ARGSUSED*/
1158static long
1159extract_mb6 (insn, dialect, invalid)
1160 unsigned long insn;
1161 int dialect ATTRIBUTE_UNUSED;
1162 int *invalid ATTRIBUTE_UNUSED;
1163{
1164 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1165}
1166
1167/* The NB field in an X form instruction. The value 32 is stored as
1168 0. */
1169
1170static unsigned long
1171insert_nb (insn, value, dialect, errmsg)
1172 unsigned long insn;
1173 long value;
1174 int dialect ATTRIBUTE_UNUSED;
1175 const char **errmsg;
1176{
1177 if (value < 0 || value > 32)
1178 *errmsg = _("value out of range");
1179 if (value == 32)
1180 value = 0;
1181 return insn | ((value & 0x1f) << 11);
1182}
1183
1184/*ARGSUSED*/
1185static long
1186extract_nb (insn, dialect, invalid)
1187 unsigned long insn;
1188 int dialect ATTRIBUTE_UNUSED;
1189 int *invalid ATTRIBUTE_UNUSED;
1190{
1191 long ret;
1192
1193 ret = (insn >> 11) & 0x1f;
1194 if (ret == 0)
1195 ret = 32;
1196 return ret;
1197}
1198
1199/* The NSI field in a D form instruction. This is the same as the SI
1200 field, only negated. The extraction function always marks it as
1201 invalid, since we never want to recognize an instruction which uses
1202 a field of this type. */
1203
1204/*ARGSUSED*/
1205static unsigned long
1206insert_nsi (insn, value, dialect, errmsg)
1207 unsigned long insn;
1208 long value;
1209 int dialect ATTRIBUTE_UNUSED;
1210 const char **errmsg ATTRIBUTE_UNUSED;
1211{
1212 return insn | ((- value) & 0xffff);
1213}
1214
1215static long
1216extract_nsi (insn, dialect, invalid)
1217 unsigned long insn;
1218 int dialect ATTRIBUTE_UNUSED;
1219 int *invalid;
1220{
1221 if (invalid != (int *) NULL)
1222 *invalid = 1;
1223 return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
1224}
1225
1226/* The RA field in a D or X form instruction which is an updating
1227 load, which means that the RA field may not be zero and may not
1228 equal the RT field. */
1229
1230static unsigned long
1231insert_ral (insn, value, dialect, errmsg)
1232 unsigned long insn;
1233 long value;
1234 int dialect ATTRIBUTE_UNUSED;
1235 const char **errmsg;
1236{
1237 if (value == 0
1238 || (unsigned long) value == ((insn >> 21) & 0x1f))
1239 *errmsg = "invalid register operand when updating";
1240 return insn | ((value & 0x1f) << 16);
1241}
1242
1243/* The RA field in an lmw instruction, which has special value
1244 restrictions. */
1245
1246static unsigned long
1247insert_ram (insn, value, dialect, errmsg)
1248 unsigned long insn;
1249 long value;
1250 int dialect ATTRIBUTE_UNUSED;
1251 const char **errmsg;
1252{
1253 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1254 *errmsg = _("index register in load range");
1255 return insn | ((value & 0x1f) << 16);
1256}
1257
1258/* The RA field in a D or X form instruction which is an updating
1259 store or an updating floating point load, which means that the RA
1260 field may not be zero. */
1261
1262static unsigned long
1263insert_ras (insn, value, dialect, errmsg)
1264 unsigned long insn;
1265 long value;
1266 int dialect ATTRIBUTE_UNUSED;
1267 const char **errmsg;
1268{
1269 if (value == 0)
1270 *errmsg = _("invalid register operand when updating");
1271 return insn | ((value & 0x1f) << 16);
1272}
1273
1274/* The RB field in an X form instruction when it must be the same as
1275 the RS field in the instruction. This is used for extended
1276 mnemonics like mr. This operand is marked FAKE. The insertion
1277 function just copies the BT field into the BA field, and the
1278 extraction function just checks that the fields are the same. */
1279
1280/*ARGSUSED*/
1281static unsigned long
1282insert_rbs (insn, value, dialect, errmsg)
1283 unsigned long insn;
1284 long value ATTRIBUTE_UNUSED;
1285 int dialect ATTRIBUTE_UNUSED;
1286 const char **errmsg ATTRIBUTE_UNUSED;
1287{
1288 return insn | (((insn >> 21) & 0x1f) << 11);
1289}
1290
1291static long
1292extract_rbs (insn, dialect, invalid)
1293 unsigned long insn;
1294 int dialect ATTRIBUTE_UNUSED;
1295 int *invalid;
1296{
1297 if (invalid != (int *) NULL
1298 && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1299 *invalid = 1;
1300 return 0;
1301}
1302
1303/* The SH field in an MD form instruction. This is split. */
1304
1305/*ARGSUSED*/
1306static unsigned long
1307insert_sh6 (insn, value, dialect, errmsg)
1308 unsigned long insn;
1309 long value;
1310 int dialect ATTRIBUTE_UNUSED;
1311 const char **errmsg ATTRIBUTE_UNUSED;
1312{
1313 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1314}
1315
1316/*ARGSUSED*/
1317static long
1318extract_sh6 (insn, dialect, invalid)
1319 unsigned long insn;
1320 int dialect ATTRIBUTE_UNUSED;
1321 int *invalid ATTRIBUTE_UNUSED;
1322{
1323 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1324}
1325
1326/* The SPR field in an XFX form instruction. This is flipped--the
1327 lower 5 bits are stored in the upper 5 and vice- versa. */
1328
1329static unsigned long
1330insert_spr (insn, value, dialect, errmsg)
1331 unsigned long insn;
1332 long value;
1333 int dialect ATTRIBUTE_UNUSED;
1334 const char **errmsg ATTRIBUTE_UNUSED;
1335{
1336 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1337}
1338
1339static long
1340extract_spr (insn, dialect, invalid)
1341 unsigned long insn;
1342 int dialect ATTRIBUTE_UNUSED;
1343 int *invalid ATTRIBUTE_UNUSED;
1344{
1345 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1346}
1347
1348/* The TBR field in an XFX instruction. This is just like SPR, but it
1349 is optional. When TBR is omitted, it must be inserted as 268 (the
1350 magic number of the TB register). These functions treat 0
1351 (indicating an omitted optional operand) as 268. This means that
1352 ``mftb 4,0'' is not handled correctly. This does not matter very
1353 much, since the architecture manual does not define mftb as
1354 accepting any values other than 268 or 269. */
1355
1356#define TB (268)
1357
1358static unsigned long
1359insert_tbr (insn, value, dialect, errmsg)
1360 unsigned long insn;
1361 long value;
1362 int dialect ATTRIBUTE_UNUSED;
1363 const char **errmsg ATTRIBUTE_UNUSED;
1364{
1365 if (value == 0)
1366 value = TB;
1367 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1368}
1369
1370static long
1371extract_tbr (insn, dialect, invalid)
1372 unsigned long insn;
1373 int dialect ATTRIBUTE_UNUSED;
1374 int *invalid ATTRIBUTE_UNUSED;
1375{
1376 long ret;
1377
1378 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1379 if (ret == TB)
1380 ret = 0;
1381 return ret;
1382}
1383
1384
1385/* Macros used to form opcodes. */
1386
1387/* The main opcode. */
1388#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1389#define OP_MASK OP (0x3f)
1390
1391/* The main opcode combined with a trap code in the TO field of a D
1392 form instruction. Used for extended mnemonics for the trap
1393 instructions. */
1394#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1395#define OPTO_MASK (OP_MASK | TO_MASK)
1396
1397/* The main opcode combined with a comparison size bit in the L field
1398 of a D form or X form instruction. Used for extended mnemonics for
1399 the comparison instructions. */
1400#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1401#define OPL_MASK OPL (0x3f,1)
1402
1403/* An A form instruction. */
1404#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1405#define A_MASK A (0x3f, 0x1f, 1)
1406
1407/* An A_MASK with the FRB field fixed. */
1408#define AFRB_MASK (A_MASK | FRB_MASK)
1409
1410/* An A_MASK with the FRC field fixed. */
1411#define AFRC_MASK (A_MASK | FRC_MASK)
1412
1413/* An A_MASK with the FRA and FRC fields fixed. */
1414#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1415
1416/* A B form instruction. */
1417#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1418#define B_MASK B (0x3f, 1, 1)
1419
1420/* A B form instruction setting the BO field. */
1421#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1422#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1423
1424/* A BBO_MASK with the y bit of the BO field removed. This permits
1425 matching a conditional branch regardless of the setting of the y
1426 bit. Similarly for the 'at' bits used for power4 branch hints. */
1427#define Y_MASK (((unsigned long) 1) << 21)
1428#define AT1_MASK (((unsigned long) 3) << 21)
1429#define AT2_MASK (((unsigned long) 9) << 21)
1430#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1431#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1432
1433/* A B form instruction setting the BO field and the condition bits of
1434 the BI field. */
1435#define BBOCB(op, bo, cb, aa, lk) \
1436 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1437#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1438
1439/* A BBOCB_MASK with the y bit of the BO field removed. */
1440#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1441#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1442#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1443
1444/* A BBOYCB_MASK in which the BI field is fixed. */
1445#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1446#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1447
1448/* An Context form instruction. */
1449#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1450#define CTX_MASK CTX(0x3f, 0x7)
1451
1452/* An User Context form instruction. */
1453#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1454#define UCTX_MASK UCTX(0x3f, 0x1f)
1455
1456/* The main opcode mask with the RA field clear. */
1457#define DRA_MASK (OP_MASK | RA_MASK)
1458
1459/* A DS form instruction. */
1460#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1461#define DS_MASK DSO (0x3f, 3)
1462
1463/* A DE form instruction. */
1464#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1465#define DE_MASK DEO (0x3e, 0xf)
1466
1467/* An EVSEL form instruction. */
1468#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1469#define EVSEL_MASK EVSEL(0x3f, 0xff)
1470
1471/* An M form instruction. */
1472#define M(op, rc) (OP (op) | ((rc) & 1))
1473#define M_MASK M (0x3f, 1)
1474
1475/* An M form instruction with the ME field specified. */
1476#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1477
1478/* An M_MASK with the MB and ME fields fixed. */
1479#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1480
1481/* An M_MASK with the SH and ME fields fixed. */
1482#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1483
1484/* An MD form instruction. */
1485#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1486#define MD_MASK MD (0x3f, 0x7, 1)
1487
1488/* An MD_MASK with the MB field fixed. */
1489#define MDMB_MASK (MD_MASK | MB6_MASK)
1490
1491/* An MD_MASK with the SH field fixed. */
1492#define MDSH_MASK (MD_MASK | SH6_MASK)
1493
1494/* An MDS form instruction. */
1495#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1496#define MDS_MASK MDS (0x3f, 0xf, 1)
1497
1498/* An MDS_MASK with the MB field fixed. */
1499#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1500
1501/* An SC form instruction. */
1502#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1503#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1504
1505/* An VX form instruction. */
1506#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1507
1508/* The mask for an VX form instruction. */
1509#define VX_MASK VX(0x3f, 0x7ff)
1510
1511/* An VA form instruction. */
1512#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1513
1514/* The mask for an VA form instruction. */
1515#define VXA_MASK VXA(0x3f, 0x3f)
1516
1517/* An VXR form instruction. */
1518#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1519
1520/* The mask for a VXR form instruction. */
1521#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1522
1523/* An X form instruction. */
1524#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1525
1526/* An X form instruction with the RC bit specified. */
1527#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1528
1529/* The mask for an X form instruction. */
1530#define X_MASK XRC (0x3f, 0x3ff, 1)
1531
1532/* An X_MASK with the RA field fixed. */
1533#define XRA_MASK (X_MASK | RA_MASK)
1534
1535/* An X_MASK with the RB field fixed. */
1536#define XRB_MASK (X_MASK | RB_MASK)
1537
1538/* An X_MASK with the RT field fixed. */
1539#define XRT_MASK (X_MASK | RT_MASK)
1540
1541/* An X_MASK with the RA and RB fields fixed. */
1542#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1543
1544/* An XRARB_MASK, but with the L bit clear. */
1545#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1546
1547/* An X_MASK with the RT and RA fields fixed. */
1548#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1549
1550/* An XRTRA_MASK, but with L bit clear. */
1551#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1552
1553/* An X form comparison instruction. */
1554#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1555
1556/* The mask for an X form comparison instruction. */
1557#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1558
1559/* The mask for an X form comparison instruction with the L field
1560 fixed. */
1561#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1562
1563/* An X form trap instruction with the TO field specified. */
1564#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1565#define XTO_MASK (X_MASK | TO_MASK)
1566
1567/* An X form tlb instruction with the SH field specified. */
1568#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1569#define XTLB_MASK (X_MASK | SH_MASK)
1570
1571/* An X form sync instruction. */
1572#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1573
1574/* An X form sync instruction with everything filled in except the LS field. */
1575#define XSYNC_MASK (0xff9fffff)
1576
1577/* An X form AltiVec dss instruction. */
1578#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1579#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1580
1581/* An XFL form instruction. */
1582#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1583#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1584
1585/* An X form isel instruction. */
1586#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1587#define XISEL_MASK XISEL(0x3f, 0x1f)
1588
1589/* An XL form instruction with the LK field set to 0. */
1590#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1591
1592/* An XL form instruction which uses the LK field. */
1593#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1594
1595/* The mask for an XL form instruction. */
1596#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1597
1598/* An XL form instruction which explicitly sets the BO field. */
1599#define XLO(op, bo, xop, lk) \
1600 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1601#define XLO_MASK (XL_MASK | BO_MASK)
1602
1603/* An XL form instruction which explicitly sets the y bit of the BO
1604 field. */
1605#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1606#define XLYLK_MASK (XL_MASK | Y_MASK)
1607
1608/* An XL form instruction which sets the BO field and the condition
1609 bits of the BI field. */
1610#define XLOCB(op, bo, cb, xop, lk) \
1611 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1612#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1613
1614/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1615#define XLBB_MASK (XL_MASK | BB_MASK)
1616#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1617#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1618
1619/* An XL_MASK with the BO and BB fields fixed. */
1620#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1621
1622/* An XL_MASK with the BO, BI and BB fields fixed. */
1623#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1624
1625/* An XO form instruction. */
1626#define XO(op, xop, oe, rc) \
1627 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1628#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1629
1630/* An XO_MASK with the RB field fixed. */
1631#define XORB_MASK (XO_MASK | RB_MASK)
1632
1633/* An XS form instruction. */
1634#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1635#define XS_MASK XS (0x3f, 0x1ff, 1)
1636
1637/* A mask for the FXM version of an XFX form instruction. */
1638#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
1639
1640/* An XFX form instruction with the FXM field filled in. */
1641#define XFXM(op, xop, fxm) \
1642 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1643
1644/* An XFX form instruction with the SPR field filled in. */
1645#define XSPR(op, xop, spr) \
1646 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1647#define XSPR_MASK (X_MASK | SPR_MASK)
1648
1649/* An XFX form instruction with the SPR field filled in except for the
1650 SPRBAT field. */
1651#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1652
1653/* An XFX form instruction with the SPR field filled in except for the
1654 SPRG field. */
1655#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1656
1657/* An X form instruction with everything filled in except the E field. */
1658#define XE_MASK (0xffff7fff)
1659
1660/* An X form user context instruction. */
1661#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1662#define XUC_MASK XUC(0x3f, 0x1f)
1663
1664/* The BO encodings used in extended conditional branch mnemonics. */
1665#define BODNZF (0x0)
1666#define BODNZFP (0x1)
1667#define BODZF (0x2)
1668#define BODZFP (0x3)
1669#define BODNZT (0x8)
1670#define BODNZTP (0x9)
1671#define BODZT (0xa)
1672#define BODZTP (0xb)
1673
1674#define BOF (0x4)
1675#define BOFP (0x5)
1676#define BOFM4 (0x6)
1677#define BOFP4 (0x7)
1678#define BOT (0xc)
1679#define BOTP (0xd)
1680#define BOTM4 (0xe)
1681#define BOTP4 (0xf)
1682
1683#define BODNZ (0x10)
1684#define BODNZP (0x11)
1685#define BODZ (0x12)
1686#define BODZP (0x13)
1687#define BODNZM4 (0x18)
1688#define BODNZP4 (0x19)
1689#define BODZM4 (0x1a)
1690#define BODZP4 (0x1b)
1691
1692#define BOU (0x14)
1693
1694/* The BI condition bit encodings used in extended conditional branch
1695 mnemonics. */
1696#define CBLT (0)
1697#define CBGT (1)
1698#define CBEQ (2)
1699#define CBSO (3)
1700
1701/* The TO encodings used in extended trap mnemonics. */
1702#define TOLGT (0x1)
1703#define TOLLT (0x2)
1704#define TOEQ (0x4)
1705#define TOLGE (0x5)
1706#define TOLNL (0x5)
1707#define TOLLE (0x6)
1708#define TOLNG (0x6)
1709#define TOGT (0x8)
1710#define TOGE (0xc)
1711#define TONL (0xc)
1712#define TOLT (0x10)
1713#define TOLE (0x14)
1714#define TONG (0x14)
1715#define TONE (0x18)
1716#define TOU (0x1f)
1717
1718
1719/* Smaller names for the flags so each entry in the opcodes table will
1720 fit on a single line. */
1721#undef PPC
1722#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
1723#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1724#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1725#define POWER4 PPC_OPCODE_POWER4 | PPCCOM
1726#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1727#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
1728#define PPCONLY PPC_OPCODE_PPC
1729#define PPC403 PPC_OPCODE_403
1730#define PPC405 PPC403
1731#define PPC750 PPC
1732#define PPC860 PPC
1733#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
1734#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
1735#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1736#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
1737#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
1738#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1739#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
1740#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
1741#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
1742#define MFDEC1 PPC_OPCODE_POWER
1743#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1744#define BOOKE PPC_OPCODE_BOOKE
1745#define BOOKE64 PPC_OPCODE_BOOKE64
1746#define CLASSIC PPC_OPCODE_CLASSIC
1747#define PPCSPE PPC_OPCODE_SPE
1748#define PPCISEL PPC_OPCODE_ISEL
1749#define PPCEFS PPC_OPCODE_EFS
1750#define PPCBRLK PPC_OPCODE_BRLOCK
1751#define PPCPMR PPC_OPCODE_PMR
1752#define PPCCHLK PPC_OPCODE_CACHELCK
1753#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1754#define PPCRFMCI PPC_OPCODE_RFMCI
1755
1756
1757/* The opcode table.
1758
1759 The format of the opcode table is:
1760
1761 NAME OPCODE MASK FLAGS { OPERANDS }
1762
1763 NAME is the name of the instruction.
1764 OPCODE is the instruction opcode.
1765 MASK is the opcode mask; this is used to tell the disassembler
1766 which bits in the actual opcode must match OPCODE.
1767 FLAGS are flags indicated what processors support the instruction.
1768 OPERANDS is the list of operands.
1769
1770 The disassembler reads the table in order and prints the first
1771 instruction which matches, so this table is sorted to put more
1772 specific instructions before more general instructions. It is also
1773 sorted by major opcode. */
1774
1775const struct powerpc_opcode powerpc_opcodes[] = {
1776{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1777{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1778{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1779{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1780{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1781{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1782{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1783{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1784{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1785{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1786{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1787{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1788{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1789{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1790{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1791
1792{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1793{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1794{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1795{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1796{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1797{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1798{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1799{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1800{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1801{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1802{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1803{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1804{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1805{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1806{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1807{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1808{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1809{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1810{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1811{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1812{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1813{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1814{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1815{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1816{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1817{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1818{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1819{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1820{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1821{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1822
1823{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1824{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1825{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1826{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1827{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1828{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1829{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1830{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1831{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1832{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1833{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1834{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1835{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1836{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1837{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1838{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1839{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1840{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1841{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1842{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1843{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1844{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1845{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1846{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1847{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1848{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1849{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1850{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1851{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1852{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1853{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1854{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1855{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1856{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1857{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1858{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1859{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1860{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1861{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1862{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1863{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1864{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1865{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1866{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1867{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1868{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1869{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1870{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1871{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
1872{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
1873{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
1874{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
1875{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
1876{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
1877{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
1878{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
1879{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
1880{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
1881{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
1882{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
1883{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1884{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1885{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1886{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1887{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1888{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1889{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1890{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1891{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1892{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1893{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1894{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1895{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1896{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1897{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1898{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1899{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1900{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1901{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1902{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1903{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
1904{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
1905{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
1906{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
1907{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1908{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1909{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1910{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1911{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1912{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1913{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1914{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1915{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1916{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1917{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1918{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1919{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1920{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1921{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1922{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1923{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1924{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1925{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1926{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1927{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1928{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1929{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1930{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1931{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1932{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1933{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1934{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1935{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1936{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1937{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1938{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1939{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1940{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1941{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1942{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1943{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1944{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1945{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1946{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1947{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1948{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1949{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1950{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1951{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1952{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1953{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1954{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1955{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1956{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1957{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1958{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1959{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1960{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1961{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1962{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1963{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1964{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1965{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1966{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1967{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1968{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1969{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1970{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1971{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1972{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1973{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1974{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1975{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1976{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1977{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1978{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1979{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1980{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1981{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1982{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1983{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1984{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1985{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1986{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1987{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1988{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1989{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1990{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1991{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1992{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1993{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1994{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1995{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1996{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1997{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1998{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1999{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2000{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2001{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2002{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2003{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2004{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2005{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2006{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2007{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2008{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2009{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2010{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2011{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2012{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2013{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2014{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2015{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2016{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2017{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2018{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2019{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2020{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2021{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2022{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2023{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2024{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2025{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2026{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2027{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2028{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2029{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2030{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2031{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2032{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2033{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2034{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2035{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2036{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2037{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2038{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2039{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2040{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2041{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2042{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2043{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2044{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2045{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2046{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2047{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2048{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2049{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2050{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2051{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2052{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2053{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2054{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2055{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2056{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2057{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2058{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2059{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2060{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2061{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2062{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2063{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2064
2065{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2066{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2067{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2068{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2069{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2070{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2071{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2072{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2073{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2074{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2075{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2076{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2077{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2078
2079{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2080
2081{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2082{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2083{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2084{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2085{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2086{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2087{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2088{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2089{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2090{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2091
2092{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2093{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2094{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2095{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2096{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2097{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2098{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2099{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2100{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2101{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2102{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2103{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2104{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2105{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2106
2107{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2108{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2109{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2110{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2111{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2112{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2113
2114{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2115{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2116{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2117{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2118{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2119{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2120{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2121{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2122{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2123{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2124{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2125{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2126{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2127{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2128{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2129{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2130{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2131{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2132{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2133{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2134{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2135{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2136
2137{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2138{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2139{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2140{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2141{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2142{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2143{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2144{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2145{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2146{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2147{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2148{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2149{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2150{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2151
2152{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2153{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2154{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2155{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2156{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2157{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2158{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2159{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2160{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2161{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2162{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2163{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2164{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2165{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2166{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2167{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2168{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2169{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2170{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2171{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2172{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2173{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2174{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2175
2176{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2177{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2178{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2179{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2180{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2181{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2182{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2183{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2184{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2185{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2186{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2187{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2188{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2189{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2190{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2191{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2192{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2193{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2194{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2195{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2196{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2197{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2198{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2199
2200{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2201{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2202{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2203{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2204{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2205{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2206{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2207{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2208{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2209{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2210{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2211{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2212{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2213{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2214{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2215{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2216
2217{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2218{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2219{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2220{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2221{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2222{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2223{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2224{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2225{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2226{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2227{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2228{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2229
2230{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2231{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2232{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2233{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2234{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2235{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2236{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2237{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2238{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2239{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2240{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2241{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2242
2243{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2244{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2245{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2246{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2247{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2248{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2249
2250{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2251{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2252{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2253{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2254{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2255{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2256
2257{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2258{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2259{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2260{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2261{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2262{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2263{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2264{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2265
2266{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2267{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2268
2269{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2270{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2271{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2272{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2273
2274{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2275{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2276{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2277{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2278
2279{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2280{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2281{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2282{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2283{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2284{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2285{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2286{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2287
2288{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2289{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2290{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2291{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2292
2293{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2294{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2295{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2296{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2297
2298{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2299{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2300{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2301{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2302
2303{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2304{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2305{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2306{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2307
2308{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2309
2310{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2311{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2312
2313{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2314{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2315
2316{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2317{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2318
2319{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2320
2321{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2322{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2323{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2324{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2325
2326{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2327{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2328{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
2329{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2330
2331{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2332{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2333{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
2334{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2335
2336{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2337{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2338{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2339
2340{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2341{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2342{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2343
2344{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2345{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2346{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2347{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2348{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2349{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2350
2351{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2352{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2353{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2354{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2355{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2356
2357{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2358{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2359{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2360{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2361{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2362{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2363{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2364{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2365{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2366{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2367{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2368{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2369{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2370{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2371{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2372{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2373{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2374{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2375{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2376{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2377{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2378{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2379{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2380{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2381{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2382{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2383{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2384{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2385{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2386{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2387{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2388{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2389{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2390{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2391{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2392{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2393{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2394{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2395{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2396{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2397{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2398{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2399{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2400{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2401{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2402{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2403{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2404{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2405{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2406{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2407{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2408{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2409{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2410{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2411{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2412{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2413{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2414{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2415{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2416{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2417{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2418{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2419{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2420{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2421{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2422{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2423{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2424{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2425{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2426{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2427{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2428{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2429{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2430{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2431{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2432{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2433{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2434{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2435{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2436{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2437{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2438{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2439{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2440{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2441{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2442{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2443{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2444{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2445{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2446{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2447{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2448{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2449{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2450{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2451{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2452{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2453{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2454{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2455{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2456{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2457{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2458{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2459{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2460{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2461{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2462{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2463{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2464{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2465{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2466{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2467{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2468{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2469{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2470{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2471{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2472{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2473{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2474{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2475{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2476{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2477{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2478{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2479{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2480{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2481{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2482{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2483{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2484{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2485{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2486{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2487{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2488{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2489{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2490{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2491{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2492{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2493{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2494{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2495{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2496{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2497{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2498{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2499{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2500{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2501{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2502{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2503{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2504{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2505{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2506{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2507{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2508{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2509{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2510{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2511{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2512{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2513{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2514{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2515{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2516{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2517{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2518{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2519{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2520{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2521{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2522{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2523{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2524{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2525{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2526{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2527{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2528{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2529{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2530{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2531{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2532{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2533{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2534{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2535{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2536{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2537{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2538{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2539{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2540{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2541{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2542{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2543{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2544{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2545{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2546{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2547{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2548{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2549{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2550{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2551{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2552{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2553{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2554{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2555{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2556{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2557{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2558{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2559{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2560{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2561{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2562{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2563{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2564{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2565{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2566{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2567{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2568{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2569{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2570{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2571{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2572{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2573{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2574{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2575{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2576{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2577{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2578{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2579{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2580{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2581{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2582{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2583{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2584{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2585{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2586{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2587{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2588{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2589{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2590{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2591{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2592{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2593{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2594{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2595{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2596{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2597{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2598{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2599{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2600{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2601{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2602{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2603{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2604{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2605{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2606{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2607{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2608{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2609{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2610{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2611{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2612{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2613{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2614{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2615{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2616{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2617{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2618{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2619{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2620{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2621
2622{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2623{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2624{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2625{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2626{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2627
2628{ "b", B(18,0,0), B_MASK, COM, { LI } },
2629{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2630{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2631{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
2632
2633{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2634
2635{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2636{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2637{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2638{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2639{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2640{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2641{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2642{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2643{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2644{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2645{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2646{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2647{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2648{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2649{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2650{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2651{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2652{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2653{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2654{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2655{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2656{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2657{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2658{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2659{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2660{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2661{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2662{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2663{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2664{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2665{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2666{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2667{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2668{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2669{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2670{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2671{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2672{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2673{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2674{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2675{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2676{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2677{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2678{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2679{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2680{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2681{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2682{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2683{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2684{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2685{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2686{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2687{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2688{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2689{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2690{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2691{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2692{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2693{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2694{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2695{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2696{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2697{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2698{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2699{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2700{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2701{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2702{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2703{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2704{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2705{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2706{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2707{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2708{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2710{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2711{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2712{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2713{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2714{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2716{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2717{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2718{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2719{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2720{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2721{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2722{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2723{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2724{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2725{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2727{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2728{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2729{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2730{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2731{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2733{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2734{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2735{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2736{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2737{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2738{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2739{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2740{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2741{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2742{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2743{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2744{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2745{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2746{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2747{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2748{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2749{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2750{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2751{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2752{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2753{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2754{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2755{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2756{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2757{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2758{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2759{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2760{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2762{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2763{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2764{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2765{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2766{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2767{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2768{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2769{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2770{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2771{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2772{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2773{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2774{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2775{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2776{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2777{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2778{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2779{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2780{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2781{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2782{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2783{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2784{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2785{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2786{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2787{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2788{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2789{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2790{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2791{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2792{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2793{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2794{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2795{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2796{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2797{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2798{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2799{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2800{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2801{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2802{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2803{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2804{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2805{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2806{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2807{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2808{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2809{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2810{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2811{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2812{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2813{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2814{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2815{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2816{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2817{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2818{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2819{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2820{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2821{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2822{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2823{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2824{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2825{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2826{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2827{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2828{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2829{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2830{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2831{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2832{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2833{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2834{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2835{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2836{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2837{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2838{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2839{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2840{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2841{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2842{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2843{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2844{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2845{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2846{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2847{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2848{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2849{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2850{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2851{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2852{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2853{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2854{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2855{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2856{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2857
2858{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2859
2860{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2861{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2862{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2863
2864{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2865{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
2866{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } },
2867
2868{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2869
2870{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2871
2872{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2873{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2874
2875{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2876{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2877
2878{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2879
2880{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2881
2882{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2883{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2884
2885{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2886
2887{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2888{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2889
2890{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2891{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2892{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2893{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2894{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2895{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2896{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2897{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2898{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2899{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2900{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2901{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2902{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2903{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2904{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2905{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2906{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2907{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2908{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2909{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2910{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2911{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2912{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2913{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2914{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2915{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2916{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2917{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2918{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2919{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2920{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2921{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2922{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2923{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2924{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2925{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2926{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2927{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2928{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2929{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2930{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2931{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2932{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2933{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2934{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2935{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2936{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2937{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2938{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2939{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2941{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2942{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2943{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2944{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2946{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2947{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2948{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2951{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2952{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2953{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2954{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2956{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2957{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2958{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2959{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2961{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2962{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2963{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2964{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2966{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2967{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2968{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2969{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2971{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2972{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2973{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2974{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2976{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2977{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2978{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2981{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2982{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2983{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2984{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2986{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2987{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2988{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2989{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2991{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2992{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2993{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2994{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2996{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2997{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2998{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2999{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3001{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3002{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3003{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3004{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3006{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3007{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3008{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3009{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3010{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3011{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3012{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3013{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3014{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3015{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3016{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3017{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3018{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3019{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3020{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3021{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3022{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3023{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3024{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3025{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3026{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3027{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3028{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3029{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3030{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3031{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3032{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3033{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3034{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3035{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3036{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3037{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3038{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3039{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3040{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3041{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3042
3043{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3044{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3045
3046{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3047{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3048
3049{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3050{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3051{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3052{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3053{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3054{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3055{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3056{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3057
3058{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3059{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3060
3061{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3062{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3063{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3064{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3065
3066{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3067{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3068{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3069{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3070{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3071{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3072
3073{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3074{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3075{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3076
3077{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3078{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3079
3080{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3081{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3082
3083{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3084{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3085
3086{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3087{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3088
3089{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3090{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3091
3092{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3093{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3094{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3095{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3096{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3097{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3098
3099{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3100{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3101
3102{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3103{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3104
3105{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3106{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3107
3108{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3109{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3110{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3111{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3112
3113{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3114{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3115
3116{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3117{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3118{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3119{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3120
3121{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3122{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3123{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3124{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3125{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3126{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3127{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3128{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3129{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3130{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3131{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3132{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3133{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3134{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3135{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3136{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3137{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3138{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3139{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3140{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3141{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3142{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3143{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3144{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3145{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3146{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3147{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3148{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3149{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3150{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3151{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3152
3153{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3154{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3155{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3156{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3157{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3158{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3159{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3160{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3161{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3162{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3163{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3164{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3165
3166{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3167{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3168
3169{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3170{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3171{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3172{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3173{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3174{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3175{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3176{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3177
3178{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3179{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3180
3181{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3182{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3183{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3184{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3185
3186{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } },
3187
3188{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3189
3190{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3191
3192{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3193
3194{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3195{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3196
3197{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3198{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3199{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3200{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3201
3202{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3203{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3204{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3205{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3206
3207{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3208{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3209
3210{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3211{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3212
3213{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3214{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3215
3216{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3217
3218{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3219
3220{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3221{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3222{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
3223{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3224
3225{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3226{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3227{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3228{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3229{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3230{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3231{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3232{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3233
3234{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3235
3236{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3237
3238{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3239{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3240
3241{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3242
3243{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3244
3245{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3246{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3247
3248{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3249{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3250
3251{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3252{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3253{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3254{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3255{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3256{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3257{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3258{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3259{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3260{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3261{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3262{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3263{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3264{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3265{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3266
3267{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3268{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3269
3270{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3271{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3272
3273{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3274
3275{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3276
3277{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3278
3279{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3280
3281{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3282
3283{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3284
3285{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3286
3287{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3288{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3289{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3290{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3291
3292{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3293{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3294{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3295{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3296
3297{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3298
3299{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3300
3301{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3302
3303{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3304{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3305{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3306{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3307
3308{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3309
3310{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3311
3312{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
3313{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } },
3314
3315{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3316
3317{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3318{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3319{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3320{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3321{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3322{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3323{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3324{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3325
3326{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3327{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3328{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3329{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3330{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3331{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3332{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3333{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3334
3335{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3336
3337{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }},
3338{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3339
3340{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3341
3342{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3343
3344{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3345
3346{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3347{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3348
3349{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3350
3351{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3352
3353{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3354{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3355
3356{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3357{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3358
3359{ "wrteei", X(31,163), XE_MASK, PPC403, { E } },
3360{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } },
3361
3362{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3363{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3364
3365{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3366
3367{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3368
3369{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3370{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3371
3372{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3373{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3374
3375{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3376
3377{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3378{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3379{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3380{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3381{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3382{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3383{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3384{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3385
3386{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3387{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3388{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3389{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3390{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3391{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3392{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3393{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3394
3395{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3396
3397{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3398
3399{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
3400
3401{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3402{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3403
3404{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3405{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3406
3407{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3408
3409{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3410
3411{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3412{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3413{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3414{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3415{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3416{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3417{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3418{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3419
3420{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3421{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3422{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3423{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3424
3425{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3426{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3427{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3428{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3429{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3430{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3431{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3432{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3433
3434{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3435{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3436{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3437{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3438{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3439{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3440{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3441{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3442
3443{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3444{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3445{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3446
3447{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
3448
3449{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3450
3451{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3452{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3453
3454{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3455
3456{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3457
3458{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3459
3460{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3461
3462{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3463{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3464{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3465{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3466
3467{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3468{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3469{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3470{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3471{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3472{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3473{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3474{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3475
3476{ "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3477
3478{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3479
3480{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3481{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3482
3483{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
3484
3485{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3486
3487{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3488{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3489
3490{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3491
3492{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3493
3494{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3495{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3496
3497{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3498
3499{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3500
3501{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3502{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3503
3504{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3505
3506{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3507{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3508{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3509{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3510{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3511{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3512{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3513{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3514{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3515{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3516{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3517{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3518{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3519{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3520{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3521{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3522{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3523{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3524{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3525{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3526{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3527{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3528{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3529{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3530{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3531{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3532{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3533{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3534{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3535{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3536{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3537{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3538{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3539{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3540{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } },
3541{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } },
3542
3543{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3544{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3545{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3546{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3547
3548{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3549
3550{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3551{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3552{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3553{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3554{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3555{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3556{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3557{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3558{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3559{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3560{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3561{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3562{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3563{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3564{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3565{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3566{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3567{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3568{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3569{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3570{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3571{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3572{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3573{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3574{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3575{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3576{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3577{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3578{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3579{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3580{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3581{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3582{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3583{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3584{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3585{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3586{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3587{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3588{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3589{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3590{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3591{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3592{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3593{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3594{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3595{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3596{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3597{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3598{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3599{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3600{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3601{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3602{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3603{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3604{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3605{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3606{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3607{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3608{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3609{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3610{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3611{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3612{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3613{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3614{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3615{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3616{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3617{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3618{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3619{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3620{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3621{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3622{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3623{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3624{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3625{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3626{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3627{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3628{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3629{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3630{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3631{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3632{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3633{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3634{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3635{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3636{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3637{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3638{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3639{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3640{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3641{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3642{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3643{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3644{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3645{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3646{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3647{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3648{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3649{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3650{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3651{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3652{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3653{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3654{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3655{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3656{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3657{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3658{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3659{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3660{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3661{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3662{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3663{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3664{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3665{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3666{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3667{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3668{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3669{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3670{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3671{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3672{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3673{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3674{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3675{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3676{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3677{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3678{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3679{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3680{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3681{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3682{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3683{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3684{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3685{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3686{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3687{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3688{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3689{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3690{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3691{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3692{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3693{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3694{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3695{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3696{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3697{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3698{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3699{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3700{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3701{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3702{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3703{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3704{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3705{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3706{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3707{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3708{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3709{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3710{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3711{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3712{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3713{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3714{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3715{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3716{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3717{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3718{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3719{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3720{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3721{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3722{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3723{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3724{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3725{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3726{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3727{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3728{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3729
3730{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3731
3732{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3733{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3734
3735{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3736
3737{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3738
3739{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3740{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3741
3742{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
3743
3744{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3745{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3746{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3747{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3748
3749{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3750{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3751{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3752{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3753
3754{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3755
3756{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3757{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3758{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3759
3760{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3761
3762{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3763
3764{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3765
3766{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3767
3768{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3769
3770{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3771{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3772
3773{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3774{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3775
3776{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3777
3778{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3779
3780{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3781
3782{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3783
3784{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3785
3786{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3787
3788{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3789
3790{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3791{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3792
3793{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3794{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3795
3796{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3797
3798{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3799
3800{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3801
3802{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3803
3804{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3805
3806{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3807{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3808{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3809{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3810
3811{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } },
3812{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } },
3813{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } },
3814{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } },
3815{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } },
3816{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } },
3817{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } },
3818{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } },
3819{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } },
3820{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } },
3821{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } },
3822{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } },
3823{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } },
3824{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } },
3825{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } },
3826{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } },
3827{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } },
3828{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } },
3829{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } },
3830{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } },
3831{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } },
3832{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } },
3833{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } },
3834{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } },
3835{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } },
3836{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } },
3837{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } },
3838{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } },
3839{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } },
3840{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } },
3841{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } },
3842{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } },
3843{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } },
3844{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
3845{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
3846{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } },
3847
3848{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3849{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3850
3851{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3852{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3853{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3854{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3855
3856{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3857{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3858
3859{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3860{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3861{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3862{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3863
3864{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3865{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3866{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3867{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3868{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3869{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3870{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3871{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3872{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3873{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3874{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3875{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3876{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3877{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3878{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3879{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3880{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3881{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3882{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3883{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3884{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3885{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } },
3886{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } },
3887{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } },
3888{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } },
3889{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } },
3890{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } },
3891{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } },
3892{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } },
3893{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } },
3894{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } },
3895{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } },
3896{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } },
3897{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } },
3898{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } },
3899{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } },
3900{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } },
3901{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } },
3902{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3903{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3904{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } },
3905{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } },
3906{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } },
3907{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } },
3908{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } },
3909{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, BOOKE, { RS } },
3910{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } },
3911{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, BOOKE, { RS } },
3912{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } },
3913{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, BOOKE, { RS } },
3914{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } },
3915{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, BOOKE, { RS } },
3916{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3917{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3918{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3919{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3920{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3921{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3922{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3923{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3924{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3925{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3926{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3927{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3928{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3929{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3930{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3931{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3932{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3933{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3934{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3935{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3936{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3937{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3938{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3939{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3940{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3941{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3942{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3943{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3944{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3945{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
3946{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
3947{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
3948{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
3949{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
3950{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
3951{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
3952{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
3953{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3954{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3955{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3956{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3957{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
3958{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
3959{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
3960{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } },
3961{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } },
3962{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } },
3963{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } },
3964{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } },
3965{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } },
3966{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } },
3967{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } },
3968{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } },
3969{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } },
3970{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } },
3971{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } },
3972{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } },
3973{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } },
3974{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } },
3975{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } },
3976{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } },
3977{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } },
3978{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } },
3979{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } },
3980{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } },
3981{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } },
3982{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } },
3983{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } },
3984{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } },
3985{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } },
3986{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RT } },
3987{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } },
3988{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } },
3989{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } },
3990{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } },
3991{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } },
3992{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } },
3993{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } },
3994{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } },
3995{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } },
3996{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } },
3997{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } },
3998{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } },
3999{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } },
4000{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } },
4001{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } },
4002{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } },
4003{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } },
4004{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } },
4005{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } },
4006{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } },
4007{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } },
4008{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } },
4009{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } },
4010{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } },
4011{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } },
4012{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } },
4013{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } },
4014{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } },
4015{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4016
4017{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4018
4019{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4020{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4021
4022{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4023
4024{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
4025
4026{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4027
4028{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4029
4030{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4031{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4032{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4033{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4034{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4035{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4036
4037{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4038{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4039{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4040{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4041
4042{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4043{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4044
4045{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4046{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4047{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4048{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4049
4050{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4051
4052{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4053
4054{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4055
4056{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4057
4058{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4059
4060{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4061{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4062
4063{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4064
4065{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4066{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4067
4068{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4069{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4070
4071{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4072
4073{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4074{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4075{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4076{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4077
4078{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4079{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4080
4081{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4082{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4083
4084{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4085{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4086
4087{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4088
4089{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4090
4091{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4092{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4093
4094{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4095
4096{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4097
4098{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4099
4100{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4101{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4102
4103{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
4104{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4105{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4106{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4107{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4108
4109{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4110
4111{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4112
4113{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4114
4115{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4116
4117{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4118
4119{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4120
4121{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4122
4123{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4124{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4125
4126{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4127{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4128
4129{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4130
4131{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4132{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4133
4134{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4135{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4136
4137{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4138
4139{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4140
4141{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4142
4143{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4144{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4145
4146{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4147
4148{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4149{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4150
4151{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4152
4153{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4154{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4155
4156{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4157{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4158
4159{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4160
4161{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
4162{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } },
4163
4164{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4165
4166{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4167{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4168
4169{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4170
4171{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4172
4173{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4174{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4175
4176{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4177
4178{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4179{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4180{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4181{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4182
4183{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4184{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4185
4186{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4187
4188{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4189{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4190
4191{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4192
4193{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4194{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4195
4196{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4197{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4198{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4199{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4200
4201{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4202
4203{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4204{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4205
4206{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4207{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4208
4209{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4210{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4211{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4212{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4213
4214{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4215
4216{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4217
4218{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4219{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4220
4221{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4222{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4223
4224{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4225{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4226{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4227{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4228
4229{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4230
4231{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4232
4233{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4234
4235{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4236{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4237{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4238
4239{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4240{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4241
4242{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4243{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4244
4245{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4246
4247{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
4248
4249{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4250
4251{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4252
4253{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4254{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4255{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4256
4257{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4258
4259{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4260
4261{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4262{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4263
4264{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
4265
4266{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4267{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4268
4269{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4270
4271{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4272{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4273
4274{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4275
4276{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4277{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4278{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4279{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4280{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4281{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4282{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4283{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4284{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4285{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4286{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4287{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4288
4289{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4290{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4291
4292{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4293{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4294
4295{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4296
4297{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4298
4299{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4300{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4301
4302{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4303{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4304
4305{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4306
4307{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4308
4309{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4310
4311{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4312
4313{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4314
4315{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4316
4317{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4318
4319{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4320
4321{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4322{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4323
4324{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4325{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4326
4327{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4328
4329{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4330
4331{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4332
4333{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4334
4335{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4336
4337{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4338
4339{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4340
4341{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4342
4343{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4344
4345{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4346
4347{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4348{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4349{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4350{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4351{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4352{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4353{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4354{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4355{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4356{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4357{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4358{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4359{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4360{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4361
4362{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4363
4364{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4365
4366{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4367
4368{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4369{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4370
4371{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4372{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4373
4374{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4375{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4376
4377{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4378{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4379
4380{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4381{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4382
4383{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4384{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4385
4386{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4387{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4388
4389{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4390{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4391
4392{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4393{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4394
4395{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4396{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4397
4398{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4399
4400{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4401
4402{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
4403{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
4404{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4405{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4406{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4407{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4408{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4409{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4410{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4411{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4412{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4413{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4414
4415{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4416
4417{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4418
4419{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4420
4421{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4422{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4423
4424{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4425{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4426{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4427{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4428
4429{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4430{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4431{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4432{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4433
4434{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4435{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4436{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4437{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4438
4439{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4440{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4441{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4442{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4443
4444{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4445{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4446{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4447{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4448
4449{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4450{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4451
4452{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4453{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4454
4455{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4456{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4457{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4458{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4459
4460{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4461{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4462
4463{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4464{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4465{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4466{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4467
4468{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4469{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4470{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4471{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4472
4473{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4474{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4475{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4476{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4477
4478{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4479{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4480{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4481{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4482
4483{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4484
4485{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4486{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4487
4488{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4489{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4490
4491{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4492
4493{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4494{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4495
4496{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4497{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4498
4499{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4500{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4501
4502{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4503{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4504
4505{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4506{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4507
4508{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4509{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4510
4511{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4512{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4513
4514{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4515{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4516
4517{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4518{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4519
4520{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4521{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4522
4523};
4524
4525const int powerpc_num_opcodes =
4526 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4527
4528
4529/* The macro table. This is only used by the assembler. */
4530
4531/* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4532 when x=0; 32-x when x is between 1 and 31; are negative if x is
4533 negative; and are 32 or more otherwise. This is what you want
4534 when, for instance, you are emulating a right shift by a
4535 rotate-left-and-mask, because the underlying instructions support
4536 shifts of size 0 but not shifts of size 32. By comparison, when
4537 extracting x bits from some word you want to use just 32-x, because
4538 the underlying instructions don't support extracting 0 bits but do
4539 support extracting the whole word (32 bits in this case). */
4540
4541const struct powerpc_macro powerpc_macros[] = {
4542{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4543{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4544{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4545{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4546{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4547{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4548{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4549{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4550{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4551{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4552{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4553{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4554{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4555{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4556{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4557{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4558
4559{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4560{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4561{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4562{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4563{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4564{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4565{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4566{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4567{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4568{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4569{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4570{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4571{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4572{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4573{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4574{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4575{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4576{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4577{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4578{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4579{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4580{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4581};
4582
4583const int powerpc_num_macros =
4584 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
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