| 1 | /* Semantic operand instances for m32r.
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| 2 |
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| 3 | THIS FILE IS MACHINE GENERATED WITH CGEN.
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| 4 |
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| 5 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
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| 6 |
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| 7 | This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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| 8 |
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| 9 | This program is free software; you can redistribute it and/or modify
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| 10 | it under the terms of the GNU General Public License as published by
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| 11 | the Free Software Foundation; either version 2, or (at your option)
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| 12 | any later version.
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| 13 |
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| 14 | This program is distributed in the hope that it will be useful,
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| 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 17 | GNU General Public License for more details.
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| 18 |
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| 19 | You should have received a copy of the GNU General Public License along
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| 20 | with this program; if not, write to the Free Software Foundation, Inc.,
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| 21 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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| 22 |
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| 23 | */
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| 24 |
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| 25 | #include "sysdep.h"
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| 26 | #include "ansidecl.h"
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| 27 | #include "bfd.h"
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| 28 | #include "symcat.h"
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| 29 | #include "m32r-desc.h"
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| 30 | #include "m32r-opc.h"
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| 31 |
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| 32 | /* Operand references. */
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| 33 |
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| 34 | #define INPUT CGEN_OPINST_INPUT
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| 35 | #define OUTPUT CGEN_OPINST_OUTPUT
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| 36 | #define END CGEN_OPINST_END
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| 37 | #define COND_REF CGEN_OPINST_COND_REF
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| 38 | #define OP_ENT(op) CONCAT2 (M32R_OPERAND_,op)
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| 39 |
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| 40 | static const CGEN_OPINST sfmt_empty_ops[] = {
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| 41 | { END }
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| 42 | };
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| 43 |
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| 44 | static const CGEN_OPINST sfmt_add_ops[] = {
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| 45 | { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 46 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 47 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 48 | { END }
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| 49 | };
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| 50 |
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| 51 | static const CGEN_OPINST sfmt_add3_ops[] = {
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| 52 | { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
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| 53 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 54 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 55 | { END }
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| 56 | };
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| 57 |
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| 58 | static const CGEN_OPINST sfmt_and3_ops[] = {
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| 59 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 60 | { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
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| 61 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 62 | { END }
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| 63 | };
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| 64 |
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| 65 | static const CGEN_OPINST sfmt_or3_ops[] = {
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| 66 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 67 | { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
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| 68 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 69 | { END }
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| 70 | };
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| 71 |
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| 72 | static const CGEN_OPINST sfmt_addi_ops[] = {
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| 73 | { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 74 | { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
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| 75 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 76 | { END }
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| 77 | };
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| 78 |
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| 79 | static const CGEN_OPINST sfmt_addv_ops[] = {
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| 80 | { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 81 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 82 | { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 83 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 84 | { END }
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| 85 | };
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| 86 |
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| 87 | static const CGEN_OPINST sfmt_addv3_ops[] = {
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| 88 | { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
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| 89 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 90 | { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 91 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 92 | { END }
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| 93 | };
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| 94 |
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| 95 | static const CGEN_OPINST sfmt_addx_ops[] = {
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| 96 | { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 97 | { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 98 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 99 | { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 100 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 101 | { END }
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| 102 | };
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| 103 |
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| 104 | static const CGEN_OPINST sfmt_bc8_ops[] = {
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| 105 | { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 106 | { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
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| 107 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 108 | { END }
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| 109 | };
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| 110 |
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| 111 | static const CGEN_OPINST sfmt_bc24_ops[] = {
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| 112 | { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 113 | { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
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| 114 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 115 | { END }
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| 116 | };
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| 117 |
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| 118 | static const CGEN_OPINST sfmt_beq_ops[] = {
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| 119 | { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
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| 120 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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| 121 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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| 122 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 123 | { END }
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| 124 | };
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| 125 |
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| 126 | static const CGEN_OPINST sfmt_beqz_ops[] = {
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| 127 | { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
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| 128 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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| 129 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 130 | { END }
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| 131 | };
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| 132 |
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| 133 | static const CGEN_OPINST sfmt_bl8_ops[] = {
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| 134 | { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
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| 135 | { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 136 | { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
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| 137 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 138 | { END }
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| 139 | };
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| 140 |
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| 141 | static const CGEN_OPINST sfmt_bl24_ops[] = {
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| 142 | { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
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| 143 | { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 144 | { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
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| 145 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 146 | { END }
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| 147 | };
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| 148 |
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| 149 | static const CGEN_OPINST sfmt_bcl8_ops[] = {
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| 150 | { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 151 | { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
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| 152 | { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 153 | { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
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| 154 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 155 | { END }
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| 156 | };
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| 157 |
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| 158 | static const CGEN_OPINST sfmt_bcl24_ops[] = {
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| 159 | { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 160 | { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
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| 161 | { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 162 | { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
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| 163 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 164 | { END }
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| 165 | };
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| 166 |
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| 167 | static const CGEN_OPINST sfmt_bra8_ops[] = {
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| 168 | { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
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| 169 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 170 | { END }
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| 171 | };
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| 172 |
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| 173 | static const CGEN_OPINST sfmt_bra24_ops[] = {
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| 174 | { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
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| 175 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 176 | { END }
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| 177 | };
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| 178 |
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| 179 | static const CGEN_OPINST sfmt_cmp_ops[] = {
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| 180 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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| 181 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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| 182 | { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 183 | { END }
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| 184 | };
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| 185 |
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| 186 | static const CGEN_OPINST sfmt_cmpi_ops[] = {
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| 187 | { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
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| 188 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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| 189 | { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 190 | { END }
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| 191 | };
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| 192 |
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| 193 | static const CGEN_OPINST sfmt_cmpz_ops[] = {
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| 194 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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| 195 | { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 196 | { END }
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| 197 | };
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| 198 |
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| 199 | static const CGEN_OPINST sfmt_div_ops[] = {
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| 200 | { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
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| 201 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 202 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
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| 203 | { END }
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| 204 | };
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| 205 |
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| 206 | static const CGEN_OPINST sfmt_jc_ops[] = {
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| 207 | { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
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| 208 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
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| 209 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
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| 210 | { END }
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| 211 | };
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| 212 |
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| 213 | static const CGEN_OPINST sfmt_jl_ops[] = {
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| 214 | { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 215 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 216 | { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
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| 217 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 218 | { END }
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| 219 | };
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| 220 |
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| 221 | static const CGEN_OPINST sfmt_jmp_ops[] = {
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| 222 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 223 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
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| 224 | { END }
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| 225 | };
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| 226 |
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| 227 | static const CGEN_OPINST sfmt_ld_ops[] = {
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| 228 | { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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| 229 | { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
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| 230 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 231 | { END }
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| 232 | };
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| 233 |
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| 234 | static const CGEN_OPINST sfmt_ld_d_ops[] = {
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| 235 | { INPUT, "h_memory_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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| 236 | { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
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| 237 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 238 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 239 | { END }
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| 240 | };
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| 241 |
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| 242 | static const CGEN_OPINST sfmt_ld_plus_ops[] = {
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| 243 | { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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| 244 | { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
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| 245 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 246 | { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
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| 247 | { END }
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| 248 | };
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| 249 |
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| 250 | static const CGEN_OPINST sfmt_ld24_ops[] = {
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| 251 | { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
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| 252 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 253 | { END }
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| 254 | };
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| 255 |
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| 256 | static const CGEN_OPINST sfmt_ldi8_ops[] = {
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| 257 | { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
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| 258 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 259 | { END }
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| 260 | };
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| 261 |
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| 262 | static const CGEN_OPINST sfmt_ldi16_ops[] = {
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| 263 | { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
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| 264 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 265 | { END }
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| 266 | };
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| 267 |
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| 268 | static const CGEN_OPINST sfmt_lock_ops[] = {
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| 269 | { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
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| 270 | { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
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| 271 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
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| 272 | { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
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| 273 | { END }
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| 274 | };
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| 275 |
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| 276 | static const CGEN_OPINST sfmt_machi_ops[] = {
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| 277 | { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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| 278 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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| 279 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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| 280 | { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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| 281 | { END }
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| 282 | };
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| 283 |
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| 284 | static const CGEN_OPINST sfmt_machi_a_ops[] = {
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| 285 | { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
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| 286 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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| 287 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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| 288 | { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
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| 289 | { END }
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| 290 | };
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| 291 |
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| 292 | static const CGEN_OPINST sfmt_mulhi_ops[] = {
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| 293 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
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| 294 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
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| 295 | { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
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| 296 | { END }
|
|---|
| 297 | };
|
|---|
| 298 |
|
|---|
| 299 | static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
|
|---|
| 300 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 301 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 302 | { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
|
|---|
| 303 | { END }
|
|---|
| 304 | };
|
|---|
| 305 |
|
|---|
| 306 | static const CGEN_OPINST sfmt_mv_ops[] = {
|
|---|
| 307 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
|
|---|
| 308 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 309 | { END }
|
|---|
| 310 | };
|
|---|
| 311 |
|
|---|
| 312 | static const CGEN_OPINST sfmt_mvfachi_ops[] = {
|
|---|
| 313 | { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
|
|---|
| 314 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 315 | { END }
|
|---|
| 316 | };
|
|---|
| 317 |
|
|---|
| 318 | static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
|
|---|
| 319 | { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
|
|---|
| 320 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 321 | { END }
|
|---|
| 322 | };
|
|---|
| 323 |
|
|---|
| 324 | static const CGEN_OPINST sfmt_mvfc_ops[] = {
|
|---|
| 325 | { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
|
|---|
| 326 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 327 | { END }
|
|---|
| 328 | };
|
|---|
| 329 |
|
|---|
| 330 | static const CGEN_OPINST sfmt_mvtachi_ops[] = {
|
|---|
| 331 | { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
|
|---|
| 332 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 333 | { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
|
|---|
| 334 | { END }
|
|---|
| 335 | };
|
|---|
| 336 |
|
|---|
| 337 | static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
|
|---|
| 338 | { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
|
|---|
| 339 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 340 | { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
|
|---|
| 341 | { END }
|
|---|
| 342 | };
|
|---|
| 343 |
|
|---|
| 344 | static const CGEN_OPINST sfmt_mvtc_ops[] = {
|
|---|
| 345 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
|
|---|
| 346 | { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
|
|---|
| 347 | { END }
|
|---|
| 348 | };
|
|---|
| 349 |
|
|---|
| 350 | static const CGEN_OPINST sfmt_nop_ops[] = {
|
|---|
| 351 | { END }
|
|---|
| 352 | };
|
|---|
| 353 |
|
|---|
| 354 | static const CGEN_OPINST sfmt_rac_ops[] = {
|
|---|
| 355 | { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
|
|---|
| 356 | { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
|
|---|
| 357 | { END }
|
|---|
| 358 | };
|
|---|
| 359 |
|
|---|
| 360 | static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
|
|---|
| 361 | { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
|
|---|
| 362 | { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
|
|---|
| 363 | { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
|
|---|
| 364 | { END }
|
|---|
| 365 | };
|
|---|
| 366 |
|
|---|
| 367 | static const CGEN_OPINST sfmt_rte_ops[] = {
|
|---|
| 368 | { INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 369 | { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 370 | { INPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
|
|---|
| 371 | { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
|
|---|
| 372 | { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 373 | { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
|
|---|
| 374 | { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 375 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
|
|---|
| 376 | { END }
|
|---|
| 377 | };
|
|---|
| 378 |
|
|---|
| 379 | static const CGEN_OPINST sfmt_seth_ops[] = {
|
|---|
| 380 | { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
|
|---|
| 381 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 382 | { END }
|
|---|
| 383 | };
|
|---|
| 384 |
|
|---|
| 385 | static const CGEN_OPINST sfmt_sll3_ops[] = {
|
|---|
| 386 | { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
|
|---|
| 387 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
|
|---|
| 388 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 389 | { END }
|
|---|
| 390 | };
|
|---|
| 391 |
|
|---|
| 392 | static const CGEN_OPINST sfmt_slli_ops[] = {
|
|---|
| 393 | { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 394 | { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
|
|---|
| 395 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 396 | { END }
|
|---|
| 397 | };
|
|---|
| 398 |
|
|---|
| 399 | static const CGEN_OPINST sfmt_st_ops[] = {
|
|---|
| 400 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 401 | { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 402 | { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
|
|---|
| 403 | { END }
|
|---|
| 404 | };
|
|---|
| 405 |
|
|---|
| 406 | static const CGEN_OPINST sfmt_st_d_ops[] = {
|
|---|
| 407 | { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
|
|---|
| 408 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 409 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 410 | { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
|
|---|
| 411 | { END }
|
|---|
| 412 | };
|
|---|
| 413 |
|
|---|
| 414 | static const CGEN_OPINST sfmt_stb_ops[] = {
|
|---|
| 415 | { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 416 | { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 417 | { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
|
|---|
| 418 | { END }
|
|---|
| 419 | };
|
|---|
| 420 |
|
|---|
| 421 | static const CGEN_OPINST sfmt_stb_d_ops[] = {
|
|---|
| 422 | { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
|
|---|
| 423 | { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 424 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 425 | { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
|
|---|
| 426 | { END }
|
|---|
| 427 | };
|
|---|
| 428 |
|
|---|
| 429 | static const CGEN_OPINST sfmt_sth_ops[] = {
|
|---|
| 430 | { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 431 | { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 432 | { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
|
|---|
| 433 | { END }
|
|---|
| 434 | };
|
|---|
| 435 |
|
|---|
| 436 | static const CGEN_OPINST sfmt_sth_d_ops[] = {
|
|---|
| 437 | { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
|
|---|
| 438 | { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 439 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 440 | { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
|
|---|
| 441 | { END }
|
|---|
| 442 | };
|
|---|
| 443 |
|
|---|
| 444 | static const CGEN_OPINST sfmt_st_plus_ops[] = {
|
|---|
| 445 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 446 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 447 | { OUTPUT, "h_memory_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
|
|---|
| 448 | { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 449 | { END }
|
|---|
| 450 | };
|
|---|
| 451 |
|
|---|
| 452 | static const CGEN_OPINST sfmt_trap_ops[] = {
|
|---|
| 453 | { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 454 | { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
|
|---|
| 455 | { INPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 456 | { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
|
|---|
| 457 | { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
|
|---|
| 458 | { OUTPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 459 | { OUTPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 460 | { OUTPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
|
|---|
| 461 | { OUTPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
|
|---|
| 462 | { OUTPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
|
|---|
| 463 | { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
|
|---|
| 464 | { END }
|
|---|
| 465 | };
|
|---|
| 466 |
|
|---|
| 467 | static const CGEN_OPINST sfmt_unlock_ops[] = {
|
|---|
| 468 | { INPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
|
|---|
| 469 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
|
|---|
| 470 | { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
|
|---|
| 471 | { OUTPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
|
|---|
| 472 | { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
|
|---|
| 473 | { END }
|
|---|
| 474 | };
|
|---|
| 475 |
|
|---|
| 476 | static const CGEN_OPINST sfmt_satb_ops[] = {
|
|---|
| 477 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
|
|---|
| 478 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 479 | { END }
|
|---|
| 480 | };
|
|---|
| 481 |
|
|---|
| 482 | static const CGEN_OPINST sfmt_sat_ops[] = {
|
|---|
| 483 | { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
|
|---|
| 484 | { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
|
|---|
| 485 | { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
|
|---|
| 486 | { END }
|
|---|
| 487 | };
|
|---|
| 488 |
|
|---|
| 489 | static const CGEN_OPINST sfmt_sadd_ops[] = {
|
|---|
| 490 | { INPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
|
|---|
| 491 | { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
|
|---|
| 492 | { OUTPUT, "h_accums_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
|
|---|
| 493 | { END }
|
|---|
| 494 | };
|
|---|
| 495 |
|
|---|
| 496 | static const CGEN_OPINST sfmt_macwu1_ops[] = {
|
|---|
| 497 | { INPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
|
|---|
| 498 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 499 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 500 | { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
|
|---|
| 501 | { END }
|
|---|
| 502 | };
|
|---|
| 503 |
|
|---|
| 504 | static const CGEN_OPINST sfmt_mulwu1_ops[] = {
|
|---|
| 505 | { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
|
|---|
| 506 | { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
|
|---|
| 507 | { OUTPUT, "h_accums_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
|
|---|
| 508 | { END }
|
|---|
| 509 | };
|
|---|
| 510 |
|
|---|
| 511 | static const CGEN_OPINST sfmt_sc_ops[] = {
|
|---|
| 512 | { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
|
|---|
| 513 | { END }
|
|---|
| 514 | };
|
|---|
| 515 |
|
|---|
| 516 | #undef INPUT
|
|---|
| 517 | #undef OUTPUT
|
|---|
| 518 | #undef END
|
|---|
| 519 | #undef COND_REF
|
|---|
| 520 | #undef OP_ENT
|
|---|
| 521 |
|
|---|
| 522 | /* Operand instance lookup table. */
|
|---|
| 523 |
|
|---|
| 524 | static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
|
|---|
| 525 | 0,
|
|---|
| 526 | & sfmt_add_ops[0],
|
|---|
| 527 | & sfmt_add3_ops[0],
|
|---|
| 528 | & sfmt_add_ops[0],
|
|---|
| 529 | & sfmt_and3_ops[0],
|
|---|
| 530 | & sfmt_add_ops[0],
|
|---|
| 531 | & sfmt_or3_ops[0],
|
|---|
| 532 | & sfmt_add_ops[0],
|
|---|
| 533 | & sfmt_and3_ops[0],
|
|---|
| 534 | & sfmt_addi_ops[0],
|
|---|
| 535 | & sfmt_addv_ops[0],
|
|---|
| 536 | & sfmt_addv3_ops[0],
|
|---|
| 537 | & sfmt_addx_ops[0],
|
|---|
| 538 | & sfmt_bc8_ops[0],
|
|---|
| 539 | & sfmt_bc24_ops[0],
|
|---|
| 540 | & sfmt_beq_ops[0],
|
|---|
| 541 | & sfmt_beqz_ops[0],
|
|---|
| 542 | & sfmt_beqz_ops[0],
|
|---|
| 543 | & sfmt_beqz_ops[0],
|
|---|
| 544 | & sfmt_beqz_ops[0],
|
|---|
| 545 | & sfmt_beqz_ops[0],
|
|---|
| 546 | & sfmt_beqz_ops[0],
|
|---|
| 547 | & sfmt_bl8_ops[0],
|
|---|
| 548 | & sfmt_bl24_ops[0],
|
|---|
| 549 | & sfmt_bcl8_ops[0],
|
|---|
| 550 | & sfmt_bcl24_ops[0],
|
|---|
| 551 | & sfmt_bc8_ops[0],
|
|---|
| 552 | & sfmt_bc24_ops[0],
|
|---|
| 553 | & sfmt_beq_ops[0],
|
|---|
| 554 | & sfmt_bra8_ops[0],
|
|---|
| 555 | & sfmt_bra24_ops[0],
|
|---|
| 556 | & sfmt_bcl8_ops[0],
|
|---|
| 557 | & sfmt_bcl24_ops[0],
|
|---|
| 558 | & sfmt_cmp_ops[0],
|
|---|
| 559 | & sfmt_cmpi_ops[0],
|
|---|
| 560 | & sfmt_cmp_ops[0],
|
|---|
| 561 | & sfmt_cmpi_ops[0],
|
|---|
| 562 | & sfmt_cmp_ops[0],
|
|---|
| 563 | & sfmt_cmpz_ops[0],
|
|---|
| 564 | & sfmt_div_ops[0],
|
|---|
| 565 | & sfmt_div_ops[0],
|
|---|
| 566 | & sfmt_div_ops[0],
|
|---|
| 567 | & sfmt_div_ops[0],
|
|---|
| 568 | & sfmt_div_ops[0],
|
|---|
| 569 | & sfmt_jc_ops[0],
|
|---|
| 570 | & sfmt_jc_ops[0],
|
|---|
| 571 | & sfmt_jl_ops[0],
|
|---|
| 572 | & sfmt_jmp_ops[0],
|
|---|
| 573 | & sfmt_ld_ops[0],
|
|---|
| 574 | & sfmt_ld_d_ops[0],
|
|---|
| 575 | & sfmt_ld_ops[0],
|
|---|
| 576 | & sfmt_ld_d_ops[0],
|
|---|
| 577 | & sfmt_ld_ops[0],
|
|---|
| 578 | & sfmt_ld_d_ops[0],
|
|---|
| 579 | & sfmt_ld_ops[0],
|
|---|
| 580 | & sfmt_ld_d_ops[0],
|
|---|
| 581 | & sfmt_ld_ops[0],
|
|---|
| 582 | & sfmt_ld_d_ops[0],
|
|---|
| 583 | & sfmt_ld_plus_ops[0],
|
|---|
| 584 | & sfmt_ld24_ops[0],
|
|---|
| 585 | & sfmt_ldi8_ops[0],
|
|---|
| 586 | & sfmt_ldi16_ops[0],
|
|---|
| 587 | & sfmt_lock_ops[0],
|
|---|
| 588 | & sfmt_machi_ops[0],
|
|---|
| 589 | & sfmt_machi_a_ops[0],
|
|---|
| 590 | & sfmt_machi_ops[0],
|
|---|
| 591 | & sfmt_machi_a_ops[0],
|
|---|
| 592 | & sfmt_machi_ops[0],
|
|---|
| 593 | & sfmt_machi_a_ops[0],
|
|---|
| 594 | & sfmt_machi_ops[0],
|
|---|
| 595 | & sfmt_machi_a_ops[0],
|
|---|
| 596 | & sfmt_add_ops[0],
|
|---|
| 597 | & sfmt_mulhi_ops[0],
|
|---|
| 598 | & sfmt_mulhi_a_ops[0],
|
|---|
| 599 | & sfmt_mulhi_ops[0],
|
|---|
| 600 | & sfmt_mulhi_a_ops[0],
|
|---|
| 601 | & sfmt_mulhi_ops[0],
|
|---|
| 602 | & sfmt_mulhi_a_ops[0],
|
|---|
| 603 | & sfmt_mulhi_ops[0],
|
|---|
| 604 | & sfmt_mulhi_a_ops[0],
|
|---|
| 605 | & sfmt_mv_ops[0],
|
|---|
| 606 | & sfmt_mvfachi_ops[0],
|
|---|
| 607 | & sfmt_mvfachi_a_ops[0],
|
|---|
| 608 | & sfmt_mvfachi_ops[0],
|
|---|
| 609 | & sfmt_mvfachi_a_ops[0],
|
|---|
| 610 | & sfmt_mvfachi_ops[0],
|
|---|
| 611 | & sfmt_mvfachi_a_ops[0],
|
|---|
| 612 | & sfmt_mvfc_ops[0],
|
|---|
| 613 | & sfmt_mvtachi_ops[0],
|
|---|
| 614 | & sfmt_mvtachi_a_ops[0],
|
|---|
| 615 | & sfmt_mvtachi_ops[0],
|
|---|
| 616 | & sfmt_mvtachi_a_ops[0],
|
|---|
| 617 | & sfmt_mvtc_ops[0],
|
|---|
| 618 | & sfmt_mv_ops[0],
|
|---|
| 619 | & sfmt_nop_ops[0],
|
|---|
| 620 | & sfmt_mv_ops[0],
|
|---|
| 621 | & sfmt_rac_ops[0],
|
|---|
| 622 | & sfmt_rac_dsi_ops[0],
|
|---|
| 623 | & sfmt_rac_ops[0],
|
|---|
| 624 | & sfmt_rac_dsi_ops[0],
|
|---|
| 625 | & sfmt_rte_ops[0],
|
|---|
| 626 | & sfmt_seth_ops[0],
|
|---|
| 627 | & sfmt_add_ops[0],
|
|---|
| 628 | & sfmt_sll3_ops[0],
|
|---|
| 629 | & sfmt_slli_ops[0],
|
|---|
| 630 | & sfmt_add_ops[0],
|
|---|
| 631 | & sfmt_sll3_ops[0],
|
|---|
| 632 | & sfmt_slli_ops[0],
|
|---|
| 633 | & sfmt_add_ops[0],
|
|---|
| 634 | & sfmt_sll3_ops[0],
|
|---|
| 635 | & sfmt_slli_ops[0],
|
|---|
| 636 | & sfmt_st_ops[0],
|
|---|
| 637 | & sfmt_st_d_ops[0],
|
|---|
| 638 | & sfmt_stb_ops[0],
|
|---|
| 639 | & sfmt_stb_d_ops[0],
|
|---|
| 640 | & sfmt_sth_ops[0],
|
|---|
| 641 | & sfmt_sth_d_ops[0],
|
|---|
| 642 | & sfmt_st_plus_ops[0],
|
|---|
| 643 | & sfmt_st_plus_ops[0],
|
|---|
| 644 | & sfmt_add_ops[0],
|
|---|
| 645 | & sfmt_addv_ops[0],
|
|---|
| 646 | & sfmt_addx_ops[0],
|
|---|
| 647 | & sfmt_trap_ops[0],
|
|---|
| 648 | & sfmt_unlock_ops[0],
|
|---|
| 649 | & sfmt_satb_ops[0],
|
|---|
| 650 | & sfmt_satb_ops[0],
|
|---|
| 651 | & sfmt_sat_ops[0],
|
|---|
| 652 | & sfmt_cmpz_ops[0],
|
|---|
| 653 | & sfmt_sadd_ops[0],
|
|---|
| 654 | & sfmt_macwu1_ops[0],
|
|---|
| 655 | & sfmt_machi_ops[0],
|
|---|
| 656 | & sfmt_mulwu1_ops[0],
|
|---|
| 657 | & sfmt_macwu1_ops[0],
|
|---|
| 658 | & sfmt_sc_ops[0],
|
|---|
| 659 | & sfmt_sc_ops[0],
|
|---|
| 660 | };
|
|---|
| 661 |
|
|---|
| 662 | /* Function to call before using the operand instance table. */
|
|---|
| 663 |
|
|---|
| 664 | void
|
|---|
| 665 | m32r_cgen_init_opinst_table (cd)
|
|---|
| 666 | CGEN_CPU_DESC cd;
|
|---|
| 667 | {
|
|---|
| 668 | int i;
|
|---|
| 669 | const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
|
|---|
| 670 | CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
|
|---|
| 671 | for (i = 0; i < MAX_INSNS; ++i)
|
|---|
| 672 | insns[i].opinst = oi[i];
|
|---|
| 673 | }
|
|---|
