| 1 | /* Assemble Matsushita MN10200 instructions.
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| 2 | Copyright 1996, 1997, 2000 Free Software Foundation, Inc.
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| 3 |
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| 4 | This program is free software; you can redistribute it and/or modify
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| 5 | it under the terms of the GNU General Public License as published by
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| 6 | the Free Software Foundation; either version 2 of the License, or
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| 7 | (at your option) any later version.
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| 8 |
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| 9 | This program is distributed in the hope that it will be useful,
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| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 12 | GNU General Public License for more details.
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| 13 |
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| 14 | You should have received a copy of the GNU General Public License
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| 15 | along with this program; if not, write to the Free Software
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| 16 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 17 |
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| 18 | #include "sysdep.h"
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| 19 | #include "opcode/mn10200.h"
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| 20 |
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| 21 | |
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| 22 |
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| 23 | const struct mn10200_operand mn10200_operands[] = {
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| 24 | #define UNUSED 0
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| 25 | {0, 0, 0},
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| 26 |
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| 27 | /* dn register in the first register operand position. */
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| 28 | #define DN0 (UNUSED+1)
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| 29 | {2, 0, MN10200_OPERAND_DREG},
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| 30 |
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| 31 | /* dn register in the second register operand position. */
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| 32 | #define DN1 (DN0+1)
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| 33 | {2, 2, MN10200_OPERAND_DREG},
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| 34 |
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| 35 | /* dm register in the first register operand position. */
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| 36 | #define DM0 (DN1+1)
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| 37 | {2, 0, MN10200_OPERAND_DREG},
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| 38 |
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| 39 | /* dm register in the second register operand position. */
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| 40 | #define DM1 (DM0+1)
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| 41 | {2, 2, MN10200_OPERAND_DREG},
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| 42 |
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| 43 | /* an register in the first register operand position. */
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| 44 | #define AN0 (DM1+1)
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| 45 | {2, 0, MN10200_OPERAND_AREG},
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| 46 |
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| 47 | /* an register in the second register operand position. */
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| 48 | #define AN1 (AN0+1)
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| 49 | {2, 2, MN10200_OPERAND_AREG},
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| 50 |
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| 51 | /* am register in the first register operand position. */
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| 52 | #define AM0 (AN1+1)
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| 53 | {2, 0, MN10200_OPERAND_AREG},
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| 54 |
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| 55 | /* am register in the second register operand position. */
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| 56 | #define AM1 (AM0+1)
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| 57 | {2, 2, MN10200_OPERAND_AREG},
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| 58 |
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| 59 | /* 8 bit unsigned immediate which may promote to a 16bit
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| 60 | unsigned immediate. */
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| 61 | #define IMM8 (AM1+1)
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| 62 | {8, 0, MN10200_OPERAND_PROMOTE},
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| 63 |
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| 64 | /* 16 bit unsigned immediate which may promote to a 32bit
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| 65 | unsigned immediate. */
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| 66 | #define IMM16 (IMM8+1)
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| 67 | {16, 0, MN10200_OPERAND_PROMOTE},
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| 68 |
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| 69 | /* 16 bit pc-relative immediate which may promote to a 16bit
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| 70 | pc-relative immediate. */
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| 71 | #define IMM16_PCREL (IMM16+1)
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| 72 | {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED},
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| 73 |
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| 74 | /* 16bit unsigned dispacement in a memory operation which
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| 75 | may promote to a 32bit displacement. */
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| 76 | #define IMM16_MEM (IMM16_PCREL+1)
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| 77 | {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR},
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| 78 |
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| 79 | /* 24 immediate, low 16 bits in the main instruction
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| 80 | word, 8 in the extension word. */
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| 81 |
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| 82 | #define IMM24 (IMM16_MEM+1)
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| 83 | {24, 0, MN10200_OPERAND_EXTENDED},
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| 84 |
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| 85 | /* 32bit pc-relative offset. */
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| 86 | #define IMM24_PCREL (IMM24+1)
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| 87 | {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED},
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| 88 |
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| 89 | /* 32bit memory offset. */
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| 90 | #define IMM24_MEM (IMM24_PCREL+1)
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| 91 | {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR},
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| 92 |
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| 93 | /* Processor status word. */
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| 94 | #define PSW (IMM24_MEM+1)
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| 95 | {0, 0, MN10200_OPERAND_PSW},
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| 96 |
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| 97 | /* MDR register. */
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| 98 | #define MDR (PSW+1)
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| 99 | {0, 0, MN10200_OPERAND_MDR},
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| 100 |
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| 101 | /* Index register. */
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| 102 | #define DI (MDR+1)
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| 103 | {2, 4, MN10200_OPERAND_DREG},
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| 104 |
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| 105 | /* 8 bit signed displacement, may promote to 16bit signed dispacement. */
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| 106 | #define SD8 (DI+1)
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| 107 | {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
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| 108 |
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| 109 | /* 16 bit signed displacement, may promote to 32bit dispacement. */
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| 110 | #define SD16 (SD8+1)
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| 111 | {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
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| 112 |
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| 113 | /* 8 bit pc-relative displacement. */
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| 114 | #define SD8N_PCREL (SD16+1)
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| 115 | {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX},
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| 116 |
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| 117 | /* 8 bit signed immediate which may promote to 16bit signed immediate. */
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| 118 | #define SIMM8 (SD8N_PCREL+1)
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| 119 | {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
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| 120 |
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| 121 | /* 16 bit signed immediate which may promote to 32bit immediate. */
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| 122 | #define SIMM16 (SIMM8+1)
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| 123 | {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
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| 124 |
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| 125 | /* 16 bit signed immediate which may not promote. */
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| 126 | #define SIMM16N (SIMM16+1)
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| 127 | {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK},
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| 128 |
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| 129 | /* Either an open paren or close paren. */
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| 130 | #define PAREN (SIMM16N+1)
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| 131 | {0, 0, MN10200_OPERAND_PAREN},
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| 132 |
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| 133 | /* dn register that appears in the first and second register positions. */
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| 134 | #define DN01 (PAREN+1)
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| 135 | {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED},
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| 136 |
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| 137 | /* an register that appears in the first and second register positions. */
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| 138 | #define AN01 (DN01+1)
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| 139 | {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
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| 140 | } ;
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| 141 |
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| 142 | #define MEM(ADDR) PAREN, ADDR, PAREN
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| 143 | #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
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| 144 | |
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| 145 |
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| 146 | /* The opcode table.
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| 147 |
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| 148 | The format of the opcode table is:
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| 149 |
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| 150 | NAME OPCODE MASK { OPERANDS }
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| 151 |
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| 152 | NAME is the name of the instruction.
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| 153 | OPCODE is the instruction opcode.
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| 154 | MASK is the opcode mask; this is used to tell the disassembler
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| 155 | which bits in the actual opcode must match OPCODE.
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| 156 | OPERANDS is the list of operands.
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| 157 |
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| 158 | The disassembler reads the table in order and prints the first
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| 159 | instruction which matches, so this table is sorted to put more
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| 160 | specific instructions before more general instructions. It is also
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| 161 | sorted by major opcode. */
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| 162 |
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| 163 | const struct mn10200_opcode mn10200_opcodes[] = {
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| 164 | { "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}},
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| 165 | { "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}},
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| 166 | { "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
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| 167 | { "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}},
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| 168 | { "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}},
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| 169 | { "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
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| 170 | { "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
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| 171 | { "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
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| 172 | { "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}},
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| 173 | { "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}},
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| 174 | { "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}},
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| 175 | { "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
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| 176 | { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
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| 177 | { "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
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| 178 | { "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
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| 179 | { "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
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| 180 | { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
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| 181 | { "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}},
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| 182 | { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
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| 183 | { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
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| 184 | { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
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| 185 | { "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}},
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| 186 | { "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}},
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| 187 | { "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}},
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| 188 | { "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}},
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| 189 | { "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
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| 190 | { "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
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| 191 | { "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
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| 192 | { "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
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| 193 | { "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
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| 194 | { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}},
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| 195 | { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}},
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| 196 | { "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}},
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| 197 | { "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}},
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| 198 | { "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}},
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| 199 | { "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}},
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| 200 | { "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}},
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| 201 | { "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
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| 202 | { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
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| 203 | { "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
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| 204 | { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
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| 205 |
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| 206 | { "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
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| 207 | { "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
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| 208 | { "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
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| 209 | { "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
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| 210 | { "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
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| 211 | { "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
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| 212 |
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| 213 | { "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
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| 214 | { "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
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| 215 | { "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
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| 216 | { "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
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| 217 | { "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
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| 218 | { "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}},
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| 219 | { "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
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| 220 | { "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
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| 221 | { "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
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| 222 | { "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
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| 223 | { "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
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| 224 | { "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
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| 225 |
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| 226 | { "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}},
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| 227 | { "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
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| 228 | { "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
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| 229 | { "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
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| 230 | { "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
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| 231 | { "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
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| 232 | { "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
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| 233 |
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| 234 | { "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}},
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| 235 | { "extx", 0xb0, 0xfc, FMT_1, {DN0}},
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| 236 | { "extxu", 0xb4, 0xfc, FMT_1, {DN0}},
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| 237 | { "extxb", 0xb8, 0xfc, FMT_1, {DN0}},
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| 238 | { "extxbu", 0xbc, 0xfc, FMT_1, {DN0}},
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| 239 |
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| 240 | { "add", 0x90, 0xf0, FMT_1, {DN1, DM0}},
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| 241 | { "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
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| 242 | { "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}},
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| 243 | { "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}},
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| 244 | { "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}},
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| 245 | { "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
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| 246 | { "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}},
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| 247 | { "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
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| 248 | { "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}},
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| 249 | { "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}},
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| 250 | { "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}},
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| 251 | { "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
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| 252 |
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| 253 | { "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}},
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| 254 | { "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
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| 255 | { "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}},
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| 256 | { "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}},
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| 257 | { "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}},
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| 258 | { "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}},
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| 259 | { "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}},
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| 260 | { "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
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| 261 | { "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}},
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| 262 |
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| 263 | { "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}},
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| 264 | { "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}},
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| 265 |
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| 266 | { "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}},
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| 267 |
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| 268 | { "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}},
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| 269 | { "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
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| 270 | { "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}},
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| 271 | { "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}},
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| 272 | { "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}},
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| 273 | { "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
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| 274 | { "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}},
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| 275 | { "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}},
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| 276 | { "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
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| 277 |
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| 278 | { "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}},
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| 279 | { "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}},
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| 280 | { "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
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| 281 | { "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
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| 282 | { "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}},
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| 283 | { "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}},
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| 284 | { "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
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| 285 | { "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
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|---|
| 286 | { "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}},
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| 287 | { "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
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| 288 | { "not", 0xf3e4, 0xfffc, FMT_4, {DN0}},
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| 289 |
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| 290 | { "asr", 0xf338, 0xfffc, FMT_4, {DN0}},
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| 291 | { "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}},
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| 292 | { "ror", 0xf334, 0xfffc, FMT_4, {DN0}},
|
|---|
| 293 | { "rol", 0xf330, 0xfffc, FMT_4, {DN0}},
|
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| 294 |
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| 295 | { "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}},
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| 296 | { "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
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| 297 | { "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
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| 298 | { "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
|
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| 299 |
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| 300 | { "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 301 | { "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 302 | { "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 303 | { "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 304 | { "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 305 | { "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 306 | { "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 307 | { "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 308 | { "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 309 | { "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 310 | { "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 311 | { "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 312 | { "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 313 | { "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 314 | { "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}},
|
|---|
| 315 |
|
|---|
| 316 | { "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 317 | { "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 318 | { "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 319 | { "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 320 | { "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 321 | { "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 322 | { "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 323 | { "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 324 | { "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 325 | { "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 326 | { "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 327 | { "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 328 | { "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 329 | { "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}},
|
|---|
| 330 |
|
|---|
| 331 | { "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}},
|
|---|
| 332 | { "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}},
|
|---|
| 333 | { "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
|
|---|
| 334 | { "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}},
|
|---|
| 335 | { "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}},
|
|---|
| 336 | { "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
|
|---|
| 337 |
|
|---|
| 338 | { "nop", 0xf6, 0xff, FMT_1, {UNUSED}},
|
|---|
| 339 |
|
|---|
| 340 | { "rts", 0xfe, 0xff, FMT_1, {UNUSED}},
|
|---|
| 341 | { "rti", 0xeb, 0xff, FMT_1, {UNUSED}},
|
|---|
| 342 |
|
|---|
| 343 | /* Extension. We need some instruction to trigger "emulated syscalls"
|
|---|
| 344 | for our simulator. */
|
|---|
| 345 | { "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}},
|
|---|
| 346 |
|
|---|
| 347 | /* Extension. When talking to the simulator, gdb requires some instruction
|
|---|
| 348 | that will trigger a "breakpoint" (really just an instruction that isn't
|
|---|
| 349 | otherwise used by the tools. This instruction must be the same size
|
|---|
| 350 | as the smallest instruction on the target machine. In the case of the
|
|---|
| 351 | mn10x00 the "break" instruction must be one byte. 0xff is available on
|
|---|
| 352 | both mn10x00 architectures. */
|
|---|
| 353 | { "break", 0xff, 0xff, FMT_1, {UNUSED}},
|
|---|
| 354 |
|
|---|
| 355 | { 0, 0, 0, 0, {0}},
|
|---|
| 356 |
|
|---|
| 357 | } ;
|
|---|
| 358 |
|
|---|
| 359 | const int mn10200_num_opcodes =
|
|---|
| 360 | sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]);
|
|---|
| 361 |
|
|---|
| 362 | |
|---|
| 363 |
|
|---|
