source: trunk/src/binutils/opcodes/m10200-opc.c@ 1036

Last change on this file since 1036 was 10, checked in by bird, 22 years ago

Initial revision
  • Property cvs2svn:cvs-rev set to 1.1
  • Property svn:eol-style set to native
  • Property svn:executable set to *
File size: 14.4 KB
Line 
1/* Assemble Matsushita MN10200 instructions.
2 Copyright 1996, 1997, 2000 Free Software Foundation, Inc.
3
4This program is free software; you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation; either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program; if not, write to the Free Software
16Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#include "sysdep.h"
19#include "opcode/mn10200.h"
20
21
22
23const struct mn10200_operand mn10200_operands[] = {
24#define UNUSED 0
25 {0, 0, 0},
26
27/* dn register in the first register operand position. */
28#define DN0 (UNUSED+1)
29 {2, 0, MN10200_OPERAND_DREG},
30
31/* dn register in the second register operand position. */
32#define DN1 (DN0+1)
33 {2, 2, MN10200_OPERAND_DREG},
34
35/* dm register in the first register operand position. */
36#define DM0 (DN1+1)
37 {2, 0, MN10200_OPERAND_DREG},
38
39/* dm register in the second register operand position. */
40#define DM1 (DM0+1)
41 {2, 2, MN10200_OPERAND_DREG},
42
43/* an register in the first register operand position. */
44#define AN0 (DM1+1)
45 {2, 0, MN10200_OPERAND_AREG},
46
47/* an register in the second register operand position. */
48#define AN1 (AN0+1)
49 {2, 2, MN10200_OPERAND_AREG},
50
51/* am register in the first register operand position. */
52#define AM0 (AN1+1)
53 {2, 0, MN10200_OPERAND_AREG},
54
55/* am register in the second register operand position. */
56#define AM1 (AM0+1)
57 {2, 2, MN10200_OPERAND_AREG},
58
59/* 8 bit unsigned immediate which may promote to a 16bit
60 unsigned immediate. */
61#define IMM8 (AM1+1)
62 {8, 0, MN10200_OPERAND_PROMOTE},
63
64/* 16 bit unsigned immediate which may promote to a 32bit
65 unsigned immediate. */
66#define IMM16 (IMM8+1)
67 {16, 0, MN10200_OPERAND_PROMOTE},
68
69/* 16 bit pc-relative immediate which may promote to a 16bit
70 pc-relative immediate. */
71#define IMM16_PCREL (IMM16+1)
72 {16, 0, MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX | MN10200_OPERAND_SIGNED},
73
74/* 16bit unsigned dispacement in a memory operation which
75 may promote to a 32bit displacement. */
76#define IMM16_MEM (IMM16_PCREL+1)
77 {16, 0, MN10200_OPERAND_PROMOTE | MN10200_OPERAND_MEMADDR},
78
79/* 24 immediate, low 16 bits in the main instruction
80 word, 8 in the extension word. */
81
82#define IMM24 (IMM16_MEM+1)
83 {24, 0, MN10200_OPERAND_EXTENDED},
84
85/* 32bit pc-relative offset. */
86#define IMM24_PCREL (IMM24+1)
87 {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_PCREL | MN10200_OPERAND_SIGNED},
88
89/* 32bit memory offset. */
90#define IMM24_MEM (IMM24_PCREL+1)
91 {24, 0, MN10200_OPERAND_EXTENDED | MN10200_OPERAND_MEMADDR},
92
93/* Processor status word. */
94#define PSW (IMM24_MEM+1)
95 {0, 0, MN10200_OPERAND_PSW},
96
97/* MDR register. */
98#define MDR (PSW+1)
99 {0, 0, MN10200_OPERAND_MDR},
100
101/* Index register. */
102#define DI (MDR+1)
103 {2, 4, MN10200_OPERAND_DREG},
104
105/* 8 bit signed displacement, may promote to 16bit signed dispacement. */
106#define SD8 (DI+1)
107 {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
108
109/* 16 bit signed displacement, may promote to 32bit dispacement. */
110#define SD16 (SD8+1)
111 {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
112
113/* 8 bit pc-relative displacement. */
114#define SD8N_PCREL (SD16+1)
115 {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PCREL | MN10200_OPERAND_RELAX},
116
117/* 8 bit signed immediate which may promote to 16bit signed immediate. */
118#define SIMM8 (SD8N_PCREL+1)
119 {8, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
120
121/* 16 bit signed immediate which may promote to 32bit immediate. */
122#define SIMM16 (SIMM8+1)
123 {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_PROMOTE},
124
125/* 16 bit signed immediate which may not promote. */
126#define SIMM16N (SIMM16+1)
127 {16, 0, MN10200_OPERAND_SIGNED | MN10200_OPERAND_NOCHECK},
128
129/* Either an open paren or close paren. */
130#define PAREN (SIMM16N+1)
131 {0, 0, MN10200_OPERAND_PAREN},
132
133/* dn register that appears in the first and second register positions. */
134#define DN01 (PAREN+1)
135 {2, 0, MN10200_OPERAND_DREG | MN10200_OPERAND_REPEATED},
136
137/* an register that appears in the first and second register positions. */
138#define AN01 (DN01+1)
139 {2, 0, MN10200_OPERAND_AREG | MN10200_OPERAND_REPEATED},
140} ;
141
142#define MEM(ADDR) PAREN, ADDR, PAREN
143#define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
144
145
146/* The opcode table.
147
148 The format of the opcode table is:
149
150 NAME OPCODE MASK { OPERANDS }
151
152 NAME is the name of the instruction.
153 OPCODE is the instruction opcode.
154 MASK is the opcode mask; this is used to tell the disassembler
155 which bits in the actual opcode must match OPCODE.
156 OPERANDS is the list of operands.
157
158 The disassembler reads the table in order and prints the first
159 instruction which matches, so this table is sorted to put more
160 specific instructions before more general instructions. It is also
161 sorted by major opcode. */
162
163const struct mn10200_opcode mn10200_opcodes[] = {
164{ "mov", 0x8000, 0xf000, FMT_2, {SIMM8, DN01}},
165{ "mov", 0x80, 0xf0, FMT_1, {DN1, DM0}},
166{ "mov", 0xf230, 0xfff0, FMT_4, {DM1, AN0}},
167{ "mov", 0xf2f0, 0xfff0, FMT_4, {AN1, DM0}},
168{ "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}},
169{ "mov", 0xf3f0, 0xfffc, FMT_4, {PSW, DN0}},
170{ "mov", 0xf3d0, 0xfff3, FMT_4, {DN1, PSW}},
171{ "mov", 0xf3e0, 0xfffc, FMT_4, {MDR, DN0}},
172{ "mov", 0xf3c0, 0xfff3, FMT_4, {DN1, MDR}},
173{ "mov", 0x20, 0xf0, FMT_1, {MEM(AN1), DM0}},
174{ "mov", 0x6000, 0xf000, FMT_2, {MEM2(SD8, AN1), DM0}},
175{ "mov", 0xf7c00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
176{ "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
177{ "mov", 0xf140, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
178{ "mov", 0xc80000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
179{ "mov", 0xf4c00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
180{ "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
181{ "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}},
182{ "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
183{ "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
184{ "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
185{ "mov", 0xf7300000, 0xfffc0000, FMT_6, {MEM(IMM16_MEM), AN0}},
186{ "mov", 0xf4d00000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), AN0}},
187{ "mov", 0x00, 0xf0, FMT_1, {DM0, MEM(AN1)}},
188{ "mov", 0x4000, 0xf000, FMT_2, {DM0, MEM2(SD8, AN1)}},
189{ "mov", 0xf7800000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
190{ "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
191{ "mov", 0xf1c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
192{ "mov", 0xc00000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
193{ "mov", 0xf4400000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
194{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}},
195{ "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM(AN1)}},
196{ "mov", 0xf7a00000, 0xfff00000, FMT_6, {AM0, MEM2(SD16, AN1)}},
197{ "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}},
198{ "mov", 0xf180, 0xffc0, FMT_4, {AM0, MEM2(DI, AN1)}},
199{ "mov", 0xf7200000, 0xfffc0000, FMT_6, {AN0, MEM(IMM16_MEM)}},
200{ "mov", 0xf4500000, 0xfffc0000, FMT_7, {AN0, MEM(IMM24_MEM)}},
201{ "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
202{ "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
203{ "mov", 0xdc0000, 0xfc0000, FMT_3, {IMM16, AN0}},
204{ "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
205
206{ "movx", 0xf57000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
207{ "movx", 0xf7700000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
208{ "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
209{ "movx", 0xf55000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
210{ "movx", 0xf7600000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
211{ "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
212
213{ "movb", 0xf52000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
214{ "movb", 0xf7d00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
215{ "movb", 0xf4a00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
216{ "movb", 0xf040, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
217{ "movb", 0xf4c40000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
218{ "movb", 0x10, 0xf0, FMT_1, {DM0, MEM(AN1)}},
219{ "movb", 0xf51000, 0xfff000, FMT_5, {DM0, MEM2(SD8, AN1)}},
220{ "movb", 0xf7900000, 0xfff00000, FMT_6, {DM0, MEM2(SD16, AN1)}},
221{ "movb", 0xf4200000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
222{ "movb", 0xf0c0, 0xffc0, FMT_4, {DM0, MEM2(DI, AN1)}},
223{ "movb", 0xc40000, 0xfc0000, FMT_3, {DN0, MEM(IMM16_MEM)}},
224{ "movb", 0xf4440000, 0xfffc0000, FMT_7, {DN0, MEM(IMM24_MEM)}},
225
226{ "movbu", 0x30, 0xf0, FMT_1, {MEM(AN1), DM0}},
227{ "movbu", 0xf53000, 0xfff000, FMT_5, {MEM2(SD8, AN1), DM0}},
228{ "movbu", 0xf7500000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), DM0}},
229{ "movbu", 0xf4900000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
230{ "movbu", 0xf080, 0xffc0, FMT_4, {MEM2(DI, AN1), DM0}},
231{ "movbu", 0xcc0000, 0xfc0000, FMT_3, {MEM(IMM16_MEM), DN0}},
232{ "movbu", 0xf4c80000, 0xfffc0000, FMT_7, {MEM(IMM24_MEM), DN0}},
233
234{ "ext", 0xf3c1, 0xfff3, FMT_4, {DN1}},
235{ "extx", 0xb0, 0xfc, FMT_1, {DN0}},
236{ "extxu", 0xb4, 0xfc, FMT_1, {DN0}},
237{ "extxb", 0xb8, 0xfc, FMT_1, {DN0}},
238{ "extxbu", 0xbc, 0xfc, FMT_1, {DN0}},
239
240{ "add", 0x90, 0xf0, FMT_1, {DN1, DM0}},
241{ "add", 0xf200, 0xfff0, FMT_4, {DM1, AN0}},
242{ "add", 0xf2c0, 0xfff0, FMT_4, {AN1, DM0}},
243{ "add", 0xf240, 0xfff0, FMT_4, {AN1, AM0}},
244{ "add", 0xd400, 0xfc00, FMT_2, {SIMM8, DN0}},
245{ "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
246{ "add", 0xf4600000, 0xfffc0000, FMT_7, {IMM24, DN0}},
247{ "add", 0xd000, 0xfc00, FMT_2, {SIMM8, AN0}},
248{ "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}},
249{ "add", 0xf4640000, 0xfffc0000, FMT_7, {IMM24, AN0}},
250{ "addc", 0xf280, 0xfff0, FMT_4, {DN1, DM0}},
251{ "addnf", 0xf50c00, 0xfffc00, FMT_5, {SIMM8, AN0}},
252
253{ "sub", 0xa0, 0xf0, FMT_1, {DN1, DM0}},
254{ "sub", 0xf210, 0xfff0, FMT_4, {DN1, AN0}},
255{ "sub", 0xf2d0, 0xfff0, FMT_4, {AN1, DM0}},
256{ "sub", 0xf250, 0xfff0, FMT_4, {AN1, AM0}},
257{ "sub", 0xf71c0000, 0xfffc0000, FMT_6, {IMM16, DN0}},
258{ "sub", 0xf4680000, 0xfffc0000, FMT_7, {IMM24, DN0}},
259{ "sub", 0xf70c0000, 0xfffc0000, FMT_6, {IMM16, AN0}},
260{ "sub", 0xf46c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
261{ "subc", 0xf290, 0xfff0, FMT_4, {DN1, DM0}},
262
263{ "mul", 0xf340, 0xfff0, FMT_4, {DN1, DM0}},
264{ "mulu", 0xf350, 0xfff0, FMT_4, {DN1, DM0}},
265
266{ "divu", 0xf360, 0xfff0, FMT_4, {DN1, DM0}},
267
268{ "cmp", 0xf390, 0xfff0, FMT_4, {DN1, DM0}},
269{ "cmp", 0xf220, 0xfff0, FMT_4, {DM1, AN0}},
270{ "cmp", 0xf2e0, 0xfff0, FMT_4, {AN1, DM0}},
271{ "cmp", 0xf260, 0xfff0, FMT_4, {AN1, AM0}},
272{ "cmp", 0xd800, 0xfc00, FMT_2, {SIMM8, DN0}},
273{ "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
274{ "cmp", 0xf4780000, 0xfffc0000, FMT_7, {IMM24, DN0}},
275{ "cmp", 0xec0000, 0xfc0000, FMT_3, {IMM16, AN0}},
276{ "cmp", 0xf47c0000, 0xfffc0000, FMT_7, {IMM24, AN0}},
277
278{ "and", 0xf300, 0xfff0, FMT_4, {DN1, DM0}},
279{ "and", 0xf50000, 0xfffc00, FMT_5, {IMM8, DN0}},
280{ "and", 0xf7000000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
281{ "and", 0xf7100000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
282{ "or", 0xf310, 0xfff0, FMT_4, {DN1, DM0}},
283{ "or", 0xf50800, 0xfffc00, FMT_5, {IMM8, DN0}},
284{ "or", 0xf7400000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
285{ "or", 0xf7140000, 0xffff0000, FMT_6, {SIMM16N, PSW}},
286{ "xor", 0xf320, 0xfff0, FMT_4, {DN1, DM0}},
287{ "xor", 0xf74c0000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
288{ "not", 0xf3e4, 0xfffc, FMT_4, {DN0}},
289
290{ "asr", 0xf338, 0xfffc, FMT_4, {DN0}},
291{ "lsr", 0xf33c, 0xfffc, FMT_4, {DN0}},
292{ "ror", 0xf334, 0xfffc, FMT_4, {DN0}},
293{ "rol", 0xf330, 0xfffc, FMT_4, {DN0}},
294
295{ "btst", 0xf50400, 0xfffc00, FMT_5, {IMM8, DN0}},
296{ "btst", 0xf7040000, 0xfffc0000, FMT_6, {SIMM16N, DN0}},
297{ "bset", 0xf020, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
298{ "bclr", 0xf030, 0xfff0, FMT_4, {DM0, MEM(AN1)}},
299
300{ "beq", 0xe800, 0xff00, FMT_2, {SD8N_PCREL}},
301{ "bne", 0xe900, 0xff00, FMT_2, {SD8N_PCREL}},
302{ "blt", 0xe000, 0xff00, FMT_2, {SD8N_PCREL}},
303{ "ble", 0xe300, 0xff00, FMT_2, {SD8N_PCREL}},
304{ "bge", 0xe200, 0xff00, FMT_2, {SD8N_PCREL}},
305{ "bgt", 0xe100, 0xff00, FMT_2, {SD8N_PCREL}},
306{ "bcs", 0xe400, 0xff00, FMT_2, {SD8N_PCREL}},
307{ "bls", 0xe700, 0xff00, FMT_2, {SD8N_PCREL}},
308{ "bcc", 0xe600, 0xff00, FMT_2, {SD8N_PCREL}},
309{ "bhi", 0xe500, 0xff00, FMT_2, {SD8N_PCREL}},
310{ "bvc", 0xf5fc00, 0xffff00, FMT_5, {SD8N_PCREL}},
311{ "bvs", 0xf5fd00, 0xffff00, FMT_5, {SD8N_PCREL}},
312{ "bnc", 0xf5fe00, 0xffff00, FMT_5, {SD8N_PCREL}},
313{ "bns", 0xf5ff00, 0xffff00, FMT_5, {SD8N_PCREL}},
314{ "bra", 0xea00, 0xff00, FMT_2, {SD8N_PCREL}},
315
316{ "beqx", 0xf5e800, 0xffff00, FMT_5, {SD8N_PCREL}},
317{ "bnex", 0xf5e900, 0xffff00, FMT_5, {SD8N_PCREL}},
318{ "bltx", 0xf5e000, 0xffff00, FMT_5, {SD8N_PCREL}},
319{ "blex", 0xf5e300, 0xffff00, FMT_5, {SD8N_PCREL}},
320{ "bgex", 0xf5e200, 0xffff00, FMT_5, {SD8N_PCREL}},
321{ "bgtx", 0xf5e100, 0xffff00, FMT_5, {SD8N_PCREL}},
322{ "bcsx", 0xf5e400, 0xffff00, FMT_5, {SD8N_PCREL}},
323{ "blsx", 0xf5e700, 0xffff00, FMT_5, {SD8N_PCREL}},
324{ "bccx", 0xf5e600, 0xffff00, FMT_5, {SD8N_PCREL}},
325{ "bhix", 0xf5e500, 0xffff00, FMT_5, {SD8N_PCREL}},
326{ "bvcx", 0xf5ec00, 0xffff00, FMT_5, {SD8N_PCREL}},
327{ "bvsx", 0xf5ed00, 0xffff00, FMT_5, {SD8N_PCREL}},
328{ "bncx", 0xf5ee00, 0xffff00, FMT_5, {SD8N_PCREL}},
329{ "bnsx", 0xf5ef00, 0xffff00, FMT_5, {SD8N_PCREL}},
330
331{ "jmp", 0xfc0000, 0xff0000, FMT_3, {IMM16_PCREL}},
332{ "jmp", 0xf4e00000, 0xffff0000, FMT_7, {IMM24_PCREL}},
333{ "jmp", 0xf000, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
334{ "jsr", 0xfd0000, 0xff0000, FMT_3, {IMM16_PCREL}},
335{ "jsr", 0xf4e10000, 0xffff0000, FMT_7, {IMM24_PCREL}},
336{ "jsr", 0xf001, 0xfff3, FMT_4, {PAREN,AN1,PAREN}},
337
338{ "nop", 0xf6, 0xff, FMT_1, {UNUSED}},
339
340{ "rts", 0xfe, 0xff, FMT_1, {UNUSED}},
341{ "rti", 0xeb, 0xff, FMT_1, {UNUSED}},
342
343/* Extension. We need some instruction to trigger "emulated syscalls"
344 for our simulator. */
345{ "syscall", 0xf010, 0xffff, FMT_4, {UNUSED}},
346
347/* Extension. When talking to the simulator, gdb requires some instruction
348 that will trigger a "breakpoint" (really just an instruction that isn't
349 otherwise used by the tools. This instruction must be the same size
350 as the smallest instruction on the target machine. In the case of the
351 mn10x00 the "break" instruction must be one byte. 0xff is available on
352 both mn10x00 architectures. */
353{ "break", 0xff, 0xff, FMT_1, {UNUSED}},
354
355{ 0, 0, 0, 0, {0}},
356
357} ;
358
359const int mn10200_num_opcodes =
360 sizeof (mn10200_opcodes) / sizeof (mn10200_opcodes[0]);
361
362
363
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