source: trunk/src/binutils/opcodes/fr30-dis.c@ 580

Last change on this file since 580 was 10, checked in by bird, 22 years ago

Initial revision
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  • Property svn:eol-style set to native
  • Property svn:executable set to *
File size: 20.0 KB
Line 
1/* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS MACHINE GENERATED WITH CGEN.
5- the resultant file is machine generated, cgen-dis.in isn't
6
7Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
8
9This file is part of the GNU Binutils and GDB, the GNU debugger.
10
11This program is free software; you can redistribute it and/or modify
12it under the terms of the GNU General Public License as published by
13the Free Software Foundation; either version 2, or (at your option)
14any later version.
15
16This program is distributed in the hope that it will be useful,
17but WITHOUT ANY WARRANTY; without even the implied warranty of
18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19GNU General Public License for more details.
20
21You should have received a copy of the GNU General Public License
22along with this program; if not, write to the Free Software Foundation, Inc.,
2359 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
34#include "fr30-desc.h"
35#include "fr30-opc.h"
36#include "opintl.h"
37
38/* Default text to print if an instruction isn't recognized. */
39#define UNKNOWN_INSN_MSG _("*unknown*")
40
41static void print_normal
42 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
43static void print_address
44 PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
45static void print_keyword
46 PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
47static void print_insn_normal
48 PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
49 bfd_vma, int));
50static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
51 disassemble_info *, char *, int));
52static int default_print_insn
53 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
54
55
56/* -- disassembler routines inserted here */
57
58/* -- dis.c */
59
60static void
61print_register_list (dis_info, value, offset, load_store)
62 PTR dis_info;
63 long value;
64 long offset;
65 int load_store; /* 0 == load, 1 == store */
66{
67 disassemble_info *info = dis_info;
68 int mask;
69 int index = 0;
70 char* comma = "";
71
72 if (load_store)
73 mask = 0x80;
74 else
75 mask = 1;
76
77 if (value & mask)
78 {
79 (*info->fprintf_func) (info->stream, "r%i", index + offset);
80 comma = ",";
81 }
82
83 for (index = 1; index <= 7; ++index)
84 {
85 if (load_store)
86 mask >>= 1;
87 else
88 mask <<= 1;
89
90 if (value & mask)
91 {
92 (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset);
93 comma = ",";
94 }
95 }
96}
97
98static void
99print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
100 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
101 PTR dis_info;
102 long value;
103 unsigned int attrs ATTRIBUTE_UNUSED;
104 bfd_vma pc ATTRIBUTE_UNUSED;
105 int length ATTRIBUTE_UNUSED;
106{
107 print_register_list (dis_info, value, 8, 0/*load*/);
108}
109
110static void
111print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
112 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
113 PTR dis_info;
114 long value;
115 unsigned int attrs ATTRIBUTE_UNUSED;
116 bfd_vma pc ATTRIBUTE_UNUSED;
117 int length ATTRIBUTE_UNUSED;
118{
119 print_register_list (dis_info, value, 0, 0/*load*/);
120}
121
122static void
123print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
124 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
125 PTR dis_info;
126 long value;
127 unsigned int attrs ATTRIBUTE_UNUSED;
128 bfd_vma pc ATTRIBUTE_UNUSED;
129 int length ATTRIBUTE_UNUSED;
130{
131 print_register_list (dis_info, value, 8, 1/*store*/);
132}
133
134static void
135print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
136 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
137 PTR dis_info;
138 long value;
139 unsigned int attrs ATTRIBUTE_UNUSED;
140 bfd_vma pc ATTRIBUTE_UNUSED;
141 int length ATTRIBUTE_UNUSED;
142{
143 print_register_list (dis_info, value, 0, 1/*store*/);
144}
145
146static void
147print_m4 (cd, dis_info, value, attrs, pc, length)
148 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
149 PTR dis_info;
150 long value;
151 unsigned int attrs ATTRIBUTE_UNUSED;
152 bfd_vma pc ATTRIBUTE_UNUSED;
153 int length ATTRIBUTE_UNUSED;
154{
155 disassemble_info *info = (disassemble_info *) dis_info;
156 (*info->fprintf_func) (info->stream, "%ld", value);
157}
158/* -- */
159
160/* Main entry point for printing operands.
161 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
162 of dis-asm.h on cgen.h.
163
164 This function is basically just a big switch statement. Earlier versions
165 used tables to look up the function to use, but
166 - if the table contains both assembler and disassembler functions then
167 the disassembler contains much of the assembler and vice-versa,
168 - there's a lot of inlining possibilities as things grow,
169 - using a switch statement avoids the function call overhead.
170
171 This function could be moved into `print_insn_normal', but keeping it
172 separate makes clear the interface between `print_insn_normal' and each of
173 the handlers.
174*/
175
176void
177fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
178 CGEN_CPU_DESC cd;
179 int opindex;
180 PTR xinfo;
181 CGEN_FIELDS *fields;
182 void const *attrs ATTRIBUTE_UNUSED;
183 bfd_vma pc;
184 int length;
185{
186 disassemble_info *info = (disassemble_info *) xinfo;
187
188 switch (opindex)
189 {
190 case FR30_OPERAND_CRI :
191 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRi, 0);
192 break;
193 case FR30_OPERAND_CRJ :
194 print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0);
195 break;
196 case FR30_OPERAND_R13 :
197 print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0);
198 break;
199 case FR30_OPERAND_R14 :
200 print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0);
201 break;
202 case FR30_OPERAND_R15 :
203 print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0);
204 break;
205 case FR30_OPERAND_RI :
206 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0);
207 break;
208 case FR30_OPERAND_RIC :
209 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ric, 0);
210 break;
211 case FR30_OPERAND_RJ :
212 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rj, 0);
213 break;
214 case FR30_OPERAND_RJC :
215 print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Rjc, 0);
216 break;
217 case FR30_OPERAND_RS1 :
218 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs1, 0);
219 break;
220 case FR30_OPERAND_RS2 :
221 print_keyword (cd, info, & fr30_cgen_opval_dr_names, fields->f_Rs2, 0);
222 break;
223 case FR30_OPERAND_CC :
224 print_normal (cd, info, fields->f_cc, 0, pc, length);
225 break;
226 case FR30_OPERAND_CCC :
227 print_normal (cd, info, fields->f_ccc, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
228 break;
229 case FR30_OPERAND_DIR10 :
230 print_normal (cd, info, fields->f_dir10, 0, pc, length);
231 break;
232 case FR30_OPERAND_DIR8 :
233 print_normal (cd, info, fields->f_dir8, 0, pc, length);
234 break;
235 case FR30_OPERAND_DIR9 :
236 print_normal (cd, info, fields->f_dir9, 0, pc, length);
237 break;
238 case FR30_OPERAND_DISP10 :
239 print_normal (cd, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
240 break;
241 case FR30_OPERAND_DISP8 :
242 print_normal (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
243 break;
244 case FR30_OPERAND_DISP9 :
245 print_normal (cd, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
246 break;
247 case FR30_OPERAND_I20 :
248 print_normal (cd, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
249 break;
250 case FR30_OPERAND_I32 :
251 print_normal (cd, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
252 break;
253 case FR30_OPERAND_I8 :
254 print_normal (cd, info, fields->f_i8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
255 break;
256 case FR30_OPERAND_LABEL12 :
257 print_address (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
258 break;
259 case FR30_OPERAND_LABEL9 :
260 print_address (cd, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
261 break;
262 case FR30_OPERAND_M4 :
263 print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
264 break;
265 case FR30_OPERAND_PS :
266 print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0);
267 break;
268 case FR30_OPERAND_REGLIST_HI_LD :
269 print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length);
270 break;
271 case FR30_OPERAND_REGLIST_HI_ST :
272 print_hi_register_list_st (cd, info, fields->f_reglist_hi_st, 0, pc, length);
273 break;
274 case FR30_OPERAND_REGLIST_LOW_LD :
275 print_low_register_list_ld (cd, info, fields->f_reglist_low_ld, 0, pc, length);
276 break;
277 case FR30_OPERAND_REGLIST_LOW_ST :
278 print_low_register_list_st (cd, info, fields->f_reglist_low_st, 0, pc, length);
279 break;
280 case FR30_OPERAND_S10 :
281 print_normal (cd, info, fields->f_s10, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
282 break;
283 case FR30_OPERAND_U10 :
284 print_normal (cd, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
285 break;
286 case FR30_OPERAND_U4 :
287 print_normal (cd, info, fields->f_u4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
288 break;
289 case FR30_OPERAND_U4C :
290 print_normal (cd, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
291 break;
292 case FR30_OPERAND_U8 :
293 print_normal (cd, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
294 break;
295 case FR30_OPERAND_UDISP6 :
296 print_normal (cd, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
297 break;
298
299 default :
300 /* xgettext:c-format */
301 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
302 opindex);
303 abort ();
304 }
305}
306
307cgen_print_fn * const fr30_cgen_print_handlers[] =
308{
309 print_insn_normal,
310};
311
312
313void
314fr30_cgen_init_dis (cd)
315 CGEN_CPU_DESC cd;
316{
317 fr30_cgen_init_opcode_table (cd);
318 fr30_cgen_init_ibld_table (cd);
319 cd->print_handlers = & fr30_cgen_print_handlers[0];
320 cd->print_operand = fr30_cgen_print_operand;
321}
322
323
324
325/* Default print handler. */
326
327static void
328print_normal (cd, dis_info, value, attrs, pc, length)
329#ifdef CGEN_PRINT_NORMAL
330 CGEN_CPU_DESC cd;
331#else
332 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
333#endif
334 PTR dis_info;
335 long value;
336 unsigned int attrs;
337#ifdef CGEN_PRINT_NORMAL
338 bfd_vma pc;
339 int length;
340#else
341 bfd_vma pc ATTRIBUTE_UNUSED;
342 int length ATTRIBUTE_UNUSED;
343#endif
344{
345 disassemble_info *info = (disassemble_info *) dis_info;
346
347#ifdef CGEN_PRINT_NORMAL
348 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
349#endif
350
351 /* Print the operand as directed by the attributes. */
352 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
353 ; /* nothing to do */
354 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
355 (*info->fprintf_func) (info->stream, "%ld", value);
356 else
357 (*info->fprintf_func) (info->stream, "0x%lx", value);
358}
359
360/* Default address handler. */
361
362static void
363print_address (cd, dis_info, value, attrs, pc, length)
364#ifdef CGEN_PRINT_NORMAL
365 CGEN_CPU_DESC cd;
366#else
367 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
368#endif
369 PTR dis_info;
370 bfd_vma value;
371 unsigned int attrs;
372#ifdef CGEN_PRINT_NORMAL
373 bfd_vma pc;
374 int length;
375#else
376 bfd_vma pc ATTRIBUTE_UNUSED;
377 int length ATTRIBUTE_UNUSED;
378#endif
379{
380 disassemble_info *info = (disassemble_info *) dis_info;
381
382#ifdef CGEN_PRINT_ADDRESS
383 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
384#endif
385
386 /* Print the operand as directed by the attributes. */
387 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
388 ; /* nothing to do */
389 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
390 (*info->print_address_func) (value, info);
391 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
392 (*info->print_address_func) (value, info);
393 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
394 (*info->fprintf_func) (info->stream, "%ld", (long) value);
395 else
396 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
397}
398
399/* Keyword print handler. */
400
401static void
402print_keyword (cd, dis_info, keyword_table, value, attrs)
403 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
404 PTR dis_info;
405 CGEN_KEYWORD *keyword_table;
406 long value;
407 unsigned int attrs ATTRIBUTE_UNUSED;
408{
409 disassemble_info *info = (disassemble_info *) dis_info;
410 const CGEN_KEYWORD_ENTRY *ke;
411
412 ke = cgen_keyword_lookup_value (keyword_table, value);
413 if (ke != NULL)
414 (*info->fprintf_func) (info->stream, "%s", ke->name);
415 else
416 (*info->fprintf_func) (info->stream, "???");
417}
418
419
420/* Default insn printer.
421
422 DIS_INFO is defined as `PTR' so the disassembler needn't know anything
423 about disassemble_info. */
424
425static void
426print_insn_normal (cd, dis_info, insn, fields, pc, length)
427 CGEN_CPU_DESC cd;
428 PTR dis_info;
429 const CGEN_INSN *insn;
430 CGEN_FIELDS *fields;
431 bfd_vma pc;
432 int length;
433{
434 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
435 disassemble_info *info = (disassemble_info *) dis_info;
436 const unsigned char *syn;
437
438 CGEN_INIT_PRINT (cd);
439
440 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
441 {
442 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
443 {
444 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
445 continue;
446 }
447 if (CGEN_SYNTAX_CHAR_P (*syn))
448 {
449 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
450 continue;
451 }
452
453 /* We have an operand. */
454 fr30_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
455 fields, CGEN_INSN_ATTRS (insn), pc, length);
456 }
457}
458
459
460/* Subroutine of print_insn. Reads an insn into the given buffers and updates
461 the extract info.
462 Returns 0 if all is well, non-zero otherwise. */
463static int
464read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
465 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
466 bfd_vma pc;
467 disassemble_info *info;
468 char *buf;
469 int buflen;
470 CGEN_EXTRACT_INFO *ex_info;
471 unsigned long *insn_value;
472{
473 int status = (*info->read_memory_func) (pc, buf, buflen, info);
474 if (status != 0)
475 {
476 (*info->memory_error_func) (status, pc, info);
477 return -1;
478 }
479
480 ex_info->dis_info = info;
481 ex_info->valid = (1 << buflen) - 1;
482 ex_info->insn_bytes = buf;
483
484 switch (buflen)
485 {
486 case 1:
487 *insn_value = buf[0];
488 break;
489 case 2:
490 *insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
491 break;
492 case 4:
493 *insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
494 break;
495 default:
496 abort ();
497 }
498
499 return 0;
500}
501
502/* Utility to print an insn.
503 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
504 The result is the size of the insn in bytes or zero for an unknown insn
505 or -1 if an error occurs fetching data (memory_error_func will have
506 been called). */
507
508static int
509print_insn (cd, pc, info, buf, buflen)
510 CGEN_CPU_DESC cd;
511 bfd_vma pc;
512 disassemble_info *info;
513 char *buf;
514 int buflen;
515{
516 unsigned long insn_value;
517 const CGEN_INSN_LIST *insn_list;
518 CGEN_EXTRACT_INFO ex_info;
519
520 int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value);
521 if (rc != 0)
522 return rc;
523
524 /* The instructions are stored in hash lists.
525 Pick the first one and keep trying until we find the right one. */
526
527 insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
528 while (insn_list != NULL)
529 {
530 const CGEN_INSN *insn = insn_list->insn;
531 CGEN_FIELDS fields;
532 int length;
533
534#ifdef CGEN_VALIDATE_INSN_SUPPORTED
535 /* not needed as insn shouldn't be in hash lists if not supported */
536 /* Supported by this cpu? */
537 if (! fr30_cgen_insn_supported (cd, insn))
538 {
539 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
540 continue;
541 }
542#endif
543
544 /* Basic bit mask must be correct. */
545 /* ??? May wish to allow target to defer this check until the extract
546 handler. */
547 if ((insn_value & CGEN_INSN_BASE_MASK (insn))
548 == CGEN_INSN_BASE_VALUE (insn))
549 {
550 /* Printing is handled in two passes. The first pass parses the
551 machine insn and extracts the fields. The second pass prints
552 them. */
553
554 /* Make sure the entire insn is loaded into insn_value, if it
555 can fit. */
556 if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
557 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
558 {
559 unsigned long full_insn_value;
560 int rc = read_insn (cd, pc, info, buf,
561 CGEN_INSN_BITSIZE (insn) / 8,
562 & ex_info, & full_insn_value);
563 if (rc != 0)
564 return rc;
565 length = CGEN_EXTRACT_FN (cd, insn)
566 (cd, insn, &ex_info, full_insn_value, &fields, pc);
567 }
568 else
569 length = CGEN_EXTRACT_FN (cd, insn)
570 (cd, insn, &ex_info, insn_value, &fields, pc);
571
572 /* length < 0 -> error */
573 if (length < 0)
574 return length;
575 if (length > 0)
576 {
577 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
578 /* length is in bits, result is in bytes */
579 return length / 8;
580 }
581 }
582
583 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
584 }
585
586 return 0;
587}
588
589/* Default value for CGEN_PRINT_INSN.
590 The result is the size of the insn in bytes or zero for an unknown insn
591 or -1 if an error occured fetching bytes. */
592
593#ifndef CGEN_PRINT_INSN
594#define CGEN_PRINT_INSN default_print_insn
595#endif
596
597static int
598default_print_insn (cd, pc, info)
599 CGEN_CPU_DESC cd;
600 bfd_vma pc;
601 disassemble_info *info;
602{
603 char buf[CGEN_MAX_INSN_SIZE];
604 int status;
605
606 /* Read the base part of the insn. */
607
608 status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info);
609 if (status != 0)
610 {
611 (*info->memory_error_func) (status, pc, info);
612 return -1;
613 }
614
615 return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8);
616}
617
618/* Main entry point.
619 Print one instruction from PC on INFO->STREAM.
620 Return the size of the instruction (in bytes). */
621
622int
623print_insn_fr30 (pc, info)
624 bfd_vma pc;
625 disassemble_info *info;
626{
627 static CGEN_CPU_DESC cd = 0;
628 static int prev_isa;
629 static int prev_mach;
630 static int prev_endian;
631 int length;
632 int isa,mach;
633 int endian = (info->endian == BFD_ENDIAN_BIG
634 ? CGEN_ENDIAN_BIG
635 : CGEN_ENDIAN_LITTLE);
636 enum bfd_architecture arch;
637
638 /* ??? gdb will set mach but leave the architecture as "unknown" */
639#ifndef CGEN_BFD_ARCH
640#define CGEN_BFD_ARCH bfd_arch_fr30
641#endif
642 arch = info->arch;
643 if (arch == bfd_arch_unknown)
644 arch = CGEN_BFD_ARCH;
645
646 /* There's no standard way to compute the isa number (e.g. for arm thumb)
647 so we leave it to the target. */
648#ifdef CGEN_COMPUTE_ISA
649 isa = CGEN_COMPUTE_ISA (info);
650#else
651 isa = 0;
652#endif
653
654 mach = info->mach;
655
656 /* If we've switched cpu's, close the current table and open a new one. */
657 if (cd
658 && (isa != prev_isa
659 || mach != prev_mach
660 || endian != prev_endian))
661 {
662 fr30_cgen_cpu_close (cd);
663 cd = 0;
664 }
665
666 /* If we haven't initialized yet, initialize the opcode table. */
667 if (! cd)
668 {
669 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
670 const char *mach_name;
671
672 if (!arch_type)
673 abort ();
674 mach_name = arch_type->printable_name;
675
676 prev_isa = isa;
677 prev_mach = mach;
678 prev_endian = endian;
679 cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
680 CGEN_CPU_OPEN_BFDMACH, mach_name,
681 CGEN_CPU_OPEN_ENDIAN, prev_endian,
682 CGEN_CPU_OPEN_END);
683 if (!cd)
684 abort ();
685 fr30_cgen_init_dis (cd);
686 }
687
688 /* We try to have as much common code as possible.
689 But at this point some targets need to take over. */
690 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
691 but if not possible try to move this hook elsewhere rather than
692 have two hooks. */
693 length = CGEN_PRINT_INSN (cd, pc, info);
694 if (length > 0)
695 return length;
696 if (length < 0)
697 return -1;
698
699 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
700 return cd->default_insn_bitsize / 8;
701}
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