source: trunk/src/binutils/opcodes/d10v-opc.c@ 1036

Last change on this file since 1036 was 610, checked in by bird, 22 years ago

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1/* d10v-opc.c -- D10V opcode list
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Written by Martin Hunt, Cygnus Support
4
5This file is part of GDB, GAS, and the GNU binutils.
6
7GDB, GAS, and the GNU binutils are free software; you can redistribute
8them and/or modify them under the terms of the GNU General Public
9License as published by the Free Software Foundation; either version
102, or (at your option) any later version.
11
12GDB, GAS, and the GNU binutils are distributed in the hope that they
13will be useful, but WITHOUT ANY WARRANTY; without even the implied
14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15the GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this file; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include <stdio.h>
22#include "sysdep.h"
23#include "opcode/d10v.h"
24
25
26/* The table is sorted. Suitable for searching by a binary search. */
27const struct pd_reg d10v_predefined_registers[] =
28{
29 { "a0", NULL, OPERAND_ACC0+0 },
30 { "a1", NULL, OPERAND_ACC1+1 },
31 { "bpc", NULL, OPERAND_CONTROL+3 },
32 { "bpsw", NULL, OPERAND_CONTROL+1 },
33 { "c", NULL, OPERAND_CFLAG+3 },
34 { "cr0", "psw", OPERAND_CONTROL },
35 { "cr1", "bpsw", OPERAND_CONTROL+1 },
36 { "cr10", "mod_s", OPERAND_CONTROL+10 },
37 { "cr11", "mod_e", OPERAND_CONTROL+11 },
38 { "cr12", NULL, OPERAND_CONTROL+12 },
39 { "cr13", NULL, OPERAND_CONTROL+13 },
40 { "cr14", "iba", OPERAND_CONTROL+14 },
41 { "cr15", NULL, OPERAND_CONTROL+15 },
42 { "cr2", "pc", OPERAND_CONTROL+2 },
43 { "cr3", "bpc", OPERAND_CONTROL+3 },
44 { "cr4", "dpsw", OPERAND_CONTROL+4 },
45 { "cr5", "dpc", OPERAND_CONTROL+5 },
46 { "cr6", NULL, OPERAND_CONTROL+6 },
47 { "cr7", "rpt_c", OPERAND_CONTROL+7 },
48 { "cr8", "rpt_s", OPERAND_CONTROL+8 },
49 { "cr9", "rpt_e", OPERAND_CONTROL+9 },
50 { "dpc", NULL, OPERAND_CONTROL+5 },
51 { "dpsw", NULL, OPERAND_CONTROL+4 },
52 { "f0", NULL, OPERAND_FFLAG+0 },
53 { "f1", NULL, OPERAND_FFLAG+1 },
54 { "iba", NULL, OPERAND_CONTROL+14 },
55 { "link", "r13", OPERAND_GPR+13 },
56 { "mod_e", NULL, OPERAND_CONTROL+11 },
57 { "mod_s", NULL, OPERAND_CONTROL+10 },
58 { "pc", NULL, OPERAND_CONTROL+2 },
59 { "psw", NULL, OPERAND_CONTROL+0 },
60 { "r0", NULL, OPERAND_GPR+0 },
61 { "r0-r1", NULL, OPERAND_GPR+0},
62 { "r1", NULL, OPERAND_GPR+1 },
63 { "r1", NULL, OPERAND_GPR+1 },
64 { "r10", NULL, OPERAND_GPR+10 },
65 { "r10-r11", NULL, OPERAND_GPR+10 },
66 { "r11", NULL, OPERAND_GPR+11 },
67 { "r12", NULL, OPERAND_GPR+12 },
68 { "r12-r13", NULL, OPERAND_GPR+12 },
69 { "r13", NULL, OPERAND_GPR+13 },
70 { "r14", NULL, OPERAND_GPR+14 },
71 { "r14-r15", NULL, OPERAND_GPR+14 },
72 { "r15", "sp", OPERAND_SP|(OPERAND_GPR+15) },
73 { "r2", NULL, OPERAND_GPR+2 },
74 { "r2-r3", NULL, OPERAND_GPR+2 },
75 { "r3", NULL, OPERAND_GPR+3 },
76 { "r4", NULL, OPERAND_GPR+4 },
77 { "r4-r5", NULL, OPERAND_GPR+4 },
78 { "r5", NULL, OPERAND_GPR+5 },
79 { "r6", NULL, OPERAND_GPR+6 },
80 { "r6-r7", NULL, OPERAND_GPR+6 },
81 { "r7", NULL, OPERAND_GPR+7 },
82 { "r8", NULL, OPERAND_GPR+8 },
83 { "r8-r9", NULL, OPERAND_GPR+8 },
84 { "r9", NULL, OPERAND_GPR+9 },
85 { "rpt_c", NULL, OPERAND_CONTROL+7 },
86 { "rpt_e", NULL, OPERAND_CONTROL+9 },
87 { "rpt_s", NULL, OPERAND_CONTROL+8 },
88 { "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) },
89};
90
91int
92d10v_reg_name_cnt()
93{
94 return (sizeof(d10v_predefined_registers) / sizeof(struct pd_reg));
95}
96
97const struct d10v_operand d10v_operands[] =
98{
99#define UNUSED (0)
100 { 0, 0, 0 },
101#define RSRC (UNUSED + 1)
102 { 4, 1, OPERAND_GPR|OPERAND_REG },
103#define RSRC_SP (RSRC + 1)
104 { 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG },
105#define RSRC_NOSP (RSRC_SP + 1)
106 { 4, 1, OPERAND_NOSP|OPERAND_GPR|OPERAND_REG },
107#define RDST (RSRC_NOSP + 1)
108 { 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG },
109#define ASRC (RDST + 1)
110 { 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
111#define ASRC0ONLY (ASRC + 1)
112 { 1, 4, OPERAND_ACC0|OPERAND_REG },
113#define ADST (ASRC0ONLY + 1)
114 { 1, 8, OPERAND_DEST|OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
115#define RSRCE (ADST + 1)
116 { 4, 1, OPERAND_EVEN|OPERAND_GPR|OPERAND_REG },
117#define RDSTE (RSRCE + 1)
118 { 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_GPR|OPERAND_REG },
119#define NUM16 (RDSTE + 1)
120 { 16, 0, OPERAND_NUM|OPERAND_SIGNED },
121#define NUM3 (NUM16 + 1) /* rac, rachi */
122 { 3, 1, OPERAND_NUM|OPERAND_SIGNED|RESTRICTED_NUM3 },
123#define NUM4 (NUM3 + 1)
124 { 4, 1, OPERAND_NUM|OPERAND_SIGNED },
125#define UNUM4 (NUM4 + 1)
126 { 4, 1, OPERAND_NUM },
127#define UNUM4S (UNUM4 + 1) /* addi, slli, srai, srli, subi */
128 { 4, 1, OPERAND_NUM|OPERAND_SHIFT },
129#define UNUM8 (UNUM4S + 1) /* repi */
130 { 8, 16, OPERAND_NUM },
131#define UNUM16 (UNUM8 + 1) /* cmpui */
132 { 16, 0, OPERAND_NUM },
133#define ANUM16 (UNUM16 + 1)
134 { 16, 0, OPERAND_ADDR|OPERAND_SIGNED },
135#define ANUM8 (ANUM16 + 1)
136 { 8, 0, OPERAND_ADDR|OPERAND_SIGNED },
137#define ASRC2 (ANUM8 + 1)
138 { 1, 8, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
139#define RSRC2 (ASRC2 + 1)
140 { 4, 5, OPERAND_GPR|OPERAND_REG },
141#define RSRC2E (RSRC2 + 1)
142 { 4, 5, OPERAND_GPR|OPERAND_REG|OPERAND_EVEN },
143#define ASRC0 (RSRC2E + 1)
144 { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
145#define ADST0 (ASRC0 + 1)
146 { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG|OPERAND_DEST },
147#define FFSRC (ADST0 + 1)
148 { 2, 1, OPERAND_REG | OPERAND_FFLAG },
149#define CFSRC (FFSRC + 1)
150 { 2, 1, OPERAND_REG | OPERAND_CFLAG },
151#define FDST (CFSRC + 1)
152 { 1, 5, OPERAND_REG | OPERAND_FFLAG | OPERAND_DEST},
153#define ATSIGN (FDST + 1)
154 { 0, 0, OPERAND_ATSIGN},
155#define ATPAR (ATSIGN + 1) /* "@(" */
156 { 0, 0, OPERAND_ATPAR},
157#define PLUS (ATPAR + 1) /* postincrement */
158 { 0, 0, OPERAND_PLUS},
159#define MINUS (PLUS + 1) /* postdecrement */
160 { 0, 0, OPERAND_MINUS},
161#define ATMINUS (MINUS + 1) /* predecrement */
162 { 0, 0, OPERAND_ATMINUS},
163#define CSRC (ATMINUS + 1) /* control register */
164 { 4, 1, OPERAND_REG|OPERAND_CONTROL},
165#define CDST (CSRC + 1) /* control register */
166 { 4, 5, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
167};
168
169const struct d10v_opcode d10v_opcodes[] = {
170 { "abs", SHORT_2, 1, EITHER, PAR|WF0, 0x4607, 0x7e1f, { RDST } },
171 { "abs", SHORT_2, 1, IU, PAR|WF0, 0x5607, 0x7eff, { ADST } },
172 { "add", SHORT_2, 1, EITHER, PAR|WCAR, 0x0200, 0x7e01, { RDST, RSRC } },
173 { "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } },
174 { "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } },
175 { "add2w", SHORT_2, 2, IU, PAR|WCAR, 0x1200, 0x7e23, { RDSTE, RSRCE } },
176 { "add3", LONG_L, 1, MU, SEQ|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } },
177 { "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
178 { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
179 { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
180 { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
181 { "addi", SHORT_2, 1, EITHER, PAR|WCAR, 0x201, 0x7e01, { RDST, UNUM4S } },
182 { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } },
183 { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } },
184 { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } },
185 { "bl", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
186 { "bl.s", SHORT_B, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4900, 0x7f00, { ANUM8 } },
187 { "bl.l", LONG_B, 3, MU, BRANCH_LINK|SEQ, 0x24800000, 0x3fff0000, { ANUM16 } },
188 { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } },
189 { "bra", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
190 { "bra.s", SHORT_B, 3, MU, ALONE|BRANCH|PAR, 0x4800, 0x7f00, { ANUM8 } },
191 { "bra.l", LONG_B, 3, MU, BRANCH|SEQ, 0x24000000, 0x3fff0000, { ANUM16 } },
192 { "brf0f", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
193 { "brf0f.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4a00, 0x7f00, { ANUM8 } },
194 { "brf0f.l", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } },
195 { "brf0t", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
196 { "brf0t.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4b00, 0x7f00, { ANUM8 } },
197 { "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } },
198 { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } },
199 { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RSRC2, UNUM4 } },
200 { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } },
201 { "cmp", SHORT_2, 1, EITHER, PAR|WF0, 0x600, 0x7e01, { RSRC2, RSRC } },
202 { "cmp", SHORT_2, 1, IU, PAR|WF0, 0x1603, 0x7eef, { ASRC2, ASRC } },
203 { "cmpeq", SHORT_2, 1, EITHER, PAR|WF0, 0x400, 0x7e01, { RSRC2, RSRC } },
204 { "cmpeq", SHORT_2, 1, IU, PAR|WF0, 0x1403, 0x7eef, { ASRC2, ASRC } },
205 { "cmpeqi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
206 { "cmpeqi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x401, 0x7e01, { RSRC2, NUM4 } },
207 { "cmpeqi.l", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } },
208 { "cmpi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
209 { "cmpi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x601, 0x7e01, { RSRC2, NUM4 } },
210 { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } },
211 { "cmpu", SHORT_2, 1, EITHER, PAR|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } },
212 { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } },
213 { "cpfg", SHORT_2, 1, MU, PAR, 0x4e0f, 0x7fdf, { FDST, CFSRC } },
214 { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } },
215 { "dbt", SHORT_2, 5, MU, ALONE|PAR, 0x5f20, 0x7fff, { 0 } },
216 { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } },
217 { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } },
218 { "exef0t", SHORT_2, 1, EITHER, PARONLY, 0x4e24, 0x7fff, { 0 } },
219 { "exef1f", SHORT_2, 1, EITHER, PARONLY, 0x4e40, 0x7fff, { 0 } },
220 { "exef1t", SHORT_2, 1, EITHER, PARONLY, 0x4e42, 0x7fff, { 0 } },
221 { "exefaf", SHORT_2, 1, EITHER, PARONLY, 0x4e00, 0x7fff, { 0 } },
222 { "exefat", SHORT_2, 1, EITHER, PARONLY, 0x4e02, 0x7fff, { 0 } },
223 { "exetaf", SHORT_2, 1, EITHER, PARONLY, 0x4e20, 0x7fff, { 0 } },
224 { "exetat", SHORT_2, 1, EITHER, PARONLY, 0x4e22, 0x7fff, { 0 } },
225 { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } },
226 { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } },
227 { "jl", SHORT_2, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4d00, 0x7fe1, { RSRC } },
228 { "jmp", SHORT_2, 3, MU, ALONE|BRANCH|PAR, 0x4c00, 0x7fe1, { RSRC } },
229 { "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
230 { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } },
231 { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } },
232 { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } },
233 { "ld", LONG_L, 1, MU, SEQ, 0x32010000, 0x3f0f0000, { RDST, ATSIGN, NUM16 } },
234 { "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } },
235 { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } },
236 { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } },
237 { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } },
238 { "ld2w", LONG_L, 1, MU, SEQ, 0x33010000, 0x3f1f0000, { RDSTE, ATSIGN, NUM16 } },
239 { "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
240 { "ldb", SHORT_2, 1, MU, PAR|RMEM, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } },
241 { "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
242 { "ldi.s", SHORT_2, 1, EITHER, PAR|RMEM, 0x4001, 0x7e01 , { RDST, NUM4 } },
243 { "ldi.l", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } },
244 { "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
245 { "ldub", SHORT_2, 1, MU, PAR|RMEM, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } },
246 { "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } },
247 { "macsu", SHORT_2, 1, IU, PAR, 0x1a00, 0x7e00, { ADST0, RSRC2, RSRC } },
248 { "macu", SHORT_2, 1, IU, PAR, 0x3a00, 0x7e00, { ADST0, RSRC2, RSRC } },
249 { "max", SHORT_2, 1, IU, PAR|WF0, 0x2600, 0x7e01, { RDST, RSRC } },
250 { "max", SHORT_2, 1, IU, PAR|WF0, 0x3600, 0x7ee3, { ADST, RSRCE } },
251 { "max", SHORT_2, 1, IU, PAR|WF0, 0x3602, 0x7eef, { ADST, ASRC } },
252 { "min", SHORT_2, 1, IU, PAR|WF0, 0x2601, 0x7e01 , { RDST, RSRC } },
253 { "min", SHORT_2, 1, IU, PAR|WF0, 0x3601, 0x7ee3 , { ADST, RSRCE } },
254 { "min", SHORT_2, 1, IU, PAR|WF0, 0x3603, 0x7eef, { ADST, ASRC } },
255 { "msb", SHORT_2, 1, IU, PAR, 0x2800, 0x7e00, { ADST0, RSRC2, RSRC } },
256 { "msbsu", SHORT_2, 1, IU, PAR, 0x1800, 0x7e00, { ADST0, RSRC2, RSRC } },
257 { "msbu", SHORT_2, 1, IU, PAR, 0x3800, 0x7e00, { ADST0, RSRC2, RSRC } },
258 { "mul", SHORT_2, 1, IU, PAR, 0x2e00, 0x7e01 , { RDST, RSRC } },
259 { "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } },
260 { "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } },
261 { "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } },
262 { "mv", SHORT_2, 1, EITHER, PAR, 0x4000, 0x7e01, { RDST, RSRC } },
263 { "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } },
264 { "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } },
265 { "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } },
266 { "mvac", SHORT_2, 1, IU, PAR, 0x3e03, 0x7eef, { ADST, ASRC } },
267 { "mvb", SHORT_2, 1, IU, PAR, 0x5400, 0x7e01, { RDST, RSRC } },
268 { "mvf0f", SHORT_2, 1, EITHER, PAR|RF0, 0x4400, 0x7e01, { RDST, RSRC } },
269 { "mvf0t", SHORT_2, 1, EITHER, PAR|RF0, 0x4401, 0x7e01, { RDST, RSRC } },
270 { "mvfacg", SHORT_2, 1, IU, PAR, 0x1e04, 0x7e0f, { RDST, ASRC } },
271 { "mvfachi", SHORT_2, 1, IU, PAR, 0x1e00, 0x7e0f, { RDST, ASRC } },
272 { "mvfaclo", SHORT_2, 1, IU, PAR, 0x1e02, 0x7e0f, { RDST, ASRC } },
273 { "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } },
274 { "mvtacg", SHORT_2, 1, IU, PAR, 0x1e41, 0x7ee1, { RSRC, ADST } },
275 { "mvtachi", SHORT_2, 1, IU, PAR, 0x1e01, 0x7ee1, { RSRC, ADST } },
276 { "mvtaclo", SHORT_2, 1, IU, PAR, 0x1e21, 0x7ee1, { RSRC, ADST } },
277 { "mvtc", SHORT_2, 1, MU, PAR, 0x5600, 0x7e01, { RSRC, CDST } },
278 { "mvub", SHORT_2, 1, IU, PAR, 0x5401, 0x7e01, { RDST, RSRC } },
279 { "neg", SHORT_2, 1, EITHER, PAR, 0x4605, 0x7e1f, { RDST } },
280 { "neg", SHORT_2, 1, IU, PAR, 0x5605, 0x7eff, { ADST } },
281 { "nop", SHORT_2, 1, EITHER, PAR, 0x5e00, 0x7fff, { 0 } },
282 { "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } },
283 { "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } },
284 { "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } },
285 /* Special case. sac&sachi must occur before rac&rachi because they have
286 intersecting masks! The masks for rac&rachi will match sac&sachi but
287 not the other way around.
288 */
289 { "sac", SHORT_2, 1, IU, PAR|RF0|WF0, 0x5209, 0x7e2f, { RDSTE, ASRC } },
290 { "sachi", SHORT_2, 1, IU, PAR|RF0|WF0, 0x4209, 0x7e0f, { RDST, ASRC } },
291 { "rac", SHORT_2, 1, IU, PAR|WF0, 0x5201, 0x7e21, { RDSTE, ASRC0ONLY, NUM3 } },
292 { "rachi", SHORT_2, 1, IU, PAR|WF0, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } },
293 { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } },
294 { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { UNUM8, ANUM16 } },
295 { "rtd", SHORT_2, 3, MU, ALONE|PAR, 0x5f60, 0x7fff, { 0 } },
296 { "rte", SHORT_2, 3, MU, ALONE|PAR, 0x5f40, 0x7fff, { 0 } },
297 { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } },
298 { "setf0f", SHORT_2, 1, MU, PAR|RF0, 0x4611, 0x7e1f, { RDST } },
299 { "setf0t", SHORT_2, 1, MU, PAR|RF0, 0x4613, 0x7e1f, { RDST } },
300 { "slae", SHORT_2, 1, IU, PAR, 0x3220, 0x7ee1, { ADST, RSRC } },
301 { "sleep", SHORT_2, 1, MU, ALONE|PAR, 0x5fc0, 0x7fff, { 0 } },
302 { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } },
303 { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } },
304 { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, UNUM4 } },
305 { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, UNUM4S } },
306 { "slx", SHORT_2, 1, IU, PAR|RF0, 0x460b, 0x7e1f, { RDST } },
307 { "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } },
308 { "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } },
309 { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, UNUM4 } },
310 { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, UNUM4S } },
311 { "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } },
312 { "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } },
313 { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, UNUM4 } },
314 { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, UNUM4S } },
315 { "srx", SHORT_2, 1, IU, PAR|RF0, 0x4609, 0x7e1f, { RDST } },
316 { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
317 { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
318 { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } },
319 { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } },
320 { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC_NOSP, MINUS } },
321 { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } },
322 { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } },
323 { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } },
324 { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } },
325 { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } },
326 { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC_NOSP, MINUS } },
327 { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } },
328 { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
329 { "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
330 { "stop", SHORT_2, 1, MU, ALONE|PAR, 0x5fe0, 0x7fff, { 0 } },
331 { "sub", SHORT_2, 1, EITHER, PAR|WCAR, 0x0, 0x7e01, { RDST, RSRC } },
332 { "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } },
333 { "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } },
334 { "sub2w", SHORT_2, 1, IU, PAR|WCAR, 0x1000, 0x7e23, { RDSTE, RSRCE } },
335 { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
336 { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
337 { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
338 { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
339 { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } },
340 { "trap", SHORT_2, 5, MU, ALONE|BRANCH_LINK|PAR, 0x5f00, 0x7fe1, { UNUM4 } },
341 { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } },
342 { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } },
343 { "wait", SHORT_2, 1, MU, ALONE|PAR, 0x5f80, 0x7fff, { 0 } },
344 { "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } },
345 { "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } },
346 { 0, 0, 0, 0, 0, 0, 0, { 0 } },
347};
348
349
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