| 1 | /* Disassembler interface for targets using CGEN. -*- C -*-
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| 2 | CGEN: Cpu tools GENerator
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| 3 |
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| 4 | THIS FILE IS MACHINE GENERATED WITH CGEN.
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| 5 | - the resultant file is machine generated, cgen-dis.in isn't
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| 6 |
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| 7 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
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| 8 |
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| 9 | This file is part of the GNU Binutils and GDB, the GNU debugger.
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| 10 |
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| 11 | This program is free software; you can redistribute it and/or modify
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| 12 | it under the terms of the GNU General Public License as published by
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| 13 | the Free Software Foundation; either version 2, or (at your option)
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| 14 | any later version.
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| 15 |
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| 16 | This program is distributed in the hope that it will be useful,
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| 17 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 19 | GNU General Public License for more details.
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| 20 |
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| 21 | You should have received a copy of the GNU General Public License
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| 22 | along with this program; if not, write to the Free Software Foundation, Inc.,
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| 23 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 24 |
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| 25 | /* ??? Eventually more and more of this stuff can go to cpu-independent files.
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| 26 | Keep that in mind. */
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| 27 |
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| 28 | #include "sysdep.h"
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| 29 | #include <stdio.h>
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| 30 | #include "ansidecl.h"
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| 31 | #include "dis-asm.h"
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| 32 | #include "bfd.h"
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| 33 | #include "symcat.h"
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| 34 | #include "@prefix@-desc.h"
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| 35 | #include "@prefix@-opc.h"
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| 36 | #include "opintl.h"
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| 37 |
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| 38 | /* Default text to print if an instruction isn't recognized. */
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| 39 | #define UNKNOWN_INSN_MSG _("*unknown*")
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| 40 |
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| 41 | static void print_normal
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| 42 | PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
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| 43 | static void print_address
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| 44 | PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
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| 45 | static void print_keyword
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| 46 | PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
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| 47 | static void print_insn_normal
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| 48 | PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
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| 49 | bfd_vma, int));
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| 50 | static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma,
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| 51 | disassemble_info *, char *, int));
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| 52 | static int default_print_insn
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| 53 | PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
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| 54 | |
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| 55 |
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| 56 | /* -- disassembler routines inserted here */
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| 57 | |
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| 58 |
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| 59 | /* Default print handler. */
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| 60 |
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| 61 | static void
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| 62 | print_normal (cd, dis_info, value, attrs, pc, length)
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| 63 | #ifdef CGEN_PRINT_NORMAL
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| 64 | CGEN_CPU_DESC cd;
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| 65 | #else
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| 66 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
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| 67 | #endif
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| 68 | PTR dis_info;
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| 69 | long value;
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| 70 | unsigned int attrs;
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| 71 | #ifdef CGEN_PRINT_NORMAL
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| 72 | bfd_vma pc;
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| 73 | int length;
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| 74 | #else
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| 75 | bfd_vma pc ATTRIBUTE_UNUSED;
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| 76 | int length ATTRIBUTE_UNUSED;
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| 77 | #endif
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| 78 | {
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| 79 | disassemble_info *info = (disassemble_info *) dis_info;
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| 80 |
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| 81 | #ifdef CGEN_PRINT_NORMAL
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| 82 | CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
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| 83 | #endif
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| 84 |
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| 85 | /* Print the operand as directed by the attributes. */
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| 86 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
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| 87 | ; /* nothing to do */
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| 88 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
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| 89 | (*info->fprintf_func) (info->stream, "%ld", value);
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| 90 | else
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| 91 | (*info->fprintf_func) (info->stream, "0x%lx", value);
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| 92 | }
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| 93 |
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| 94 | /* Default address handler. */
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| 95 |
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| 96 | static void
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| 97 | print_address (cd, dis_info, value, attrs, pc, length)
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| 98 | #ifdef CGEN_PRINT_NORMAL
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| 99 | CGEN_CPU_DESC cd;
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| 100 | #else
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| 101 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
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| 102 | #endif
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| 103 | PTR dis_info;
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| 104 | bfd_vma value;
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| 105 | unsigned int attrs;
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| 106 | #ifdef CGEN_PRINT_NORMAL
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| 107 | bfd_vma pc;
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| 108 | int length;
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| 109 | #else
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| 110 | bfd_vma pc ATTRIBUTE_UNUSED;
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| 111 | int length ATTRIBUTE_UNUSED;
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| 112 | #endif
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| 113 | {
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| 114 | disassemble_info *info = (disassemble_info *) dis_info;
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| 115 |
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| 116 | #ifdef CGEN_PRINT_ADDRESS
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| 117 | CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
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| 118 | #endif
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| 119 |
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| 120 | /* Print the operand as directed by the attributes. */
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| 121 | if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
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| 122 | ; /* nothing to do */
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| 123 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
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| 124 | (*info->print_address_func) (value, info);
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| 125 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
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| 126 | (*info->print_address_func) (value, info);
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| 127 | else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
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| 128 | (*info->fprintf_func) (info->stream, "%ld", (long) value);
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| 129 | else
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| 130 | (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
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| 131 | }
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| 132 |
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| 133 | /* Keyword print handler. */
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| 134 |
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| 135 | static void
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| 136 | print_keyword (cd, dis_info, keyword_table, value, attrs)
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| 137 | CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
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| 138 | PTR dis_info;
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| 139 | CGEN_KEYWORD *keyword_table;
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| 140 | long value;
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| 141 | unsigned int attrs ATTRIBUTE_UNUSED;
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| 142 | {
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| 143 | disassemble_info *info = (disassemble_info *) dis_info;
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| 144 | const CGEN_KEYWORD_ENTRY *ke;
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| 145 |
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| 146 | ke = cgen_keyword_lookup_value (keyword_table, value);
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| 147 | if (ke != NULL)
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| 148 | (*info->fprintf_func) (info->stream, "%s", ke->name);
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| 149 | else
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| 150 | (*info->fprintf_func) (info->stream, "???");
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| 151 | }
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| 152 | |
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| 153 |
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| 154 | /* Default insn printer.
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| 155 |
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| 156 | DIS_INFO is defined as `PTR' so the disassembler needn't know anything
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| 157 | about disassemble_info. */
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| 158 |
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| 159 | static void
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| 160 | print_insn_normal (cd, dis_info, insn, fields, pc, length)
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| 161 | CGEN_CPU_DESC cd;
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| 162 | PTR dis_info;
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| 163 | const CGEN_INSN *insn;
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| 164 | CGEN_FIELDS *fields;
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| 165 | bfd_vma pc;
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| 166 | int length;
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| 167 | {
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| 168 | const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
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| 169 | disassemble_info *info = (disassemble_info *) dis_info;
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| 170 | const CGEN_SYNTAX_CHAR_TYPE *syn;
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| 171 |
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| 172 | CGEN_INIT_PRINT (cd);
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| 173 |
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| 174 | for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
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| 175 | {
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| 176 | if (CGEN_SYNTAX_MNEMONIC_P (*syn))
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| 177 | {
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| 178 | (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
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| 179 | continue;
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| 180 | }
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| 181 | if (CGEN_SYNTAX_CHAR_P (*syn))
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| 182 | {
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| 183 | (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
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| 184 | continue;
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| 185 | }
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| 186 |
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| 187 | /* We have an operand. */
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| 188 | @arch@_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
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| 189 | fields, CGEN_INSN_ATTRS (insn), pc, length);
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| 190 | }
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| 191 | }
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| 192 | |
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| 193 |
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| 194 | /* Subroutine of print_insn. Reads an insn into the given buffers and updates
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| 195 | the extract info.
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| 196 | Returns 0 if all is well, non-zero otherwise. */
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| 197 | static int
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| 198 | read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
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| 199 | CGEN_CPU_DESC cd;
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| 200 | bfd_vma pc;
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| 201 | disassemble_info *info;
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| 202 | char *buf;
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| 203 | int buflen;
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| 204 | CGEN_EXTRACT_INFO *ex_info;
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| 205 | unsigned long *insn_value;
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| 206 | {
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| 207 | int status = (*info->read_memory_func) (pc, buf, buflen, info);
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| 208 | if (status != 0)
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| 209 | {
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| 210 | (*info->memory_error_func) (status, pc, info);
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| 211 | return -1;
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| 212 | }
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| 213 |
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| 214 | ex_info->dis_info = info;
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| 215 | ex_info->valid = (1 << buflen) - 1;
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| 216 | ex_info->insn_bytes = buf;
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| 217 |
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| 218 | *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
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| 219 | return 0;
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| 220 | }
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| 221 |
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| 222 | /* Utility to print an insn.
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| 223 | BUF is the base part of the insn, target byte order, BUFLEN bytes long.
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| 224 | The result is the size of the insn in bytes or zero for an unknown insn
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| 225 | or -1 if an error occurs fetching data (memory_error_func will have
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| 226 | been called). */
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| 227 |
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| 228 | static int
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| 229 | print_insn (cd, pc, info, buf, buflen)
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| 230 | CGEN_CPU_DESC cd;
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| 231 | bfd_vma pc;
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| 232 | disassemble_info *info;
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| 233 | char *buf;
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| 234 | int buflen;
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| 235 | {
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| 236 | unsigned long insn_value;
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| 237 | const CGEN_INSN_LIST *insn_list;
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| 238 | CGEN_EXTRACT_INFO ex_info;
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| 239 |
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| 240 | int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value);
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| 241 | if (rc != 0)
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| 242 | return rc;
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| 243 |
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| 244 | /* The instructions are stored in hash lists.
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| 245 | Pick the first one and keep trying until we find the right one. */
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| 246 |
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| 247 | insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
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| 248 | while (insn_list != NULL)
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| 249 | {
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| 250 | const CGEN_INSN *insn = insn_list->insn;
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| 251 | CGEN_FIELDS fields;
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| 252 | int length;
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| 253 |
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| 254 | #ifdef CGEN_VALIDATE_INSN_SUPPORTED
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| 255 | /* not needed as insn shouldn't be in hash lists if not supported */
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| 256 | /* Supported by this cpu? */
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| 257 | if (! @arch@_cgen_insn_supported (cd, insn))
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| 258 | {
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| 259 | insn_list = CGEN_DIS_NEXT_INSN (insn_list);
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| 260 | continue;
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| 261 | }
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| 262 | #endif
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| 263 |
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| 264 | /* Basic bit mask must be correct. */
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| 265 | /* ??? May wish to allow target to defer this check until the extract
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| 266 | handler. */
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| 267 | if ((insn_value & CGEN_INSN_BASE_MASK (insn))
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| 268 | == CGEN_INSN_BASE_VALUE (insn))
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| 269 | {
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| 270 | /* Printing is handled in two passes. The first pass parses the
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| 271 | machine insn and extracts the fields. The second pass prints
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| 272 | them. */
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| 273 |
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| 274 | /* Make sure the entire insn is loaded into insn_value, if it
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| 275 | can fit. */
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| 276 | if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize &&
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| 277 | (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
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| 278 | {
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| 279 | unsigned long full_insn_value;
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| 280 | int rc = read_insn (cd, pc, info, buf,
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| 281 | CGEN_INSN_BITSIZE (insn) / 8,
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| 282 | & ex_info, & full_insn_value);
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| 283 | if (rc != 0)
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| 284 | return rc;
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| 285 | length = CGEN_EXTRACT_FN (cd, insn)
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| 286 | (cd, insn, &ex_info, full_insn_value, &fields, pc);
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| 287 | }
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| 288 | else
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| 289 | length = CGEN_EXTRACT_FN (cd, insn)
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| 290 | (cd, insn, &ex_info, insn_value, &fields, pc);
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| 291 |
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| 292 | /* length < 0 -> error */
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| 293 | if (length < 0)
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| 294 | return length;
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| 295 | if (length > 0)
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| 296 | {
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| 297 | CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
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| 298 | /* length is in bits, result is in bytes */
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| 299 | return length / 8;
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| 300 | }
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| 301 | }
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| 302 |
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| 303 | insn_list = CGEN_DIS_NEXT_INSN (insn_list);
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| 304 | }
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| 305 |
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| 306 | return 0;
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| 307 | }
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| 308 |
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| 309 | /* Default value for CGEN_PRINT_INSN.
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| 310 | The result is the size of the insn in bytes or zero for an unknown insn
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| 311 | or -1 if an error occured fetching bytes. */
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| 312 |
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| 313 | #ifndef CGEN_PRINT_INSN
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| 314 | #define CGEN_PRINT_INSN default_print_insn
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| 315 | #endif
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| 316 |
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| 317 | static int
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| 318 | default_print_insn (cd, pc, info)
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| 319 | CGEN_CPU_DESC cd;
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| 320 | bfd_vma pc;
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| 321 | disassemble_info *info;
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| 322 | {
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| 323 | char buf[CGEN_MAX_INSN_SIZE];
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| 324 | int status;
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| 325 |
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| 326 | /* Read the base part of the insn. */
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| 327 |
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| 328 | status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info);
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| 329 | if (status != 0)
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| 330 | {
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| 331 | (*info->memory_error_func) (status, pc, info);
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| 332 | return -1;
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| 333 | }
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| 334 |
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| 335 | return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8);
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| 336 | }
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| 337 |
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| 338 | /* Main entry point.
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| 339 | Print one instruction from PC on INFO->STREAM.
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| 340 | Return the size of the instruction (in bytes). */
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| 341 |
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| 342 | int
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| 343 | print_insn_@arch@ (pc, info)
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| 344 | bfd_vma pc;
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| 345 | disassemble_info *info;
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| 346 | {
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| 347 | static CGEN_CPU_DESC cd = 0;
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| 348 | static int prev_isa;
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| 349 | static int prev_mach;
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| 350 | static int prev_endian;
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| 351 | int length;
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| 352 | int isa,mach;
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| 353 | int endian = (info->endian == BFD_ENDIAN_BIG
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| 354 | ? CGEN_ENDIAN_BIG
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| 355 | : CGEN_ENDIAN_LITTLE);
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| 356 | enum bfd_architecture arch;
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| 357 |
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| 358 | /* ??? gdb will set mach but leave the architecture as "unknown" */
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| 359 | #ifndef CGEN_BFD_ARCH
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| 360 | #define CGEN_BFD_ARCH bfd_arch_@arch@
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| 361 | #endif
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| 362 | arch = info->arch;
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| 363 | if (arch == bfd_arch_unknown)
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| 364 | arch = CGEN_BFD_ARCH;
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| 365 |
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| 366 | /* There's no standard way to compute the isa number (e.g. for arm thumb)
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| 367 | so we leave it to the target. */
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| 368 | #ifdef CGEN_COMPUTE_ISA
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| 369 | isa = CGEN_COMPUTE_ISA (info);
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| 370 | #else
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| 371 | isa = 0;
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| 372 | #endif
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| 373 |
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| 374 | mach = info->mach;
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| 375 |
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| 376 | /* If we've switched cpu's, close the current table and open a new one. */
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| 377 | if (cd
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| 378 | && (isa != prev_isa
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| 379 | || mach != prev_mach
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| 380 | || endian != prev_endian))
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| 381 | {
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| 382 | @arch@_cgen_cpu_close (cd);
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| 383 | cd = 0;
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| 384 | }
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| 385 |
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| 386 | /* If we haven't initialized yet, initialize the opcode table. */
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| 387 | if (! cd)
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| 388 | {
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| 389 | const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
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| 390 | const char *mach_name;
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| 391 |
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| 392 | if (!arch_type)
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| 393 | abort ();
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| 394 | mach_name = arch_type->printable_name;
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| 395 |
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| 396 | prev_isa = isa;
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| 397 | prev_mach = mach;
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| 398 | prev_endian = endian;
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| 399 | cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
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| 400 | CGEN_CPU_OPEN_BFDMACH, mach_name,
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| 401 | CGEN_CPU_OPEN_ENDIAN, prev_endian,
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| 402 | CGEN_CPU_OPEN_END);
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| 403 | if (!cd)
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| 404 | abort ();
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| 405 | @arch@_cgen_init_dis (cd);
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| 406 | }
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| 407 |
|
|---|
| 408 | /* We try to have as much common code as possible.
|
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| 409 | But at this point some targets need to take over. */
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|---|
| 410 | /* ??? Some targets may need a hook elsewhere. Try to avoid this,
|
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| 411 | but if not possible try to move this hook elsewhere rather than
|
|---|
| 412 | have two hooks. */
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|---|
| 413 | length = CGEN_PRINT_INSN (cd, pc, info);
|
|---|
| 414 | if (length > 0)
|
|---|
| 415 | return length;
|
|---|
| 416 | if (length < 0)
|
|---|
| 417 | return -1;
|
|---|
| 418 |
|
|---|
| 419 | (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
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|---|
| 420 | return cd->default_insn_bitsize / 8;
|
|---|
| 421 | }
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|---|