| 1 | /* Opcode table for the ARM.
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| 2 |
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| 3 | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000
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| 4 | Free Software Foundation, Inc.
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| 5 |
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| 6 | This program is free software; you can redistribute it and/or modify
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| 7 | it under the terms of the GNU General Public License as published by
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| 8 | the Free Software Foundation; either version 2, or (at your option)
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| 9 | any later version.
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| 10 |
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| 11 | This program is distributed in the hope that it will be useful,
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 14 | GNU General Public License for more details.
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| 15 |
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| 16 | You should have received a copy of the GNU General Public License
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| 17 | along with this program; if not, write to the Free Software
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| 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 19 |
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| 20 |
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| 21 | struct arm_opcode {
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| 22 | unsigned long value, mask; /* recognise instruction if (op&mask)==value */
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| 23 | char *assembler; /* how to disassemble this instruction */
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| 24 | };
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| 25 |
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| 26 | struct thumb_opcode
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| 27 | {
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| 28 | unsigned short value, mask; /* recognise instruction if (op&mask)==value */
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| 29 | char * assembler; /* how to disassemble this instruction */
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| 30 | };
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| 31 |
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| 32 | /* format of the assembler string :
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| 33 |
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| 34 | %% %
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| 35 | %<bitfield>d print the bitfield in decimal
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| 36 | %<bitfield>x print the bitfield in hex
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| 37 | %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
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| 38 | %<bitfield>r print as an ARM register
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| 39 | %<bitfield>f print a floating point constant if >7 else a
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| 40 | floating point register
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| 41 | %c print condition code (always bits 28-31)
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| 42 | %P print floating point precision in arithmetic insn
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| 43 | %Q print floating point precision in ldf/stf insn
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| 44 | %R print floating point rounding mode
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| 45 | %<bitnum>'c print specified char iff bit is one
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| 46 | %<bitnum>`c print specified char iff bit is zero
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| 47 | %<bitnum>?ab print a if bit is one else print b
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| 48 | %p print 'p' iff bits 12-15 are 15
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| 49 | %t print 't' iff bit 21 set and bit 24 clear
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| 50 | %h print 'h' iff bit 5 set, else print 'b'
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| 51 | %o print operand2 (immediate or register + shift)
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| 52 | %a print address for ldr/str instruction
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| 53 | %s print address for ldr/str halfword/signextend instruction
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| 54 | %b print branch destination
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| 55 | %B print arm BLX(1) destination
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| 56 | %A print address for ldc/stc/ldf/stf instruction
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| 57 | %m print register mask for ldm/stm instruction
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| 58 | %C print the PSR sub type.
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| 59 | %F print the COUNT field of a LFM/SFM instruction.
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| 60 | Thumb specific format options:
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| 61 | %D print Thumb register (bits 0..2 as high number if bit 7 set)
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| 62 | %S print Thumb register (bits 3..5 as high number if bit 6 set)
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| 63 | %<bitfield>I print bitfield as a signed decimal
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| 64 | (top bit of range being the sign bit)
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| 65 | %M print Thumb register mask
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| 66 | %N print Thumb register mask (with LR)
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| 67 | %O print Thumb register mask (with PC)
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| 68 | %T print Thumb condition code (always bits 8-11)
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| 69 | %<bitfield>B print Thumb branch destination (signed displacement)
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| 70 | %<bitfield>W print (bitfield * 4) as a decimal
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| 71 | %<bitfield>H print (bitfield * 2) as a decimal
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| 72 | %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
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| 73 | */
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| 74 |
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| 75 | /* Note: There is a partial ordering in this table - it must be searched from
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| 76 | the top to obtain a correct match. */
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| 77 |
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| 78 | static struct arm_opcode arm_opcodes[] =
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| 79 | {
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| 80 | /* ARM instructions. */
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| 81 | {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
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| 82 | {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
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| 83 | {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
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| 84 | {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 85 | {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
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| 86 | {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 87 | {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 88 |
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| 89 | /* XScale instructions. */
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| 90 | {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
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| 91 | {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
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| 92 | {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
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| 93 | {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
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| 94 | {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
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| 95 | {0xf450f000, 0xfc70f000, "pld\t%a"},
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| 96 |
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| 97 | /* V5 Instructions. */
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| 98 | {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
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| 99 | {0xfa000000, 0xfe000000, "blx\t%B"},
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| 100 | {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
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| 101 | {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
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| 102 | {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
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| 103 | {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
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| 104 | {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 105 | {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 106 | {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 107 |
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| 108 | /* V5E "El Segundo" Instructions. */
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| 109 | {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
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| 110 | {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
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| 111 | {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 112 | {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 113 | {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 114 | {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 115 |
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| 116 | {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 117 | {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
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| 118 |
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| 119 | {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 120 | {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 121 | {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 122 | {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
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| 123 |
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| 124 | {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
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| 125 | {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
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| 126 | {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
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| 127 | {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
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| 128 |
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| 129 | {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
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| 130 | {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
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| 131 |
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| 132 | {0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
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| 133 | {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
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| 134 | {0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
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| 135 | {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
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| 136 |
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| 137 | {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
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| 138 | {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
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| 139 |
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| 140 | /* ARM Instructions. */
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| 141 | {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"},
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| 142 | {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"},
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| 143 | {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
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| 144 | {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
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| 145 | {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
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| 146 | {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
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| 147 | {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
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| 148 | {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
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| 149 | {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
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| 150 | {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
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| 151 | {0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
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| 152 | {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
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| 153 | {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
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| 154 | {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
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| 155 | {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
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| 156 | {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
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| 157 | {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
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| 158 | {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
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| 159 | {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
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| 160 | {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
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| 161 | {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
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| 162 | {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
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| 163 | {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
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| 164 | {0x06000010, 0x0e000010, "undefined"},
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| 165 | {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
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| 166 | {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
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| 167 | {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
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| 168 | {0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
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| 169 | {0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
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| 170 |
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| 171 | /* Floating point coprocessor instructions */
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| 172 | {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 173 | {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 174 | {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 175 | {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 176 | {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 177 | {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 178 | {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 179 | {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 180 | {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 181 | {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 182 | {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 183 | {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 184 | {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
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| 185 | {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
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| 186 | {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
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| 187 | {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
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| 188 | {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
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| 189 | {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
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| 190 | {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
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| 191 | {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
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| 192 | {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
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| 193 | {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
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| 194 | {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
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| 195 | {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
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| 196 | {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
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| 197 | {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
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| 198 | {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
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| 199 | {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
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| 200 | {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
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| 201 | {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
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| 202 | {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
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| 203 | {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
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| 204 | {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
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| 205 | {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
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| 206 | {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
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| 207 | {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
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| 208 | {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
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| 209 | {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
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| 210 | {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
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| 211 | {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
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| 212 | {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
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| 213 | {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
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| 214 | {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
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| 215 |
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| 216 | /* Generic coprocessor instructions */
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| 217 | {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 218 | {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 219 | {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
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| 220 | {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
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| 221 | {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
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| 222 |
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| 223 | /* The rest. */
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| 224 | {0x00000000, 0x00000000, "undefined instruction %0-31x"},
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| 225 | {0x00000000, 0x00000000, 0}
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| 226 | };
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| 227 |
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| 228 | #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */
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| 229 |
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| 230 | static struct thumb_opcode thumb_opcodes[] =
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| 231 | {
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| 232 | /* Thumb instructions. */
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| 233 |
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| 234 | /* ARM V5 ISA extends Thumb. */
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| 235 | {0xbe00, 0xff00, "bkpt\t%0-7x"},
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| 236 | {0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */
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| 237 | /* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb()
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| 238 | as an extension of the special processing there for Thumb BL.
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| 239 | BL and BLX(1) involve 2 successive 16-bit instructions, which must
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| 240 | always appear together in the correct order. So, the empty
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| 241 | string is put in this table, and the string interpreter takes <empty>
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| 242 | to mean it has a pair of BL-ish instructions. */
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| 243 | {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
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| 244 | /* Format 5 instructions do not update the PSR. */
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| 245 | {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"},
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| 246 | /* Format 4. */
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| 247 | {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"},
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| 248 | {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"},
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|---|
| 249 | {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"},
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|---|
| 250 | {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"},
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| 251 | {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"},
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| 252 | {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"},
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| 253 | {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"},
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| 254 | {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"},
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| 255 | {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},
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| 256 | {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"},
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| 257 | {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},
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| 258 | {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},
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| 259 | {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"},
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| 260 | {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"},
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| 261 | {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"},
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| 262 | {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"},
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| 263 | /* format 13 */
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|---|
| 264 | {0xB000, 0xFF80, "add\tsp, #%0-6W"},
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| 265 | {0xB080, 0xFF80, "sub\tsp, #%0-6W"},
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| 266 | /* format 5 */
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|---|
| 267 | {0x4700, 0xFF80, "bx\t%S"},
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| 268 | {0x4400, 0xFF00, "add\t%D, %S"},
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|---|
| 269 | {0x4500, 0xFF00, "cmp\t%D, %S"},
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|---|
| 270 | {0x4600, 0xFF00, "mov\t%D, %S"},
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|---|
| 271 | /* format 14 */
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|---|
| 272 | {0xB400, 0xFE00, "push\t%N"},
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| 273 | {0xBC00, 0xFE00, "pop\t%O"},
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|---|
| 274 | /* format 2 */
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|---|
| 275 | {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"},
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|---|
| 276 | {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"},
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|---|
| 277 | {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"},
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|---|
| 278 | {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"},
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|---|
| 279 | /* format 8 */
|
|---|
| 280 | {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
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|---|
| 281 | {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},
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|---|
| 282 | {0x5600, 0xF600, "ldrs%11?hb\t%0-2r, [%3-5r, %6-8r]"},
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|---|
| 283 | /* format 7 */
|
|---|
| 284 | {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},
|
|---|
| 285 | {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},
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|---|
| 286 | /* format 1 */
|
|---|
| 287 | {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"},
|
|---|
| 288 | {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"},
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|---|
| 289 | {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"},
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|---|
| 290 | /* format 3 */
|
|---|
| 291 | {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"},
|
|---|
| 292 | {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},
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|---|
| 293 | {0x3000, 0xF800, "add\t%8-10r, #%0-7d"},
|
|---|
| 294 | {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"},
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|---|
| 295 | /* format 6 */
|
|---|
| 296 | {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
|
|---|
| 297 | /* format 9 */
|
|---|
| 298 | {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
|
|---|
| 299 | {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
|
|---|
| 300 | {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
|
|---|
| 301 | {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
|
|---|
| 302 | /* format 10 */
|
|---|
| 303 | {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},
|
|---|
| 304 | {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},
|
|---|
| 305 | /* format 11 */
|
|---|
| 306 | {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},
|
|---|
| 307 | {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},
|
|---|
| 308 | /* format 12 */
|
|---|
| 309 | {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
|
|---|
| 310 | {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},
|
|---|
| 311 | /* format 15 */
|
|---|
| 312 | {0xC000, 0xF800, "stmia\t%8-10r!,%M"},
|
|---|
| 313 | {0xC800, 0xF800, "ldmia\t%8-10r!,%M"},
|
|---|
| 314 | /* format 18 */
|
|---|
| 315 | {0xE000, 0xF800, "b\t%0-10B"},
|
|---|
| 316 | {0xE800, 0xF800, "undefined"},
|
|---|
| 317 | /* format 19 */
|
|---|
| 318 | {0xF000, 0xF800, ""}, /* special processing required in disassembler */
|
|---|
| 319 | {0xF800, 0xF800, "second half of BL instruction %0-15x"},
|
|---|
| 320 | /* format 16 */
|
|---|
| 321 | {0xD000, 0xFF00, "beq\t%0-7B"},
|
|---|
| 322 | {0xD100, 0xFF00, "bne\t%0-7B"},
|
|---|
| 323 | {0xD200, 0xFF00, "bcs\t%0-7B"},
|
|---|
| 324 | {0xD300, 0xFF00, "bcc\t%0-7B"},
|
|---|
| 325 | {0xD400, 0xFF00, "bmi\t%0-7B"},
|
|---|
| 326 | {0xD500, 0xFF00, "bpl\t%0-7B"},
|
|---|
| 327 | {0xD600, 0xFF00, "bvs\t%0-7B"},
|
|---|
| 328 | {0xD700, 0xFF00, "bvc\t%0-7B"},
|
|---|
| 329 | {0xD800, 0xFF00, "bhi\t%0-7B"},
|
|---|
| 330 | {0xD900, 0xFF00, "bls\t%0-7B"},
|
|---|
| 331 | {0xDA00, 0xFF00, "bge\t%0-7B"},
|
|---|
| 332 | {0xDB00, 0xFF00, "blt\t%0-7B"},
|
|---|
| 333 | {0xDC00, 0xFF00, "bgt\t%0-7B"},
|
|---|
| 334 | {0xDD00, 0xFF00, "ble\t%0-7B"},
|
|---|
| 335 | /* format 17 */
|
|---|
| 336 | {0xDE00, 0xFF00, "bal\t%0-7B"},
|
|---|
| 337 | {0xDF00, 0xFF00, "swi\t%0-7d"},
|
|---|
| 338 | /* format 9 */
|
|---|
| 339 | {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
|
|---|
| 340 | {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
|
|---|
| 341 | {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
|
|---|
| 342 | {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
|
|---|
| 343 | /* the rest */
|
|---|
| 344 | {0x0000, 0x0000, "undefined instruction %0-15x"},
|
|---|
| 345 | {0x0000, 0x0000, 0}
|
|---|
| 346 | };
|
|---|
| 347 |
|
|---|
| 348 | #define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \
|
|---|
| 349 | ^ 0x200000) - 0x200000) /* 23bit */
|
|---|
| 350 |
|
|---|
