| 1 | /* itbl-parse.y | 
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| 2 | Copyright 1997 Free Software Foundation, Inc. | 
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| 3 |  | 
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| 4 | This file is part of GAS, the GNU Assembler. | 
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| 5 |  | 
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| 6 | GAS is free software; you can redistribute it and/or modify | 
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| 7 | it under the terms of the GNU General Public License as published by | 
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| 8 | the Free Software Foundation; either version 2, or (at your option) | 
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| 9 | any later version. | 
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| 10 |  | 
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| 11 | GAS is distributed in the hope that it will be useful, | 
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| 12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | 
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| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | 
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| 14 | GNU General Public License for more details. | 
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| 15 |  | 
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| 16 | You should have received a copy of the GNU General Public License | 
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| 17 | along with GAS; see the file COPYING.  If not, write to the Free | 
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| 18 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | 
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| 19 | 02111-1307, USA.  */ | 
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| 20 |  | 
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| 21 | %{ | 
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| 22 |  | 
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| 23 | /* | 
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| 24 |  | 
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| 25 | Yacc grammar for instruction table entries. | 
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| 26 |  | 
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| 27 | ======================================================================= | 
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| 28 | Original Instruction table specification document: | 
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| 29 |  | 
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| 30 | MIPS Coprocessor Table Specification | 
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| 31 | ==================================== | 
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| 32 |  | 
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| 33 | This document describes the format of the MIPS coprocessor table.  The | 
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| 34 | table specifies a list of valid functions, data registers and control | 
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| 35 | registers that can be used in coprocessor instructions.  This list, | 
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| 36 | together with the coprocessor instruction classes listed below, | 
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| 37 | specifies the complete list of coprocessor instructions that will | 
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| 38 | be recognized and assembled by the GNU assembler.  In effect, | 
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| 39 | this makes the GNU assembler table-driven, where the table is | 
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| 40 | specified by the programmer. | 
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| 41 |  | 
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| 42 | The table is an ordinary text file that the GNU assembler reads when | 
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| 43 | it starts.  Using the information in the table, the assembler | 
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| 44 | generates an internal list of valid coprocessor registers and | 
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| 45 | functions.  The assembler uses this internal list in addition to the | 
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| 46 | standard MIPS registers and instructions which are built-in to the | 
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| 47 | assembler during code generation. | 
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| 48 |  | 
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| 49 | To specify the coprocessor table when invoking the GNU assembler, use | 
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| 50 | the command line option "--itbl file", where file is the | 
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| 51 | complete name of the table, including path and extension. | 
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| 52 |  | 
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| 53 | Examples: | 
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| 54 |  | 
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| 55 | gas -t cop.tbl test.s -o test.o | 
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| 56 | gas -t /usr/local/lib/cop.tbl test.s -o test.o | 
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| 57 | gas --itbl d:\gnu\data\cop.tbl test.s -o test.o | 
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| 58 |  | 
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| 59 | Only one table may be supplied during a single invocation of | 
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| 60 | the assembler. | 
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| 61 |  | 
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| 62 |  | 
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| 63 | Instruction classes | 
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| 64 | =================== | 
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| 65 |  | 
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| 66 | Below is a list of the valid coprocessor instruction classes for | 
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| 67 | any given coprocessor "z".  These instructions are already recognized | 
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| 68 | by the assembler, and are listed here only for reference. | 
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| 69 |  | 
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| 70 | Class   format                        instructions | 
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| 71 | ------------------------------------------------- | 
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| 72 | Class1: | 
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| 73 | op base rt offset | 
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| 74 | LWCz rt,offset (base) | 
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| 75 | SWCz rt,offset (base) | 
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| 76 | Class2: | 
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| 77 | COPz sub rt rd 0 | 
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| 78 | MTCz rt,rd | 
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| 79 | MFCz rt,rd | 
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| 80 | CTCz rt,rd | 
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| 81 | CFCz rt,rd | 
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| 82 | Class3: | 
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| 83 | COPz CO cofun | 
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| 84 | COPz cofun | 
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| 85 | Class4: | 
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| 86 | COPz BC br offset | 
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| 87 | BCzT offset | 
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| 88 | BCzF offset | 
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| 89 | Class5: | 
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| 90 | COPz sub rt rd 0 | 
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| 91 | DMFCz rt,rd | 
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| 92 | DMTCz rt,rd | 
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| 93 | Class6: | 
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| 94 | op base rt offset | 
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| 95 | LDCz rt,offset (base) | 
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| 96 | SDCz rt,offset (base) | 
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| 97 | Class7: | 
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| 98 | COPz BC br offset | 
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| 99 | BCzTL offset | 
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| 100 | BCzFL offset | 
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| 101 |  | 
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| 102 | The coprocessor table defines coprocessor-specific registers that can | 
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| 103 | be used with all of the above classes of instructions, where | 
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| 104 | appropriate.  It also defines additional coprocessor-specific | 
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| 105 | functions for Class3 (COPz cofun) instructions, Thus, the table allows | 
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| 106 | the programmer to use convenient mnemonics and operands for these | 
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| 107 | functions, instead of the COPz mmenmonic and cofun operand. | 
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| 108 |  | 
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| 109 | The names of the MIPS general registers and their aliases are defined | 
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| 110 | by the assembler and will be recognized as valid register names by the | 
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| 111 | assembler when used (where allowed) in coprocessor instructions. | 
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| 112 | However, the names and values of all coprocessor data and control | 
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| 113 | register mnemonics must be specified in the coprocessor table. | 
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| 114 |  | 
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| 115 |  | 
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| 116 | Table Grammar | 
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| 117 | ============= | 
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| 118 |  | 
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| 119 | Here is the grammar for the coprocessor table: | 
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| 120 |  | 
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| 121 | table -> entry* | 
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| 122 |  | 
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| 123 | entry -> [z entrydef] [comment] '\n' | 
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| 124 |  | 
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| 125 | entrydef -> type name val | 
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| 126 | entrydef -> 'insn' name val funcdef ; type of entry (instruction) | 
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| 127 |  | 
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| 128 | z -> 'p'['0'..'3']               ; processor number | 
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| 129 | type -> ['dreg' | 'creg' | 'greg' ]      ; type of entry (register) | 
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| 130 | ; 'dreg', 'creg' or 'greg' specifies a data, control, or general | 
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| 131 | ;           register mnemonic, respectively | 
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| 132 | name -> [ltr|dec]*               ; mnemonic of register/function | 
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| 133 | val -> [dec|hex]                 ; register/function number (integer constant) | 
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| 134 |  | 
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| 135 | funcdef -> frange flags fields | 
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| 136 | ; bitfield range for opcode | 
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| 137 | ; list of fields' formats | 
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| 138 | fields -> field* | 
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| 139 | field -> [','] ftype frange flags | 
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| 140 | flags -> ['*' flagexpr] | 
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| 141 | flagexpr -> '[' flagexpr ']' | 
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| 142 | flagexpr -> val '|' flagexpr | 
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| 143 | ftype -> [ type | 'immed' | 'addr' ] | 
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| 144 | ; 'immed' specifies an immediate value; see grammar for "val" above | 
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| 145 | ; 'addr' specifies a C identifier; name of symbol to be resolved at | 
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| 146 | ;           link time | 
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| 147 | frange -> ':' val '-' val   ; starting to ending bit positions, where | 
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| 148 | ; where 0 is least significant bit | 
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| 149 | frange -> (null)            ; default range of 31-0 will be assumed | 
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| 150 |  | 
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| 151 | comment -> [';'|'#'] [char]* | 
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| 152 | char -> any printable character | 
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| 153 | ltr -> ['a'..'z'|'A'..'Z'] | 
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| 154 | dec -> ['0'..'9']*                                       ; value in decimal | 
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| 155 | hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']*        ; value in hexidecimal | 
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| 156 |  | 
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| 157 |  | 
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| 158 | Examples | 
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| 159 | ======== | 
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| 160 |  | 
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| 161 | Example 1: | 
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| 162 |  | 
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| 163 | The table: | 
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| 164 |  | 
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| 165 | p1 dreg d1 1             ; data register "d1" for COP1 has value 1 | 
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| 166 | p1 creg c3 3             ; ctrl register "c3" for COP1 has value 3 | 
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| 167 | p3 func fill 0x1f:24-20           ; function "fill" for COP3 has value 31 and | 
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| 168 | ; no fields | 
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| 169 |  | 
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| 170 | will allow the assembler to accept the following coprocessor instructions: | 
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| 171 |  | 
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| 172 | LWC1 d1,0x100 ($2) | 
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| 173 | fill | 
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| 174 |  | 
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| 175 | Here, the general purpose register "$2", and instruction "LWC1", are standard | 
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| 176 | mnemonics built-in to the MIPS assembler. | 
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| 177 |  | 
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| 178 |  | 
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| 179 | Example 2: | 
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| 180 |  | 
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| 181 | The table: | 
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| 182 |  | 
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| 183 | p3 dreg d3 3             ; data register "d3" for COP3 has value 3 | 
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| 184 | p3 creg c2 22            ; control register "c2" for COP3 has value 22 | 
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| 185 | p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0 | 
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| 186 | ; function "fee" for COP3 has value 31, and 3 fields | 
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| 187 | ; consisting of a data register, a control register, | 
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| 188 | ; and an immediate value. | 
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| 189 |  | 
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| 190 | will allow the assembler to accept the following coprocessor instruction: | 
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| 191 |  | 
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| 192 | fee d3,c2,0x1 | 
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| 193 |  | 
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| 194 | and will emit the object code: | 
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| 195 |  | 
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| 196 | 31-26  25 24-20 19-18  17-13 12-8  7-0 | 
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| 197 | COPz   CO fun                     dreg  creg  immed | 
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| 198 | 010011 1  11111 00       00011 10110 00000001 | 
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| 199 |  | 
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| 200 | 0x4ff07601 | 
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| 201 |  | 
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| 202 |  | 
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| 203 | Example 3: | 
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| 204 |  | 
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| 205 | The table: | 
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| 206 |  | 
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| 207 | p3 dreg d3 3             ; data register "d3" for COP3 has value 3 | 
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| 208 | p3 creg c2 22            ; control register "c2" for COP3 has value 22 | 
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| 209 | p3 func fuu 0x01f00001 dreg:17-13 creg:12-8 | 
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| 210 |  | 
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| 211 | will allow the assembler to accept the following coprocessor | 
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| 212 | instruction: | 
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| 213 |  | 
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| 214 | fuu d3,c2 | 
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| 215 |  | 
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| 216 | and will emit the object code: | 
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| 217 |  | 
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| 218 | 31-26  25 24-20 19-18  17-13 12-8  7-0 | 
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| 219 | COPz   CO fun                     dreg  creg | 
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| 220 | 010011 1  11111 00       00011 10110 00000001 | 
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| 221 |  | 
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| 222 | 0x4ff07601 | 
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| 223 |  | 
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| 224 | In this way, the programmer can force arbitrary bits of an instruction | 
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| 225 | to have predefined values. | 
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| 226 |  | 
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| 227 | ======================================================================= | 
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| 228 | Additional notes: | 
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| 229 |  | 
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| 230 | Encoding of ranges: | 
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| 231 | To handle more than one bit position range within an instruction, | 
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| 232 | use 0s to mask out the ranges which don't apply. | 
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| 233 | May decide to modify the syntax to allow commas separate multiple | 
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| 234 | ranges within an instruction (range','range). | 
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| 235 |  | 
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| 236 | Changes in grammar: | 
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| 237 | The number of parms argument to the function entry | 
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| 238 | was deleted from the original format such that we now count the fields. | 
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| 239 |  | 
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| 240 | ---- | 
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| 241 | FIXME! should really change lexical analyzer | 
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| 242 | to recognize 'dreg' etc. in context sensative way. | 
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| 243 | Currently function names or mnemonics may be incorrectly parsed as keywords | 
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| 244 |  | 
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| 245 | FIXME! hex is ambiguous with any digit | 
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| 246 |  | 
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| 247 | */ | 
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| 248 |  | 
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| 249 | #include <stdio.h> | 
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| 250 | #include "itbl-ops.h" | 
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| 251 |  | 
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| 252 | /* #define DEBUG */ | 
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| 253 |  | 
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| 254 | #ifdef DEBUG | 
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| 255 | #ifndef DBG_LVL | 
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| 256 | #define DBG_LVL 1 | 
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| 257 | #endif | 
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| 258 | #else | 
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| 259 | #define DBG_LVL 0 | 
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| 260 | #endif | 
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| 261 |  | 
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| 262 | #if DBG_LVL >= 1 | 
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| 263 | #define DBG(x) printf x | 
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| 264 | #else | 
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| 265 | #define DBG(x) | 
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| 266 | #endif | 
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| 267 |  | 
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| 268 | #if DBG_LVL >= 2 | 
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| 269 | #define DBGL2(x) printf x | 
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| 270 | #else | 
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| 271 | #define DBGL2(x) | 
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| 272 | #endif | 
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| 273 |  | 
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| 274 | static int sbit, ebit; | 
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| 275 | static struct itbl_entry *insn=0; | 
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| 276 | extern int insntbl_line; | 
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| 277 | int yyparse PARAMS ((void)); | 
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| 278 | int yylex PARAMS ((void)); | 
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| 279 | static int yyerror PARAMS ((const char *)); | 
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| 280 |  | 
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| 281 | %} | 
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| 282 |  | 
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| 283 | %union | 
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| 284 | { | 
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| 285 | char *str; | 
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| 286 | int num; | 
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| 287 | int processor; | 
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| 288 | unsigned long val; | 
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| 289 | } | 
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| 290 |  | 
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| 291 | %token      DREG CREG GREG IMMED ADDR INSN NUM ID NL PNUM | 
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| 292 | %type       <val> value flags flagexpr | 
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| 293 | %type       <num> number NUM ftype regtype pnum PNUM | 
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| 294 | %type       <str> ID name | 
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| 295 |  | 
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| 296 | %start insntbl | 
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| 297 |  | 
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| 298 | %% | 
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| 299 |  | 
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| 300 | insntbl: | 
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| 301 | entrys | 
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| 302 | ; | 
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| 303 |  | 
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| 304 | entrys: | 
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| 305 | entry entrys | 
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| 306 | | | 
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| 307 | ; | 
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| 308 |  | 
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| 309 | entry: | 
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| 310 | pnum regtype name value NL | 
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| 311 | { | 
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| 312 | DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n", | 
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| 313 | insntbl_line, $1, $2, $3, $4)); | 
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| 314 | itbl_add_reg ($1, $2, $3, $4); | 
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| 315 | } | 
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| 316 | | pnum INSN name value range flags | 
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| 317 | { | 
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| 318 | DBG (("line %d: entry pnum=%d type=INSN name=%s value=x%x", | 
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| 319 | insntbl_line, $1, $3, $4)); | 
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| 320 | DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, $6)); | 
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| 321 | insn=itbl_add_insn ($1, $3, $4, sbit, ebit, $6); | 
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| 322 | } | 
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| 323 | fieldspecs NL | 
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| 324 | | NL | 
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| 325 | | error NL | 
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| 326 | ; | 
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| 327 |  | 
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| 328 | fieldspecs: | 
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| 329 | ',' fieldspec fieldspecs | 
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| 330 | | fieldspec fieldspecs | 
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| 331 | | | 
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| 332 | ; | 
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| 333 |  | 
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| 334 | ftype: | 
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| 335 | regtype | 
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| 336 | { | 
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| 337 | DBGL2 (("ftype\n")); | 
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| 338 | $$ = $1; | 
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| 339 | } | 
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| 340 | | ADDR | 
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| 341 | { | 
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| 342 | DBGL2 (("addr\n")); | 
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| 343 | $$ = ADDR; | 
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| 344 | } | 
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| 345 | | IMMED | 
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| 346 | { | 
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| 347 | DBGL2 (("immed\n")); | 
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| 348 | $$ = IMMED; | 
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| 349 | } | 
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| 350 | ; | 
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| 351 |  | 
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| 352 | fieldspec: | 
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| 353 | ftype range flags | 
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| 354 | { | 
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| 355 | DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n", | 
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| 356 | insntbl_line, $1, sbit, ebit, $3)); | 
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| 357 | itbl_add_operand (insn, $1, sbit, ebit, $3); | 
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| 358 | } | 
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| 359 | ; | 
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| 360 |  | 
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| 361 | flagexpr: | 
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| 362 | NUM '|' flagexpr | 
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| 363 | { | 
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| 364 | $$ = $1 | $3; | 
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| 365 | } | 
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| 366 | | '[' flagexpr ']' | 
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| 367 | { | 
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| 368 | $$ = $2; | 
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| 369 | } | 
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| 370 | | NUM | 
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| 371 | { | 
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| 372 | $$ = $1; | 
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| 373 | } | 
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| 374 | ; | 
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| 375 |  | 
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| 376 | flags: | 
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| 377 | '*' flagexpr | 
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| 378 | { | 
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| 379 | DBGL2 (("flags=%d\n", $2)); | 
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| 380 | $$ = $2; | 
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| 381 | } | 
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| 382 | | | 
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| 383 | { | 
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| 384 | $$ = 0; | 
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| 385 | } | 
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| 386 | ; | 
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| 387 |  | 
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| 388 | range: | 
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| 389 | ':' NUM '-' NUM | 
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| 390 | { | 
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| 391 | DBGL2 (("range %d %d\n", $2, $4)); | 
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| 392 | sbit = $2; | 
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| 393 | ebit = $4; | 
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| 394 | } | 
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| 395 | | | 
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| 396 | { | 
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| 397 | sbit = 31; | 
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| 398 | ebit = 0; | 
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| 399 | } | 
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| 400 | ; | 
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| 401 |  | 
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| 402 | pnum: | 
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| 403 | PNUM | 
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| 404 | { | 
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| 405 | DBGL2 (("pnum=%d\n",$1)); | 
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| 406 | $$ = $1; | 
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| 407 | } | 
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| 408 | ; | 
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| 409 |  | 
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| 410 | regtype: | 
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| 411 | DREG | 
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| 412 | { | 
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| 413 | DBGL2 (("dreg\n")); | 
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| 414 | $$ = DREG; | 
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| 415 | } | 
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| 416 | | CREG | 
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| 417 | { | 
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| 418 | DBGL2 (("creg\n")); | 
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| 419 | $$ = CREG; | 
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| 420 | } | 
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| 421 | | GREG | 
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| 422 | { | 
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| 423 | DBGL2 (("greg\n")); | 
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| 424 | $$ = GREG; | 
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| 425 | } | 
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| 426 | ; | 
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| 427 |  | 
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| 428 | name: | 
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| 429 | ID | 
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| 430 | { | 
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| 431 | DBGL2 (("name=%s\n",$1)); | 
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| 432 | $$ = $1; | 
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| 433 | } | 
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| 434 | ; | 
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| 435 |  | 
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| 436 | number: | 
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| 437 | NUM | 
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| 438 | { | 
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| 439 | DBGL2 (("num=%d\n",$1)); | 
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| 440 | $$ = $1; | 
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| 441 | } | 
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| 442 | ; | 
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| 443 |  | 
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| 444 | value: | 
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| 445 | NUM | 
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| 446 | { | 
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| 447 | DBGL2 (("val=x%x\n",$1)); | 
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| 448 | $$ = $1; | 
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| 449 | } | 
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| 450 | ; | 
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| 451 | %% | 
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| 452 |  | 
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| 453 | static int | 
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| 454 | yyerror (msg) | 
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| 455 | const char *msg; | 
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| 456 | { | 
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| 457 | printf ("line %d: %s\n", insntbl_line, msg); | 
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| 458 | return 0; | 
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| 459 | } | 
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