source: trunk/src/binutils/bfd/coff-sh.c@ 108

Last change on this file since 108 was 10, checked in by bird, 23 years ago

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1/* BFD back-end for Hitachi Super-H COFF binaries.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Cygnus Support.
5 Written by Steve Chamberlain, <sac@cygnus.com>.
6 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
7
8This file is part of BFD, the Binary File Descriptor library.
9
10This program is free software; you can redistribute it and/or modify
11it under the terms of the GNU General Public License as published by
12the Free Software Foundation; either version 2 of the License, or
13(at your option) any later version.
14
15This program is distributed in the hope that it will be useful,
16but WITHOUT ANY WARRANTY; without even the implied warranty of
17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18GNU General Public License for more details.
19
20You should have received a copy of the GNU General Public License
21along with this program; if not, write to the Free Software
22Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23
24#include "bfd.h"
25#include "sysdep.h"
26#include "libbfd.h"
27#include "bfdlink.h"
28#include "coff/sh.h"
29#include "coff/internal.h"
30
31#ifdef COFF_WITH_PE
32#include "coff/pe.h"
33
34#ifndef COFF_IMAGE_WITH_PE
35static boolean sh_align_load_span
36 PARAMS ((bfd *, asection *, bfd_byte *,
37 boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
38 PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, boolean *));
39
40#define _bfd_sh_align_load_span sh_align_load_span
41#endif
42#endif
43
44#include "libcoff.h"
45
46/* Internal functions. */
47static bfd_reloc_status_type sh_reloc
48 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
49static long get_symbol_value PARAMS ((asymbol *));
50static boolean sh_relax_section
51 PARAMS ((bfd *, asection *, struct bfd_link_info *, boolean *));
52static boolean sh_relax_delete_bytes
53 PARAMS ((bfd *, asection *, bfd_vma, int));
54#ifndef COFF_IMAGE_WITH_PE
55static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
56#endif
57static boolean sh_align_loads
58 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, boolean *));
59static boolean sh_swap_insns
60 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
61static boolean sh_relocate_section
62 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
63 struct internal_reloc *, struct internal_syment *, asection **));
64static bfd_byte *sh_coff_get_relocated_section_contents
65 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
66 bfd_byte *, boolean, asymbol **));
67
68#ifdef COFF_WITH_PE
69/* Can't build import tables with 2**4 alignment. */
70#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
71#else
72/* Default section alignment to 2**4. */
73#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
74#endif
75
76#ifdef COFF_IMAGE_WITH_PE
77/* Align PE executables. */
78#define COFF_PAGE_SIZE 0x1000
79#endif
80
81/* Generate long file names. */
82#define COFF_LONG_FILENAMES
83
84#ifdef COFF_WITH_PE
85/* Return true if this relocation should
86 appear in the output .reloc section. */
87static boolean in_reloc_p (abfd, howto)
88 bfd * abfd ATTRIBUTE_UNUSED;
89 reloc_howto_type * howto;
90{
91 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
92}
93#endif
94
95/* The supported relocations. There are a lot of relocations defined
96 in coff/internal.h which we do not expect to ever see. */
97static reloc_howto_type sh_coff_howtos[] =
98{
99 EMPTY_HOWTO (0),
100 EMPTY_HOWTO (1),
101#ifdef COFF_WITH_PE
102 /* Windows CE */
103 HOWTO (R_SH_IMM32CE, /* type */
104 0, /* rightshift */
105 2, /* size (0 = byte, 1 = short, 2 = long) */
106 32, /* bitsize */
107 false, /* pc_relative */
108 0, /* bitpos */
109 complain_overflow_bitfield, /* complain_on_overflow */
110 sh_reloc, /* special_function */
111 "r_imm32ce", /* name */
112 true, /* partial_inplace */
113 0xffffffff, /* src_mask */
114 0xffffffff, /* dst_mask */
115 false), /* pcrel_offset */
116#else
117 EMPTY_HOWTO (2),
118#endif
119 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
120 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
121 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
122 EMPTY_HOWTO (6), /* R_SH_IMM24 */
123 EMPTY_HOWTO (7), /* R_SH_LOW16 */
124 EMPTY_HOWTO (8),
125 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
126
127 HOWTO (R_SH_PCDISP8BY2, /* type */
128 1, /* rightshift */
129 1, /* size (0 = byte, 1 = short, 2 = long) */
130 8, /* bitsize */
131 true, /* pc_relative */
132 0, /* bitpos */
133 complain_overflow_signed, /* complain_on_overflow */
134 sh_reloc, /* special_function */
135 "r_pcdisp8by2", /* name */
136 true, /* partial_inplace */
137 0xff, /* src_mask */
138 0xff, /* dst_mask */
139 true), /* pcrel_offset */
140
141 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
142
143 HOWTO (R_SH_PCDISP, /* type */
144 1, /* rightshift */
145 1, /* size (0 = byte, 1 = short, 2 = long) */
146 12, /* bitsize */
147 true, /* pc_relative */
148 0, /* bitpos */
149 complain_overflow_signed, /* complain_on_overflow */
150 sh_reloc, /* special_function */
151 "r_pcdisp12by2", /* name */
152 true, /* partial_inplace */
153 0xfff, /* src_mask */
154 0xfff, /* dst_mask */
155 true), /* pcrel_offset */
156
157 EMPTY_HOWTO (13),
158
159 HOWTO (R_SH_IMM32, /* type */
160 0, /* rightshift */
161 2, /* size (0 = byte, 1 = short, 2 = long) */
162 32, /* bitsize */
163 false, /* pc_relative */
164 0, /* bitpos */
165 complain_overflow_bitfield, /* complain_on_overflow */
166 sh_reloc, /* special_function */
167 "r_imm32", /* name */
168 true, /* partial_inplace */
169 0xffffffff, /* src_mask */
170 0xffffffff, /* dst_mask */
171 false), /* pcrel_offset */
172
173 EMPTY_HOWTO (15),
174#ifdef COFF_WITH_PE
175 HOWTO (R_SH_IMAGEBASE, /* type */
176 0, /* rightshift */
177 2, /* size (0 = byte, 1 = short, 2 = long) */
178 32, /* bitsize */
179 false, /* pc_relative */
180 0, /* bitpos */
181 complain_overflow_bitfield, /* complain_on_overflow */
182 sh_reloc, /* special_function */
183 "rva32", /* name */
184 true, /* partial_inplace */
185 0xffffffff, /* src_mask */
186 0xffffffff, /* dst_mask */
187 false), /* pcrel_offset */
188#else
189 EMPTY_HOWTO (16), /* R_SH_IMM8 */
190#endif
191 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
192 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
193 EMPTY_HOWTO (19), /* R_SH_IMM4 */
194 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
195 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
196
197 HOWTO (R_SH_PCRELIMM8BY2, /* type */
198 1, /* rightshift */
199 1, /* size (0 = byte, 1 = short, 2 = long) */
200 8, /* bitsize */
201 true, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_unsigned, /* complain_on_overflow */
204 sh_reloc, /* special_function */
205 "r_pcrelimm8by2", /* name */
206 true, /* partial_inplace */
207 0xff, /* src_mask */
208 0xff, /* dst_mask */
209 true), /* pcrel_offset */
210
211 HOWTO (R_SH_PCRELIMM8BY4, /* type */
212 2, /* rightshift */
213 1, /* size (0 = byte, 1 = short, 2 = long) */
214 8, /* bitsize */
215 true, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_unsigned, /* complain_on_overflow */
218 sh_reloc, /* special_function */
219 "r_pcrelimm8by4", /* name */
220 true, /* partial_inplace */
221 0xff, /* src_mask */
222 0xff, /* dst_mask */
223 true), /* pcrel_offset */
224
225 HOWTO (R_SH_IMM16, /* type */
226 0, /* rightshift */
227 1, /* size (0 = byte, 1 = short, 2 = long) */
228 16, /* bitsize */
229 false, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_bitfield, /* complain_on_overflow */
232 sh_reloc, /* special_function */
233 "r_imm16", /* name */
234 true, /* partial_inplace */
235 0xffff, /* src_mask */
236 0xffff, /* dst_mask */
237 false), /* pcrel_offset */
238
239 HOWTO (R_SH_SWITCH16, /* type */
240 0, /* rightshift */
241 1, /* size (0 = byte, 1 = short, 2 = long) */
242 16, /* bitsize */
243 false, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_bitfield, /* complain_on_overflow */
246 sh_reloc, /* special_function */
247 "r_switch16", /* name */
248 true, /* partial_inplace */
249 0xffff, /* src_mask */
250 0xffff, /* dst_mask */
251 false), /* pcrel_offset */
252
253 HOWTO (R_SH_SWITCH32, /* type */
254 0, /* rightshift */
255 2, /* size (0 = byte, 1 = short, 2 = long) */
256 32, /* bitsize */
257 false, /* pc_relative */
258 0, /* bitpos */
259 complain_overflow_bitfield, /* complain_on_overflow */
260 sh_reloc, /* special_function */
261 "r_switch32", /* name */
262 true, /* partial_inplace */
263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 false), /* pcrel_offset */
266
267 HOWTO (R_SH_USES, /* type */
268 0, /* rightshift */
269 1, /* size (0 = byte, 1 = short, 2 = long) */
270 16, /* bitsize */
271 false, /* pc_relative */
272 0, /* bitpos */
273 complain_overflow_bitfield, /* complain_on_overflow */
274 sh_reloc, /* special_function */
275 "r_uses", /* name */
276 true, /* partial_inplace */
277 0xffff, /* src_mask */
278 0xffff, /* dst_mask */
279 false), /* pcrel_offset */
280
281 HOWTO (R_SH_COUNT, /* type */
282 0, /* rightshift */
283 2, /* size (0 = byte, 1 = short, 2 = long) */
284 32, /* bitsize */
285 false, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_bitfield, /* complain_on_overflow */
288 sh_reloc, /* special_function */
289 "r_count", /* name */
290 true, /* partial_inplace */
291 0xffffffff, /* src_mask */
292 0xffffffff, /* dst_mask */
293 false), /* pcrel_offset */
294
295 HOWTO (R_SH_ALIGN, /* type */
296 0, /* rightshift */
297 2, /* size (0 = byte, 1 = short, 2 = long) */
298 32, /* bitsize */
299 false, /* pc_relative */
300 0, /* bitpos */
301 complain_overflow_bitfield, /* complain_on_overflow */
302 sh_reloc, /* special_function */
303 "r_align", /* name */
304 true, /* partial_inplace */
305 0xffffffff, /* src_mask */
306 0xffffffff, /* dst_mask */
307 false), /* pcrel_offset */
308
309 HOWTO (R_SH_CODE, /* type */
310 0, /* rightshift */
311 2, /* size (0 = byte, 1 = short, 2 = long) */
312 32, /* bitsize */
313 false, /* pc_relative */
314 0, /* bitpos */
315 complain_overflow_bitfield, /* complain_on_overflow */
316 sh_reloc, /* special_function */
317 "r_code", /* name */
318 true, /* partial_inplace */
319 0xffffffff, /* src_mask */
320 0xffffffff, /* dst_mask */
321 false), /* pcrel_offset */
322
323 HOWTO (R_SH_DATA, /* type */
324 0, /* rightshift */
325 2, /* size (0 = byte, 1 = short, 2 = long) */
326 32, /* bitsize */
327 false, /* pc_relative */
328 0, /* bitpos */
329 complain_overflow_bitfield, /* complain_on_overflow */
330 sh_reloc, /* special_function */
331 "r_data", /* name */
332 true, /* partial_inplace */
333 0xffffffff, /* src_mask */
334 0xffffffff, /* dst_mask */
335 false), /* pcrel_offset */
336
337 HOWTO (R_SH_LABEL, /* type */
338 0, /* rightshift */
339 2, /* size (0 = byte, 1 = short, 2 = long) */
340 32, /* bitsize */
341 false, /* pc_relative */
342 0, /* bitpos */
343 complain_overflow_bitfield, /* complain_on_overflow */
344 sh_reloc, /* special_function */
345 "r_label", /* name */
346 true, /* partial_inplace */
347 0xffffffff, /* src_mask */
348 0xffffffff, /* dst_mask */
349 false), /* pcrel_offset */
350
351 HOWTO (R_SH_SWITCH8, /* type */
352 0, /* rightshift */
353 0, /* size (0 = byte, 1 = short, 2 = long) */
354 8, /* bitsize */
355 false, /* pc_relative */
356 0, /* bitpos */
357 complain_overflow_bitfield, /* complain_on_overflow */
358 sh_reloc, /* special_function */
359 "r_switch8", /* name */
360 true, /* partial_inplace */
361 0xff, /* src_mask */
362 0xff, /* dst_mask */
363 false) /* pcrel_offset */
364};
365
366#define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
367
368/* Check for a bad magic number. */
369#define BADMAG(x) SHBADMAG(x)
370
371/* Customize coffcode.h (this is not currently used). */
372#define SH 1
373
374/* FIXME: This should not be set here. */
375#define __A_MAGIC_SET__
376
377#ifndef COFF_WITH_PE
378/* Swap the r_offset field in and out. */
379#define SWAP_IN_RELOC_OFFSET bfd_h_get_32
380#define SWAP_OUT_RELOC_OFFSET bfd_h_put_32
381
382/* Swap out extra information in the reloc structure. */
383#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
384 do \
385 { \
386 dst->r_stuff[0] = 'S'; \
387 dst->r_stuff[1] = 'C'; \
388 } \
389 while (0)
390#endif
391
392/* Get the value of a symbol, when performing a relocation. */
393
394static long
395get_symbol_value (symbol)
396 asymbol *symbol;
397{
398 bfd_vma relocation;
399
400 if (bfd_is_com_section (symbol->section))
401 relocation = 0;
402 else
403 relocation = (symbol->value +
404 symbol->section->output_section->vma +
405 symbol->section->output_offset);
406
407 return relocation;
408}
409
410#ifdef COFF_WITH_PE
411/* Convert an rtype to howto for the COFF backend linker.
412 Copied from coff-i386. */
413#define coff_rtype_to_howto coff_sh_rtype_to_howto
414
415static reloc_howto_type *
416coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
417 bfd * abfd ATTRIBUTE_UNUSED;
418 asection * sec;
419 struct internal_reloc * rel;
420 struct coff_link_hash_entry * h;
421 struct internal_syment * sym;
422 bfd_vma * addendp;
423{
424 reloc_howto_type * howto;
425
426 howto = sh_coff_howtos + rel->r_type;
427
428 *addendp = 0;
429
430 if (howto->pc_relative)
431 *addendp += sec->vma;
432
433 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
434 {
435 /* This is a common symbol. The section contents include the
436 size (sym->n_value) as an addend. The relocate_section
437 function will be adding in the final value of the symbol. We
438 need to subtract out the current size in order to get the
439 correct result. */
440 BFD_ASSERT (h != NULL);
441 }
442
443 if (howto->pc_relative)
444 {
445 *addendp -= 4;
446
447 /* If the symbol is defined, then the generic code is going to
448 add back the symbol value in order to cancel out an
449 adjustment it made to the addend. However, we set the addend
450 to 0 at the start of this function. We need to adjust here,
451 to avoid the adjustment the generic code will make. FIXME:
452 This is getting a bit hackish. */
453 if (sym != NULL && sym->n_scnum != 0)
454 *addendp -= sym->n_value;
455 }
456
457 if (rel->r_type == R_SH_IMAGEBASE)
458 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
459
460 return howto;
461}
462
463/* This structure is used to map BFD reloc codes to SH PE relocs. */
464struct shcoff_reloc_map
465{
466 unsigned char bfd_reloc_val;
467 unsigned char shcoff_reloc_val;
468};
469
470/* An array mapping BFD reloc codes to SH PE relocs. */
471static const struct shcoff_reloc_map sh_reloc_map[] =
472{
473 { BFD_RELOC_32, R_SH_IMM32CE },
474 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
475 { BFD_RELOC_CTOR, R_SH_IMM32CE },
476};
477
478/* Given a BFD reloc code, return the howto structure for the
479 corresponding SH PE reloc. */
480#define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
481
482static reloc_howto_type *
483sh_coff_reloc_type_lookup (abfd, code)
484 bfd * abfd ATTRIBUTE_UNUSED;
485 bfd_reloc_code_real_type code;
486{
487 unsigned int i;
488
489 for (i = 0; i < sizeof (sh_reloc_map) / sizeof (struct shcoff_reloc_map); i++)
490 {
491 if (sh_reloc_map[i].bfd_reloc_val == code)
492 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
493 }
494
495 fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
496 return NULL;
497}
498#endif /* COFF_WITH_PE */
499
500/* This macro is used in coffcode.h to get the howto corresponding to
501 an internal reloc. */
502
503#define RTYPE2HOWTO(relent, internal) \
504 ((relent)->howto = \
505 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
506 ? &sh_coff_howtos[(internal)->r_type] \
507 : (reloc_howto_type *) NULL))
508
509/* This is the same as the macro in coffcode.h, except that it copies
510 r_offset into reloc_entry->addend for some relocs. */
511#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
512 { \
513 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
514 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
515 coffsym = (obj_symbols (abfd) \
516 + (cache_ptr->sym_ptr_ptr - symbols)); \
517 else if (ptr) \
518 coffsym = coff_symbol_from (abfd, ptr); \
519 if (coffsym != (coff_symbol_type *) NULL \
520 && coffsym->native->u.syment.n_scnum == 0) \
521 cache_ptr->addend = 0; \
522 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
523 && ptr->section != (asection *) NULL) \
524 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
525 else \
526 cache_ptr->addend = 0; \
527 if ((reloc).r_type == R_SH_SWITCH8 \
528 || (reloc).r_type == R_SH_SWITCH16 \
529 || (reloc).r_type == R_SH_SWITCH32 \
530 || (reloc).r_type == R_SH_USES \
531 || (reloc).r_type == R_SH_COUNT \
532 || (reloc).r_type == R_SH_ALIGN) \
533 cache_ptr->addend = (reloc).r_offset; \
534 }
535
536/* This is the howto function for the SH relocations. */
537
538static bfd_reloc_status_type
539sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
540 error_message)
541 bfd *abfd;
542 arelent *reloc_entry;
543 asymbol *symbol_in;
544 PTR data;
545 asection *input_section;
546 bfd *output_bfd;
547 char **error_message ATTRIBUTE_UNUSED;
548{
549 unsigned long insn;
550 bfd_vma sym_value;
551 unsigned short r_type;
552 bfd_vma addr = reloc_entry->address;
553 bfd_byte *hit_data = addr + (bfd_byte *) data;
554
555 r_type = reloc_entry->howto->type;
556
557 if (output_bfd != NULL)
558 {
559 /* Partial linking--do nothing. */
560 reloc_entry->address += input_section->output_offset;
561 return bfd_reloc_ok;
562 }
563
564 /* Almost all relocs have to do with relaxing. If any work must be
565 done for them, it has been done in sh_relax_section. */
566 if (r_type != R_SH_IMM32
567#ifdef COFF_WITH_PE
568 && r_type != R_SH_IMM32CE
569 && r_type != R_SH_IMAGEBASE
570#endif
571 && (r_type != R_SH_PCDISP
572 || (symbol_in->flags & BSF_LOCAL) != 0))
573 return bfd_reloc_ok;
574
575 if (symbol_in != NULL
576 && bfd_is_und_section (symbol_in->section))
577 return bfd_reloc_undefined;
578
579 sym_value = get_symbol_value (symbol_in);
580
581 switch (r_type)
582 {
583 case R_SH_IMM32:
584#ifdef COFF_WITH_PE
585 case R_SH_IMM32CE:
586#endif
587 insn = bfd_get_32 (abfd, hit_data);
588 insn += sym_value + reloc_entry->addend;
589 bfd_put_32 (abfd, insn, hit_data);
590 break;
591#ifdef COFF_WITH_PE
592 case R_SH_IMAGEBASE:
593 insn = bfd_get_32 (abfd, hit_data);
594 insn += (sym_value + reloc_entry->addend
595 - pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase);
596 bfd_put_32 (abfd, insn, hit_data);
597 break;
598#endif
599 case R_SH_PCDISP:
600 insn = bfd_get_16 (abfd, hit_data);
601 sym_value += reloc_entry->addend;
602 sym_value -= (input_section->output_section->vma
603 + input_section->output_offset
604 + addr
605 + 4);
606 sym_value += (insn & 0xfff) << 1;
607 if (insn & 0x800)
608 sym_value -= 0x1000;
609 insn = (insn & 0xf000) | (sym_value & 0xfff);
610 bfd_put_16 (abfd, insn, hit_data);
611 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
612 return bfd_reloc_overflow;
613 break;
614 default:
615 abort ();
616 break;
617 }
618
619 return bfd_reloc_ok;
620}
621
622#define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
623
624/* We can do relaxing. */
625#define coff_bfd_relax_section sh_relax_section
626
627/* We use the special COFF backend linker. */
628#define coff_relocate_section sh_relocate_section
629
630/* When relaxing, we need to use special code to get the relocated
631 section contents. */
632#define coff_bfd_get_relocated_section_contents \
633 sh_coff_get_relocated_section_contents
634
635#include "coffcode.h"
636
637
638/* This function handles relaxing on the SH.
639
640 Function calls on the SH look like this:
641
642 movl L1,r0
643 ...
644 jsr @r0
645 ...
646 L1:
647 .long function
648
649 The compiler and assembler will cooperate to create R_SH_USES
650 relocs on the jsr instructions. The r_offset field of the
651 R_SH_USES reloc is the PC relative offset to the instruction which
652 loads the register (the r_offset field is computed as though it
653 were a jump instruction, so the offset value is actually from four
654 bytes past the instruction). The linker can use this reloc to
655 determine just which function is being called, and thus decide
656 whether it is possible to replace the jsr with a bsr.
657
658 If multiple function calls are all based on a single register load
659 (i.e., the same function is called multiple times), the compiler
660 guarantees that each function call will have an R_SH_USES reloc.
661 Therefore, if the linker is able to convert each R_SH_USES reloc
662 which refers to that address, it can safely eliminate the register
663 load.
664
665 When the assembler creates an R_SH_USES reloc, it examines it to
666 determine which address is being loaded (L1 in the above example).
667 It then counts the number of references to that address, and
668 creates an R_SH_COUNT reloc at that address. The r_offset field of
669 the R_SH_COUNT reloc will be the number of references. If the
670 linker is able to eliminate a register load, it can use the
671 R_SH_COUNT reloc to see whether it can also eliminate the function
672 address.
673
674 SH relaxing also handles another, unrelated, matter. On the SH, if
675 a load or store instruction is not aligned on a four byte boundary,
676 the memory cycle interferes with the 32 bit instruction fetch,
677 causing a one cycle bubble in the pipeline. Therefore, we try to
678 align load and store instructions on four byte boundaries if we
679 can, by swapping them with one of the adjacent instructions. */
680
681static boolean
682sh_relax_section (abfd, sec, link_info, again)
683 bfd *abfd;
684 asection *sec;
685 struct bfd_link_info *link_info;
686 boolean *again;
687{
688 struct internal_reloc *internal_relocs;
689 struct internal_reloc *free_relocs = NULL;
690 boolean have_code;
691 struct internal_reloc *irel, *irelend;
692 bfd_byte *contents = NULL;
693 bfd_byte *free_contents = NULL;
694
695 *again = false;
696
697 if (link_info->relocateable
698 || (sec->flags & SEC_RELOC) == 0
699 || sec->reloc_count == 0)
700 return true;
701
702 /* If this is the first time we have been called for this section,
703 initialize the cooked size. */
704 if (sec->_cooked_size == 0)
705 sec->_cooked_size = sec->_raw_size;
706
707 internal_relocs = (_bfd_coff_read_internal_relocs
708 (abfd, sec, link_info->keep_memory,
709 (bfd_byte *) NULL, false,
710 (struct internal_reloc *) NULL));
711 if (internal_relocs == NULL)
712 goto error_return;
713 if (! link_info->keep_memory)
714 free_relocs = internal_relocs;
715
716 have_code = false;
717
718 irelend = internal_relocs + sec->reloc_count;
719 for (irel = internal_relocs; irel < irelend; irel++)
720 {
721 bfd_vma laddr, paddr, symval;
722 unsigned short insn;
723 struct internal_reloc *irelfn, *irelscan, *irelcount;
724 struct internal_syment sym;
725 bfd_signed_vma foff;
726
727 if (irel->r_type == R_SH_CODE)
728 have_code = true;
729
730 if (irel->r_type != R_SH_USES)
731 continue;
732
733 /* Get the section contents. */
734 if (contents == NULL)
735 {
736 if (coff_section_data (abfd, sec) != NULL
737 && coff_section_data (abfd, sec)->contents != NULL)
738 contents = coff_section_data (abfd, sec)->contents;
739 else
740 {
741 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
742 if (contents == NULL)
743 goto error_return;
744 free_contents = contents;
745
746 if (! bfd_get_section_contents (abfd, sec, contents,
747 (file_ptr) 0, sec->_raw_size))
748 goto error_return;
749 }
750 }
751
752 /* The r_offset field of the R_SH_USES reloc will point us to
753 the register load. The 4 is because the r_offset field is
754 computed as though it were a jump offset, which are based
755 from 4 bytes after the jump instruction. */
756 laddr = irel->r_vaddr - sec->vma + 4;
757 /* Careful to sign extend the 32-bit offset. */
758 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
759 if (laddr >= sec->_raw_size)
760 {
761 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset",
762 bfd_get_filename (abfd),
763 (unsigned long) irel->r_vaddr);
764 continue;
765 }
766 insn = bfd_get_16 (abfd, contents + laddr);
767
768 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
769 if ((insn & 0xf000) != 0xd000)
770 {
771 ((*_bfd_error_handler)
772 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
773 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr, insn));
774 continue;
775 }
776
777 /* Get the address from which the register is being loaded. The
778 displacement in the mov.l instruction is quadrupled. It is a
779 displacement from four bytes after the movl instruction, but,
780 before adding in the PC address, two least significant bits
781 of the PC are cleared. We assume that the section is aligned
782 on a four byte boundary. */
783 paddr = insn & 0xff;
784 paddr *= 4;
785 paddr += (laddr + 4) &~ 3;
786 if (paddr >= sec->_raw_size)
787 {
788 ((*_bfd_error_handler)
789 ("%s: 0x%lx: warning: bad R_SH_USES load offset",
790 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
791 continue;
792 }
793
794 /* Get the reloc for the address from which the register is
795 being loaded. This reloc will tell us which function is
796 actually being called. */
797 paddr += sec->vma;
798 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
799 if (irelfn->r_vaddr == paddr
800#ifdef COFF_WITH_PE
801 && (irelfn->r_type == R_SH_IMM32
802 || irelfn->r_type == R_SH_IMM32CE
803 || irelfn->r_type == R_SH_IMAGEBASE))
804
805#else
806 && irelfn->r_type == R_SH_IMM32)
807#endif
808 break;
809 if (irelfn >= irelend)
810 {
811 ((*_bfd_error_handler)
812 ("%s: 0x%lx: warning: could not find expected reloc",
813 bfd_get_filename (abfd), (unsigned long) paddr));
814 continue;
815 }
816
817 /* Get the value of the symbol referred to by the reloc. */
818 if (! _bfd_coff_get_external_symbols (abfd))
819 goto error_return;
820 bfd_coff_swap_sym_in (abfd,
821 ((bfd_byte *) obj_coff_external_syms (abfd)
822 + (irelfn->r_symndx
823 * bfd_coff_symesz (abfd))),
824 &sym);
825 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
826 {
827 ((*_bfd_error_handler)
828 ("%s: 0x%lx: warning: symbol in unexpected section",
829 bfd_get_filename (abfd), (unsigned long) paddr));
830 continue;
831 }
832
833 if (sym.n_sclass != C_EXT)
834 {
835 symval = (sym.n_value
836 - sec->vma
837 + sec->output_section->vma
838 + sec->output_offset);
839 }
840 else
841 {
842 struct coff_link_hash_entry *h;
843
844 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
845 BFD_ASSERT (h != NULL);
846 if (h->root.type != bfd_link_hash_defined
847 && h->root.type != bfd_link_hash_defweak)
848 {
849 /* This appears to be a reference to an undefined
850 symbol. Just ignore it--it will be caught by the
851 regular reloc processing. */
852 continue;
853 }
854
855 symval = (h->root.u.def.value
856 + h->root.u.def.section->output_section->vma
857 + h->root.u.def.section->output_offset);
858 }
859
860 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
861
862 /* See if this function call can be shortened. */
863 foff = (symval
864 - (irel->r_vaddr
865 - sec->vma
866 + sec->output_section->vma
867 + sec->output_offset
868 + 4));
869 if (foff < -0x1000 || foff >= 0x1000)
870 {
871 /* After all that work, we can't shorten this function call. */
872 continue;
873 }
874
875 /* Shorten the function call. */
876
877 /* For simplicity of coding, we are going to modify the section
878 contents, the section relocs, and the BFD symbol table. We
879 must tell the rest of the code not to free up this
880 information. It would be possible to instead create a table
881 of changes which have to be made, as is done in coff-mips.c;
882 that would be more work, but would require less memory when
883 the linker is run. */
884
885 if (coff_section_data (abfd, sec) == NULL)
886 {
887 sec->used_by_bfd =
888 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
889 if (sec->used_by_bfd == NULL)
890 goto error_return;
891 }
892
893 coff_section_data (abfd, sec)->relocs = internal_relocs;
894 coff_section_data (abfd, sec)->keep_relocs = true;
895 free_relocs = NULL;
896
897 coff_section_data (abfd, sec)->contents = contents;
898 coff_section_data (abfd, sec)->keep_contents = true;
899 free_contents = NULL;
900
901 obj_coff_keep_syms (abfd) = true;
902
903 /* Replace the jsr with a bsr. */
904
905 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
906 replace the jsr with a bsr. */
907 irel->r_type = R_SH_PCDISP;
908 irel->r_symndx = irelfn->r_symndx;
909 if (sym.n_sclass != C_EXT)
910 {
911 /* If this needs to be changed because of future relaxing,
912 it will be handled here like other internal PCDISP
913 relocs. */
914 bfd_put_16 (abfd,
915 0xb000 | ((foff >> 1) & 0xfff),
916 contents + irel->r_vaddr - sec->vma);
917 }
918 else
919 {
920 /* We can't fully resolve this yet, because the external
921 symbol value may be changed by future relaxing. We let
922 the final link phase handle it. */
923 bfd_put_16 (abfd, 0xb000, contents + irel->r_vaddr - sec->vma);
924 }
925
926 /* See if there is another R_SH_USES reloc referring to the same
927 register load. */
928 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
929 if (irelscan->r_type == R_SH_USES
930 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
931 break;
932 if (irelscan < irelend)
933 {
934 /* Some other function call depends upon this register load,
935 and we have not yet converted that function call.
936 Indeed, we may never be able to convert it. There is
937 nothing else we can do at this point. */
938 continue;
939 }
940
941 /* Look for a R_SH_COUNT reloc on the location where the
942 function address is stored. Do this before deleting any
943 bytes, to avoid confusion about the address. */
944 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
945 if (irelcount->r_vaddr == paddr
946 && irelcount->r_type == R_SH_COUNT)
947 break;
948
949 /* Delete the register load. */
950 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
951 goto error_return;
952
953 /* That will change things, so, just in case it permits some
954 other function call to come within range, we should relax
955 again. Note that this is not required, and it may be slow. */
956 *again = true;
957
958 /* Now check whether we got a COUNT reloc. */
959 if (irelcount >= irelend)
960 {
961 ((*_bfd_error_handler)
962 ("%s: 0x%lx: warning: could not find expected COUNT reloc",
963 bfd_get_filename (abfd), (unsigned long) paddr));
964 continue;
965 }
966
967 /* The number of uses is stored in the r_offset field. We've
968 just deleted one. */
969 if (irelcount->r_offset == 0)
970 {
971 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count",
972 bfd_get_filename (abfd),
973 (unsigned long) paddr));
974 continue;
975 }
976
977 --irelcount->r_offset;
978
979 /* If there are no more uses, we can delete the address. Reload
980 the address from irelfn, in case it was changed by the
981 previous call to sh_relax_delete_bytes. */
982 if (irelcount->r_offset == 0)
983 {
984 if (! sh_relax_delete_bytes (abfd, sec,
985 irelfn->r_vaddr - sec->vma, 4))
986 goto error_return;
987 }
988
989 /* We've done all we can with that function call. */
990 }
991
992 /* Look for load and store instructions that we can align on four
993 byte boundaries. */
994 if (have_code)
995 {
996 boolean swapped;
997
998 /* Get the section contents. */
999 if (contents == NULL)
1000 {
1001 if (coff_section_data (abfd, sec) != NULL
1002 && coff_section_data (abfd, sec)->contents != NULL)
1003 contents = coff_section_data (abfd, sec)->contents;
1004 else
1005 {
1006 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
1007 if (contents == NULL)
1008 goto error_return;
1009 free_contents = contents;
1010
1011 if (! bfd_get_section_contents (abfd, sec, contents,
1012 (file_ptr) 0, sec->_raw_size))
1013 goto error_return;
1014 }
1015 }
1016
1017 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1018 goto error_return;
1019
1020 if (swapped)
1021 {
1022 if (coff_section_data (abfd, sec) == NULL)
1023 {
1024 sec->used_by_bfd =
1025 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
1026 if (sec->used_by_bfd == NULL)
1027 goto error_return;
1028 }
1029
1030 coff_section_data (abfd, sec)->relocs = internal_relocs;
1031 coff_section_data (abfd, sec)->keep_relocs = true;
1032 free_relocs = NULL;
1033
1034 coff_section_data (abfd, sec)->contents = contents;
1035 coff_section_data (abfd, sec)->keep_contents = true;
1036 free_contents = NULL;
1037
1038 obj_coff_keep_syms (abfd) = true;
1039 }
1040 }
1041
1042 if (free_relocs != NULL)
1043 {
1044 free (free_relocs);
1045 free_relocs = NULL;
1046 }
1047
1048 if (free_contents != NULL)
1049 {
1050 if (! link_info->keep_memory)
1051 free (free_contents);
1052 else
1053 {
1054 /* Cache the section contents for coff_link_input_bfd. */
1055 if (coff_section_data (abfd, sec) == NULL)
1056 {
1057 sec->used_by_bfd =
1058 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
1059 if (sec->used_by_bfd == NULL)
1060 goto error_return;
1061 coff_section_data (abfd, sec)->relocs = NULL;
1062 }
1063 coff_section_data (abfd, sec)->contents = contents;
1064 }
1065 }
1066
1067 return true;
1068
1069 error_return:
1070 if (free_relocs != NULL)
1071 free (free_relocs);
1072 if (free_contents != NULL)
1073 free (free_contents);
1074 return false;
1075}
1076
1077/* Delete some bytes from a section while relaxing. */
1078
1079static boolean
1080sh_relax_delete_bytes (abfd, sec, addr, count)
1081 bfd *abfd;
1082 asection *sec;
1083 bfd_vma addr;
1084 int count;
1085{
1086 bfd_byte *contents;
1087 struct internal_reloc *irel, *irelend;
1088 struct internal_reloc *irelalign;
1089 bfd_vma toaddr;
1090 bfd_byte *esym, *esymend;
1091 bfd_size_type symesz;
1092 struct coff_link_hash_entry **sym_hash;
1093 asection *o;
1094
1095 contents = coff_section_data (abfd, sec)->contents;
1096
1097 /* The deletion must stop at the next ALIGN reloc for an aligment
1098 power larger than the number of bytes we are deleting. */
1099
1100 irelalign = NULL;
1101 toaddr = sec->_cooked_size;
1102
1103 irel = coff_section_data (abfd, sec)->relocs;
1104 irelend = irel + sec->reloc_count;
1105 for (; irel < irelend; irel++)
1106 {
1107 if (irel->r_type == R_SH_ALIGN
1108 && irel->r_vaddr - sec->vma > addr
1109 && count < (1 << irel->r_offset))
1110 {
1111 irelalign = irel;
1112 toaddr = irel->r_vaddr - sec->vma;
1113 break;
1114 }
1115 }
1116
1117 /* Actually delete the bytes. */
1118 memmove (contents + addr, contents + addr + count, toaddr - addr - count);
1119 if (irelalign == NULL)
1120 sec->_cooked_size -= count;
1121 else
1122 {
1123 int i;
1124
1125#define NOP_OPCODE (0x0009)
1126
1127 BFD_ASSERT ((count & 1) == 0);
1128 for (i = 0; i < count; i += 2)
1129 bfd_put_16 (abfd, NOP_OPCODE, contents + toaddr - count + i);
1130 }
1131
1132 /* Adjust all the relocs. */
1133 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1134 {
1135 bfd_vma nraddr, stop;
1136 bfd_vma start = 0;
1137 int insn = 0;
1138 struct internal_syment sym;
1139 int off, adjust, oinsn;
1140 bfd_signed_vma voff = 0;
1141 boolean overflow;
1142
1143 /* Get the new reloc address. */
1144 nraddr = irel->r_vaddr - sec->vma;
1145 if ((irel->r_vaddr - sec->vma > addr
1146 && irel->r_vaddr - sec->vma < toaddr)
1147 || (irel->r_type == R_SH_ALIGN
1148 && irel->r_vaddr - sec->vma == toaddr))
1149 nraddr -= count;
1150
1151 /* See if this reloc was for the bytes we have deleted, in which
1152 case we no longer care about it. Don't delete relocs which
1153 represent addresses, though. */
1154 if (irel->r_vaddr - sec->vma >= addr
1155 && irel->r_vaddr - sec->vma < addr + count
1156 && irel->r_type != R_SH_ALIGN
1157 && irel->r_type != R_SH_CODE
1158 && irel->r_type != R_SH_DATA
1159 && irel->r_type != R_SH_LABEL)
1160 irel->r_type = R_SH_UNUSED;
1161
1162 /* If this is a PC relative reloc, see if the range it covers
1163 includes the bytes we have deleted. */
1164 switch (irel->r_type)
1165 {
1166 default:
1167 break;
1168
1169 case R_SH_PCDISP8BY2:
1170 case R_SH_PCDISP:
1171 case R_SH_PCRELIMM8BY2:
1172 case R_SH_PCRELIMM8BY4:
1173 start = irel->r_vaddr - sec->vma;
1174 insn = bfd_get_16 (abfd, contents + nraddr);
1175 break;
1176 }
1177
1178 switch (irel->r_type)
1179 {
1180 default:
1181 start = stop = addr;
1182 break;
1183
1184 case R_SH_IMM32:
1185#ifdef COFF_WITH_PE
1186 case R_SH_IMM32CE:
1187 case R_SH_IMAGEBASE:
1188#endif
1189 /* If this reloc is against a symbol defined in this
1190 section, and the symbol will not be adjusted below, we
1191 must check the addend to see it will put the value in
1192 range to be adjusted, and hence must be changed. */
1193 bfd_coff_swap_sym_in (abfd,
1194 ((bfd_byte *) obj_coff_external_syms (abfd)
1195 + (irel->r_symndx
1196 * bfd_coff_symesz (abfd))),
1197 &sym);
1198 if (sym.n_sclass != C_EXT
1199 && sym.n_scnum == sec->target_index
1200 && ((bfd_vma) sym.n_value <= addr
1201 || (bfd_vma) sym.n_value >= toaddr))
1202 {
1203 bfd_vma val;
1204
1205 val = bfd_get_32 (abfd, contents + nraddr);
1206 val += sym.n_value;
1207 if (val > addr && val < toaddr)
1208 bfd_put_32 (abfd, val - count, contents + nraddr);
1209 }
1210 start = stop = addr;
1211 break;
1212
1213 case R_SH_PCDISP8BY2:
1214 off = insn & 0xff;
1215 if (off & 0x80)
1216 off -= 0x100;
1217 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1218 break;
1219
1220 case R_SH_PCDISP:
1221 bfd_coff_swap_sym_in (abfd,
1222 ((bfd_byte *) obj_coff_external_syms (abfd)
1223 + (irel->r_symndx
1224 * bfd_coff_symesz (abfd))),
1225 &sym);
1226 if (sym.n_sclass == C_EXT)
1227 start = stop = addr;
1228 else
1229 {
1230 off = insn & 0xfff;
1231 if (off & 0x800)
1232 off -= 0x1000;
1233 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1234 }
1235 break;
1236
1237 case R_SH_PCRELIMM8BY2:
1238 off = insn & 0xff;
1239 stop = start + 4 + off * 2;
1240 break;
1241
1242 case R_SH_PCRELIMM8BY4:
1243 off = insn & 0xff;
1244 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1245 break;
1246
1247 case R_SH_SWITCH8:
1248 case R_SH_SWITCH16:
1249 case R_SH_SWITCH32:
1250 /* These relocs types represent
1251 .word L2-L1
1252 The r_offset field holds the difference between the reloc
1253 address and L1. That is the start of the reloc, and
1254 adding in the contents gives us the top. We must adjust
1255 both the r_offset field and the section contents. */
1256
1257 start = irel->r_vaddr - sec->vma;
1258 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1259
1260 if (start > addr
1261 && start < toaddr
1262 && (stop <= addr || stop >= toaddr))
1263 irel->r_offset += count;
1264 else if (stop > addr
1265 && stop < toaddr
1266 && (start <= addr || start >= toaddr))
1267 irel->r_offset -= count;
1268
1269 start = stop;
1270
1271 if (irel->r_type == R_SH_SWITCH16)
1272 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1273 else if (irel->r_type == R_SH_SWITCH8)
1274 voff = bfd_get_8 (abfd, contents + nraddr);
1275 else
1276 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1277 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1278
1279 break;
1280
1281 case R_SH_USES:
1282 start = irel->r_vaddr - sec->vma;
1283 stop = (bfd_vma) ((bfd_signed_vma) start
1284 + (long) irel->r_offset
1285 + 4);
1286 break;
1287 }
1288
1289 if (start > addr
1290 && start < toaddr
1291 && (stop <= addr || stop >= toaddr))
1292 adjust = count;
1293 else if (stop > addr
1294 && stop < toaddr
1295 && (start <= addr || start >= toaddr))
1296 adjust = - count;
1297 else
1298 adjust = 0;
1299
1300 if (adjust != 0)
1301 {
1302 oinsn = insn;
1303 overflow = false;
1304 switch (irel->r_type)
1305 {
1306 default:
1307 abort ();
1308 break;
1309
1310 case R_SH_PCDISP8BY2:
1311 case R_SH_PCRELIMM8BY2:
1312 insn += adjust / 2;
1313 if ((oinsn & 0xff00) != (insn & 0xff00))
1314 overflow = true;
1315 bfd_put_16 (abfd, insn, contents + nraddr);
1316 break;
1317
1318 case R_SH_PCDISP:
1319 insn += adjust / 2;
1320 if ((oinsn & 0xf000) != (insn & 0xf000))
1321 overflow = true;
1322 bfd_put_16 (abfd, insn, contents + nraddr);
1323 break;
1324
1325 case R_SH_PCRELIMM8BY4:
1326 BFD_ASSERT (adjust == count || count >= 4);
1327 if (count >= 4)
1328 insn += adjust / 4;
1329 else
1330 {
1331 if ((irel->r_vaddr & 3) == 0)
1332 ++insn;
1333 }
1334 if ((oinsn & 0xff00) != (insn & 0xff00))
1335 overflow = true;
1336 bfd_put_16 (abfd, insn, contents + nraddr);
1337 break;
1338
1339 case R_SH_SWITCH8:
1340 voff += adjust;
1341 if (voff < 0 || voff >= 0xff)
1342 overflow = true;
1343 bfd_put_8 (abfd, voff, contents + nraddr);
1344 break;
1345
1346 case R_SH_SWITCH16:
1347 voff += adjust;
1348 if (voff < - 0x8000 || voff >= 0x8000)
1349 overflow = true;
1350 bfd_put_signed_16 (abfd, voff, contents + nraddr);
1351 break;
1352
1353 case R_SH_SWITCH32:
1354 voff += adjust;
1355 bfd_put_signed_32 (abfd, voff, contents + nraddr);
1356 break;
1357
1358 case R_SH_USES:
1359 irel->r_offset += adjust;
1360 break;
1361 }
1362
1363 if (overflow)
1364 {
1365 ((*_bfd_error_handler)
1366 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
1367 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
1368 bfd_set_error (bfd_error_bad_value);
1369 return false;
1370 }
1371 }
1372
1373 irel->r_vaddr = nraddr + sec->vma;
1374 }
1375
1376 /* Look through all the other sections. If there contain any IMM32
1377 relocs against internal symbols which we are not going to adjust
1378 below, we may need to adjust the addends. */
1379 for (o = abfd->sections; o != NULL; o = o->next)
1380 {
1381 struct internal_reloc *internal_relocs;
1382 struct internal_reloc *irelscan, *irelscanend;
1383 bfd_byte *ocontents;
1384
1385 if (o == sec
1386 || (o->flags & SEC_RELOC) == 0
1387 || o->reloc_count == 0)
1388 continue;
1389
1390 /* We always cache the relocs. Perhaps, if info->keep_memory is
1391 false, we should free them, if we are permitted to, when we
1392 leave sh_coff_relax_section. */
1393 internal_relocs = (_bfd_coff_read_internal_relocs
1394 (abfd, o, true, (bfd_byte *) NULL, false,
1395 (struct internal_reloc *) NULL));
1396 if (internal_relocs == NULL)
1397 return false;
1398
1399 ocontents = NULL;
1400 irelscanend = internal_relocs + o->reloc_count;
1401 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1402 {
1403 struct internal_syment sym;
1404
1405#ifdef COFF_WITH_PE
1406 if (irelscan->r_type != R_SH_IMM32
1407 && irelscan->r_type != R_SH_IMAGEBASE
1408 && irelscan->r_type != R_SH_IMM32CE)
1409#else
1410 if (irelscan->r_type != R_SH_IMM32)
1411#endif
1412 continue;
1413
1414 bfd_coff_swap_sym_in (abfd,
1415 ((bfd_byte *) obj_coff_external_syms (abfd)
1416 + (irelscan->r_symndx
1417 * bfd_coff_symesz (abfd))),
1418 &sym);
1419 if (sym.n_sclass != C_EXT
1420 && sym.n_scnum == sec->target_index
1421 && ((bfd_vma) sym.n_value <= addr
1422 || (bfd_vma) sym.n_value >= toaddr))
1423 {
1424 bfd_vma val;
1425
1426 if (ocontents == NULL)
1427 {
1428 if (coff_section_data (abfd, o)->contents != NULL)
1429 ocontents = coff_section_data (abfd, o)->contents;
1430 else
1431 {
1432 /* We always cache the section contents.
1433 Perhaps, if info->keep_memory is false, we
1434 should free them, if we are permitted to,
1435 when we leave sh_coff_relax_section. */
1436 ocontents = (bfd_byte *) bfd_malloc (o->_raw_size);
1437 if (ocontents == NULL)
1438 return false;
1439 if (! bfd_get_section_contents (abfd, o, ocontents,
1440 (file_ptr) 0,
1441 o->_raw_size))
1442 return false;
1443 coff_section_data (abfd, o)->contents = ocontents;
1444 }
1445 }
1446
1447 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1448 val += sym.n_value;
1449 if (val > addr && val < toaddr)
1450 bfd_put_32 (abfd, val - count,
1451 ocontents + irelscan->r_vaddr - o->vma);
1452
1453 coff_section_data (abfd, o)->keep_contents = true;
1454 }
1455 }
1456 }
1457
1458 /* Adjusting the internal symbols will not work if something has
1459 already retrieved the generic symbols. It would be possible to
1460 make this work by adjusting the generic symbols at the same time.
1461 However, this case should not arise in normal usage. */
1462 if (obj_symbols (abfd) != NULL
1463 || obj_raw_syments (abfd) != NULL)
1464 {
1465 ((*_bfd_error_handler)
1466 ("%s: fatal: generic symbols retrieved before relaxing",
1467 bfd_get_filename (abfd)));
1468 bfd_set_error (bfd_error_invalid_operation);
1469 return false;
1470 }
1471
1472 /* Adjust all the symbols. */
1473 sym_hash = obj_coff_sym_hashes (abfd);
1474 symesz = bfd_coff_symesz (abfd);
1475 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1476 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1477 while (esym < esymend)
1478 {
1479 struct internal_syment isym;
1480
1481 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1482
1483 if (isym.n_scnum == sec->target_index
1484 && (bfd_vma) isym.n_value > addr
1485 && (bfd_vma) isym.n_value < toaddr)
1486 {
1487 isym.n_value -= count;
1488
1489 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1490
1491 if (*sym_hash != NULL)
1492 {
1493 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1494 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1495 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1496 && (*sym_hash)->root.u.def.value < toaddr);
1497 (*sym_hash)->root.u.def.value -= count;
1498 }
1499 }
1500
1501 esym += (isym.n_numaux + 1) * symesz;
1502 sym_hash += isym.n_numaux + 1;
1503 }
1504
1505 /* See if we can move the ALIGN reloc forward. We have adjusted
1506 r_vaddr for it already. */
1507 if (irelalign != NULL)
1508 {
1509 bfd_vma alignto, alignaddr;
1510
1511 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1512 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1513 1 << irelalign->r_offset);
1514 if (alignto != alignaddr)
1515 {
1516 /* Tail recursion. */
1517 return sh_relax_delete_bytes (abfd, sec, alignaddr,
1518 alignto - alignaddr);
1519 }
1520 }
1521
1522 return true;
1523}
1524
1525
1526/* This is yet another version of the SH opcode table, used to rapidly
1527 get information about a particular instruction. */
1528
1529/* The opcode map is represented by an array of these structures. The
1530 array is indexed by the high order four bits in the instruction. */
1531
1532struct sh_major_opcode
1533{
1534 /* A pointer to the instruction list. This is an array which
1535 contains all the instructions with this major opcode. */
1536 const struct sh_minor_opcode *minor_opcodes;
1537 /* The number of elements in minor_opcodes. */
1538 unsigned short count;
1539};
1540
1541/* This structure holds information for a set of SH opcodes. The
1542 instruction code is anded with the mask value, and the resulting
1543 value is used to search the order opcode list. */
1544
1545struct sh_minor_opcode
1546{
1547 /* The sorted opcode list. */
1548 const struct sh_opcode *opcodes;
1549 /* The number of elements in opcodes. */
1550 unsigned short count;
1551 /* The mask value to use when searching the opcode list. */
1552 unsigned short mask;
1553};
1554
1555/* This structure holds information for an SH instruction. An array
1556 of these structures is sorted in order by opcode. */
1557
1558struct sh_opcode
1559{
1560 /* The code for this instruction, after it has been anded with the
1561 mask value in the sh_major_opcode structure. */
1562 unsigned short opcode;
1563 /* Flags for this instruction. */
1564 unsigned long flags;
1565};
1566
1567/* Flag which appear in the sh_opcode structure. */
1568
1569/* This instruction loads a value from memory. */
1570#define LOAD (0x1)
1571
1572/* This instruction stores a value to memory. */
1573#define STORE (0x2)
1574
1575/* This instruction is a branch. */
1576#define BRANCH (0x4)
1577
1578/* This instruction has a delay slot. */
1579#define DELAY (0x8)
1580
1581/* This instruction uses the value in the register in the field at
1582 mask 0x0f00 of the instruction. */
1583#define USES1 (0x10)
1584#define USES1_REG(x) ((x & 0x0f00) >> 8)
1585
1586/* This instruction uses the value in the register in the field at
1587 mask 0x00f0 of the instruction. */
1588#define USES2 (0x20)
1589#define USES2_REG(x) ((x & 0x00f0) >> 4)
1590
1591/* This instruction uses the value in register 0. */
1592#define USESR0 (0x40)
1593
1594/* This instruction sets the value in the register in the field at
1595 mask 0x0f00 of the instruction. */
1596#define SETS1 (0x80)
1597#define SETS1_REG(x) ((x & 0x0f00) >> 8)
1598
1599/* This instruction sets the value in the register in the field at
1600 mask 0x00f0 of the instruction. */
1601#define SETS2 (0x100)
1602#define SETS2_REG(x) ((x & 0x00f0) >> 4)
1603
1604/* This instruction sets register 0. */
1605#define SETSR0 (0x200)
1606
1607/* This instruction sets a special register. */
1608#define SETSSP (0x400)
1609
1610/* This instruction uses a special register. */
1611#define USESSP (0x800)
1612
1613/* This instruction uses the floating point register in the field at
1614 mask 0x0f00 of the instruction. */
1615#define USESF1 (0x1000)
1616#define USESF1_REG(x) ((x & 0x0f00) >> 8)
1617
1618/* This instruction uses the floating point register in the field at
1619 mask 0x00f0 of the instruction. */
1620#define USESF2 (0x2000)
1621#define USESF2_REG(x) ((x & 0x00f0) >> 4)
1622
1623/* This instruction uses floating point register 0. */
1624#define USESF0 (0x4000)
1625
1626/* This instruction sets the floating point register in the field at
1627 mask 0x0f00 of the instruction. */
1628#define SETSF1 (0x8000)
1629#define SETSF1_REG(x) ((x & 0x0f00) >> 8)
1630
1631#define USESAS (0x10000)
1632#define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1633#define USESR8 (0x20000)
1634#define SETSAS (0x40000)
1635#define SETSAS_REG(x) USESAS_REG (x)
1636
1637#ifndef COFF_IMAGE_WITH_PE
1638static boolean sh_insn_uses_reg
1639 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1640static boolean sh_insn_sets_reg
1641 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1642static boolean sh_insn_uses_or_sets_reg
1643 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1644static boolean sh_insn_uses_freg
1645 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1646static boolean sh_insn_sets_freg
1647 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1648static boolean sh_insn_uses_or_sets_freg
1649 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1650static boolean sh_insns_conflict
1651 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1652 const struct sh_opcode *));
1653static boolean sh_load_use
1654 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1655 const struct sh_opcode *));
1656#endif
1657/* The opcode maps. */
1658
1659#define MAP(a) a, sizeof a / sizeof a[0]
1660
1661static const struct sh_opcode sh_opcode00[] =
1662{
1663 { 0x0008, SETSSP }, /* clrt */
1664 { 0x0009, 0 }, /* nop */
1665 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1666 { 0x0018, SETSSP }, /* sett */
1667 { 0x0019, SETSSP }, /* div0u */
1668 { 0x001b, 0 }, /* sleep */
1669 { 0x0028, SETSSP }, /* clrmac */
1670 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1671 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1672 { 0x0048, SETSSP }, /* clrs */
1673 { 0x0058, SETSSP } /* sets */
1674};
1675
1676static const struct sh_opcode sh_opcode01[] =
1677{
1678 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1679 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
1680 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
1681 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1682 { 0x0029, SETS1 | USESSP }, /* movt rn */
1683 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
1684 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1685 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1686 { 0x0083, LOAD | USES1 }, /* pref @rn */
1687 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1688 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1689 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1690 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1691 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1692};
1693
1694/* These sixteen instructions can be handled with one table entry below. */
1695#if 0
1696 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */
1697 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */
1698 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */
1699 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */
1700 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */
1701 { 0x0052, SETS1 | USESSP }, /* stc mod,rn */
1702 { 0x0062, SETS1 | USESSP }, /* stc rs,rn */
1703 { 0x0072, SETS1 | USESSP }, /* stc re,rn */
1704 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */
1705 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */
1706 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */
1707 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */
1708 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */
1709 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */
1710 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */
1711 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */
1712#endif
1713
1714static const struct sh_opcode sh_opcode02[] =
1715{
1716 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
1717 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1718 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1719 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1720 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1721 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1722 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1723 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1724 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1725};
1726
1727static const struct sh_minor_opcode sh_opcode0[] =
1728{
1729 { MAP (sh_opcode00), 0xffff },
1730 { MAP (sh_opcode01), 0xf0ff },
1731 { MAP (sh_opcode02), 0xf00f }
1732};
1733
1734static const struct sh_opcode sh_opcode10[] =
1735{
1736 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1737};
1738
1739static const struct sh_minor_opcode sh_opcode1[] =
1740{
1741 { MAP (sh_opcode10), 0xf000 }
1742};
1743
1744static const struct sh_opcode sh_opcode20[] =
1745{
1746 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1747 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1748 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1749 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1750 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1751 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1752 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1753 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1754 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1755 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1756 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1757 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1758 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1759 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1760 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1761};
1762
1763static const struct sh_minor_opcode sh_opcode2[] =
1764{
1765 { MAP (sh_opcode20), 0xf00f }
1766};
1767
1768static const struct sh_opcode sh_opcode30[] =
1769{
1770 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1771 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1772 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1773 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1774 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1775 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1776 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1777 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1778 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1779 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1780 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1781 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1782 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1783 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1784};
1785
1786static const struct sh_minor_opcode sh_opcode3[] =
1787{
1788 { MAP (sh_opcode30), 0xf00f }
1789};
1790
1791static const struct sh_opcode sh_opcode40[] =
1792{
1793 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1794 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1795 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
1796 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1797 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1798 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
1799 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1800 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1801 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1802 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
1803 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1804 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1805 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
1806 { 0x4014, SETSSP | USES1 }, /* setrc rm */
1807 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1808 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
1809 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1810 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1811 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1812 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
1813 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1814 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1815 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
1816 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1817 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1818 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
1819 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1820 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1821 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1822 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
1823 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1824 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1825 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1826 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1827 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1828 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1829 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1830 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1831 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1832 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1833 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1834 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1835 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1836 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1837 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1838 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1839 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1840 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1841 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1842 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1843 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
1844#if 0 /* These groups sixteen insns can be
1845 handled with one table entry each below. */
1846 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */
1847 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */
1848 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */
1849 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */
1850 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */
1851 { 0x4053, STORE | SETS1 | USES1 | USESSP }, /* stc.l mod,@-rn */
1852 { 0x4063, STORE | SETS1 | USES1 | USESSP }, /* stc.l rs,@-rn */
1853 { 0x4073, STORE | SETS1 | USES1 | USESSP }, /* stc.l re,@-rn */
1854 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l r0_bank,@-rn */
1855 ..
1856 { 0x40f3, STORE | SETS1 | USES1 | USESSP }, /* stc.l r7_bank,@-rn */
1857
1858 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */
1859 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */
1860 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */
1861 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */
1862 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */
1863 { 0x4057, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,mod */
1864 { 0x4067, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rs */
1865 { 0x4077, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,re */
1866 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r0_bank */
1867 ..
1868 { 0x40f7, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,r7_bank */
1869
1870 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */
1871 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */
1872 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */
1873 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */
1874 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */
1875 { 0x405e, SETSSP | USES1 }, /* ldc rm,mod */
1876 { 0x406e, SETSSP | USES1 }, /* ldc rm,rs */
1877 { 0x407e, SETSSP | USES1 } /* ldc rm,re */
1878 { 0x408e, SETSSP | USES1 } /* ldc rm,r0_bank */
1879 ..
1880 { 0x40fe, SETSSP | USES1 } /* ldc rm,r7_bank */
1881#endif
1882};
1883
1884static const struct sh_opcode sh_opcode41[] =
1885{
1886 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1887 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1888 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1889 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1890 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
1891 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1892};
1893
1894static const struct sh_minor_opcode sh_opcode4[] =
1895{
1896 { MAP (sh_opcode40), 0xf0ff },
1897 { MAP (sh_opcode41), 0xf00f }
1898};
1899
1900static const struct sh_opcode sh_opcode50[] =
1901{
1902 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1903};
1904
1905static const struct sh_minor_opcode sh_opcode5[] =
1906{
1907 { MAP (sh_opcode50), 0xf000 }
1908};
1909
1910static const struct sh_opcode sh_opcode60[] =
1911{
1912 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1913 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1914 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1915 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1916 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1917 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1918 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1919 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1920 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1921 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1922 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1923 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1924 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1925 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1926 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1927 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1928};
1929
1930static const struct sh_minor_opcode sh_opcode6[] =
1931{
1932 { MAP (sh_opcode60), 0xf00f }
1933};
1934
1935static const struct sh_opcode sh_opcode70[] =
1936{
1937 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1938};
1939
1940static const struct sh_minor_opcode sh_opcode7[] =
1941{
1942 { MAP (sh_opcode70), 0xf000 }
1943};
1944
1945static const struct sh_opcode sh_opcode80[] =
1946{
1947 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1948 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
1949 { 0x8200, SETSSP }, /* setrc #imm */
1950 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1951 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1952 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1953 { 0x8900, BRANCH | USESSP }, /* bt label */
1954 { 0x8b00, BRANCH | USESSP }, /* bf label */
1955 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
1956 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
1957 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
1958 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1959};
1960
1961static const struct sh_minor_opcode sh_opcode8[] =
1962{
1963 { MAP (sh_opcode80), 0xff00 }
1964};
1965
1966static const struct sh_opcode sh_opcode90[] =
1967{
1968 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1969};
1970
1971static const struct sh_minor_opcode sh_opcode9[] =
1972{
1973 { MAP (sh_opcode90), 0xf000 }
1974};
1975
1976static const struct sh_opcode sh_opcodea0[] =
1977{
1978 { 0xa000, BRANCH | DELAY } /* bra label */
1979};
1980
1981static const struct sh_minor_opcode sh_opcodea[] =
1982{
1983 { MAP (sh_opcodea0), 0xf000 }
1984};
1985
1986static const struct sh_opcode sh_opcodeb0[] =
1987{
1988 { 0xb000, BRANCH | DELAY } /* bsr label */
1989};
1990
1991static const struct sh_minor_opcode sh_opcodeb[] =
1992{
1993 { MAP (sh_opcodeb0), 0xf000 }
1994};
1995
1996static const struct sh_opcode sh_opcodec0[] =
1997{
1998 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1999 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
2000 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
2001 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
2002 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
2003 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
2004 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
2005 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
2006 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
2007 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
2008 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
2009 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
2010 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
2011 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
2012 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
2013 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
2014};
2015
2016static const struct sh_minor_opcode sh_opcodec[] =
2017{
2018 { MAP (sh_opcodec0), 0xff00 }
2019};
2020
2021static const struct sh_opcode sh_opcoded0[] =
2022{
2023 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
2024};
2025
2026static const struct sh_minor_opcode sh_opcoded[] =
2027{
2028 { MAP (sh_opcoded0), 0xf000 }
2029};
2030
2031static const struct sh_opcode sh_opcodee0[] =
2032{
2033 { 0xe000, SETS1 } /* mov #imm,rn */
2034};
2035
2036static const struct sh_minor_opcode sh_opcodee[] =
2037{
2038 { MAP (sh_opcodee0), 0xf000 }
2039};
2040
2041static const struct sh_opcode sh_opcodef0[] =
2042{
2043 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
2044 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
2045 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
2046 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
2047 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
2048 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
2049 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
2050 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
2051 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
2052 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
2053 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
2054 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
2055 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
2056 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
2057};
2058
2059static const struct sh_opcode sh_opcodef1[] =
2060{
2061 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
2062 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
2063 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
2064 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
2065 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
2066 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
2067 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
2068 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
2069 { 0xf08d, SETSF1 }, /* fldi0 fn */
2070 { 0xf09d, SETSF1 } /* fldi1 fn */
2071};
2072
2073static const struct sh_minor_opcode sh_opcodef[] =
2074{
2075 { MAP (sh_opcodef0), 0xf00f },
2076 { MAP (sh_opcodef1), 0xf0ff }
2077};
2078
2079static struct sh_major_opcode sh_opcodes[] =
2080{
2081 { MAP (sh_opcode0) },
2082 { MAP (sh_opcode1) },
2083 { MAP (sh_opcode2) },
2084 { MAP (sh_opcode3) },
2085 { MAP (sh_opcode4) },
2086 { MAP (sh_opcode5) },
2087 { MAP (sh_opcode6) },
2088 { MAP (sh_opcode7) },
2089 { MAP (sh_opcode8) },
2090 { MAP (sh_opcode9) },
2091 { MAP (sh_opcodea) },
2092 { MAP (sh_opcodeb) },
2093 { MAP (sh_opcodec) },
2094 { MAP (sh_opcoded) },
2095 { MAP (sh_opcodee) },
2096 { MAP (sh_opcodef) }
2097};
2098
2099/* The double data transfer / parallel processing insns are not
2100 described here. This will cause sh_align_load_span to leave them alone. */
2101
2102static const struct sh_opcode sh_dsp_opcodef0[] =
2103{
2104 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2105 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2106 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2107 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2108 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2109 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2110 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2111 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2112};
2113
2114static const struct sh_minor_opcode sh_dsp_opcodef[] =
2115{
2116 { MAP (sh_dsp_opcodef0), 0xfc0d }
2117};
2118
2119#ifndef COFF_IMAGE_WITH_PE
2120/* Given an instruction, return a pointer to the corresponding
2121 sh_opcode structure. Return NULL if the instruction is not
2122 recognized. */
2123
2124static const struct sh_opcode *
2125sh_insn_info (insn)
2126 unsigned int insn;
2127{
2128 const struct sh_major_opcode *maj;
2129 const struct sh_minor_opcode *min, *minend;
2130
2131 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2132 min = maj->minor_opcodes;
2133 minend = min + maj->count;
2134 for (; min < minend; min++)
2135 {
2136 unsigned int l;
2137 const struct sh_opcode *op, *opend;
2138
2139 l = insn & min->mask;
2140 op = min->opcodes;
2141 opend = op + min->count;
2142
2143 /* Since the opcodes tables are sorted, we could use a binary
2144 search here if the count were above some cutoff value. */
2145 for (; op < opend; op++)
2146 if (op->opcode == l)
2147 return op;
2148 }
2149
2150 return NULL;
2151}
2152
2153/* See whether an instruction uses or sets a general purpose register */
2154
2155static boolean
2156sh_insn_uses_or_sets_reg (insn, op, reg)
2157 unsigned int insn;
2158 const struct sh_opcode *op;
2159 unsigned int reg;
2160{
2161 if (sh_insn_uses_reg (insn, op, reg))
2162 return true;
2163
2164 return sh_insn_sets_reg (insn, op, reg);
2165}
2166
2167/* See whether an instruction uses a general purpose register. */
2168
2169static boolean
2170sh_insn_uses_reg (insn, op, reg)
2171 unsigned int insn;
2172 const struct sh_opcode *op;
2173 unsigned int reg;
2174{
2175 unsigned int f;
2176
2177 f = op->flags;
2178
2179 if ((f & USES1) != 0
2180 && USES1_REG (insn) == reg)
2181 return true;
2182 if ((f & USES2) != 0
2183 && USES2_REG (insn) == reg)
2184 return true;
2185 if ((f & USESR0) != 0
2186 && reg == 0)
2187 return true;
2188 if ((f & USESAS) && reg == USESAS_REG (insn))
2189 return true;
2190 if ((f & USESR8) && reg == 8)
2191 return true;
2192
2193 return false;
2194}
2195
2196/* See whether an instruction sets a general purpose register. */
2197
2198static boolean
2199sh_insn_sets_reg (insn, op, reg)
2200 unsigned int insn;
2201 const struct sh_opcode *op;
2202 unsigned int reg;
2203{
2204 unsigned int f;
2205
2206 f = op->flags;
2207
2208 if ((f & SETS1) != 0
2209 && SETS1_REG (insn) == reg)
2210 return true;
2211 if ((f & SETS2) != 0
2212 && SETS2_REG (insn) == reg)
2213 return true;
2214 if ((f & SETSR0) != 0
2215 && reg == 0)
2216 return true;
2217 if ((f & SETSAS) && reg == SETSAS_REG (insn))
2218 return true;
2219
2220 return false;
2221}
2222
2223/* See whether an instruction uses or sets a floating point register */
2224
2225static boolean
2226sh_insn_uses_or_sets_freg (insn, op, reg)
2227 unsigned int insn;
2228 const struct sh_opcode *op;
2229 unsigned int reg;
2230{
2231 if (sh_insn_uses_freg (insn, op, reg))
2232 return true;
2233
2234 return sh_insn_sets_freg (insn, op, reg);
2235}
2236
2237/* See whether an instruction uses a floating point register. */
2238
2239static boolean
2240sh_insn_uses_freg (insn, op, freg)
2241 unsigned int insn;
2242 const struct sh_opcode *op;
2243 unsigned int freg;
2244{
2245 unsigned int f;
2246
2247 f = op->flags;
2248
2249 /* We can't tell if this is a double-precision insn, so just play safe
2250 and assume that it might be. So not only have we test FREG against
2251 itself, but also even FREG against FREG+1 - if the using insn uses
2252 just the low part of a double precision value - but also an odd
2253 FREG against FREG-1 - if the setting insn sets just the low part
2254 of a double precision value.
2255 So what this all boils down to is that we have to ignore the lowest
2256 bit of the register number. */
2257
2258 if ((f & USESF1) != 0
2259 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
2260 return true;
2261 if ((f & USESF2) != 0
2262 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
2263 return true;
2264 if ((f & USESF0) != 0
2265 && freg == 0)
2266 return true;
2267
2268 return false;
2269}
2270
2271/* See whether an instruction sets a floating point register. */
2272
2273static boolean
2274sh_insn_sets_freg (insn, op, freg)
2275 unsigned int insn;
2276 const struct sh_opcode *op;
2277 unsigned int freg;
2278{
2279 unsigned int f;
2280
2281 f = op->flags;
2282
2283 /* We can't tell if this is a double-precision insn, so just play safe
2284 and assume that it might be. So not only have we test FREG against
2285 itself, but also even FREG against FREG+1 - if the using insn uses
2286 just the low part of a double precision value - but also an odd
2287 FREG against FREG-1 - if the setting insn sets just the low part
2288 of a double precision value.
2289 So what this all boils down to is that we have to ignore the lowest
2290 bit of the register number. */
2291
2292 if ((f & SETSF1) != 0
2293 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
2294 return true;
2295
2296 return false;
2297}
2298
2299/* See whether instructions I1 and I2 conflict, assuming I1 comes
2300 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
2301 This should return true if there is a conflict, or false if the
2302 instructions can be swapped safely. */
2303
2304static boolean
2305sh_insns_conflict (i1, op1, i2, op2)
2306 unsigned int i1;
2307 const struct sh_opcode *op1;
2308 unsigned int i2;
2309 const struct sh_opcode *op2;
2310{
2311 unsigned int f1, f2;
2312
2313 f1 = op1->flags;
2314 f2 = op2->flags;
2315
2316 /* Load of fpscr conflicts with floating point operations.
2317 FIXME: shouldn't test raw opcodes here. */
2318 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2319 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
2320 return true;
2321
2322 if ((f1 & (BRANCH | DELAY)) != 0
2323 || (f2 & (BRANCH | DELAY)) != 0)
2324 return true;
2325
2326 if (((f1 | f2) & SETSSP)
2327 && (f1 & (SETSSP | USESSP))
2328 && (f2 & (SETSSP | USESSP)))
2329 return true;
2330
2331 if ((f1 & SETS1) != 0
2332 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
2333 return true;
2334 if ((f1 & SETS2) != 0
2335 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
2336 return true;
2337 if ((f1 & SETSR0) != 0
2338 && sh_insn_uses_or_sets_reg (i2, op2, 0))
2339 return true;
2340 if ((f1 & SETSAS)
2341 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
2342 return true;
2343 if ((f1 & SETSF1) != 0
2344 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
2345 return true;
2346
2347 if ((f2 & SETS1) != 0
2348 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
2349 return true;
2350 if ((f2 & SETS2) != 0
2351 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
2352 return true;
2353 if ((f2 & SETSR0) != 0
2354 && sh_insn_uses_or_sets_reg (i1, op1, 0))
2355 return true;
2356 if ((f2 & SETSAS)
2357 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
2358 return true;
2359 if ((f2 & SETSF1) != 0
2360 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
2361 return true;
2362
2363 /* The instructions do not conflict. */
2364 return false;
2365}
2366
2367/* I1 is a load instruction, and I2 is some other instruction. Return
2368 true if I1 loads a register which I2 uses. */
2369
2370static boolean
2371sh_load_use (i1, op1, i2, op2)
2372 unsigned int i1;
2373 const struct sh_opcode *op1;
2374 unsigned int i2;
2375 const struct sh_opcode *op2;
2376{
2377 unsigned int f1;
2378
2379 f1 = op1->flags;
2380
2381 if ((f1 & LOAD) == 0)
2382 return false;
2383
2384 /* If both SETS1 and SETSSP are set, that means a load to a special
2385 register using postincrement addressing mode, which we don't care
2386 about here. */
2387 if ((f1 & SETS1) != 0
2388 && (f1 & SETSSP) == 0
2389 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
2390 return true;
2391
2392 if ((f1 & SETSR0) != 0
2393 && sh_insn_uses_reg (i2, op2, 0))
2394 return true;
2395
2396 if ((f1 & SETSF1) != 0
2397 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
2398 return true;
2399
2400 return false;
2401}
2402
2403/* Try to align loads and stores within a span of memory. This is
2404 called by both the ELF and the COFF sh targets. ABFD and SEC are
2405 the BFD and section we are examining. CONTENTS is the contents of
2406 the section. SWAP is the routine to call to swap two instructions.
2407 RELOCS is a pointer to the internal relocation information, to be
2408 passed to SWAP. PLABEL is a pointer to the current label in a
2409 sorted list of labels; LABEL_END is the end of the list. START and
2410 STOP are the range of memory to examine. If a swap is made,
2411 *PSWAPPED is set to true. */
2412
2413#ifdef COFF_WITH_PE
2414static
2415#endif
2416boolean
2417_bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2418 plabel, label_end, start, stop, pswapped)
2419 bfd *abfd;
2420 asection *sec;
2421 bfd_byte *contents;
2422 boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
2423 PTR relocs;
2424 bfd_vma **plabel;
2425 bfd_vma *label_end;
2426 bfd_vma start;
2427 bfd_vma stop;
2428 boolean *pswapped;
2429{
2430 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2431 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
2432 bfd_vma i;
2433
2434 /* The SH4 has a Harvard architecture, hence aligning loads is not
2435 desirable. In fact, it is counter-productive, since it interferes
2436 with the schedules generated by the compiler. */
2437 if (abfd->arch_info->mach == bfd_mach_sh4)
2438 return true;
2439
2440 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2441 instructions. */
2442 if (dsp)
2443 {
2444 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2445 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
2446 }
2447
2448 /* Instructions should be aligned on 2 byte boundaries. */
2449 if ((start & 1) == 1)
2450 ++start;
2451
2452 /* Now look through the unaligned addresses. */
2453 i = start;
2454 if ((i & 2) == 0)
2455 i += 2;
2456 for (; i < stop; i += 4)
2457 {
2458 unsigned int insn;
2459 const struct sh_opcode *op;
2460 unsigned int prev_insn = 0;
2461 const struct sh_opcode *prev_op = NULL;
2462
2463 insn = bfd_get_16 (abfd, contents + i);
2464 op = sh_insn_info (insn);
2465 if (op == NULL
2466 || (op->flags & (LOAD | STORE)) == 0)
2467 continue;
2468
2469 /* This is a load or store which is not on a four byte boundary. */
2470
2471 while (*plabel < label_end && **plabel < i)
2472 ++*plabel;
2473
2474 if (i > start)
2475 {
2476 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2477 /* If INSN is the field b of a parallel processing insn, it is not
2478 a load / store after all. Note that the test here might mistake
2479 the field_b of a pcopy insn for the starting code of a parallel
2480 processing insn; this might miss a swapping opportunity, but at
2481 least we're on the safe side. */
2482 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2483 continue;
2484
2485 /* Check if prev_insn is actually the field b of a parallel
2486 processing insn. Again, this can give a spurious match
2487 after a pcopy. */
2488 if (dsp && i - 2 > start)
2489 {
2490 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
2491
2492 if ((pprev_insn & 0xfc00) == 0xf800)
2493 prev_op = NULL;
2494 else
2495 prev_op = sh_insn_info (prev_insn);
2496 }
2497 else
2498 prev_op = sh_insn_info (prev_insn);
2499
2500 /* If the load/store instruction is in a delay slot, we
2501 can't swap. */
2502 if (prev_op == NULL
2503 || (prev_op->flags & DELAY) != 0)
2504 continue;
2505 }
2506 if (i > start
2507 && (*plabel >= label_end || **plabel != i)
2508 && prev_op != NULL
2509 && (prev_op->flags & (LOAD | STORE)) == 0
2510 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2511 {
2512 boolean ok;
2513
2514 /* The load/store instruction does not have a label, and
2515 there is a previous instruction; PREV_INSN is not
2516 itself a load/store instruction, and PREV_INSN and
2517 INSN do not conflict. */
2518
2519 ok = true;
2520
2521 if (i >= start + 4)
2522 {
2523 unsigned int prev2_insn;
2524 const struct sh_opcode *prev2_op;
2525
2526 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2527 prev2_op = sh_insn_info (prev2_insn);
2528
2529 /* If the instruction before PREV_INSN has a delay
2530 slot--that is, PREV_INSN is in a delay slot--we
2531 can not swap. */
2532 if (prev2_op == NULL
2533 || (prev2_op->flags & DELAY) != 0)
2534 ok = false;
2535
2536 /* If the instruction before PREV_INSN is a load,
2537 and it sets a register which INSN uses, then
2538 putting INSN immediately after PREV_INSN will
2539 cause a pipeline bubble, so there is no point to
2540 making the swap. */
2541 if (ok
2542 && (prev2_op->flags & LOAD) != 0
2543 && sh_load_use (prev2_insn, prev2_op, insn, op))
2544 ok = false;
2545 }
2546
2547 if (ok)
2548 {
2549 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
2550 return false;
2551 *pswapped = true;
2552 continue;
2553 }
2554 }
2555
2556 while (*plabel < label_end && **plabel < i + 2)
2557 ++*plabel;
2558
2559 if (i + 2 < stop
2560 && (*plabel >= label_end || **plabel != i + 2))
2561 {
2562 unsigned int next_insn;
2563 const struct sh_opcode *next_op;
2564
2565 /* There is an instruction after the load/store
2566 instruction, and it does not have a label. */
2567 next_insn = bfd_get_16 (abfd, contents + i + 2);
2568 next_op = sh_insn_info (next_insn);
2569 if (next_op != NULL
2570 && (next_op->flags & (LOAD | STORE)) == 0
2571 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2572 {
2573 boolean ok;
2574
2575 /* NEXT_INSN is not itself a load/store instruction,
2576 and it does not conflict with INSN. */
2577
2578 ok = true;
2579
2580 /* If PREV_INSN is a load, and it sets a register
2581 which NEXT_INSN uses, then putting NEXT_INSN
2582 immediately after PREV_INSN will cause a pipeline
2583 bubble, so there is no reason to make this swap. */
2584 if (prev_op != NULL
2585 && (prev_op->flags & LOAD) != 0
2586 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
2587 ok = false;
2588
2589 /* If INSN is a load, and it sets a register which
2590 the insn after NEXT_INSN uses, then doing the
2591 swap will cause a pipeline bubble, so there is no
2592 reason to make the swap. However, if the insn
2593 after NEXT_INSN is itself a load or store
2594 instruction, then it is misaligned, so
2595 optimistically hope that it will be swapped
2596 itself, and just live with the pipeline bubble if
2597 it isn't. */
2598 if (ok
2599 && i + 4 < stop
2600 && (op->flags & LOAD) != 0)
2601 {
2602 unsigned int next2_insn;
2603 const struct sh_opcode *next2_op;
2604
2605 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2606 next2_op = sh_insn_info (next2_insn);
2607 if ((next2_op->flags & (LOAD | STORE)) == 0
2608 && sh_load_use (insn, op, next2_insn, next2_op))
2609 ok = false;
2610 }
2611
2612 if (ok)
2613 {
2614 if (! (*swap) (abfd, sec, relocs, contents, i))
2615 return false;
2616 *pswapped = true;
2617 continue;
2618 }
2619 }
2620 }
2621 }
2622
2623 return true;
2624}
2625#endif /* not COFF_IMAGE_WITH_PE */
2626
2627/* Look for loads and stores which we can align to four byte
2628 boundaries. See the longer comment above sh_relax_section for why
2629 this is desirable. This sets *PSWAPPED if some instruction was
2630 swapped. */
2631
2632static boolean
2633sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2634 bfd *abfd;
2635 asection *sec;
2636 struct internal_reloc *internal_relocs;
2637 bfd_byte *contents;
2638 boolean *pswapped;
2639{
2640 struct internal_reloc *irel, *irelend;
2641 bfd_vma *labels = NULL;
2642 bfd_vma *label, *label_end;
2643
2644 *pswapped = false;
2645
2646 irelend = internal_relocs + sec->reloc_count;
2647
2648 /* Get all the addresses with labels on them. */
2649 labels = (bfd_vma *) bfd_malloc (sec->reloc_count * sizeof (bfd_vma));
2650 if (labels == NULL)
2651 goto error_return;
2652 label_end = labels;
2653 for (irel = internal_relocs; irel < irelend; irel++)
2654 {
2655 if (irel->r_type == R_SH_LABEL)
2656 {
2657 *label_end = irel->r_vaddr - sec->vma;
2658 ++label_end;
2659 }
2660 }
2661
2662 /* Note that the assembler currently always outputs relocs in
2663 address order. If that ever changes, this code will need to sort
2664 the label values and the relocs. */
2665
2666 label = labels;
2667
2668 for (irel = internal_relocs; irel < irelend; irel++)
2669 {
2670 bfd_vma start, stop;
2671
2672 if (irel->r_type != R_SH_CODE)
2673 continue;
2674
2675 start = irel->r_vaddr - sec->vma;
2676
2677 for (irel++; irel < irelend; irel++)
2678 if (irel->r_type == R_SH_DATA)
2679 break;
2680 if (irel < irelend)
2681 stop = irel->r_vaddr - sec->vma;
2682 else
2683 stop = sec->_cooked_size;
2684
2685 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2686 (PTR) internal_relocs, &label,
2687 label_end, start, stop, pswapped))
2688 goto error_return;
2689 }
2690
2691 free (labels);
2692
2693 return true;
2694
2695 error_return:
2696 if (labels != NULL)
2697 free (labels);
2698 return false;
2699}
2700
2701/* Swap two SH instructions. */
2702
2703static boolean
2704sh_swap_insns (abfd, sec, relocs, contents, addr)
2705 bfd *abfd;
2706 asection *sec;
2707 PTR relocs;
2708 bfd_byte *contents;
2709 bfd_vma addr;
2710{
2711 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2712 unsigned short i1, i2;
2713 struct internal_reloc *irel, *irelend;
2714
2715 /* Swap the instructions themselves. */
2716 i1 = bfd_get_16 (abfd, contents + addr);
2717 i2 = bfd_get_16 (abfd, contents + addr + 2);
2718 bfd_put_16 (abfd, i2, contents + addr);
2719 bfd_put_16 (abfd, i1, contents + addr + 2);
2720
2721 /* Adjust all reloc addresses. */
2722 irelend = internal_relocs + sec->reloc_count;
2723 for (irel = internal_relocs; irel < irelend; irel++)
2724 {
2725 int type, add;
2726
2727 /* There are a few special types of relocs that we don't want to
2728 adjust. These relocs do not apply to the instruction itself,
2729 but are only associated with the address. */
2730 type = irel->r_type;
2731 if (type == R_SH_ALIGN
2732 || type == R_SH_CODE
2733 || type == R_SH_DATA
2734 || type == R_SH_LABEL)
2735 continue;
2736
2737 /* If an R_SH_USES reloc points to one of the addresses being
2738 swapped, we must adjust it. It would be incorrect to do this
2739 for a jump, though, since we want to execute both
2740 instructions after the jump. (We have avoided swapping
2741 around a label, so the jump will not wind up executing an
2742 instruction it shouldn't). */
2743 if (type == R_SH_USES)
2744 {
2745 bfd_vma off;
2746
2747 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2748 if (off == addr)
2749 irel->r_offset += 2;
2750 else if (off == addr + 2)
2751 irel->r_offset -= 2;
2752 }
2753
2754 if (irel->r_vaddr - sec->vma == addr)
2755 {
2756 irel->r_vaddr += 2;
2757 add = -2;
2758 }
2759 else if (irel->r_vaddr - sec->vma == addr + 2)
2760 {
2761 irel->r_vaddr -= 2;
2762 add = 2;
2763 }
2764 else
2765 add = 0;
2766
2767 if (add != 0)
2768 {
2769 bfd_byte *loc;
2770 unsigned short insn, oinsn;
2771 boolean overflow;
2772
2773 loc = contents + irel->r_vaddr - sec->vma;
2774 overflow = false;
2775 switch (type)
2776 {
2777 default:
2778 break;
2779
2780 case R_SH_PCDISP8BY2:
2781 case R_SH_PCRELIMM8BY2:
2782 insn = bfd_get_16 (abfd, loc);
2783 oinsn = insn;
2784 insn += add / 2;
2785 if ((oinsn & 0xff00) != (insn & 0xff00))
2786 overflow = true;
2787 bfd_put_16 (abfd, insn, loc);
2788 break;
2789
2790 case R_SH_PCDISP:
2791 insn = bfd_get_16 (abfd, loc);
2792 oinsn = insn;
2793 insn += add / 2;
2794 if ((oinsn & 0xf000) != (insn & 0xf000))
2795 overflow = true;
2796 bfd_put_16 (abfd, insn, loc);
2797 break;
2798
2799 case R_SH_PCRELIMM8BY4:
2800 /* This reloc ignores the least significant 3 bits of
2801 the program counter before adding in the offset.
2802 This means that if ADDR is at an even address, the
2803 swap will not affect the offset. If ADDR is an at an
2804 odd address, then the instruction will be crossing a
2805 four byte boundary, and must be adjusted. */
2806 if ((addr & 3) != 0)
2807 {
2808 insn = bfd_get_16 (abfd, loc);
2809 oinsn = insn;
2810 insn += add / 2;
2811 if ((oinsn & 0xff00) != (insn & 0xff00))
2812 overflow = true;
2813 bfd_put_16 (abfd, insn, loc);
2814 }
2815
2816 break;
2817 }
2818
2819 if (overflow)
2820 {
2821 ((*_bfd_error_handler)
2822 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
2823 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
2824 bfd_set_error (bfd_error_bad_value);
2825 return false;
2826 }
2827 }
2828 }
2829
2830 return true;
2831}
2832
2833
2834/* This is a modification of _bfd_coff_generic_relocate_section, which
2835 will handle SH relaxing. */
2836
2837static boolean
2838sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2839 relocs, syms, sections)
2840 bfd *output_bfd ATTRIBUTE_UNUSED;
2841 struct bfd_link_info *info;
2842 bfd *input_bfd;
2843 asection *input_section;
2844 bfd_byte *contents;
2845 struct internal_reloc *relocs;
2846 struct internal_syment *syms;
2847 asection **sections;
2848{
2849 struct internal_reloc *rel;
2850 struct internal_reloc *relend;
2851
2852 rel = relocs;
2853 relend = rel + input_section->reloc_count;
2854 for (; rel < relend; rel++)
2855 {
2856 long symndx;
2857 struct coff_link_hash_entry *h;
2858 struct internal_syment *sym;
2859 bfd_vma addend;
2860 bfd_vma val;
2861 reloc_howto_type *howto;
2862 bfd_reloc_status_type rstat;
2863
2864 /* Almost all relocs have to do with relaxing. If any work must
2865 be done for them, it has been done in sh_relax_section. */
2866 if (rel->r_type != R_SH_IMM32
2867#ifdef COFF_WITH_PE
2868 && rel->r_type != R_SH_IMM32CE
2869 && rel->r_type != R_SH_IMAGEBASE
2870#endif
2871 && rel->r_type != R_SH_PCDISP)
2872 continue;
2873
2874 symndx = rel->r_symndx;
2875
2876 if (symndx == -1)
2877 {
2878 h = NULL;
2879 sym = NULL;
2880 }
2881 else
2882 {
2883 if (symndx < 0
2884 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2885 {
2886 (*_bfd_error_handler)
2887 ("%s: illegal symbol index %ld in relocs",
2888 bfd_get_filename (input_bfd), symndx);
2889 bfd_set_error (bfd_error_bad_value);
2890 return false;
2891 }
2892 h = obj_coff_sym_hashes (input_bfd)[symndx];
2893 sym = syms + symndx;
2894 }
2895
2896 if (sym != NULL && sym->n_scnum != 0)
2897 addend = - sym->n_value;
2898 else
2899 addend = 0;
2900
2901 if (rel->r_type == R_SH_PCDISP)
2902 addend -= 4;
2903
2904 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2905 howto = NULL;
2906 else
2907 howto = &sh_coff_howtos[rel->r_type];
2908
2909 if (howto == NULL)
2910 {
2911 bfd_set_error (bfd_error_bad_value);
2912 return false;
2913 }
2914
2915#ifdef COFF_WITH_PE
2916 if (rel->r_type == R_SH_IMAGEBASE)
2917 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2918#endif
2919
2920 val = 0;
2921
2922 if (h == NULL)
2923 {
2924 asection *sec;
2925
2926 /* There is nothing to do for an internal PCDISP reloc. */
2927 if (rel->r_type == R_SH_PCDISP)
2928 continue;
2929
2930 if (symndx == -1)
2931 {
2932 sec = bfd_abs_section_ptr;
2933 val = 0;
2934 }
2935 else
2936 {
2937 sec = sections[symndx];
2938 val = (sec->output_section->vma
2939 + sec->output_offset
2940 + sym->n_value
2941 - sec->vma);
2942 }
2943 }
2944 else
2945 {
2946 if (h->root.type == bfd_link_hash_defined
2947 || h->root.type == bfd_link_hash_defweak)
2948 {
2949 asection *sec;
2950
2951 sec = h->root.u.def.section;
2952 val = (h->root.u.def.value
2953 + sec->output_section->vma
2954 + sec->output_offset);
2955 }
2956 else if (! info->relocateable)
2957 {
2958 if (! ((*info->callbacks->undefined_symbol)
2959 (info, h->root.root.string, input_bfd, input_section,
2960 rel->r_vaddr - input_section->vma, true)))
2961 return false;
2962 }
2963 }
2964
2965 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2966 contents,
2967 rel->r_vaddr - input_section->vma,
2968 val, addend);
2969
2970 switch (rstat)
2971 {
2972 default:
2973 abort ();
2974 case bfd_reloc_ok:
2975 break;
2976 case bfd_reloc_overflow:
2977 {
2978 const char *name;
2979 char buf[SYMNMLEN + 1];
2980
2981 if (symndx == -1)
2982 name = "*ABS*";
2983 else if (h != NULL)
2984 name = h->root.root.string;
2985 else if (sym->_n._n_n._n_zeroes == 0
2986 && sym->_n._n_n._n_offset != 0)
2987 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2988 else
2989 {
2990 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2991 buf[SYMNMLEN] = '\0';
2992 name = buf;
2993 }
2994
2995 if (! ((*info->callbacks->reloc_overflow)
2996 (info, name, howto->name, (bfd_vma) 0, input_bfd,
2997 input_section, rel->r_vaddr - input_section->vma)))
2998 return false;
2999 }
3000 }
3001 }
3002
3003 return true;
3004}
3005
3006/* This is a version of bfd_generic_get_relocated_section_contents
3007 which uses sh_relocate_section. */
3008
3009static bfd_byte *
3010sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
3011 data, relocateable, symbols)
3012 bfd *output_bfd;
3013 struct bfd_link_info *link_info;
3014 struct bfd_link_order *link_order;
3015 bfd_byte *data;
3016 boolean relocateable;
3017 asymbol **symbols;
3018{
3019 asection *input_section = link_order->u.indirect.section;
3020 bfd *input_bfd = input_section->owner;
3021 asection **sections = NULL;
3022 struct internal_reloc *internal_relocs = NULL;
3023 struct internal_syment *internal_syms = NULL;
3024
3025 /* We only need to handle the case of relaxing, or of having a
3026 particular set of section contents, specially. */
3027 if (relocateable
3028 || coff_section_data (input_bfd, input_section) == NULL
3029 || coff_section_data (input_bfd, input_section)->contents == NULL)
3030 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
3031 link_order, data,
3032 relocateable,
3033 symbols);
3034
3035 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
3036 input_section->_raw_size);
3037
3038 if ((input_section->flags & SEC_RELOC) != 0
3039 && input_section->reloc_count > 0)
3040 {
3041 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
3042 bfd_byte *esym, *esymend;
3043 struct internal_syment *isymp;
3044 asection **secpp;
3045
3046 if (! _bfd_coff_get_external_symbols (input_bfd))
3047 goto error_return;
3048
3049 internal_relocs = (_bfd_coff_read_internal_relocs
3050 (input_bfd, input_section, false, (bfd_byte *) NULL,
3051 false, (struct internal_reloc *) NULL));
3052 if (internal_relocs == NULL)
3053 goto error_return;
3054
3055 internal_syms = ((struct internal_syment *)
3056 bfd_malloc (obj_raw_syment_count (input_bfd)
3057 * sizeof (struct internal_syment)));
3058 if (internal_syms == NULL)
3059 goto error_return;
3060
3061 sections = (asection **) bfd_malloc (obj_raw_syment_count (input_bfd)
3062 * sizeof (asection *));
3063 if (sections == NULL)
3064 goto error_return;
3065
3066 isymp = internal_syms;
3067 secpp = sections;
3068 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
3069 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
3070 while (esym < esymend)
3071 {
3072 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
3073
3074 if (isymp->n_scnum != 0)
3075 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
3076 else
3077 {
3078 if (isymp->n_value == 0)
3079 *secpp = bfd_und_section_ptr;
3080 else
3081 *secpp = bfd_com_section_ptr;
3082 }
3083
3084 esym += (isymp->n_numaux + 1) * symesz;
3085 secpp += isymp->n_numaux + 1;
3086 isymp += isymp->n_numaux + 1;
3087 }
3088
3089 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
3090 input_section, data, internal_relocs,
3091 internal_syms, sections))
3092 goto error_return;
3093
3094 free (sections);
3095 sections = NULL;
3096 free (internal_syms);
3097 internal_syms = NULL;
3098 free (internal_relocs);
3099 internal_relocs = NULL;
3100 }
3101
3102 return data;
3103
3104 error_return:
3105 if (internal_relocs != NULL)
3106 free (internal_relocs);
3107 if (internal_syms != NULL)
3108 free (internal_syms);
3109 if (sections != NULL)
3110 free (sections);
3111 return NULL;
3112}
3113
3114/* The target vectors. */
3115
3116#ifndef TARGET_SHL_SYM
3117CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL)
3118#endif
3119
3120#ifdef TARGET_SHL_SYM
3121#define TARGET_SYM TARGET_SHL_SYM
3122#else
3123#define TARGET_SYM shlcoff_vec
3124#endif
3125
3126#ifndef TARGET_SHL_NAME
3127#define TARGET_SHL_NAME "coff-shl"
3128#endif
3129
3130#ifdef COFF_WITH_PE
3131CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3132 SEC_CODE | SEC_DATA, '_', NULL);
3133#else
3134CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3135 0, '_', NULL)
3136#endif
3137
3138#ifndef TARGET_SHL_SYM
3139/* Some people want versions of the SH COFF target which do not align
3140 to 16 byte boundaries. We implement that by adding a couple of new
3141 target vectors. These are just like the ones above, but they
3142 change the default section alignment. To generate them in the
3143 assembler, use -small. To use them in the linker, use -b
3144 coff-sh{l}-small and -oformat coff-sh{l}-small.
3145
3146 Yes, this is a horrible hack. A general solution for setting
3147 section alignment in COFF is rather complex. ELF handles this
3148 correctly. */
3149
3150/* Only recognize the small versions if the target was not defaulted.
3151 Otherwise we won't recognize the non default endianness. */
3152
3153static const bfd_target *
3154coff_small_object_p (abfd)
3155 bfd *abfd;
3156{
3157 if (abfd->target_defaulted)
3158 {
3159 bfd_set_error (bfd_error_wrong_format);
3160 return NULL;
3161 }
3162 return coff_object_p (abfd);
3163}
3164
3165/* Set the section alignment for the small versions. */
3166
3167static boolean
3168coff_small_new_section_hook (abfd, section)
3169 bfd *abfd;
3170 asection *section;
3171{
3172 if (! coff_new_section_hook (abfd, section))
3173 return false;
3174
3175 /* We must align to at least a four byte boundary, because longword
3176 accesses must be on a four byte boundary. */
3177 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3178 section->alignment_power = 2;
3179
3180 return true;
3181}
3182
3183/* This is copied from bfd_coff_std_swap_table so that we can change
3184 the default section alignment power. */
3185
3186static const bfd_coff_backend_data bfd_coff_small_swap_table =
3187{
3188 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3189 coff_swap_aux_out, coff_swap_sym_out,
3190 coff_swap_lineno_out, coff_swap_reloc_out,
3191 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3192 coff_swap_scnhdr_out,
3193 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
3194#ifdef COFF_LONG_FILENAMES
3195 true,
3196#else
3197 false,
3198#endif
3199#ifdef COFF_LONG_SECTION_NAMES
3200 true,
3201#else
3202 false,
3203#endif
3204 2,
3205#ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
3206 true,
3207#else
3208 false,
3209#endif
3210#ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3211 4,
3212#else
3213 2,
3214#endif
3215 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3216 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3217 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3218 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3219 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
3220 coff_classify_symbol, coff_compute_section_file_positions,
3221 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3222 coff_adjust_symndx, coff_link_add_one_symbol,
3223 coff_link_output_has_begun, coff_final_link_postscript
3224};
3225
3226#define coff_small_close_and_cleanup \
3227 coff_close_and_cleanup
3228#define coff_small_bfd_free_cached_info \
3229 coff_bfd_free_cached_info
3230#define coff_small_get_section_contents \
3231 coff_get_section_contents
3232#define coff_small_get_section_contents_in_window \
3233 coff_get_section_contents_in_window
3234
3235extern const bfd_target shlcoff_small_vec;
3236
3237const bfd_target shcoff_small_vec =
3238{
3239 "coff-sh-small", /* name */
3240 bfd_target_coff_flavour,
3241 BFD_ENDIAN_BIG, /* data byte order is big */
3242 BFD_ENDIAN_BIG, /* header byte order is big */
3243
3244 (HAS_RELOC | EXEC_P | /* object flags */
3245 HAS_LINENO | HAS_DEBUG |
3246 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3247
3248 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3249 '_', /* leading symbol underscore */
3250 '/', /* ar_pad_char */
3251 15, /* ar_max_namelen */
3252 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3253 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3254 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3255 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3256 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3257 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3258
3259 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3260 bfd_generic_archive_p, _bfd_dummy_target},
3261 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3262 bfd_false},
3263 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3264 _bfd_write_archive_contents, bfd_false},
3265
3266 BFD_JUMP_TABLE_GENERIC (coff_small),
3267 BFD_JUMP_TABLE_COPY (coff),
3268 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3269 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3270 BFD_JUMP_TABLE_SYMBOLS (coff),
3271 BFD_JUMP_TABLE_RELOCS (coff),
3272 BFD_JUMP_TABLE_WRITE (coff),
3273 BFD_JUMP_TABLE_LINK (coff),
3274 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3275
3276 & shlcoff_small_vec,
3277
3278 (PTR) &bfd_coff_small_swap_table
3279};
3280
3281const bfd_target shlcoff_small_vec =
3282{
3283 "coff-shl-small", /* name */
3284 bfd_target_coff_flavour,
3285 BFD_ENDIAN_LITTLE, /* data byte order is little */
3286 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3287
3288 (HAS_RELOC | EXEC_P | /* object flags */
3289 HAS_LINENO | HAS_DEBUG |
3290 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3291
3292 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3293 '_', /* leading symbol underscore */
3294 '/', /* ar_pad_char */
3295 15, /* ar_max_namelen */
3296 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3297 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3298 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3299 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3300 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3301 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3302
3303 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
3304 bfd_generic_archive_p, _bfd_dummy_target},
3305 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
3306 bfd_false},
3307 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
3308 _bfd_write_archive_contents, bfd_false},
3309
3310 BFD_JUMP_TABLE_GENERIC (coff_small),
3311 BFD_JUMP_TABLE_COPY (coff),
3312 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3313 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3314 BFD_JUMP_TABLE_SYMBOLS (coff),
3315 BFD_JUMP_TABLE_RELOCS (coff),
3316 BFD_JUMP_TABLE_WRITE (coff),
3317 BFD_JUMP_TABLE_LINK (coff),
3318 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3319
3320 & shcoff_small_vec,
3321
3322 (PTR) &bfd_coff_small_swap_table
3323};
3324#endif
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