| 1 | // locks.h - Thread synchronization primitives. X86 implementation.
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| 2 |
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| 3 | /* Copyright (C) 2002 Free Software Foundation
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| 4 |
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| 5 | This file is part of libgcj.
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| 6 |
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| 7 | This software is copyrighted work licensed under the terms of the
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| 8 | Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
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| 9 | details. */
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| 10 |
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| 11 | #ifndef __SYSDEP_LOCKS_H__
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| 12 | #define __SYSDEP_LOCKS_H__
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| 13 |
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| 14 | typedef size_t obj_addr_t; /* Integer type big enough for object */
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| 15 | /* address. */
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| 16 |
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| 17 | // Atomically replace *addr by new_val if it was initially equal to old.
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| 18 | // Return true if the comparison succeeded.
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| 19 | // Assumed to have acquire semantics, i.e. later memory operations
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| 20 | // cannot execute before the compare_and_swap finishes.
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| 21 | inline static bool
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| 22 | compare_and_swap(volatile obj_addr_t *addr,
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| 23 | obj_addr_t old,
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| 24 | obj_addr_t new_val)
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| 25 | {
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| 26 | char result;
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| 27 | __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
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| 28 | : "+m"(*(addr)), "=q"(result)
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| 29 | : "r" (new_val), "a"(old)
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| 30 | : "memory");
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| 31 | return (bool) result;
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| 32 | }
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| 33 |
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| 34 | // Set *addr to new_val with release semantics, i.e. making sure
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| 35 | // that prior loads and stores complete before this
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| 36 | // assignment.
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| 37 | // On X86, the hardware shouldn't reorder reads and writes,
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| 38 | // so we just have to convince gcc not to do it either.
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| 39 | inline static void
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| 40 | release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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| 41 | {
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| 42 | __asm__ __volatile__(" " : : : "memory");
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| 43 | *(addr) = new_val;
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| 44 | }
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| 45 |
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| 46 | // Compare_and_swap with release semantics instead of acquire semantics.
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| 47 | // On many architecture, the operation makes both guarantees, so the
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| 48 | // implementation can be the same.
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| 49 | inline static bool
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| 50 | compare_and_swap_release(volatile obj_addr_t *addr,
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| 51 | obj_addr_t old,
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| 52 | obj_addr_t new_val)
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| 53 | {
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| 54 | return compare_and_swap(addr, old, new_val);
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| 55 | }
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| 56 |
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| 57 | // Ensure that subsequent instructions do not execute on stale
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| 58 | // data that was loaded from memory before the barrier.
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| 59 | // On X86, the hardware ensures that reads are properly ordered.
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| 60 | inline static void
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| 61 | read_barrier()
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| 62 | {
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| 63 | }
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| 64 |
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| 65 | // Ensure that prior stores to memory are completed with respect to other
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| 66 | // processors.
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| 67 | inline static void
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| 68 | write_barrier()
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| 69 | {
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| 70 | // X86 does not reorder writes. We just need to ensure that gcc also doesn't.
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| 71 | __asm__ __volatile__(" " : : : "memory");
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| 72 | }
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| 73 | #endif
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