source: trunk/binutils/opcodes/tic4x-dis.c@ 3418

Last change on this file since 3418 was 607, checked in by bird, 22 years ago

Initial revision
  • Property cvs2svn:cvs-rev set to 1.1
  • Property svn:eol-style set to native
  • Property svn:executable set to *
File size: 20.6 KB
Line 
1/* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
2
3 Copyright 2002, 2003 Free Software Foundation, Inc.
4
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#include <math.h>
22#include "libiberty.h"
23#include "dis-asm.h"
24#include "opcode/tic4x.h"
25
26#define TIC4X_DEBUG 0
27
28#define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
29#define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
30
31typedef enum
32 {
33 IMMED_SINT,
34 IMMED_SUINT,
35 IMMED_SFLOAT,
36 IMMED_INT,
37 IMMED_UINT,
38 IMMED_FLOAT
39 }
40immed_t;
41
42typedef enum
43 {
44 INDIRECT_SHORT,
45 INDIRECT_LONG,
46 INDIRECT_TIC4X
47 }
48indirect_t;
49
50static int tic4x_version = 0;
51static int tic4x_dp = 0;
52
53static int tic4x_pc_offset
54 PARAMS ((unsigned int));
55static int tic4x_print_char
56 PARAMS ((struct disassemble_info *, char));
57static int tic4x_print_str
58 PARAMS ((struct disassemble_info *, char *));
59static int tic4x_print_register
60 PARAMS ((struct disassemble_info *, unsigned long));
61static int tic4x_print_addr
62 PARAMS ((struct disassemble_info *, unsigned long));
63static int tic4x_print_relative
64 PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
65void tic4x_print_ftoa
66 PARAMS ((unsigned int, FILE *, fprintf_ftype));
67static int tic4x_print_direct
68 PARAMS ((struct disassemble_info *, unsigned long));
69static int tic4x_print_immed
70 PARAMS ((struct disassemble_info *, immed_t, unsigned long));
71static int tic4x_print_cond
72 PARAMS ((struct disassemble_info *, unsigned int));
73static int tic4x_print_indirect
74 PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
75static int tic4x_print_op
76 PARAMS ((struct disassemble_info *, unsigned long, tic4x_inst_t *, unsigned long));
77static void tic4x_hash_opcode_special
78 PARAMS ((tic4x_inst_t **, const tic4x_inst_t *));
79static void tic4x_hash_opcode
80 PARAMS ((tic4x_inst_t **, tic4x_inst_t **, const tic4x_inst_t *, unsigned long));
81static int tic4x_disassemble
82 PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
83int print_insn_tic4x
84 PARAMS ((bfd_vma, struct disassemble_info *));
85
86
87static int
88tic4x_pc_offset (op)
89 unsigned int op;
90{
91 /* Determine the PC offset for a C[34]x instruction.
92 This could be simplified using some boolean algebra
93 but at the expense of readability. */
94 switch (op >> 24)
95 {
96 case 0x60: /* br */
97 case 0x62: /* call (C4x) */
98 case 0x64: /* rptb (C4x) */
99 return 1;
100 case 0x61: /* brd */
101 case 0x63: /* laj */
102 case 0x65: /* rptbd (C4x) */
103 return 3;
104 case 0x66: /* swi */
105 case 0x67:
106 return 0;
107 default:
108 break;
109 }
110
111 switch ((op & 0xffe00000) >> 20)
112 {
113 case 0x6a0: /* bB */
114 case 0x720: /* callB */
115 case 0x740: /* trapB */
116 return 1;
117
118 case 0x6a2: /* bBd */
119 case 0x6a6: /* bBat */
120 case 0x6aa: /* bBaf */
121 case 0x722: /* lajB */
122 case 0x748: /* latB */
123 case 0x798: /* rptbd */
124 return 3;
125
126 default:
127 break;
128 }
129
130 switch ((op & 0xfe200000) >> 20)
131 {
132 case 0x6e0: /* dbB */
133 return 1;
134
135 case 0x6e2: /* dbBd */
136 return 3;
137
138 default:
139 break;
140 }
141
142 return 0;
143}
144
145static int
146tic4x_print_char (info, ch)
147 struct disassemble_info * info;
148 char ch;
149{
150 if (info != NULL)
151 (*info->fprintf_func) (info->stream, "%c", ch);
152 return 1;
153}
154
155static int
156tic4x_print_str (info, str)
157 struct disassemble_info *info;
158 char *str;
159{
160 if (info != NULL)
161 (*info->fprintf_func) (info->stream, "%s", str);
162 return 1;
163}
164
165static int
166tic4x_print_register (info, regno)
167 struct disassemble_info *info;
168 unsigned long regno;
169{
170 static tic4x_register_t **registertable = NULL;
171 unsigned int i;
172
173 if (registertable == NULL)
174 {
175 registertable = (tic4x_register_t **)
176 xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE);
177 for (i = 0; i < tic3x_num_registers; i++)
178 registertable[tic3x_registers[i].regno] = (void *)&tic3x_registers[i];
179 if (IS_CPU_TIC4X (tic4x_version))
180 {
181 /* Add C4x additional registers, overwriting
182 any C3x registers if necessary. */
183 for (i = 0; i < tic4x_num_registers; i++)
184 registertable[tic4x_registers[i].regno] = (void *)&tic4x_registers[i];
185 }
186 }
187 if ((int) regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX))
188 return 0;
189 if (info != NULL)
190 (*info->fprintf_func) (info->stream, "%s", registertable[regno]->name);
191 return 1;
192}
193
194static int
195tic4x_print_addr (info, addr)
196 struct disassemble_info *info;
197 unsigned long addr;
198{
199 if (info != NULL)
200 (*info->print_address_func)(addr, info);
201 return 1;
202}
203
204static int
205tic4x_print_relative (info, pc, offset, opcode)
206 struct disassemble_info *info;
207 unsigned long pc;
208 long offset;
209 unsigned long opcode;
210{
211 return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
212}
213
214static int
215tic4x_print_direct (info, arg)
216 struct disassemble_info *info;
217 unsigned long arg;
218{
219 if (info != NULL)
220 {
221 (*info->fprintf_func) (info->stream, "@");
222 tic4x_print_addr (info, arg + (tic4x_dp << 16));
223 }
224 return 1;
225}
226
227/* FIXME: make the floating point stuff not rely on host
228 floating point arithmetic. */
229void
230tic4x_print_ftoa (val, stream, pfunc)
231 unsigned int val;
232 FILE *stream;
233 fprintf_ftype pfunc;
234{
235 int e;
236 int s;
237 int f;
238 double num = 0.0;
239
240 e = EXTRS (val, 31, 24); /* exponent */
241 if (e != -128)
242 {
243 s = EXTRU (val, 23, 23); /* sign bit */
244 f = EXTRU (val, 22, 0); /* mantissa */
245 if (s)
246 f += -2 * (1 << 23);
247 else
248 f += (1 << 23);
249 num = f / (double)(1 << 23);
250 num = ldexp (num, e);
251 }
252 (*pfunc)(stream, "%.9g", num);
253}
254
255static int
256tic4x_print_immed (info, type, arg)
257 struct disassemble_info *info;
258 immed_t type;
259 unsigned long arg;
260{
261 int s;
262 int f;
263 int e;
264 double num = 0.0;
265
266 if (info == NULL)
267 return 1;
268 switch (type)
269 {
270 case IMMED_SINT:
271 case IMMED_INT:
272 (*info->fprintf_func) (info->stream, "%d", (long)arg);
273 break;
274
275 case IMMED_SUINT:
276 case IMMED_UINT:
277 (*info->fprintf_func) (info->stream, "%u", arg);
278 break;
279
280 case IMMED_SFLOAT:
281 e = EXTRS (arg, 15, 12);
282 if (e != -8)
283 {
284 s = EXTRU (arg, 11, 11);
285 f = EXTRU (arg, 10, 0);
286 if (s)
287 f += -2 * (1 << 11);
288 else
289 f += (1 << 11);
290 num = f / (double)(1 << 11);
291 num = ldexp (num, e);
292 }
293 (*info->fprintf_func) (info->stream, "%f", num);
294 break;
295 case IMMED_FLOAT:
296 e = EXTRS (arg, 31, 24);
297 if (e != -128)
298 {
299 s = EXTRU (arg, 23, 23);
300 f = EXTRU (arg, 22, 0);
301 if (s)
302 f += -2 * (1 << 23);
303 else
304 f += (1 << 23);
305 num = f / (double)(1 << 23);
306 num = ldexp (num, e);
307 }
308 (*info->fprintf_func) (info->stream, "%f", num);
309 break;
310 }
311 return 1;
312}
313
314static int
315tic4x_print_cond (info, cond)
316 struct disassemble_info *info;
317 unsigned int cond;
318{
319 static tic4x_cond_t **condtable = NULL;
320 unsigned int i;
321
322 if (condtable == NULL)
323 {
324 condtable = (tic4x_cond_t **)xmalloc (sizeof (tic4x_cond_t *) * 32);
325 for (i = 0; i < tic4x_num_conds; i++)
326 condtable[tic4x_conds[i].cond] = (void *)&tic4x_conds[i];
327 }
328 if (cond > 31 || condtable[cond] == NULL)
329 return 0;
330 if (info != NULL)
331 (*info->fprintf_func) (info->stream, "%s", condtable[cond]->name);
332 return 1;
333}
334
335static int
336tic4x_print_indirect (info, type, arg)
337 struct disassemble_info *info;
338 indirect_t type;
339 unsigned long arg;
340{
341 unsigned int aregno;
342 unsigned int modn;
343 unsigned int disp;
344 char *a;
345
346 aregno = 0;
347 modn = 0;
348 disp = 1;
349 switch(type)
350 {
351 case INDIRECT_TIC4X: /* *+ARn(disp) */
352 disp = EXTRU (arg, 7, 3);
353 aregno = EXTRU (arg, 2, 0) + REG_AR0;
354 modn = 0;
355 break;
356 case INDIRECT_SHORT:
357 disp = 1;
358 aregno = EXTRU (arg, 2, 0) + REG_AR0;
359 modn = EXTRU (arg, 7, 3);
360 break;
361 case INDIRECT_LONG:
362 disp = EXTRU (arg, 7, 0);
363 aregno = EXTRU (arg, 10, 8) + REG_AR0;
364 modn = EXTRU (arg, 15, 11);
365 if (modn > 7 && disp != 0)
366 return 0;
367 break;
368 default:
369 (*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type);
370 return 0;
371 }
372 if (modn > TIC3X_MODN_MAX)
373 return 0;
374 a = tic4x_indirects[modn].name;
375 while (*a)
376 {
377 switch (*a)
378 {
379 case 'a':
380 tic4x_print_register (info, aregno);
381 break;
382 case 'd':
383 tic4x_print_immed (info, IMMED_UINT, disp);
384 break;
385 case 'y':
386 tic4x_print_str (info, "ir0");
387 break;
388 case 'z':
389 tic4x_print_str (info, "ir1");
390 break;
391 default:
392 tic4x_print_char (info, *a);
393 break;
394 }
395 a++;
396 }
397 return 1;
398}
399
400static int
401tic4x_print_op (info, instruction, p, pc)
402 struct disassemble_info *info;
403 unsigned long instruction;
404 tic4x_inst_t *p;
405 unsigned long pc;
406{
407 int val;
408 char *s;
409 char *parallel = NULL;
410
411 /* Print instruction name. */
412 s = p->name;
413 while (*s && parallel == NULL)
414 {
415 switch (*s)
416 {
417 case 'B':
418 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
419 return 0;
420 break;
421 case 'C':
422 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
423 return 0;
424 break;
425 case '_':
426 parallel = s + 1; /* Skip past `_' in name */
427 break;
428 default:
429 tic4x_print_char (info, *s);
430 break;
431 }
432 s++;
433 }
434
435 /* Print arguments. */
436 s = p->args;
437 if (*s)
438 tic4x_print_char (info, ' ');
439
440 while (*s)
441 {
442 switch (*s)
443 {
444 case '*': /* indirect 0--15 */
445 if (! tic4x_print_indirect (info, INDIRECT_LONG,
446 EXTRU (instruction, 15, 0)))
447 return 0;
448 break;
449
450 case '#': /* only used for ldp, ldpk */
451 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
452 break;
453
454 case '@': /* direct 0--15 */
455 tic4x_print_direct (info, EXTRU (instruction, 15, 0));
456 break;
457
458 case 'A': /* address register 24--22 */
459 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
460 REG_AR0))
461 return 0;
462 break;
463
464 case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
465 address 0--23. */
466 if (IS_CPU_TIC4X (tic4x_version))
467 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
468 p->opcode);
469 else
470 tic4x_print_addr (info, EXTRU (instruction, 23, 0));
471 break;
472
473 case 'C': /* indirect (short C4x) 0--7 */
474 if (! IS_CPU_TIC4X (tic4x_version))
475 return 0;
476 if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
477 EXTRU (instruction, 7, 0)))
478 return 0;
479 break;
480
481 case 'D':
482 /* Cockup if get here... */
483 break;
484
485 case 'E': /* register 0--7 */
486 case 'e':
487 if (! tic4x_print_register (info, EXTRU (instruction, 7, 0)))
488 return 0;
489 break;
490
491 case 'F': /* 16-bit float immediate 0--15 */
492 tic4x_print_immed (info, IMMED_SFLOAT,
493 EXTRU (instruction, 15, 0));
494 break;
495
496 case 'i': /* Extended indirect 0--7 */
497 if ( EXTRU (instruction, 7, 5) == 7 )
498 {
499 if( !tic4x_print_register (info, EXTRU (instruction, 4, 0)) )
500 return 0;
501 break;
502 }
503 /* Fallthrough */
504
505 case 'I': /* indirect (short) 0--7 */
506 if (! tic4x_print_indirect (info, INDIRECT_SHORT,
507 EXTRU (instruction, 7, 0)))
508 return 0;
509 break;
510
511 case 'j': /* Extended indirect 8--15 */
512 if ( EXTRU (instruction, 15, 13) == 7 )
513 {
514 if( !tic4x_print_register (info, EXTRU (instruction, 12, 8)) )
515 return 0;
516 break;
517 }
518
519 case 'J': /* indirect (short) 8--15 */
520 if (! tic4x_print_indirect (info, INDIRECT_SHORT,
521 EXTRU (instruction, 15, 8)))
522 return 0;
523 break;
524
525 case 'G': /* register 8--15 */
526 case 'g':
527 if (! tic4x_print_register (info, EXTRU (instruction, 15, 8)))
528 return 0;
529 break;
530
531 case 'H': /* register 16--18 */
532 if (! tic4x_print_register (info, EXTRU (instruction, 18, 16)))
533 return 0;
534 break;
535
536 case 'K': /* register 19--21 */
537 if (! tic4x_print_register (info, EXTRU (instruction, 21, 19)))
538 return 0;
539 break;
540
541 case 'L': /* register 22--24 */
542 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22)))
543 return 0;
544 break;
545
546 case 'M': /* register 22--22 */
547 tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
548 break;
549
550 case 'N': /* register 23--23 */
551 tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
552 break;
553
554 case 'O': /* indirect (short C4x) 8--15 */
555 if (! IS_CPU_TIC4X (tic4x_version))
556 return 0;
557 if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
558 EXTRU (instruction, 15, 8)))
559 return 0;
560 break;
561
562 case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
563 tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
564 p->opcode);
565 break;
566
567 case 'Q': /* register 0--15 */
568 case 'q':
569 if (! tic4x_print_register (info, EXTRU (instruction, 15, 0)))
570 return 0;
571 break;
572
573 case 'R': /* register 16--20 */
574 case 'r':
575 if (! tic4x_print_register (info, EXTRU (instruction, 20, 16)))
576 return 0;
577 break;
578
579 case 'S': /* 16-bit signed immediate 0--15 */
580 tic4x_print_immed (info, IMMED_SINT,
581 EXTRS (instruction, 15, 0));
582 break;
583
584 case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */
585 if (! IS_CPU_TIC4X (tic4x_version))
586 return 0;
587 if (! tic4x_print_immed (info, IMMED_SUINT,
588 EXTRU (instruction, 20, 16)))
589 return 0;
590 break;
591
592 case 'U': /* 16-bit unsigned int immediate 0--15 */
593 tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
594 break;
595
596 case 'V': /* 5/9-bit unsigned vector 0--4/8 */
597 tic4x_print_immed (info, IMMED_SUINT,
598 IS_CPU_TIC4X (tic4x_version) ?
599 EXTRU (instruction, 8, 0) :
600 EXTRU (instruction, 4, 0) & ~0x20);
601 break;
602
603 case 'W': /* 8-bit signed immediate 0--7 */
604 if (! IS_CPU_TIC4X (tic4x_version))
605 return 0;
606 tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
607 break;
608
609 case 'X': /* expansion register 4--0 */
610 val = EXTRU (instruction, 4, 0) + REG_IVTP;
611 if (val < REG_IVTP || val > REG_TVTP)
612 return 0;
613 if (! tic4x_print_register (info, val))
614 return 0;
615 break;
616
617 case 'Y': /* address register 16--20 */
618 val = EXTRU (instruction, 20, 16);
619 if (val < REG_AR0 || val > REG_SP)
620 return 0;
621 if (! tic4x_print_register (info, val))
622 return 0;
623 break;
624
625 case 'Z': /* expansion register 16--20 */
626 val = EXTRU (instruction, 20, 16) + REG_IVTP;
627 if (val < REG_IVTP || val > REG_TVTP)
628 return 0;
629 if (! tic4x_print_register (info, val))
630 return 0;
631 break;
632
633 case '|': /* Parallel instruction */
634 tic4x_print_str (info, " || ");
635 tic4x_print_str (info, parallel);
636 tic4x_print_char (info, ' ');
637 break;
638
639 case ';':
640 tic4x_print_char (info, ',');
641 break;
642
643 default:
644 tic4x_print_char (info, *s);
645 break;
646 }
647 s++;
648 }
649 return 1;
650}
651
652static void
653tic4x_hash_opcode_special (optable_special, inst)
654 tic4x_inst_t **optable_special;
655 const tic4x_inst_t *inst;
656{
657 int i;
658
659 for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
660 if( optable_special[i] != NULL
661 && optable_special[i]->opcode == inst->opcode )
662 {
663 /* Collision (we have it already) - overwrite */
664 optable_special[i] = (void *)inst;
665 return;
666 }
667
668 for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
669 if( optable_special[i] == NULL )
670 {
671 /* Add the new opcode */
672 optable_special[i] = (void *)inst;
673 return;
674 }
675
676 /* This should never occur. This happens if the number of special
677 instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
678 of this variable */
679#if TIC4X_DEBUG
680 printf("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
681#endif
682}
683
684static void
685tic4x_hash_opcode (optable, optable_special, inst, tic4x_oplevel)
686 tic4x_inst_t **optable;
687 tic4x_inst_t **optable_special;
688 const tic4x_inst_t *inst;
689 const unsigned long tic4x_oplevel;
690{
691 int j;
692 int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE);
693 int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE);
694
695 /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should
696 have unique entries so there's no point having a linked list
697 for each entry? */
698 for (j = opcode; j < opmask; j++)
699 if ( (j & opmask) == opcode
700 && inst->oplevel & tic4x_oplevel )
701 {
702#if TIC4X_DEBUG
703 /* We should only have collisions for synonyms like
704 ldp for ldi. */
705 if (optable[j] != NULL)
706 printf("Collision at index %d, %s and %s\n",
707 j, optable[j]->name, inst->name);
708#endif
709 /* Catch those ops that collide with others already inside the
710 hash, and have a opmask greater than the one we use in the
711 hash. Store them in a special-list, that will handle full
712 32-bit INSN, not only the first 11-bit (or so). */
713 if ( optable[j] != NULL
714 && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)) )
715 {
716 /* Add the instruction already on the list */
717 tic4x_hash_opcode_special(optable_special, optable[j]);
718
719 /* Add the new instruction */
720 tic4x_hash_opcode_special(optable_special, inst);
721 }
722
723 optable[j] = (void *)inst;
724 }
725}
726
727/* Disassemble the instruction in 'instruction'.
728 'pc' should be the address of this instruction, it will
729 be used to print the target address if this is a relative jump or call
730 the disassembled instruction is written to 'info'.
731 The function returns the length of this instruction in words. */
732
733static int
734tic4x_disassemble (pc, instruction, info)
735 unsigned long pc;
736 unsigned long instruction;
737 struct disassemble_info *info;
738{
739 static tic4x_inst_t **optable = NULL;
740 static tic4x_inst_t **optable_special = NULL;
741 tic4x_inst_t *p;
742 int i;
743 unsigned long tic4x_oplevel;
744
745 tic4x_version = info->mach;
746
747 tic4x_oplevel = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0;
748 tic4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
749
750 if (optable == NULL)
751 {
752 optable = (tic4x_inst_t **)
753 xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
754
755 optable_special = (tic4x_inst_t **)
756 xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE );
757
758 /* Install opcodes in reverse order so that preferred
759 forms overwrite synonyms. */
760 for (i = tic4x_num_insts - 1; i >= 0; i--)
761 tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], tic4x_oplevel);
762
763 /* We now need to remove the insn that are special from the
764 "normal" optable, to make the disasm search this extra list
765 for them.
766 */
767 for (i=0; i<TIC4X_SPESOP_SIZE; i++)
768 if ( optable_special[i] != NULL )
769 optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL;
770 }
771
772 /* See if we can pick up any loading of the DP register... */
773 if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
774 tic4x_dp = EXTRU (instruction, 15, 0);
775
776 p = optable[instruction >> (32 - TIC4X_HASH_SIZE)];
777 if ( p != NULL )
778 {
779 if ( ((instruction & p->opmask) == p->opcode)
780 && tic4x_print_op (NULL, instruction, p, pc) )
781 tic4x_print_op (info, instruction, p, pc);
782 else
783 (*info->fprintf_func) (info->stream, "%08x", instruction);
784 }
785 else
786 {
787 for (i = 0; i<TIC4X_SPESOP_SIZE; i++)
788 if (optable_special[i] != NULL
789 && optable_special[i]->opcode == instruction )
790 {
791 (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
792 break;
793 }
794 if (i==TIC4X_SPESOP_SIZE)
795 (*info->fprintf_func) (info->stream, "%08x", instruction);
796 }
797
798 /* Return size of insn in words. */
799 return 1;
800}
801
802/* The entry point from objdump and gdb. */
803int
804print_insn_tic4x (memaddr, info)
805 bfd_vma memaddr;
806 struct disassemble_info *info;
807{
808 int status;
809 unsigned long pc;
810 unsigned long op;
811 bfd_byte buffer[4];
812
813 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
814 if (status != 0)
815 {
816 (*info->memory_error_func) (status, memaddr, info);
817 return -1;
818 }
819
820 pc = memaddr;
821 op = bfd_getl32 (buffer);
822 info->bytes_per_line = 4;
823 info->bytes_per_chunk = 4;
824 info->octets_per_byte = 4;
825 info->display_endian = BFD_ENDIAN_LITTLE;
826 return tic4x_disassemble (pc, op, info) * 4;
827}
Note: See TracBrowser for help on using the repository browser.