| 1 | /* s390-opc.c -- S390 opcode list
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| 2 | Copyright 2000, 2001 Free Software Foundation, Inc.
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| 3 | Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
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| 4 |
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| 5 | This file is part of GDB, GAS, and the GNU binutils.
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| 6 |
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| 7 | This program is free software; you can redistribute it and/or modify
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| 8 | it under the terms of the GNU General Public License as published by
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| 9 | the Free Software Foundation; either version 2 of the License, or
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| 10 | (at your option) any later version.
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| 11 |
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| 12 | This program is distributed in the hope that it will be useful,
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| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 15 | GNU General Public License for more details.
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| 16 |
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| 17 | You should have received a copy of the GNU General Public License
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| 18 | along with this program; if not, write to the Free Software
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| 19 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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| 20 | 02111-1307, USA. */
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| 21 |
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| 22 | #include <stdio.h>
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| 23 | #include "ansidecl.h"
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| 24 | #include "opcode/s390.h"
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| 25 |
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| 26 | /* This file holds the S390 opcode table. The opcode table
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| 27 | includes almost all of the extended instruction mnemonics. This
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| 28 | permits the disassembler to use them, and simplifies the assembler
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| 29 | logic, at the cost of increasing the table size. The table is
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| 30 | strictly constant data, so the compiler should be able to put it in
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| 31 | the .text section.
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| 32 |
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| 33 | This file also holds the operand table. All knowledge about
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| 34 | inserting operands into instructions and vice-versa is kept in this
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| 35 | file. */
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| 36 |
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| 37 | /* The operands table.
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| 38 | The fields are bits, shift, insert, extract, flags. */
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| 39 |
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| 40 | const struct s390_operand s390_operands[] =
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| 41 | {
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| 42 | #define UNUSED 0
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| 43 | { 0, 0, 0 }, /* Indicates the end of the operand list */
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| 44 |
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| 45 | #define R_8 1 /* GPR starting at position 8 */
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| 46 | { 4, 8, S390_OPERAND_GPR },
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| 47 | #define R_12 2 /* GPR starting at position 12 */
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| 48 | { 4, 12, S390_OPERAND_GPR },
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| 49 | #define R_16 3 /* GPR starting at position 16 */
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| 50 | { 4, 16, S390_OPERAND_GPR },
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| 51 | #define R_20 4 /* GPR starting at position 20 */
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| 52 | { 4, 20, S390_OPERAND_GPR },
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| 53 | #define R_24 5 /* GPR starting at position 24 */
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| 54 | { 4, 24, S390_OPERAND_GPR },
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| 55 | #define R_28 6 /* GPR starting at position 28 */
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| 56 | { 4, 28, S390_OPERAND_GPR },
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| 57 | #define R_32 7 /* GPR starting at position 32 */
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| 58 | { 4, 32, S390_OPERAND_GPR },
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| 59 |
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| 60 | #define F_8 8 /* FPR starting at position 8 */
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| 61 | { 4, 8, S390_OPERAND_FPR },
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| 62 | #define F_12 9 /* FPR starting at position 12 */
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| 63 | { 4, 12, S390_OPERAND_FPR },
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| 64 | #define F_16 10 /* FPR starting at position 16 */
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| 65 | { 4, 16, S390_OPERAND_FPR },
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| 66 | #define F_20 11 /* FPR starting at position 16 */
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| 67 | { 4, 16, S390_OPERAND_FPR },
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| 68 | #define F_24 12 /* FPR starting at position 24 */
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| 69 | { 4, 24, S390_OPERAND_FPR },
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| 70 | #define F_28 13 /* FPR starting at position 28 */
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| 71 | { 4, 28, S390_OPERAND_FPR },
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| 72 | #define F_32 14 /* FPR starting at position 32 */
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| 73 | { 4, 32, S390_OPERAND_FPR },
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| 74 |
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| 75 | #define A_8 15 /* Access reg. starting at position 8 */
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| 76 | { 4, 8, S390_OPERAND_AR },
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| 77 | #define A_12 16 /* Access reg. starting at position 12 */
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| 78 | { 4, 12, S390_OPERAND_AR },
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| 79 | #define A_24 17 /* Access reg. starting at position 24 */
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| 80 | { 4, 24, S390_OPERAND_AR },
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| 81 | #define A_28 18 /* Access reg. starting at position 28 */
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| 82 | { 4, 28, S390_OPERAND_AR },
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| 83 |
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| 84 | #define C_8 19 /* Control reg. starting at position 8 */
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| 85 | { 4, 8, S390_OPERAND_CR },
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| 86 | #define C_12 20 /* Control reg. starting at position 12 */
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| 87 | { 4, 12, S390_OPERAND_CR },
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| 88 |
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| 89 | #define B_16 21 /* Base register starting at position 16 */
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| 90 | { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
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| 91 | #define B_32 22 /* Base register starting at position 32 */
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| 92 | { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
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| 93 |
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| 94 | #define X_12 23 /* Index register starting at position 12 */
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| 95 | { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
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| 96 |
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| 97 | #define D_20 24 /* Displacement starting at position 20 */
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| 98 | { 12, 20, S390_OPERAND_DISP },
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| 99 | #define D_36 25 /* Displacement starting at position 36 */
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| 100 | { 12, 36, S390_OPERAND_DISP },
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| 101 |
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| 102 | #define L4_8 26 /* 4 bit length starting at position 8 */
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| 103 | { 4, 8, S390_OPERAND_LENGTH },
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| 104 | #define L4_12 27 /* 4 bit length starting at position 12 */
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| 105 | { 4, 12, S390_OPERAND_LENGTH },
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| 106 | #define L8_8 28 /* 8 bit length starting at position 8 */
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| 107 | { 8, 8, S390_OPERAND_LENGTH },
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| 108 |
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| 109 | #define U4_8 29 /* 4 bit unsigned value starting at 8 */
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| 110 | { 4, 8, 0 },
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| 111 | #define U4_12 30 /* 4 bit unsigned value starting at 12 */
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| 112 | { 4, 12, 0 },
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| 113 | #define U4_16 31 /* 4 bit unsigned value starting at 16 */
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| 114 | { 4, 16, 0 },
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| 115 | #define U4_20 32 /* 4 bit unsigned value starting at 20 */
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| 116 | { 4, 20, 0 },
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| 117 | #define U8_8 33 /* 8 bit unsigned value starting at 8 */
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| 118 | { 8, 8, 0 },
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| 119 | #define U8_16 34 /* 8 bit unsigned value starting at 16 */
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| 120 | { 8, 16, 0 },
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| 121 | #define I16_16 35 /* 16 bit signed value starting at 16 */
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| 122 | { 16, 16, S390_OPERAND_SIGNED },
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| 123 | #define U16_16 36 /* 16 bit unsigned value starting at 16 */
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| 124 | { 16, 16, 0 },
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| 125 | #define J16_16 37 /* PC relative jump offset at 16 */
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| 126 | { 16, 16, S390_OPERAND_PCREL },
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| 127 | #define J32_16 38 /* PC relative long offset at 16 */
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| 128 | { 32, 16, S390_OPERAND_PCREL }
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| 129 | };
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| 130 |
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| 131 |
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| 132 | /* Macros used to form opcodes. */
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| 133 |
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| 134 | /* 8/16/48 bit opcodes. */
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| 135 | #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 136 | #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
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| 137 | #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
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| 138 | (x >> 16) & 255, (x >> 8) & 255, x & 255}
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| 139 |
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| 140 | /* The new format of the INSTR_x_y and MASK_x_y defines is based
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| 141 | on the following rules:
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| 142 | 1) the middle part of the definition (x in INSTR_x_y) is the official
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| 143 | names of the instruction format that you can find in the principals
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| 144 | of operation.
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| 145 | 2) the last part of the definition (y in INSTR_x_y) gives you an idea
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| 146 | which operands the binary represenation of the instruction has.
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| 147 | The meanings of the letters in y are:
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| 148 | a - access register
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| 149 | c - control register
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| 150 | d - displacement, 12 bit
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| 151 | f - floating pointer register
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| 152 | i - signed integer, 4 or 8 bit
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| 153 | l - length, 4 or 8 bit
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| 154 | p - pc relative
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| 155 | r - general purpose register
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| 156 | u - unsigned integer, 4 or 8 bit
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| 157 | 0 - operand skipped.
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| 158 | The order of the letters reflects the layout of the format in
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| 159 | storage and not the order of the paramaters of the instructions.
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| 160 | The use of the letters is not a 100% match with the PoP but it is
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| 161 | quite close.
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| 162 |
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| 163 | For example the instruction "mvo" is defined in the PoP as follows:
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| 164 |
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| 165 | MVO D1(L1,B1),D2(L2,B2) [SS]
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| 166 |
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| 167 | --------------------------------------
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| 168 | | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
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| 169 | --------------------------------------
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| 170 | 0 8 12 16 20 32 36
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| 171 |
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| 172 | The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
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| 173 |
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| 174 | #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */
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| 175 | #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
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| 176 | #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
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| 177 | #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
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| 178 | #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
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| 179 | #define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */
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| 180 | #define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
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| 181 | #define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
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| 182 | #define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
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| 183 | #define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
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| 184 | #define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */
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| 185 | #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
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| 186 | #define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
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| 187 | #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
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| 188 | #define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */
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| 189 | #define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
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| 190 | #define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */
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| 191 | #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
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| 192 | #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
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| 193 | #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
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| 194 | #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
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| 195 | #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
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| 196 | #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
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| 197 | #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */
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| 198 | #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */
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| 199 | #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */
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| 200 | #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */
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| 201 | #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
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| 202 | #define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */
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| 203 | #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
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| 204 | #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
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| 205 | #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
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| 206 | #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
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| 207 | #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
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| 208 | #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
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| 209 | #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
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| 210 | #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
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| 211 | #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
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| 212 | #define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
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| 213 | #define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
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| 214 | #define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
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| 215 | #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */
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| 216 | #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */
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| 217 | #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
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| 218 | #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
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| 219 | #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
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| 220 | #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
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| 221 | #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
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| 222 | #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
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| 223 | #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
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| 224 | #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
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| 225 | #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
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| 226 | #define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
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| 227 | #define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
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| 228 | #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
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| 229 | #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
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| 230 | #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */
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| 231 | #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
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| 232 |
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| 233 | #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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| 234 | #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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| 235 | #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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| 236 | #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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| 237 | #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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| 238 | #define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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| 239 | #define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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| 240 | #define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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| 241 | #define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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| 242 | #define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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| 243 | #define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
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| 244 | #define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
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| 245 | #define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
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| 246 | #define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
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| 247 | #define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
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| 248 | #define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
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| 249 | #define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
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| 250 | #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
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| 251 | #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
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| 252 | #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
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| 253 | #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
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| 254 | #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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| 255 | #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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| 256 | #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
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| 257 | #define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
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| 258 | #define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
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| 259 | #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
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| 260 | #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 261 | #define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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| 262 | #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 263 | #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 264 | #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 265 | #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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| 266 | #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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| 267 | #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 268 | #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 269 | #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 270 | #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
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| 271 | #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 272 | #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 273 | #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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| 274 | #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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| 275 | #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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| 276 | #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
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| 277 | #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
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| 278 | #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 279 | #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 280 | #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 281 | #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 282 | #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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| 283 | #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 284 | #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 285 | #define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 286 | #define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 287 | #define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 288 | #define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
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| 289 | #define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
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| 290 | #define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
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| 291 |
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| 292 | /* The opcode formats table (blueprints for .insn pseudo mnemonic). */
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| 293 |
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| 294 | const struct s390_opcode s390_opformats[] =
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| 295 | {
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| 296 | { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 },
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| 297 | { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 },
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| 298 | { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 },
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| 299 | { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 },
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| 300 | { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 },
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| 301 | { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 },
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| 302 | { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 },
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| 303 | { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 },
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| 304 | { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 },
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| 305 | { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 },
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| 306 | { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 },
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| 307 | { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 },
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| 308 | { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
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| 309 | { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 },
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| 310 | { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 },
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| 311 | { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
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| 312 | { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 },
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| 313 | };
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| 314 |
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| 315 | const int s390_num_opformats =
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| 316 | sizeof (s390_opformats) / sizeof (s390_opformats[0]);
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| 317 |
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| 318 | #include "s390-opc.tab"
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