| 1 | /* Opcode table for PDP-11. | 
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| 2 | Copyright 2001, 2002 Free Software Foundation, Inc. | 
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| 3 |  | 
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| 4 | This file is free software; you can redistribute it and/or modify | 
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| 5 | it under the terms of the GNU General Public License as published by | 
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| 6 | the Free Software Foundation; either version 2 of the License, or | 
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| 7 | (at your option) any later version. | 
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| 8 |  | 
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| 9 | This program is distributed in the hope that it will be useful, | 
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| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | 
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| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the | 
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| 12 | GNU General Public License for more details. | 
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| 13 |  | 
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| 14 | You should have received a copy of the GNU General Public License | 
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| 15 | along with this program; if not, write to the Free Software | 
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| 16 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */ | 
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| 17 |  | 
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| 18 | #include "opcode/pdp11.h" | 
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| 19 |  | 
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| 20 | const struct pdp11_opcode pdp11_opcodes[] = | 
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| 21 | { | 
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| 22 | /* name,      pattern, mask,  opcode type,            insn type,    alias */ | 
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| 23 | { "halt",     0x0000, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 24 | { "wait",     0x0001, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 25 | { "rti",      0x0002, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 26 | { "bpt",      0x0003, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 27 | { "iot",      0x0004, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 28 | { "reset",    0x0005, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 29 | { "rtt",      0x0006, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_LEIS }, | 
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| 30 | { "mfpt",     0x0007, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_MFPT }, | 
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| 31 | { "jmp",      0x0040, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 32 | { "rts",      0x0080, 0xfff8, PDP11_OPCODE_REG,       PDP11_BASIC }, | 
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| 33 | { "",         0x0088, 0xfff8, PDP11_OPCODE_ILLEGAL,   PDP11_NONE }, | 
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| 34 | { "",         0x0090, 0xfff8, PDP11_OPCODE_ILLEGAL,   PDP11_NONE }, | 
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| 35 | { "spl",      0x0098, 0xfff8, PDP11_OPCODE_IMM3,      PDP11_SPL }, | 
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| 36 | { "nop",      0x00a0, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 37 | { "clc",      0x00a1, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 38 | { "clv",      0x00a2, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 39 | { "cl_3",     0x00a3, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 40 | { "clz",      0x00a4, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 41 | { "cl_5",     0x00a5, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 42 | { "cl_6",     0x00a6, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 43 | { "cl_7",     0x00a7, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 44 | { "cln",      0x00a8, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 45 | { "cl_9",     0x00a9, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 46 | { "cl_a",     0x00aa, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 47 | { "cl_b",     0x00ab, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 48 | { "cl_c",     0x00ac, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 49 | { "cl_d",     0x00ad, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 50 | { "cl_e",     0x00ae, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 51 | { "ccc",      0x00af, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 52 | { "se_0",     0x00b0, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 53 | { "sec",      0x00a1, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 54 | { "sev",      0x00b2, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 55 | { "se_3",     0x00b3, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 56 | { "sez",      0x00b4, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 57 | { "se_5",     0x00b5, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 58 | { "se_6",     0x00b6, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 59 | { "se_7",     0x00b7, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 60 | { "sen",      0x00b8, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 61 | { "se_9",     0x00b9, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 62 | { "se_a",     0x00ba, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 63 | { "se_b",     0x00bb, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 64 | { "se_c",     0x00bc, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 65 | { "se_d",     0x00bd, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 66 | { "se_e",     0x00be, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 67 | { "scc",      0x00bf, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_BASIC }, | 
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| 68 | { "swab",     0x00c0, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 69 | { "br",       0x0100, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 70 | { "bne",      0x0200, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 71 | { "beq",      0x0300, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 72 | { "bge",      0x0400, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 73 | { "blt",      0x0500, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 74 | { "bgt",      0x0600, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 75 | { "ble",      0x0700, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 76 | { "jsr",      0x0800, 0xfe00, PDP11_OPCODE_REG_OP,    PDP11_BASIC }, | 
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| 77 | { "clr",      0x0a00, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 78 | { "com",      0x0a40, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 79 | { "inc",      0x0a80, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 80 | { "dec",      0x0ac0, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 81 | { "neg",      0x0b00, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 82 | { "adc",      0x0b40, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 83 | { "sbc",      0x0b80, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 84 | { "tst",      0x0bc0, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 85 | { "ror",      0x0c00, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 86 | { "rol",      0x0c40, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 87 | { "asr",      0x0c80, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 88 | { "asl",      0x0cc0, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 89 | { "mark",     0x0d00, 0xffc0, PDP11_OPCODE_IMM6,      PDP11_LEIS }, | 
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| 90 | { "mfpi",     0x0d40, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 91 | { "mtpi",     0x0d80, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 92 | { "sxt",      0x0dc0, 0xffc0, PDP11_OPCODE_OP,        PDP11_LEIS }, | 
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| 93 | { "csm",      0x0e00, 0xffc0, PDP11_OPCODE_OP,        PDP11_CSM }, | 
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| 94 | { "tstset",   0x0e40, 0xffc0, PDP11_OPCODE_OP,        PDP11_MPROC }, | 
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| 95 | { "wrtlck",   0x0e80, 0xffc0, PDP11_OPCODE_OP,        PDP11_MPROC }, | 
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| 96 | /*{ "",         0x0ec0, 0xffe0, PDP11_OPCODE_ILLEGAL,   PDP11_NONE },*/ | 
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| 97 | { "mov",      0x1000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 98 | { "cmp",      0x2000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 99 | { "bit",      0x3000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 100 | { "bic",      0x4000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 101 | { "bis",      0x5000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 102 | { "add",      0x6000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 103 | { "mul",      0x7000, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, | 
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| 104 | { "div",      0x7200, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, | 
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| 105 | { "ash",      0x7400, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, | 
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| 106 | { "ashc",     0x7600, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS }, | 
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| 107 | { "xor",      0x7800, 0xfe00, PDP11_OPCODE_REG_OP,    PDP11_LEIS }, | 
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| 108 | { "fadd",     0x7a00, 0xfff8, PDP11_OPCODE_REG,       PDP11_FIS }, | 
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| 109 | { "fsub",     0x7a08, 0xfff8, PDP11_OPCODE_REG,       PDP11_FIS }, | 
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| 110 | { "fmul",     0x7a10, 0xfff8, PDP11_OPCODE_REG,       PDP11_FIS }, | 
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| 111 | { "fdiv",     0x7a18, 0xfff8, PDP11_OPCODE_REG,       PDP11_FIS }, | 
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| 112 | /*{ "",         0x7a20, 0xffe0, PDP11_OPCODE_ILLEGAL,   PDP11_NONE },*/ | 
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| 113 | /*{ "",         0x7a40, 0xffc0, PDP11_OPCODE_ILLEGAL,   PDP11_NONE },*/ | 
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| 114 | /*{ "",         0x7a80, 0xff80, PDP11_OPCODE_ILLEGAL,   PDP11_NONE },*/ | 
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| 115 | /*{ "",         0x7b00, 0xffe0, PDP11_OPCODE_ILLEGAL,   PDP11_NONE },*/ | 
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| 116 | { "l2dr",     0x7c10, 0xfff8, PDP11_OPCODE_REG,       PDP11_CIS },/*l2d*/ | 
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| 117 | { "movc",     0x7c18, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 118 | { "movrc",    0x7c19, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 119 | { "movtc",    0x7c1a, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 120 | { "locc",     0x7c20, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 121 | { "skpc",     0x7c21, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 122 | { "scanc",    0x7c22, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 123 | { "spanc",    0x7c23, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 124 | { "cmpc",     0x7c24, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 125 | { "matc",     0x7c25, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 126 | { "addn",     0x7c28, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 127 | { "subn",     0x7c29, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 128 | { "cmpn",     0x7c2a, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 129 | { "cvtnl",    0x7c2b, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 130 | { "cvtpn",    0x7c2c, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 131 | { "cvtnp",    0x7c2d, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 132 | { "ashn",     0x7c2e, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 133 | { "cvtln",    0x7c2f, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 134 | { "l3dr",     0x7c30, 0xfff8, PDP11_OPCODE_REG,       PDP11_CIS },/*l3d*/ | 
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| 135 | { "addp",     0x7c38, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 136 | { "subp",     0x7c39, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 137 | { "cmpp",     0x7c3a, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 138 | { "cvtpl",    0x7c3b, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 139 | { "mulp",     0x7c3c, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 140 | { "divp",     0x7c3d, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 141 | { "ashp",     0x7c3e, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 142 | { "cvtlp",    0x7c3f, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 143 | { "movci",    0x7c58, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 144 | { "movrci",   0x7c59, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 145 | { "movtci",   0x7c5a, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 146 | { "locci",    0x7c60, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 147 | { "skpci",    0x7c61, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 148 | { "scanci",   0x7c62, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 149 | { "spanci",   0x7c63, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 150 | { "cmpci",    0x7c64, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 151 | { "matci",    0x7c65, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 152 | { "addni",    0x7c68, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 153 | { "subni",    0x7c69, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 154 | { "cmpni",    0x7c6a, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 155 | { "cvtnli",   0x7c6b, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 156 | { "cvtpni",   0x7c6c, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 157 | { "cvtnpi",   0x7c6d, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 158 | { "ashni",    0x7c6e, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 159 | { "cvtlni",   0x7c6f, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 160 | { "addpi",    0x7c78, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 161 | { "subpi",    0x7c79, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 162 | { "cmppi",    0x7c7a, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 163 | { "cvtpli",   0x7c7b, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 164 | { "mulpi",    0x7c7c, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 165 | { "divpi",    0x7c7d, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 166 | { "ashpi",    0x7c7e, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 167 | { "cvtlpi",   0x7c7f, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_CIS }, | 
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| 168 | { "med",      0x7d80, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_UCODE }, | 
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| 169 | { "xfc",      0x7dc0, 0xffc0, PDP11_OPCODE_IMM6,      PDP11_UCODE }, | 
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| 170 | { "sob",      0x7e00, 0xfe00, PDP11_OPCODE_REG_DISPL, PDP11_LEIS }, | 
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| 171 | { "bpl",      0x8000, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 172 | { "bmi",      0x8100, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 173 | { "bhi",      0x8200, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 174 | { "blos",     0x8300, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 175 | { "bvc",      0x8400, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 176 | { "bvs",      0x8500, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 177 | { "bcc",      0x8600, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC },/*bhis*/ | 
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| 178 | { "bcs",      0x8700, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC },/*blo*/ | 
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| 179 | { "emt",      0x8800, 0xff00, PDP11_OPCODE_IMM8,      PDP11_BASIC }, | 
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| 180 | { "sys",      0x8900, 0xff00, PDP11_OPCODE_IMM8,      PDP11_BASIC },/*trap*/ | 
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| 181 | { "clrb",     0x8a00, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 182 | { "comb",     0x8a40, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 183 | { "incb",     0x8a80, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 184 | { "decb",     0x8ac0, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 185 | { "negb",     0x8b00, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 186 | { "adcb",     0x8b40, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 187 | { "sbcb",     0x8b80, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 188 | { "tstb",     0x8bc0, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 189 | { "rorb",     0x8c00, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 190 | { "rolb",     0x8c40, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 191 | { "asrb",     0x8c80, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 192 | { "aslb",     0x8cc0, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 193 | { "mtps",     0x8d00, 0xffc0, PDP11_OPCODE_OP,        PDP11_MXPS }, | 
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| 194 | { "mfpd",     0x8d40, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 195 | { "mtpd",     0x8d80, 0xffc0, PDP11_OPCODE_OP,        PDP11_BASIC }, | 
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| 196 | { "mfps",     0x8dc0, 0xffc0, PDP11_OPCODE_OP,        PDP11_MXPS }, | 
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| 197 | { "movb",     0x9000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 198 | { "cmpb",     0xa000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 199 | { "bitb",     0xb000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 200 | { "bicb",     0xc000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 201 | { "bisb",     0xd000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 202 | { "sub",      0xe000, 0xf000, PDP11_OPCODE_OP_OP,     PDP11_BASIC }, | 
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| 203 | { "cfcc",     0xf000, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_FPP }, | 
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| 204 | { "setf",     0xf001, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_FPP }, | 
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| 205 | { "seti",     0xf002, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_FPP }, | 
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| 206 | { "ldub",     0xf003, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_UCODE }, | 
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| 207 | /* fpp trap   0xf004..0xf008 */ | 
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| 208 | { "setd",     0xf009, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_FPP }, | 
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| 209 | { "setl",     0xf00a, 0xffff, PDP11_OPCODE_NO_OPS,    PDP11_FPP }, | 
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| 210 | /* fpp trap   0xf00b..0xf03f */ | 
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| 211 | { "ldfps",    0xf040, 0xffc0, PDP11_OPCODE_OP,        PDP11_FPP }, | 
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| 212 | { "stfps",    0xf080, 0xffc0, PDP11_OPCODE_OP,        PDP11_FPP }, | 
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| 213 | { "stst",     0xf0c0, 0xffc0, PDP11_OPCODE_OP,        PDP11_FPP }, | 
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| 214 | { "clrf",     0xf100, 0xffc0, PDP11_OPCODE_FOP,       PDP11_FPP }, | 
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| 215 | { "tstf",     0xf140, 0xffc0, PDP11_OPCODE_FOP,       PDP11_FPP }, | 
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| 216 | { "absf",     0xf180, 0xffc0, PDP11_OPCODE_FOP,       PDP11_FPP }, | 
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| 217 | { "negf",     0xf1c0, 0xffc0, PDP11_OPCODE_FOP,       PDP11_FPP }, | 
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| 218 | { "mulf",     0xf200, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 219 | { "modf",     0xf300, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 220 | { "addf",     0xf400, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 221 | { "ldf",      0xf500, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP },/*movif*/ | 
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| 222 | { "subf",     0xf600, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 223 | { "cmpf",     0xf700, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 224 | { "stf",      0xf800, 0xff00, PDP11_OPCODE_AC_FOP,    PDP11_FPP },/*movfi*/ | 
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| 225 | { "divf",     0xf900, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 226 | { "stexp",    0xfa00, 0xff00, PDP11_OPCODE_AC_OP,     PDP11_FPP }, | 
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| 227 | { "stcfi",    0xfb00, 0xff00, PDP11_OPCODE_AC_OP,     PDP11_FPP }, | 
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| 228 | { "stcff",    0xfc00, 0xff00, PDP11_OPCODE_AC_FOP,    PDP11_FPP },/* ? */ | 
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| 229 | { "ldexp",    0xfd00, 0xff00, PDP11_OPCODE_OP_AC,     PDP11_FPP }, | 
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| 230 | { "ldcif",    0xfe00, 0xff00, PDP11_OPCODE_OP_AC,     PDP11_FPP }, | 
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| 231 | { "ldcff",    0xff00, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP },/* ? */ | 
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| 232 | /* This entry MUST be last; it is a "catch-all" entry that will match when no | 
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| 233 | * other opcode entry matches during disassembly. | 
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| 234 | */ | 
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| 235 | { "",         0x0000, 0x0000, PDP11_OPCODE_ILLEGAL,   PDP11_NONE }, | 
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| 236 | }; | 
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| 237 |  | 
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| 238 | const struct pdp11_opcode pdp11_aliases[] = | 
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| 239 | { | 
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| 240 | /* name,      pattern, mask,  opcode type,            insn type */ | 
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| 241 | { "l2d",      0x7c10, 0xfff8, PDP11_OPCODE_REG,       PDP11_CIS }, | 
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| 242 | { "l3d",      0x7c30, 0xfff8, PDP11_OPCODE_REG,       PDP11_CIS }, | 
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| 243 | { "bhis",     0x8600, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 244 | { "blo",      0x8700, 0xff00, PDP11_OPCODE_DISPL,     PDP11_BASIC }, | 
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| 245 | { "trap",     0x8900, 0xff00, PDP11_OPCODE_IMM8,      PDP11_BASIC }, | 
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| 246 | /* fpp xxxd alternate names to xxxf opcodes */ | 
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| 247 | { "clrd",     0xf100, 0xffc0, PDP11_OPCODE_FOP,       PDP11_FPP }, | 
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| 248 | { "tstd",     0xf140, 0xffc0, PDP11_OPCODE_FOP,       PDP11_FPP }, | 
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| 249 | { "absd",     0xf180, 0xffc0, PDP11_OPCODE_FOP,       PDP11_FPP }, | 
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| 250 | { "negd",     0xf1c0, 0xffc0, PDP11_OPCODE_FOP,       PDP11_FPP }, | 
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| 251 | { "muld",     0xf200, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 252 | { "modd",     0xf300, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 253 | { "addd",     0xf400, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 254 | { "ldd",      0xf500, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP },/*movif*/ | 
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| 255 | { "subd",     0xf600, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 256 | { "cmpd",     0xf700, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 257 | { "std",      0xf800, 0xff00, PDP11_OPCODE_AC_FOP,    PDP11_FPP },/*movfi*/ | 
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| 258 | { "divd",     0xf900, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP }, | 
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| 259 | { "stcfl",    0xfb00, 0xff00, PDP11_OPCODE_AC_OP,     PDP11_FPP }, | 
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| 260 | { "stcdi",    0xfb00, 0xff00, PDP11_OPCODE_AC_OP,     PDP11_FPP }, | 
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| 261 | { "stcdl",    0xfb00, 0xff00, PDP11_OPCODE_AC_OP,     PDP11_FPP }, | 
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| 262 | { "stcfd",    0xfc00, 0xff00, PDP11_OPCODE_AC_FOP,    PDP11_FPP },/* ? */ | 
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| 263 | { "stcdf",    0xfc00, 0xff00, PDP11_OPCODE_AC_FOP,    PDP11_FPP },/* ? */ | 
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| 264 | { "ldcid",    0xfe00, 0xff00, PDP11_OPCODE_OP_AC,     PDP11_FPP }, | 
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| 265 | { "ldclf",    0xfe00, 0xff00, PDP11_OPCODE_OP_AC,     PDP11_FPP }, | 
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| 266 | { "ldcld",    0xfe00, 0xff00, PDP11_OPCODE_OP_AC,     PDP11_FPP }, | 
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| 267 | { "ldcfd",    0xff00, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP },/* ? */ | 
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| 268 | { "ldcdf",    0xff00, 0xff00, PDP11_OPCODE_FOP_AC,    PDP11_FPP },/* ? */ | 
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| 269 | }; | 
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| 270 |  | 
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| 271 | const int pdp11_num_opcodes = sizeof pdp11_opcodes / sizeof pdp11_opcodes[0]; | 
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| 272 | const int pdp11_num_aliases = sizeof pdp11_aliases / sizeof pdp11_aliases[0]; | 
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