source: trunk/binutils/opcodes/m32r-dis.c@ 2476

Last change on this file since 2476 was 610, checked in by bird, 22 years ago

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1/* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS MACHINE GENERATED WITH CGEN.
5- the resultant file is machine generated, cgen-dis.in isn't
6
7Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002
8Free Software Foundation, Inc.
9
10This file is part of the GNU Binutils and GDB, the GNU debugger.
11
12This program is free software; you can redistribute it and/or modify
13it under the terms of the GNU General Public License as published by
14the Free Software Foundation; either version 2, or (at your option)
15any later version.
16
17This program is distributed in the hope that it will be useful,
18but WITHOUT ANY WARRANTY; without even the implied warranty of
19MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20GNU General Public License for more details.
21
22You should have received a copy of the GNU General Public License
23along with this program; if not, write to the Free Software Foundation, Inc.,
2459 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25
26/* ??? Eventually more and more of this stuff can go to cpu-independent files.
27 Keep that in mind. */
28
29#include "sysdep.h"
30#include <stdio.h>
31#include "ansidecl.h"
32#include "dis-asm.h"
33#include "bfd.h"
34#include "symcat.h"
35#include "libiberty.h"
36#include "m32r-desc.h"
37#include "m32r-opc.h"
38#include "opintl.h"
39
40/* Default text to print if an instruction isn't recognized. */
41#define UNKNOWN_INSN_MSG _("*unknown*")
42
43static void print_normal
44 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
45static void print_address
46 PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
47static void print_keyword
48 PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
49static void print_insn_normal
50 PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
51 bfd_vma, int));
52static int print_insn
53 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
54static int default_print_insn
55 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
56static int read_insn
57 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
58 CGEN_EXTRACT_INFO *, unsigned long *));
59
60
61/* -- disassembler routines inserted here */
62
63/* -- dis.c */
64static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int));
65static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
66
67/* Immediate values are prefixed with '#'. */
68
69#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
70 do \
71 { \
72 if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \
73 (*info->fprintf_func) (info->stream, "#"); \
74 } \
75 while (0)
76
77/* Handle '#' prefixes as operands. */
78
79static void
80print_hash (cd, dis_info, value, attrs, pc, length)
81 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
82 PTR dis_info;
83 long value ATTRIBUTE_UNUSED;
84 unsigned int attrs ATTRIBUTE_UNUSED;
85 bfd_vma pc ATTRIBUTE_UNUSED;
86 int length ATTRIBUTE_UNUSED;
87{
88 disassemble_info *info = (disassemble_info *) dis_info;
89 (*info->fprintf_func) (info->stream, "#");
90}
91
92#undef CGEN_PRINT_INSN
93#define CGEN_PRINT_INSN my_print_insn
94
95static int
96my_print_insn (cd, pc, info)
97 CGEN_CPU_DESC cd;
98 bfd_vma pc;
99 disassemble_info *info;
100{
101 char buffer[CGEN_MAX_INSN_SIZE];
102 char *buf = buffer;
103 int status;
104 int buflen = (pc & 3) == 0 ? 4 : 2;
105
106 /* Read the base part of the insn. */
107
108 status = (*info->read_memory_func) (pc, buf, buflen, info);
109 if (status != 0)
110 {
111 (*info->memory_error_func) (status, pc, info);
112 return -1;
113 }
114
115 /* 32 bit insn? */
116 if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
117 return print_insn (cd, pc, info, buf, buflen);
118
119 /* Print the first insn. */
120 if ((pc & 3) == 0)
121 {
122 if (print_insn (cd, pc, info, buf, 2) == 0)
123 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
124 buf += 2;
125 }
126
127 if (buf[0] & 0x80)
128 {
129 /* Parallel. */
130 (*info->fprintf_func) (info->stream, " || ");
131 buf[0] &= 0x7f;
132 }
133 else
134 (*info->fprintf_func) (info->stream, " -> ");
135
136 /* The "& 3" is to pass a consistent address.
137 Parallel insns arguably both begin on the word boundary.
138 Also, branch insns are calculated relative to the word boundary. */
139 if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
140 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
141
142 return (pc & 3) ? 2 : 4;
143}
144
145/* -- */
146
147void m32r_cgen_print_operand
148 PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
149 void const *, bfd_vma, int));
150
151/* Main entry point for printing operands.
152 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
153 of dis-asm.h on cgen.h.
154
155 This function is basically just a big switch statement. Earlier versions
156 used tables to look up the function to use, but
157 - if the table contains both assembler and disassembler functions then
158 the disassembler contains much of the assembler and vice-versa,
159 - there's a lot of inlining possibilities as things grow,
160 - using a switch statement avoids the function call overhead.
161
162 This function could be moved into `print_insn_normal', but keeping it
163 separate makes clear the interface between `print_insn_normal' and each of
164 the handlers. */
165
166void
167m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
168 CGEN_CPU_DESC cd;
169 int opindex;
170 PTR xinfo;
171 CGEN_FIELDS *fields;
172 void const *attrs ATTRIBUTE_UNUSED;
173 bfd_vma pc;
174 int length;
175{
176 disassemble_info *info = (disassemble_info *) xinfo;
177
178 switch (opindex)
179 {
180 case M32R_OPERAND_ACC :
181 print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
182 break;
183 case M32R_OPERAND_ACCD :
184 print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
185 break;
186 case M32R_OPERAND_ACCS :
187 print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
188 break;
189 case M32R_OPERAND_DCR :
190 print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
191 break;
192 case M32R_OPERAND_DISP16 :
193 print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
194 break;
195 case M32R_OPERAND_DISP24 :
196 print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
197 break;
198 case M32R_OPERAND_DISP8 :
199 print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
200 break;
201 case M32R_OPERAND_DR :
202 print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
203 break;
204 case M32R_OPERAND_HASH :
205 print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
206 break;
207 case M32R_OPERAND_HI16 :
208 print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
209 break;
210 case M32R_OPERAND_IMM1 :
211 print_normal (cd, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
212 break;
213 case M32R_OPERAND_SCR :
214 print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
215 break;
216 case M32R_OPERAND_SIMM16 :
217 print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
218 break;
219 case M32R_OPERAND_SIMM8 :
220 print_normal (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
221 break;
222 case M32R_OPERAND_SLO16 :
223 print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
224 break;
225 case M32R_OPERAND_SR :
226 print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
227 break;
228 case M32R_OPERAND_SRC1 :
229 print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
230 break;
231 case M32R_OPERAND_SRC2 :
232 print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
233 break;
234 case M32R_OPERAND_UIMM16 :
235 print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
236 break;
237 case M32R_OPERAND_UIMM24 :
238 print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
239 break;
240 case M32R_OPERAND_UIMM4 :
241 print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
242 break;
243 case M32R_OPERAND_UIMM5 :
244 print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
245 break;
246 case M32R_OPERAND_ULO16 :
247 print_normal (cd, info, fields->f_uimm16, 0, pc, length);
248 break;
249
250 default :
251 /* xgettext:c-format */
252 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
253 opindex);
254 abort ();
255 }
256}
257
258cgen_print_fn * const m32r_cgen_print_handlers[] =
259{
260 print_insn_normal,
261};
262
263
264void
265m32r_cgen_init_dis (cd)
266 CGEN_CPU_DESC cd;
267{
268 m32r_cgen_init_opcode_table (cd);
269 m32r_cgen_init_ibld_table (cd);
270 cd->print_handlers = & m32r_cgen_print_handlers[0];
271 cd->print_operand = m32r_cgen_print_operand;
272}
273
274
275
276/* Default print handler. */
277
278static void
279print_normal (cd, dis_info, value, attrs, pc, length)
280 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
281 PTR dis_info;
282 long value;
283 unsigned int attrs;
284 bfd_vma pc ATTRIBUTE_UNUSED;
285 int length ATTRIBUTE_UNUSED;
286{
287 disassemble_info *info = (disassemble_info *) dis_info;
288
289#ifdef CGEN_PRINT_NORMAL
290 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
291#endif
292
293 /* Print the operand as directed by the attributes. */
294 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
295 ; /* nothing to do */
296 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
297 (*info->fprintf_func) (info->stream, "%ld", value);
298 else
299 (*info->fprintf_func) (info->stream, "0x%lx", value);
300}
301
302/* Default address handler. */
303
304static void
305print_address (cd, dis_info, value, attrs, pc, length)
306 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
307 PTR dis_info;
308 bfd_vma value;
309 unsigned int attrs;
310 bfd_vma pc ATTRIBUTE_UNUSED;
311 int length ATTRIBUTE_UNUSED;
312{
313 disassemble_info *info = (disassemble_info *) dis_info;
314
315#ifdef CGEN_PRINT_ADDRESS
316 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
317#endif
318
319 /* Print the operand as directed by the attributes. */
320 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
321 ; /* nothing to do */
322 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
323 (*info->print_address_func) (value, info);
324 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
325 (*info->print_address_func) (value, info);
326 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
327 (*info->fprintf_func) (info->stream, "%ld", (long) value);
328 else
329 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
330}
331
332/* Keyword print handler. */
333
334static void
335print_keyword (cd, dis_info, keyword_table, value, attrs)
336 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
337 PTR dis_info;
338 CGEN_KEYWORD *keyword_table;
339 long value;
340 unsigned int attrs ATTRIBUTE_UNUSED;
341{
342 disassemble_info *info = (disassemble_info *) dis_info;
343 const CGEN_KEYWORD_ENTRY *ke;
344
345 ke = cgen_keyword_lookup_value (keyword_table, value);
346 if (ke != NULL)
347 (*info->fprintf_func) (info->stream, "%s", ke->name);
348 else
349 (*info->fprintf_func) (info->stream, "???");
350}
351
352
353/* Default insn printer.
354
355 DIS_INFO is defined as `PTR' so the disassembler needn't know anything
356 about disassemble_info. */
357
358static void
359print_insn_normal (cd, dis_info, insn, fields, pc, length)
360 CGEN_CPU_DESC cd;
361 PTR dis_info;
362 const CGEN_INSN *insn;
363 CGEN_FIELDS *fields;
364 bfd_vma pc;
365 int length;
366{
367 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
368 disassemble_info *info = (disassemble_info *) dis_info;
369 const CGEN_SYNTAX_CHAR_TYPE *syn;
370
371 CGEN_INIT_PRINT (cd);
372
373 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
374 {
375 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
376 {
377 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
378 continue;
379 }
380 if (CGEN_SYNTAX_CHAR_P (*syn))
381 {
382 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
383 continue;
384 }
385
386 /* We have an operand. */
387 m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
388 fields, CGEN_INSN_ATTRS (insn), pc, length);
389 }
390}
391
392
393/* Subroutine of print_insn. Reads an insn into the given buffers and updates
394 the extract info.
395 Returns 0 if all is well, non-zero otherwise. */
396
397static int
398read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
399 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
400 bfd_vma pc;
401 disassemble_info *info;
402 char *buf;
403 int buflen;
404 CGEN_EXTRACT_INFO *ex_info;
405 unsigned long *insn_value;
406{
407 int status = (*info->read_memory_func) (pc, buf, buflen, info);
408 if (status != 0)
409 {
410 (*info->memory_error_func) (status, pc, info);
411 return -1;
412 }
413
414 ex_info->dis_info = info;
415 ex_info->valid = (1 << buflen) - 1;
416 ex_info->insn_bytes = buf;
417
418 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
419 return 0;
420}
421
422/* Utility to print an insn.
423 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
424 The result is the size of the insn in bytes or zero for an unknown insn
425 or -1 if an error occurs fetching data (memory_error_func will have
426 been called). */
427
428static int
429print_insn (cd, pc, info, buf, buflen)
430 CGEN_CPU_DESC cd;
431 bfd_vma pc;
432 disassemble_info *info;
433 char *buf;
434 unsigned int buflen;
435{
436 CGEN_INSN_INT insn_value;
437 const CGEN_INSN_LIST *insn_list;
438 CGEN_EXTRACT_INFO ex_info;
439 int basesize;
440
441 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
442 basesize = cd->base_insn_bitsize < buflen * 8 ?
443 cd->base_insn_bitsize : buflen * 8;
444 insn_value = cgen_get_insn_value (cd, buf, basesize);
445
446
447 /* Fill in ex_info fields like read_insn would. Don't actually call
448 read_insn, since the incoming buffer is already read (and possibly
449 modified a la m32r). */
450 ex_info.valid = (1 << buflen) - 1;
451 ex_info.dis_info = info;
452 ex_info.insn_bytes = buf;
453
454 /* The instructions are stored in hash lists.
455 Pick the first one and keep trying until we find the right one. */
456
457 insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
458 while (insn_list != NULL)
459 {
460 const CGEN_INSN *insn = insn_list->insn;
461 CGEN_FIELDS fields;
462 int length;
463 unsigned long insn_value_cropped;
464
465#ifdef CGEN_VALIDATE_INSN_SUPPORTED
466 /* Not needed as insn shouldn't be in hash lists if not supported. */
467 /* Supported by this cpu? */
468 if (! m32r_cgen_insn_supported (cd, insn))
469 {
470 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
471 continue;
472 }
473#endif
474
475 /* Basic bit mask must be correct. */
476 /* ??? May wish to allow target to defer this check until the extract
477 handler. */
478
479 /* Base size may exceed this instruction's size. Extract the
480 relevant part from the buffer. */
481 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
482 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
483 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
484 info->endian == BFD_ENDIAN_BIG);
485 else
486 insn_value_cropped = insn_value;
487
488 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
489 == CGEN_INSN_BASE_VALUE (insn))
490 {
491 /* Printing is handled in two passes. The first pass parses the
492 machine insn and extracts the fields. The second pass prints
493 them. */
494
495 /* Make sure the entire insn is loaded into insn_value, if it
496 can fit. */
497 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
498 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
499 {
500 unsigned long full_insn_value;
501 int rc = read_insn (cd, pc, info, buf,
502 CGEN_INSN_BITSIZE (insn) / 8,
503 & ex_info, & full_insn_value);
504 if (rc != 0)
505 return rc;
506 length = CGEN_EXTRACT_FN (cd, insn)
507 (cd, insn, &ex_info, full_insn_value, &fields, pc);
508 }
509 else
510 length = CGEN_EXTRACT_FN (cd, insn)
511 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
512
513 /* length < 0 -> error */
514 if (length < 0)
515 return length;
516 if (length > 0)
517 {
518 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
519 /* length is in bits, result is in bytes */
520 return length / 8;
521 }
522 }
523
524 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
525 }
526
527 return 0;
528}
529
530/* Default value for CGEN_PRINT_INSN.
531 The result is the size of the insn in bytes or zero for an unknown insn
532 or -1 if an error occured fetching bytes. */
533
534#ifndef CGEN_PRINT_INSN
535#define CGEN_PRINT_INSN default_print_insn
536#endif
537
538static int
539default_print_insn (cd, pc, info)
540 CGEN_CPU_DESC cd;
541 bfd_vma pc;
542 disassemble_info *info;
543{
544 char buf[CGEN_MAX_INSN_SIZE];
545 int buflen;
546 int status;
547
548 /* Attempt to read the base part of the insn. */
549 buflen = cd->base_insn_bitsize / 8;
550 status = (*info->read_memory_func) (pc, buf, buflen, info);
551
552 /* Try again with the minimum part, if min < base. */
553 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
554 {
555 buflen = cd->min_insn_bitsize / 8;
556 status = (*info->read_memory_func) (pc, buf, buflen, info);
557 }
558
559 if (status != 0)
560 {
561 (*info->memory_error_func) (status, pc, info);
562 return -1;
563 }
564
565 return print_insn (cd, pc, info, buf, buflen);
566}
567
568/* Main entry point.
569 Print one instruction from PC on INFO->STREAM.
570 Return the size of the instruction (in bytes). */
571
572typedef struct cpu_desc_list {
573 struct cpu_desc_list *next;
574 int isa;
575 int mach;
576 int endian;
577 CGEN_CPU_DESC cd;
578} cpu_desc_list;
579
580int
581print_insn_m32r (pc, info)
582 bfd_vma pc;
583 disassemble_info *info;
584{
585 static cpu_desc_list *cd_list = 0;
586 cpu_desc_list *cl = 0;
587 static CGEN_CPU_DESC cd = 0;
588 static int prev_isa;
589 static int prev_mach;
590 static int prev_endian;
591 int length;
592 int isa,mach;
593 int endian = (info->endian == BFD_ENDIAN_BIG
594 ? CGEN_ENDIAN_BIG
595 : CGEN_ENDIAN_LITTLE);
596 enum bfd_architecture arch;
597
598 /* ??? gdb will set mach but leave the architecture as "unknown" */
599#ifndef CGEN_BFD_ARCH
600#define CGEN_BFD_ARCH bfd_arch_m32r
601#endif
602 arch = info->arch;
603 if (arch == bfd_arch_unknown)
604 arch = CGEN_BFD_ARCH;
605
606 /* There's no standard way to compute the machine or isa number
607 so we leave it to the target. */
608#ifdef CGEN_COMPUTE_MACH
609 mach = CGEN_COMPUTE_MACH (info);
610#else
611 mach = info->mach;
612#endif
613
614#ifdef CGEN_COMPUTE_ISA
615 isa = CGEN_COMPUTE_ISA (info);
616#else
617 isa = info->insn_sets;
618#endif
619
620 /* If we've switched cpu's, try to find a handle we've used before */
621 if (cd
622 && (isa != prev_isa
623 || mach != prev_mach
624 || endian != prev_endian))
625 {
626 cd = 0;
627 for (cl = cd_list; cl; cl = cl->next)
628 {
629 if (cl->isa == isa &&
630 cl->mach == mach &&
631 cl->endian == endian)
632 {
633 cd = cl->cd;
634 break;
635 }
636 }
637 }
638
639 /* If we haven't initialized yet, initialize the opcode table. */
640 if (! cd)
641 {
642 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
643 const char *mach_name;
644
645 if (!arch_type)
646 abort ();
647 mach_name = arch_type->printable_name;
648
649 prev_isa = isa;
650 prev_mach = mach;
651 prev_endian = endian;
652 cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
653 CGEN_CPU_OPEN_BFDMACH, mach_name,
654 CGEN_CPU_OPEN_ENDIAN, prev_endian,
655 CGEN_CPU_OPEN_END);
656 if (!cd)
657 abort ();
658
659 /* save this away for future reference */
660 cl = xmalloc (sizeof (struct cpu_desc_list));
661 cl->cd = cd;
662 cl->isa = isa;
663 cl->mach = mach;
664 cl->endian = endian;
665 cl->next = cd_list;
666 cd_list = cl;
667
668 m32r_cgen_init_dis (cd);
669 }
670
671 /* We try to have as much common code as possible.
672 But at this point some targets need to take over. */
673 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
674 but if not possible try to move this hook elsewhere rather than
675 have two hooks. */
676 length = CGEN_PRINT_INSN (cd, pc, info);
677 if (length > 0)
678 return length;
679 if (length < 0)
680 return -1;
681
682 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
683 return cd->default_insn_bitsize / 8;
684}
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