| 1 | /* Assemble Matsushita MN10300 instructions.
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| 2 | Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
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| 3 |
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| 4 | This program is free software; you can redistribute it and/or modify
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| 5 | it under the terms of the GNU General Public License as published by
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| 6 | the Free Software Foundation; either version 2 of the License, or
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| 7 | (at your option) any later version.
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| 8 |
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| 9 | This program is distributed in the hope that it will be useful,
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| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 12 | GNU General Public License for more details.
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| 13 |
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| 14 | You should have received a copy of the GNU General Public License
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| 15 | along with this program; if not, write to the Free Software
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| 16 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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| 17 |
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| 18 | /* This file is formatted at > 80 columns. Attempting to read it on a
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| 19 | screeen with less than 80 columns will be difficult. */
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| 20 | #include "sysdep.h"
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| 21 | #include "opcode/mn10300.h"
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| 22 |
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| 23 | |
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| 24 |
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| 25 | const struct mn10300_operand mn10300_operands[] = {
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| 26 | #define UNUSED 0
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| 27 | {0, 0, 0},
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| 28 |
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| 29 | /* dn register in the first register operand position. */
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| 30 | #define DN0 (UNUSED+1)
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| 31 | {2, 0, MN10300_OPERAND_DREG},
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| 32 |
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| 33 | /* dn register in the second register operand position. */
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| 34 | #define DN1 (DN0+1)
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| 35 | {2, 2, MN10300_OPERAND_DREG},
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| 36 |
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| 37 | /* dn register in the third register operand position. */
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| 38 | #define DN2 (DN1+1)
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| 39 | {2, 4, MN10300_OPERAND_DREG},
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| 40 |
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| 41 | /* dm register in the first register operand position. */
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| 42 | #define DM0 (DN2+1)
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| 43 | {2, 0, MN10300_OPERAND_DREG},
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| 44 |
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| 45 | /* dm register in the second register operand position. */
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| 46 | #define DM1 (DM0+1)
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| 47 | {2, 2, MN10300_OPERAND_DREG},
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| 48 |
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| 49 | /* dm register in the third register operand position. */
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| 50 | #define DM2 (DM1+1)
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| 51 | {2, 4, MN10300_OPERAND_DREG},
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| 52 |
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| 53 | /* an register in the first register operand position. */
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| 54 | #define AN0 (DM2+1)
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| 55 | {2, 0, MN10300_OPERAND_AREG},
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| 56 |
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| 57 | /* an register in the second register operand position. */
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| 58 | #define AN1 (AN0+1)
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| 59 | {2, 2, MN10300_OPERAND_AREG},
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| 60 |
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| 61 | /* an register in the third register operand position. */
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| 62 | #define AN2 (AN1+1)
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| 63 | {2, 4, MN10300_OPERAND_AREG},
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| 64 |
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| 65 | /* am register in the first register operand position. */
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| 66 | #define AM0 (AN2+1)
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| 67 | {2, 0, MN10300_OPERAND_AREG},
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| 68 |
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| 69 | /* am register in the second register operand position. */
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| 70 | #define AM1 (AM0+1)
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| 71 | {2, 2, MN10300_OPERAND_AREG},
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| 72 |
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| 73 | /* am register in the third register operand position. */
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| 74 | #define AM2 (AM1+1)
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| 75 | {2, 4, MN10300_OPERAND_AREG},
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| 76 |
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| 77 | /* 8 bit unsigned immediate which may promote to a 16bit
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| 78 | unsigned immediate. */
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| 79 | #define IMM8 (AM2+1)
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| 80 | {8, 0, MN10300_OPERAND_PROMOTE},
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| 81 |
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| 82 | /* 16 bit unsigned immediate which may promote to a 32bit
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| 83 | unsigned immediate. */
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| 84 | #define IMM16 (IMM8+1)
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| 85 | {16, 0, MN10300_OPERAND_PROMOTE},
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| 86 |
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| 87 | /* 16 bit pc-relative immediate which may promote to a 16bit
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| 88 | pc-relative immediate. */
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| 89 | #define IMM16_PCREL (IMM16+1)
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| 90 | {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
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| 91 |
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| 92 | /* 16bit unsigned displacement in a memory operation which
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| 93 | may promote to a 32bit displacement. */
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| 94 | #define IMM16_MEM (IMM16_PCREL+1)
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| 95 | {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
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| 96 |
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| 97 | /* 32bit immediate, high 16 bits in the main instruction
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| 98 | word, 16bits in the extension word.
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| 99 |
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| 100 | The "bits" field indicates how many bits are in the
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| 101 | main instruction word for MN10300_OPERAND_SPLIT! */
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| 102 | #define IMM32 (IMM16_MEM+1)
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| 103 | {16, 0, MN10300_OPERAND_SPLIT},
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| 104 |
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| 105 | /* 32bit pc-relative offset. */
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| 106 | #define IMM32_PCREL (IMM32+1)
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| 107 | {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
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| 108 |
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| 109 | /* 32bit memory offset. */
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| 110 | #define IMM32_MEM (IMM32_PCREL+1)
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| 111 | {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
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| 112 |
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| 113 | /* 32bit immediate, high 16 bits in the main instruction
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| 114 | word, 16bits in the extension word, low 16bits are left
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| 115 | shifted 8 places.
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| 116 |
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| 117 | The "bits" field indicates how many bits are in the
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| 118 | main instruction word for MN10300_OPERAND_SPLIT! */
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| 119 | #define IMM32_LOWSHIFT8 (IMM32_MEM+1)
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| 120 | {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
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| 121 |
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| 122 | /* 32bit immediate, high 24 bits in the main instruction
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| 123 | word, 8 in the extension word.
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| 124 |
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| 125 | The "bits" field indicates how many bits are in the
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| 126 | main instruction word for MN10300_OPERAND_SPLIT! */
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| 127 | #define IMM32_HIGH24 (IMM32_LOWSHIFT8+1)
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| 128 | {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
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| 129 |
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| 130 | /* 32bit immediate, high 24 bits in the main instruction
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| 131 | word, 8 in the extension word, low 8 bits are left
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| 132 | shifted 16 places.
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| 133 |
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| 134 | The "bits" field indicates how many bits are in the
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| 135 | main instruction word for MN10300_OPERAND_SPLIT! */
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| 136 | #define IMM32_HIGH24_LOWSHIFT16 (IMM32_HIGH24+1)
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| 137 | {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
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| 138 |
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| 139 | /* Stack pointer. */
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| 140 | #define SP (IMM32_HIGH24_LOWSHIFT16+1)
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| 141 | {8, 0, MN10300_OPERAND_SP},
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| 142 |
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| 143 | /* Processor status word. */
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| 144 | #define PSW (SP+1)
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| 145 | {0, 0, MN10300_OPERAND_PSW},
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| 146 |
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| 147 | /* MDR register. */
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| 148 | #define MDR (PSW+1)
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| 149 | {0, 0, MN10300_OPERAND_MDR},
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| 150 |
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| 151 | /* Index register. */
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| 152 | #define DI (MDR+1)
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| 153 | {2, 2, MN10300_OPERAND_DREG},
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| 154 |
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| 155 | /* 8 bit signed displacement, may promote to 16bit signed displacement. */
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| 156 | #define SD8 (DI+1)
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| 157 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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| 158 |
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| 159 | /* 16 bit signed displacement, may promote to 32bit displacement. */
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| 160 | #define SD16 (SD8+1)
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| 161 | {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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| 162 |
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| 163 | /* 8 bit signed displacement that can not promote. */
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| 164 | #define SD8N (SD16+1)
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| 165 | {8, 0, MN10300_OPERAND_SIGNED},
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| 166 |
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| 167 | /* 8 bit pc-relative displacement. */
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| 168 | #define SD8N_PCREL (SD8N+1)
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| 169 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
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| 170 |
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| 171 | /* 8 bit signed displacement shifted left 8 bits in the instruction. */
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| 172 | #define SD8N_SHIFT8 (SD8N_PCREL+1)
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| 173 | {8, 8, MN10300_OPERAND_SIGNED},
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| 174 |
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| 175 | /* 8 bit signed immediate which may promote to 16bit signed immediate. */
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| 176 | #define SIMM8 (SD8N_SHIFT8+1)
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| 177 | {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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| 178 |
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| 179 | /* 16 bit signed immediate which may promote to 32bit immediate. */
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| 180 | #define SIMM16 (SIMM8+1)
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| 181 | {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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| 182 |
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| 183 | /* Either an open paren or close paren. */
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| 184 | #define PAREN (SIMM16+1)
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| 185 | {0, 0, MN10300_OPERAND_PAREN},
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| 186 |
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| 187 | /* dn register that appears in the first and second register positions. */
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| 188 | #define DN01 (PAREN+1)
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| 189 | {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
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| 190 |
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| 191 | /* an register that appears in the first and second register positions. */
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| 192 | #define AN01 (DN01+1)
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| 193 | {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
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| 194 |
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| 195 | /* 16bit pc-relative displacement which may promote to 32bit pc-relative
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| 196 | displacement. */
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| 197 | #define D16_SHIFT (AN01+1)
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| 198 | {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
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| 199 |
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| 200 | /* 8 bit immediate found in the extension word. */
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| 201 | #define IMM8E (D16_SHIFT+1)
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| 202 | {8, 0, MN10300_OPERAND_EXTENDED},
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| 203 |
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| 204 | /* Register list found in the extension word shifted 8 bits left. */
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| 205 | #define REGSE_SHIFT8 (IMM8E+1)
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| 206 | {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
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| 207 |
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| 208 | /* Register list shifted 8 bits left. */
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| 209 | #define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
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| 210 | {8, 8, MN10300_OPERAND_REG_LIST},
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| 211 |
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| 212 | /* Reigster list. */
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| 213 | #define REGS (REGS_SHIFT8+1)
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| 214 | {8, 0, MN10300_OPERAND_REG_LIST},
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| 215 |
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| 216 | /* UStack pointer. */
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| 217 | #define USP (REGS+1)
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| 218 | {0, 0, MN10300_OPERAND_USP},
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| 219 |
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| 220 | /* SStack pointer. */
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| 221 | #define SSP (USP+1)
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| 222 | {0, 0, MN10300_OPERAND_SSP},
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| 223 |
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| 224 | /* MStack pointer. */
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| 225 | #define MSP (SSP+1)
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| 226 | {0, 0, MN10300_OPERAND_MSP},
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| 227 |
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| 228 | /* PC . */
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| 229 | #define PC (MSP+1)
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| 230 | {0, 0, MN10300_OPERAND_PC},
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| 231 |
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| 232 | /* 4 bit immediate for syscall. */
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| 233 | #define IMM4 (PC+1)
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| 234 | {4, 0, 0},
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| 235 |
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| 236 | /* Processor status word. */
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| 237 | #define EPSW (IMM4+1)
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| 238 | {0, 0, MN10300_OPERAND_EPSW},
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| 239 |
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| 240 | /* rn register in the first register operand position. */
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| 241 | #define RN0 (EPSW+1)
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| 242 | {4, 0, MN10300_OPERAND_RREG},
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| 243 |
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| 244 | /* rn register in the fourth register operand position. */
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| 245 | #define RN2 (RN0+1)
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| 246 | {4, 4, MN10300_OPERAND_RREG},
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| 247 |
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| 248 | /* rm register in the first register operand position. */
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| 249 | #define RM0 (RN2+1)
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| 250 | {4, 0, MN10300_OPERAND_RREG},
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| 251 |
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| 252 | /* rm register in the second register operand position. */
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| 253 | #define RM1 (RM0+1)
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| 254 | {4, 2, MN10300_OPERAND_RREG},
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| 255 |
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| 256 | /* rm register in the third register operand position. */
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| 257 | #define RM2 (RM1+1)
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| 258 | {4, 4, MN10300_OPERAND_RREG},
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| 259 |
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| 260 | #define RN02 (RM2+1)
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| 261 | {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
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| 262 |
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| 263 | #define XRN0 (RN02+1)
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| 264 | {4, 0, MN10300_OPERAND_XRREG},
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| 265 |
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| 266 | #define XRM2 (XRN0+1)
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| 267 | {4, 4, MN10300_OPERAND_XRREG},
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| 268 |
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| 269 | /* + for autoincrement */
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| 270 | #define PLUS (XRM2+1)
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| 271 | {0, 0, MN10300_OPERAND_PLUS},
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| 272 |
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| 273 | #define XRN02 (PLUS+1)
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| 274 | {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
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| 275 |
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| 276 | /* Ick */
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| 277 | #define RD0 (XRN02+1)
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| 278 | {4, -8, MN10300_OPERAND_RREG},
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| 279 |
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| 280 | #define RD2 (RD0+1)
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| 281 | {4, -4, MN10300_OPERAND_RREG},
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| 282 |
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| 283 | /* 8 unsigned displacement in a memory operation which
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| 284 | may promote to a 32bit displacement. */
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| 285 | #define IMM8_MEM (RD2+1)
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| 286 | {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
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| 287 |
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| 288 | /* Index register. */
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| 289 | #define RI (IMM8_MEM+1)
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| 290 | {4, 4, MN10300_OPERAND_RREG},
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| 291 |
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| 292 | /* 24 bit signed displacement, may promote to 32bit displacement. */
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| 293 | #define SD24 (RI+1)
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| 294 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
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| 295 |
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| 296 | /* 24 bit unsigned immediate which may promote to a 32bit
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| 297 | unsigned immediate. */
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| 298 | #define IMM24 (SD24+1)
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| 299 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
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| 300 |
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| 301 | /* 24 bit signed immediate which may promote to a 32bit
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| 302 | signed immediate. */
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| 303 | #define SIMM24 (IMM24+1)
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| 304 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
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| 305 |
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| 306 | /* 24bit unsigned displacement in a memory operation which
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| 307 | may promote to a 32bit displacement. */
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| 308 | #define IMM24_MEM (SIMM24+1)
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| 309 | {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
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| 310 | /* 32bit immediate, high 8 bits in the main instruction
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| 311 | word, 24 in the extension word.
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| 312 |
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| 313 | The "bits" field indicates how many bits are in the
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| 314 | main instruction word for MN10300_OPERAND_SPLIT! */
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| 315 | #define IMM32_HIGH8 (IMM24_MEM+1)
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| 316 | {8, 0, MN10300_OPERAND_SPLIT},
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| 317 |
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| 318 | /* Similarly, but a memory address. */
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| 319 | #define IMM32_HIGH8_MEM (IMM32_HIGH8+1)
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| 320 | {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
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| 321 |
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| 322 | /* rm register in the seventh register operand position. */
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| 323 | #define RM6 (IMM32_HIGH8_MEM+1)
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| 324 | {4, 12, MN10300_OPERAND_RREG},
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| 325 |
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| 326 | /* rm register in the fifth register operand position. */
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| 327 | #define RN4 (RM6+1)
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| 328 | {4, 8, MN10300_OPERAND_RREG},
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| 329 |
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| 330 | /* 4 bit immediate for dsp instructions. */
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| 331 | #define IMM4_2 (RN4+1)
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| 332 | {4, 4, 0},
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| 333 |
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| 334 | /* 4 bit immediate for dsp instructions. */
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| 335 | #define SIMM4_2 (IMM4_2+1)
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| 336 | {4, 4, MN10300_OPERAND_SIGNED},
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| 337 |
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| 338 | /* 4 bit immediate for dsp instructions. */
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| 339 | #define SIMM4_6 (SIMM4_2+1)
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| 340 | {4, 12, MN10300_OPERAND_SIGNED},
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| 341 |
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| 342 | } ;
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| 343 |
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| 344 | #define MEM(ADDR) PAREN, ADDR, PAREN
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| 345 | #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
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| 346 | #define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
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| 347 | #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
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| 348 | |
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| 349 |
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| 350 | /* The opcode table.
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| 351 |
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| 352 | The format of the opcode table is:
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| 353 |
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| 354 | NAME OPCODE MASK MATCH_MASK, FORMAT, PROCESSOR { OPERANDS }
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| 355 |
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| 356 | NAME is the name of the instruction.
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| 357 | OPCODE is the instruction opcode.
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| 358 | MASK is the opcode mask; this is used to tell the disassembler
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| 359 | which bits in the actual opcode must match OPCODE.
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| 360 | OPERANDS is the list of operands.
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| 361 |
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| 362 | The disassembler reads the table in order and prints the first
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| 363 | instruction which matches, so this table is sorted to put more
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| 364 | specific instructions before more general instructions. It is also
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| 365 | sorted by major opcode. */
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| 366 |
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| 367 | const struct mn10300_opcode mn10300_opcodes[] = {
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| 368 | { "mov", 0x8000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}},
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| 369 | { "mov", 0x80, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}},
|
|---|
| 370 | { "mov", 0xf1e0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
|
|---|
| 371 | { "mov", 0xf1d0, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
|
|---|
| 372 | { "mov", 0x9000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}},
|
|---|
| 373 | { "mov", 0x90, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
|
|---|
| 374 | { "mov", 0x3c, 0xfc, 0, FMT_S0, 0, {SP, AN0}},
|
|---|
| 375 | { "mov", 0xf2f0, 0xfff3, 0, FMT_D0, 0, {AM1, SP}},
|
|---|
| 376 | { "mov", 0xf2e4, 0xfffc, 0, FMT_D0, 0, {PSW, DN0}},
|
|---|
| 377 | { "mov", 0xf2f3, 0xfff3, 0, FMT_D0, 0, {DM1, PSW}},
|
|---|
| 378 | { "mov", 0xf2e0, 0xfffc, 0, FMT_D0, 0, {MDR, DN0}},
|
|---|
| 379 | { "mov", 0xf2f2, 0xfff3, 0, FMT_D0, 0, {DM1, MDR}},
|
|---|
| 380 | { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
|
|---|
| 381 | { "mov", 0x5800, 0xfcff, 0, FMT_S1, 0, {MEM(SP), DN0}},
|
|---|
| 382 | { "mov", 0x300000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
|
|---|
| 383 | { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
|
|---|
| 384 | { "mov", 0x5c00, 0xfcff, 0, FMT_S1, 0, {MEM(SP), AN0}},
|
|---|
| 385 | { "mov", 0xfaa00000, 0xfffc0000, 0, FMT_D2, 0, {MEM(IMM16_MEM), AN0}},
|
|---|
| 386 | { "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
|
|---|
| 387 | { "mov", 0x4200, 0xf3ff, 0, FMT_S1, 0, {DM1, MEM(SP)}},
|
|---|
| 388 | { "mov", 0x010000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
|
|---|
| 389 | { "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
|
|---|
| 390 | { "mov", 0x4300, 0xf3ff, 0, FMT_S1, 0, {AM1, MEM(SP)}},
|
|---|
| 391 | { "mov", 0xfa800000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM(IMM16_MEM)}},
|
|---|
| 392 | { "mov", 0x5c00, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), AN0}},
|
|---|
| 393 | { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
|
|---|
| 394 | { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
|
|---|
| 395 | { "mov", 0x5800, 0xfc00, 0, FMT_S1, 0, {MEM2(IMM8, SP), DN0}},
|
|---|
| 396 | { "mov", 0xfab40000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
|
|---|
| 397 | { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
|
|---|
| 398 | { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
|
|---|
| 399 | { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
|
|---|
| 400 | { "mov", 0xfab00000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), AN0}},
|
|---|
| 401 | { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
|
|---|
| 402 | { "mov", 0x4300, 0xf300, 0, FMT_S1, 0, {AM1, MEM2(IMM8, SP)}},
|
|---|
| 403 | { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
|
|---|
| 404 | { "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
|
|---|
| 405 | { "mov", 0x4200, 0xf300, 0, FMT_S1, 0, {DM1, MEM2(IMM8, SP)}},
|
|---|
| 406 | { "mov", 0xfa910000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
|
|---|
| 407 | { "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
|
|---|
| 408 | { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
|
|---|
| 409 | { "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
|
|---|
| 410 | { "mov", 0xfa900000, 0xfff30000, 0, FMT_D2, 0, {AM1, MEM2(IMM16, SP)}},
|
|---|
| 411 | { "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
|
|---|
| 412 |
|
|---|
| 413 | { "mov", 0xf020, 0xfffc, 0, FMT_D0, AM33, {USP, AN0}},
|
|---|
| 414 | { "mov", 0xf024, 0xfffc, 0, FMT_D0, AM33, {SSP, AN0}},
|
|---|
| 415 | { "mov", 0xf028, 0xfffc, 0, FMT_D0, AM33, {MSP, AN0}},
|
|---|
| 416 | { "mov", 0xf02c, 0xfffc, 0, FMT_D0, AM33, {PC, AN0}},
|
|---|
| 417 | { "mov", 0xf030, 0xfff3, 0, FMT_D0, AM33, {AN1, USP}},
|
|---|
| 418 | { "mov", 0xf031, 0xfff3, 0, FMT_D0, AM33, {AN1, SSP}},
|
|---|
| 419 | { "mov", 0xf032, 0xfff3, 0, FMT_D0, AM33, {AN1, MSP}},
|
|---|
| 420 | { "mov", 0xf2ec, 0xfffc, 0, FMT_D0, AM33, {EPSW, DN0}},
|
|---|
| 421 | { "mov", 0xf2f1, 0xfff3, 0, FMT_D0, AM33, {DM1, EPSW}},
|
|---|
| 422 | { "mov", 0xf500, 0xffc0, 0, FMT_D0, AM33, {AM2, RN0}},
|
|---|
| 423 | { "mov", 0xf540, 0xffc0, 0, FMT_D0, AM33, {DM2, RN0}},
|
|---|
| 424 | { "mov", 0xf580, 0xffc0, 0, FMT_D0, AM33, {RM1, AN0}},
|
|---|
| 425 | { "mov", 0xf5c0, 0xffc0, 0, FMT_D0, AM33, {RM1, DN0}},
|
|---|
| 426 | { "mov", 0xf90800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 427 | { "mov", 0xf9e800, 0xffff00, 0, FMT_D6, AM33, {XRM2, RN0}},
|
|---|
| 428 | { "mov", 0xf9f800, 0xffff00, 0, FMT_D6, AM33, {RM2, XRN0}},
|
|---|
| 429 | { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
|
|---|
| 430 | { "mov", 0xf98a00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}},
|
|---|
| 431 | { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
|
|---|
| 432 | { "mov", 0xfb0e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
|
|---|
| 433 | { "mov", 0xfd0e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
|
|---|
| 434 | { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
|
|---|
| 435 | { "mov", 0xf99a00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}},
|
|---|
| 436 | { "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
|
|---|
| 437 | { "mov", 0xfb1e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
|
|---|
| 438 | { "mov", 0xfd1e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
|
|---|
| 439 | { "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
|
|---|
| 440 | { "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
|
|---|
| 441 | { "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
|
|---|
| 442 | { "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
|
|---|
| 443 | { "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
|
|---|
| 444 | { "mov", 0xfb8a0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
|
|---|
| 445 | { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
|
|---|
| 446 | { "mov", 0xfb9a0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
|
|---|
| 447 | { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
|
|---|
| 448 | { "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
|
|---|
| 449 | { "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
|
|---|
| 450 | { "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
|
|---|
| 451 | { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
|
|---|
| 452 | { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
|
|---|
| 453 | { "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
|
|---|
| 454 | { "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
|
|---|
| 455 | /* These must come after most of the other move instructions to avoid matching
|
|---|
| 456 | a symbolic name with IMMxx operands. Ugh. */
|
|---|
| 457 | { "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}},
|
|---|
| 458 | { "mov", 0xfccc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 459 | { "mov", 0x240000, 0xfc0000, 0, FMT_S2, 0, {IMM16, AN0}},
|
|---|
| 460 | { "mov", 0xfcdc0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
|
|---|
| 461 | { "mov", 0xfca40000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
|
|---|
| 462 | { "mov", 0xfca00000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), AN0}},
|
|---|
| 463 | { "mov", 0xfc810000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
|
|---|
| 464 | { "mov", 0xfc800000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM(IMM32_MEM)}},
|
|---|
| 465 | { "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
|
|---|
| 466 | { "mov", 0xfcb40000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
|
|---|
| 467 | { "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
|
|---|
| 468 | { "mov", 0xfcb00000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), AN0}},
|
|---|
| 469 | { "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
|
|---|
| 470 | { "mov", 0xfc910000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
|
|---|
| 471 | { "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
|
|---|
| 472 | { "mov", 0xfc900000, 0xfff30000, 0, FMT_D4, 0, {AM1, MEM2(IMM32, SP)}},
|
|---|
| 473 | /* These non-promoting variants need to come after all the other memory
|
|---|
| 474 | moves. */
|
|---|
| 475 | { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM30, {MEM2(SD8N, AM0), SP}},
|
|---|
| 476 | { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}},
|
|---|
| 477 | /* These are the same as the previous non-promoting versions. The am33
|
|---|
| 478 | does not have restrictions on the offsets used to load/store the stack
|
|---|
| 479 | pointer. */
|
|---|
| 480 | { "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
|
|---|
| 481 | { "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
|
|---|
| 482 | /* These must come last so that we favor shorter move instructions for
|
|---|
| 483 | loading immediates into d0-d3/a0-a3. */
|
|---|
| 484 | { "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 485 | { "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 486 | { "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 487 | { "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, XRN02}},
|
|---|
| 488 | { "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, XRN02}},
|
|---|
| 489 | { "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}},
|
|---|
| 490 | { "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
|
|---|
| 491 | { "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
|
|---|
| 492 | { "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
|
|---|
| 493 | { "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
|
|---|
| 494 | { "mov", 0xfe8a0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
|
|---|
| 495 | { "mov", 0xfe9a0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
|
|---|
| 496 |
|
|---|
| 497 | { "movu", 0xfb180000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 498 | { "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 499 | { "movu", 0xfe180000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 500 |
|
|---|
| 501 | { "mcst9", 0xf630, 0xfff0, 0, FMT_D0, AM33, {DN01}},
|
|---|
| 502 | { "mcst48", 0xf660, 0xfff0, 0, FMT_D0, AM33, {DN01}},
|
|---|
| 503 | { "swap", 0xf680, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}},
|
|---|
| 504 | { "swap", 0xf9cb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 505 | { "swaph", 0xf690, 0xfff0, 0, FMT_D0, AM33, {DM1, DN0}},
|
|---|
| 506 | { "swaph", 0xf9db00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 507 | { "getchx", 0xf6c0, 0xfff0, 0, FMT_D0, AM33, {DN01}},
|
|---|
| 508 | { "getclx", 0xf6d0, 0xfff0, 0, FMT_D0, AM33, {DN01}},
|
|---|
| 509 | { "mac", 0xfb0f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
|
|---|
| 510 | { "mac", 0xf90b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 511 | { "mac", 0xfb0b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 512 | { "mac", 0xfd0b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 513 | { "mac", 0xfe0b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 514 | { "macu", 0xfb1f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
|
|---|
| 515 | { "macu", 0xf91b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 516 | { "macu", 0xfb1b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 517 | { "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 518 | { "macu", 0xfe1b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 519 | { "macb", 0xfb2f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 520 | { "macb", 0xf92b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 521 | { "macb", 0xfb2b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 522 | { "macb", 0xfd2b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 523 | { "macb", 0xfe2b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 524 | { "macbu", 0xfb3f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 525 | { "macbu", 0xf93b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 526 | { "macbu", 0xfb3b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 527 | { "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 528 | { "macbu", 0xfe3b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 529 | { "mach", 0xfb4f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
|
|---|
| 530 | { "mach", 0xf94b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 531 | { "mach", 0xfb4b0000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 532 | { "mach", 0xfd4b0000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 533 | { "mach", 0xfe4b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 534 | { "machu", 0xfb5f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
|
|---|
| 535 | { "machu", 0xf95b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 536 | { "machu", 0xfb5b0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 537 | { "machu", 0xfd5b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 538 | { "machu", 0xfe5b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 539 | { "dmach", 0xfb6f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 540 | { "dmach", 0xf96b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 541 | { "dmach", 0xfe6b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 542 | { "dmachu", 0xfb7f0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 543 | { "dmachu", 0xf97b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 544 | { "dmachu", 0xfe7b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 545 | { "dmulh", 0xfb8f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
|
|---|
| 546 | { "dmulh", 0xf98b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 547 | { "dmulh", 0xfe8b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 548 | { "dmulhu", 0xfb9f0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
|
|---|
| 549 | { "dmulhu", 0xf99b00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 550 | { "dmulhu", 0xfe9b0000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 551 | { "mcste", 0xf9bb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 552 | { "mcste", 0xfbbb0000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 553 | { "swhw", 0xf9eb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 554 |
|
|---|
| 555 | { "movbu", 0xf040, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
|
|---|
| 556 | { "movbu", 0xf84000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
|
|---|
| 557 | { "movbu", 0xfa400000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
|
|---|
| 558 | { "movbu", 0xf8b800, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}},
|
|---|
| 559 | { "movbu", 0xf8b800, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
|
|---|
| 560 | { "movbu", 0xfab80000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
|
|---|
| 561 | { "movbu", 0xf400, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
|
|---|
| 562 | { "movbu", 0x340000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
|
|---|
| 563 | { "movbu", 0xf050, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
|
|---|
| 564 | { "movbu", 0xf85000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
|
|---|
| 565 | { "movbu", 0xfa500000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
|
|---|
| 566 | { "movbu", 0xf89200, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}},
|
|---|
| 567 | { "movbu", 0xf89200, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
|
|---|
| 568 | { "movbu", 0xfa920000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
|
|---|
| 569 | { "movbu", 0xf440, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
|
|---|
| 570 | { "movbu", 0x020000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
|
|---|
| 571 | { "movbu", 0xf92a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
|
|---|
| 572 | { "movbu", 0xf93a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
|
|---|
| 573 | { "movbu", 0xf9aa00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}},
|
|---|
| 574 | { "movbu", 0xf9ba00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}},
|
|---|
| 575 | { "movbu", 0xfb2a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
|
|---|
| 576 | { "movbu", 0xfd2a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
|
|---|
| 577 | { "movbu", 0xfb3a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
|
|---|
| 578 | { "movbu", 0xfd3a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
|
|---|
| 579 | { "movbu", 0xfbaa0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
|
|---|
| 580 | { "movbu", 0xfdaa0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
|
|---|
| 581 | { "movbu", 0xfbba0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
|
|---|
| 582 | { "movbu", 0xfdba0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
|
|---|
| 583 | { "movbu", 0xfb2e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
|
|---|
| 584 | { "movbu", 0xfd2e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
|
|---|
| 585 | { "movbu", 0xfb3e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
|
|---|
| 586 | { "movbu", 0xfd3e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
|
|---|
| 587 | { "movbu", 0xfbae0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
|
|---|
| 588 | { "movbu", 0xfbbe0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
|
|---|
| 589 | { "movbu", 0xfc400000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
|
|---|
| 590 | { "movbu", 0xfcb80000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
|
|---|
| 591 | { "movbu", 0xfca80000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
|
|---|
| 592 | { "movbu", 0xfc500000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
|
|---|
| 593 | { "movbu", 0xfc920000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
|
|---|
| 594 | { "movbu", 0xfc820000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
|
|---|
| 595 | { "movbu", 0xfe2a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
|
|---|
| 596 | { "movbu", 0xfe3a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
|
|---|
| 597 | { "movbu", 0xfeaa0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,SP), RN2}},
|
|---|
| 598 | { "movbu", 0xfeba0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
|
|---|
| 599 | { "movbu", 0xfe2e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
|
|---|
| 600 | { "movbu", 0xfe3e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
|
|---|
| 601 |
|
|---|
| 602 | { "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
|
|---|
| 603 | { "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
|
|---|
| 604 | { "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
|
|---|
| 605 | { "movhu", 0xf8bc00, 0xfffcff, 0, FMT_D1, 0, {MEM(SP), DN0}},
|
|---|
| 606 | { "movhu", 0xf8bc00, 0xfffc00, 0, FMT_D1, 0, {MEM2(IMM8, SP), DN0}},
|
|---|
| 607 | { "movhu", 0xfabc0000, 0xfffc0000, 0, FMT_D2, 0, {MEM2(IMM16, SP), DN0}},
|
|---|
| 608 | { "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
|
|---|
| 609 | { "movhu", 0x380000, 0xfc0000, 0, FMT_S2, 0, {MEM(IMM16_MEM), DN0}},
|
|---|
| 610 | { "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
|
|---|
| 611 | { "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
|
|---|
| 612 | { "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
|
|---|
| 613 | { "movhu", 0xf89300, 0xfff3ff, 0, FMT_D1, 0, {DM1, MEM(SP)}},
|
|---|
| 614 | { "movhu", 0xf89300, 0xfff300, 0, FMT_D1, 0, {DM1, MEM2(IMM8, SP)}},
|
|---|
| 615 | { "movhu", 0xfa930000, 0xfff30000, 0, FMT_D2, 0, {DM1, MEM2(IMM16, SP)}},
|
|---|
| 616 | { "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
|
|---|
| 617 | { "movhu", 0x030000, 0xf30000, 0, FMT_S2, 0, {DM1, MEM(IMM16_MEM)}},
|
|---|
| 618 | { "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
|
|---|
| 619 | { "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
|
|---|
| 620 | { "movhu", 0xf9ca00, 0xffff0f, 0, FMT_D6, AM33, {MEM(SP), RN2}},
|
|---|
| 621 | { "movhu", 0xf9da00, 0xffff0f, 0, FMT_D6, AM33, {RM2, MEM(SP)}},
|
|---|
| 622 | { "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
|
|---|
| 623 | { "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
|
|---|
| 624 | { "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
|
|---|
| 625 | { "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
|
|---|
| 626 | { "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
|
|---|
| 627 | { "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
|
|---|
| 628 | { "movhu", 0xfbca0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM2(IMM8, SP), RN2}},
|
|---|
| 629 | { "movhu", 0xfdca0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
|
|---|
| 630 | { "movhu", 0xfbda0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM2(IMM8, SP)}},
|
|---|
| 631 | { "movhu", 0xfdda0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
|
|---|
| 632 | { "movhu", 0xfb4e0000, 0xffff0f00, 0, FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
|
|---|
| 633 | { "movhu", 0xfd4e0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
|
|---|
| 634 | { "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
|
|---|
| 635 | { "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
|
|---|
| 636 | { "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
|
|---|
| 637 | { "movhu", 0xfcbc0000, 0xfffc0000, 0, FMT_D4, 0, {MEM2(IMM32, SP), DN0}},
|
|---|
| 638 | { "movhu", 0xfcac0000, 0xfffc0000, 0, FMT_D4, 0, {MEM(IMM32_MEM), DN0}},
|
|---|
| 639 | { "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
|
|---|
| 640 | { "movhu", 0xfc930000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM2(IMM32, SP)}},
|
|---|
| 641 | { "movhu", 0xfc830000, 0xfff30000, 0, FMT_D4, 0, {DM1, MEM(IMM32_MEM)}},
|
|---|
| 642 | { "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
|
|---|
| 643 | { "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
|
|---|
| 644 | { "movhu", 0xfeca0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP), RN2}},
|
|---|
| 645 | { "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
|
|---|
| 646 | { "movhu", 0xfe4e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
|
|---|
| 647 | { "movhu", 0xfb5e0000, 0xffff0f00, 0, FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
|
|---|
| 648 | { "movhu", 0xfd5e0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
|
|---|
| 649 | { "movhu", 0xfe5e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},
|
|---|
| 650 | { "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
|
|---|
| 651 | { "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
|
|---|
| 652 | { "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
|
|---|
| 653 | { "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
|
|---|
| 654 | { "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
|
|---|
| 655 | { "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
|
|---|
| 656 |
|
|---|
| 657 | { "ext", 0xf2d0, 0xfffc, 0, FMT_D0, 0, {DN0}},
|
|---|
| 658 | { "ext", 0xf91800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 659 |
|
|---|
| 660 | { "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 661 | { "extb", 0x10, 0xfc, 0, FMT_S0, 0, {DN0}},
|
|---|
| 662 | { "extb", 0xf92800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 663 |
|
|---|
| 664 | { "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 665 | { "extbu", 0x14, 0xfc, 0, FMT_S0, 0, {DN0}},
|
|---|
| 666 | { "extbu", 0xf93800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 667 |
|
|---|
| 668 | { "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 669 | { "exth", 0x18, 0xfc, 0, FMT_S0, 0, {DN0}},
|
|---|
| 670 | { "exth", 0xf94800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 671 |
|
|---|
| 672 | { "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 673 | { "exthu", 0x1c, 0xfc, 0, FMT_S0, 0, {DN0}},
|
|---|
| 674 | { "exthu", 0xf95800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 675 |
|
|---|
| 676 | { "movm", 0xce00, 0xff00, 0, FMT_S1, 0, {MEM(SP), REGS}},
|
|---|
| 677 | { "movm", 0xcf00, 0xff00, 0, FMT_S1, 0, {REGS, MEM(SP)}},
|
|---|
| 678 | { "movm", 0xf8ce00, 0xffff00, 0, FMT_D1, AM33, {MEM(USP), REGS}},
|
|---|
| 679 | { "movm", 0xf8cf00, 0xffff00, 0, FMT_D1, AM33, {REGS, MEM(USP)}},
|
|---|
| 680 |
|
|---|
| 681 | { "clr", 0x00, 0xf3, 0, FMT_S0, 0, {DN1}},
|
|---|
| 682 | { "clr", 0xf96800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 683 |
|
|---|
| 684 | { "add", 0xfb7c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 685 | { "add", 0xe0, 0xf0, 0, FMT_S0, 0, {DM1, DN0}},
|
|---|
| 686 | { "add", 0xf160, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
|
|---|
| 687 | { "add", 0xf150, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
|
|---|
| 688 | { "add", 0xf170, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
|
|---|
| 689 | { "add", 0x2800, 0xfc00, 0, FMT_S1, 0, {SIMM8, DN0}},
|
|---|
| 690 | { "add", 0xfac00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 691 | { "add", 0x2000, 0xfc00, 0, FMT_S1, 0, {SIMM8, AN0}},
|
|---|
| 692 | { "add", 0xfad00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, AN0}},
|
|---|
| 693 | { "add", 0xf8fe00, 0xffff00, 0, FMT_D1, 0, {SIMM8, SP}},
|
|---|
| 694 | { "add", 0xfafe0000, 0xffff0000, 0, FMT_D2, 0, {SIMM16, SP}},
|
|---|
| 695 | { "add", 0xf97800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 696 | { "add", 0xfcc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 697 | { "add", 0xfcd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
|
|---|
| 698 | { "add", 0xfcfe0000, 0xffff0000, 0, FMT_D4, 0, {IMM32, SP}},
|
|---|
| 699 | { "add", 0xfb780000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 700 | { "add", 0xfd780000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 701 | { "add", 0xfe780000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 702 |
|
|---|
| 703 | { "addc", 0xfb8c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 704 | { "addc", 0xf140, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 705 | { "addc", 0xf98800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 706 | { "addc", 0xfb880000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 707 | { "addc", 0xfd880000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 708 | { "addc", 0xfe880000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 709 |
|
|---|
| 710 | { "sub", 0xfb9c0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 711 | { "sub", 0xf100, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 712 | { "sub", 0xf120, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
|
|---|
| 713 | { "sub", 0xf110, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
|
|---|
| 714 | { "sub", 0xf130, 0xfff0, 0, FMT_D0, 0, {AM1, AN0}},
|
|---|
| 715 | { "sub", 0xf99800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 716 | { "sub", 0xfcc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 717 | { "sub", 0xfcd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
|
|---|
| 718 | { "sub", 0xfb980000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 719 | { "sub", 0xfd980000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 720 | { "sub", 0xfe980000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 721 |
|
|---|
| 722 | { "subc", 0xfbac0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 723 | { "subc", 0xf180, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 724 | { "subc", 0xf9a800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 725 | { "subc", 0xfba80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 726 | { "subc", 0xfda80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 727 | { "subc", 0xfea80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 728 |
|
|---|
| 729 | { "mul", 0xfbad0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
|
|---|
| 730 | { "mul", 0xf240, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 731 | { "mul", 0xf9a900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 732 | { "mul", 0xfba90000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 733 | { "mul", 0xfda90000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 734 | { "mul", 0xfea90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 735 |
|
|---|
| 736 | { "mulu", 0xfbbd0000, 0xffff0000, 0xc, FMT_D7, AM33, {RM2, RN0, RD2, RD0}},
|
|---|
| 737 | { "mulu", 0xf250, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 738 | { "mulu", 0xf9b900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 739 | { "mulu", 0xfbb90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 740 | { "mulu", 0xfdb90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 741 | { "mulu", 0xfeb90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 742 |
|
|---|
| 743 | { "div", 0xf260, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 744 | { "div", 0xf9c900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 745 |
|
|---|
| 746 | { "divu", 0xf270, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 747 | { "divu", 0xf9d900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 748 |
|
|---|
| 749 | { "inc", 0x40, 0xf3, 0, FMT_S0, 0, {DN1}},
|
|---|
| 750 | { "inc", 0x41, 0xf3, 0, FMT_S0, 0, {AN1}},
|
|---|
| 751 | { "inc", 0xf9b800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 752 |
|
|---|
| 753 | { "inc4", 0x50, 0xfc, 0, FMT_S0, 0, {AN0}},
|
|---|
| 754 | { "inc4", 0xf9c800, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 755 |
|
|---|
| 756 | { "cmp", 0xa000, 0xf000, 0, FMT_S1, 0, {SIMM8, DN01}},
|
|---|
| 757 | { "cmp", 0xa0, 0xf0, 0x3, FMT_S0, 0, {DM1, DN0}},
|
|---|
| 758 | { "cmp", 0xf1a0, 0xfff0, 0, FMT_D0, 0, {DM1, AN0}},
|
|---|
| 759 | { "cmp", 0xf190, 0xfff0, 0, FMT_D0, 0, {AM1, DN0}},
|
|---|
| 760 | { "cmp", 0xb000, 0xf000, 0, FMT_S1, 0, {IMM8, AN01}},
|
|---|
| 761 | { "cmp", 0xb0, 0xf0, 0x3, FMT_S0, 0, {AM1, AN0}},
|
|---|
| 762 | { "cmp", 0xfac80000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 763 | { "cmp", 0xfad80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, AN0}},
|
|---|
| 764 | { "cmp", 0xf9d800, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 765 | { "cmp", 0xfcc80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 766 | { "cmp", 0xfcd80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, AN0}},
|
|---|
| 767 | { "cmp", 0xfbd80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 768 | { "cmp", 0xfdd80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
|
|---|
| 769 | { "cmp", 0xfed80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 770 |
|
|---|
| 771 | { "and", 0xfb0d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 772 | { "and", 0xf200, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 773 | { "and", 0xf8e000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 774 | { "and", 0xfae00000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 775 | { "and", 0xfafc0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
|
|---|
| 776 | { "and", 0xfcfc0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}},
|
|---|
| 777 | { "and", 0xf90900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 778 | { "and", 0xfce00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 779 | { "and", 0xfb090000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 780 | { "and", 0xfd090000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 781 | { "and", 0xfe090000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 782 |
|
|---|
| 783 | { "or", 0xfb1d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 784 | { "or", 0xf210, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 785 | { "or", 0xf8e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 786 | { "or", 0xfae40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 787 | { "or", 0xfafd0000, 0xffff0000, 0, FMT_D2, 0, {IMM16, PSW}},
|
|---|
| 788 | { "or", 0xfcfd0000, 0xffff0000, 0, FMT_D4, AM33, {IMM32, EPSW}},
|
|---|
| 789 | { "or", 0xf91900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 790 | { "or", 0xfce40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 791 | { "or", 0xfb190000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 792 | { "or", 0xfd190000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 793 | { "or", 0xfe190000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 794 |
|
|---|
| 795 | { "xor", 0xfb2d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 796 | { "xor", 0xf220, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 797 | { "xor", 0xfae80000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 798 | { "xor", 0xf92900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 799 | { "xor", 0xfce80000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 800 | { "xor", 0xfb290000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 801 | { "xor", 0xfd290000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 802 | { "xor", 0xfe290000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 803 |
|
|---|
| 804 | { "not", 0xf230, 0xfffc, 0, FMT_D0, 0, {DN0}},
|
|---|
| 805 | { "not", 0xf93900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 806 |
|
|---|
| 807 | { "btst", 0xf8ec00, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 808 | { "btst", 0xfaec0000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 809 | { "btst", 0xfcec0000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 810 | /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
|
|---|
| 811 | them to match last since they do not promote. */
|
|---|
| 812 | { "btst", 0xfbe90000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 813 | { "btst", 0xfde90000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 814 | { "btst", 0xfee90000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 815 | { "btst", 0xfe020000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
|
|---|
| 816 | { "btst", 0xfaf80000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
|
|---|
| 817 |
|
|---|
| 818 | { "bset", 0xf080, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
|
|---|
| 819 | { "bset", 0xfe000000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
|
|---|
| 820 | { "bset", 0xfaf00000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8, AN0)}},
|
|---|
| 821 |
|
|---|
| 822 | { "bclr", 0xf090, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
|
|---|
| 823 | { "bclr", 0xfe010000, 0xffff0000, 0, FMT_D5, 0, {IMM8E, MEM(IMM32_LOWSHIFT8)}},
|
|---|
| 824 | { "bclr", 0xfaf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
|
|---|
| 825 |
|
|---|
| 826 | { "asr", 0xfb4d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 827 | { "asr", 0xf2b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 828 | { "asr", 0xf8c800, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 829 | { "asr", 0xf94900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 830 | { "asr", 0xfb490000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 831 | { "asr", 0xfd490000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 832 | { "asr", 0xfe490000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 833 | { "asr", 0xf8c801, 0xfffcff, 0, FMT_D1, 0, {DN0}},
|
|---|
| 834 | { "asr", 0xfb490001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
|
|---|
| 835 |
|
|---|
| 836 | { "lsr", 0xfb5d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 837 | { "lsr", 0xf2a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 838 | { "lsr", 0xf8c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 839 | { "lsr", 0xf95900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 840 | { "lsr", 0xfb590000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, RN02}},
|
|---|
| 841 | { "lsr", 0xfd590000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 842 | { "lsr", 0xfe590000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 843 | { "lsr", 0xf8c401, 0xfffcff, 0, FMT_D1, 0, {DN0}},
|
|---|
| 844 | { "lsr", 0xfb590001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
|
|---|
| 845 |
|
|---|
| 846 | { "asl", 0xfb6d0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 847 | { "asl", 0xf290, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 848 | { "asl", 0xf8c000, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 849 | { "asl", 0xf96900, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 850 | { "asl", 0xfb690000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
|
|---|
| 851 | { "asl", 0xfd690000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
|
|---|
| 852 | { "asl", 0xfe690000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
|
|---|
| 853 | { "asl", 0xf8c001, 0xfffcff, 0, FMT_D1, 0, {DN0}},
|
|---|
| 854 | { "asl", 0xfb690001, 0xffff00ff, 0, FMT_D7, AM33, {RN02}},
|
|---|
| 855 |
|
|---|
| 856 | { "asl2", 0x54, 0xfc, 0, FMT_S0, 0, {DN0}},
|
|---|
| 857 | { "asl2", 0xf97900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 858 |
|
|---|
| 859 | { "ror", 0xf284, 0xfffc, 0, FMT_D0, 0, {DN0}},
|
|---|
| 860 | { "ror", 0xf98900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 861 |
|
|---|
| 862 | { "rol", 0xf280, 0xfffc, 0, FMT_D0, 0, {DN0}},
|
|---|
| 863 | { "rol", 0xf99900, 0xffff00, 0, FMT_D6, AM33, {RN02}},
|
|---|
| 864 |
|
|---|
| 865 | { "beq", 0xc800, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 866 | { "bne", 0xc900, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 867 | { "bgt", 0xc100, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 868 | { "bge", 0xc200, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 869 | { "ble", 0xc300, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 870 | { "blt", 0xc000, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 871 | { "bhi", 0xc500, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 872 | { "bcc", 0xc600, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 873 | { "bls", 0xc700, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 874 | { "bcs", 0xc400, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 875 | { "bvc", 0xf8e800, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}},
|
|---|
| 876 | { "bvs", 0xf8e900, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}},
|
|---|
| 877 | { "bnc", 0xf8ea00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}},
|
|---|
| 878 | { "bns", 0xf8eb00, 0xffff00, 0, FMT_D1, 0, {SD8N_PCREL}},
|
|---|
| 879 | { "bra", 0xca00, 0xff00, 0, FMT_S1, 0, {SD8N_PCREL}},
|
|---|
| 880 |
|
|---|
| 881 | { "leq", 0xd8, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 882 | { "lne", 0xd9, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 883 | { "lgt", 0xd1, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 884 | { "lge", 0xd2, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 885 | { "lle", 0xd3, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 886 | { "llt", 0xd0, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 887 | { "lhi", 0xd5, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 888 | { "lcc", 0xd6, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 889 | { "lls", 0xd7, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 890 | { "lcs", 0xd4, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 891 | { "lra", 0xda, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 892 | { "setlb", 0xdb, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 893 |
|
|---|
| 894 | { "jmp", 0xf0f4, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}},
|
|---|
| 895 | { "jmp", 0xcc0000, 0xff0000, 0, FMT_S2, 0, {IMM16_PCREL}},
|
|---|
| 896 | { "jmp", 0xdc000000, 0xff000000, 0, FMT_S4, 0, {IMM32_HIGH24}},
|
|---|
| 897 | { "call", 0xcd000000, 0xff000000, 0, FMT_S4, 0, {D16_SHIFT,REGS,IMM8E}},
|
|---|
| 898 | { "call", 0xdd000000, 0xff000000, 0, FMT_S6, 0, {IMM32_HIGH24_LOWSHIFT16, REGSE_SHIFT8,IMM8E}},
|
|---|
| 899 | { "calls", 0xf0f0, 0xfffc, 0, FMT_D0, 0, {PAREN,AN0,PAREN}},
|
|---|
| 900 | { "calls", 0xfaff0000, 0xffff0000, 0, FMT_D2, 0, {IMM16_PCREL}},
|
|---|
| 901 | { "calls", 0xfcff0000, 0xffff0000, 0, FMT_D4, 0, {IMM32_PCREL}},
|
|---|
| 902 |
|
|---|
| 903 | { "ret", 0xdf0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}},
|
|---|
| 904 | { "retf", 0xde0000, 0xff0000, 0, FMT_S2, 0, {REGS_SHIFT8, IMM8}},
|
|---|
| 905 | { "rets", 0xf0fc, 0xffff, 0, FMT_D0, 0, {UNUSED}},
|
|---|
| 906 | { "rti", 0xf0fd, 0xffff, 0, FMT_D0, 0, {UNUSED}},
|
|---|
| 907 | { "trap", 0xf0fe, 0xffff, 0, FMT_D0, 0, {UNUSED}},
|
|---|
| 908 | { "rtm", 0xf0ff, 0xffff, 0, FMT_D0, 0, {UNUSED}},
|
|---|
| 909 | { "nop", 0xcb, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 910 |
|
|---|
| 911 | /* UDF instructions. */
|
|---|
| 912 | { "udf00", 0xf600, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 913 | { "udf00", 0xf90000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 914 | { "udf00", 0xfb000000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 915 | { "udf00", 0xfd000000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 916 | { "udf01", 0xf610, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 917 | { "udf01", 0xf91000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 918 | { "udf01", 0xfb100000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 919 | { "udf01", 0xfd100000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 920 | { "udf02", 0xf620, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 921 | { "udf02", 0xf92000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 922 | { "udf02", 0xfb200000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 923 | { "udf02", 0xfd200000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 924 | { "udf03", 0xf630, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 925 | { "udf03", 0xf93000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 926 | { "udf03", 0xfb300000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 927 | { "udf03", 0xfd300000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 928 | { "udf04", 0xf640, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 929 | { "udf04", 0xf94000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 930 | { "udf04", 0xfb400000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 931 | { "udf04", 0xfd400000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 932 | { "udf05", 0xf650, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 933 | { "udf05", 0xf95000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 934 | { "udf05", 0xfb500000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 935 | { "udf05", 0xfd500000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 936 | { "udf06", 0xf660, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 937 | { "udf06", 0xf96000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 938 | { "udf06", 0xfb600000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 939 | { "udf06", 0xfd600000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 940 | { "udf07", 0xf670, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 941 | { "udf07", 0xf97000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 942 | { "udf07", 0xfb700000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 943 | { "udf07", 0xfd700000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 944 | { "udf08", 0xf680, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 945 | { "udf08", 0xf98000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 946 | { "udf08", 0xfb800000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 947 | { "udf08", 0xfd800000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 948 | { "udf09", 0xf690, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 949 | { "udf09", 0xf99000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 950 | { "udf09", 0xfb900000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 951 | { "udf09", 0xfd900000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 952 | { "udf10", 0xf6a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 953 | { "udf10", 0xf9a000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 954 | { "udf10", 0xfba00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 955 | { "udf10", 0xfda00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 956 | { "udf11", 0xf6b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 957 | { "udf11", 0xf9b000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 958 | { "udf11", 0xfbb00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 959 | { "udf11", 0xfdb00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 960 | { "udf12", 0xf6c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 961 | { "udf12", 0xf9c000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 962 | { "udf12", 0xfbc00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 963 | { "udf12", 0xfdc00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 964 | { "udf13", 0xf6d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 965 | { "udf13", 0xf9d000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 966 | { "udf13", 0xfbd00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 967 | { "udf13", 0xfdd00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 968 | { "udf14", 0xf6e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 969 | { "udf14", 0xf9e000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 970 | { "udf14", 0xfbe00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 971 | { "udf14", 0xfde00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 972 | { "udf15", 0xf6f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 973 | { "udf15", 0xf9f000, 0xfffc00, 0, FMT_D1, 0, {SIMM8, DN0}},
|
|---|
| 974 | { "udf15", 0xfbf00000, 0xfffc0000, 0, FMT_D2, 0, {SIMM16, DN0}},
|
|---|
| 975 | { "udf15", 0xfdf00000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 976 | { "udf20", 0xf500, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 977 | { "udf21", 0xf510, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 978 | { "udf22", 0xf520, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 979 | { "udf23", 0xf530, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 980 | { "udf24", 0xf540, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 981 | { "udf25", 0xf550, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 982 | { "udf26", 0xf560, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 983 | { "udf27", 0xf570, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 984 | { "udf28", 0xf580, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 985 | { "udf29", 0xf590, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 986 | { "udf30", 0xf5a0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 987 | { "udf31", 0xf5b0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 988 | { "udf32", 0xf5c0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 989 | { "udf33", 0xf5d0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 990 | { "udf34", 0xf5e0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 991 | { "udf35", 0xf5f0, 0xfff0, 0, FMT_D0, 0, {DM1, DN0}},
|
|---|
| 992 | { "udfu00", 0xf90400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 993 | { "udfu00", 0xfb040000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 994 | { "udfu00", 0xfd040000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 995 | { "udfu01", 0xf91400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 996 | { "udfu01", 0xfb140000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 997 | { "udfu01", 0xfd140000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 998 | { "udfu02", 0xf92400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 999 | { "udfu02", 0xfb240000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1000 | { "udfu02", 0xfd240000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1001 | { "udfu03", 0xf93400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1002 | { "udfu03", 0xfb340000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1003 | { "udfu03", 0xfd340000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1004 | { "udfu04", 0xf94400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1005 | { "udfu04", 0xfb440000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1006 | { "udfu04", 0xfd440000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1007 | { "udfu05", 0xf95400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1008 | { "udfu05", 0xfb540000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1009 | { "udfu05", 0xfd540000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1010 | { "udfu06", 0xf96400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1011 | { "udfu06", 0xfb640000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1012 | { "udfu06", 0xfd640000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1013 | { "udfu07", 0xf97400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1014 | { "udfu07", 0xfb740000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1015 | { "udfu07", 0xfd740000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1016 | { "udfu08", 0xf98400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1017 | { "udfu08", 0xfb840000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1018 | { "udfu08", 0xfd840000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1019 | { "udfu09", 0xf99400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1020 | { "udfu09", 0xfb940000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1021 | { "udfu09", 0xfd940000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1022 | { "udfu10", 0xf9a400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1023 | { "udfu10", 0xfba40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1024 | { "udfu10", 0xfda40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1025 | { "udfu11", 0xf9b400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1026 | { "udfu11", 0xfbb40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1027 | { "udfu11", 0xfdb40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1028 | { "udfu12", 0xf9c400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1029 | { "udfu12", 0xfbc40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1030 | { "udfu12", 0xfdc40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1031 | { "udfu13", 0xf9d400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1032 | { "udfu13", 0xfbd40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1033 | { "udfu13", 0xfdd40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1034 | { "udfu14", 0xf9e400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1035 | { "udfu14", 0xfbe40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1036 | { "udfu14", 0xfde40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1037 | { "udfu15", 0xf9f400, 0xfffc00, 0, FMT_D1, 0, {IMM8, DN0}},
|
|---|
| 1038 | { "udfu15", 0xfbf40000, 0xfffc0000, 0, FMT_D2, 0, {IMM16, DN0}},
|
|---|
| 1039 | { "udfu15", 0xfdf40000, 0xfffc0000, 0, FMT_D4, 0, {IMM32, DN0}},
|
|---|
| 1040 |
|
|---|
| 1041 | { "putx", 0xf500, 0xfff0, 0, FMT_D0, AM30, {DN01}},
|
|---|
| 1042 | { "getx", 0xf6f0, 0xfff0, 0, FMT_D0, AM30, {DN01}},
|
|---|
| 1043 | { "mulq", 0xf600, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
|
|---|
| 1044 | { "mulq", 0xf90000, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}},
|
|---|
| 1045 | { "mulq", 0xfb000000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}},
|
|---|
| 1046 | { "mulq", 0xfd000000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}},
|
|---|
| 1047 | { "mulqu", 0xf610, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
|
|---|
| 1048 | { "mulqu", 0xf91400, 0xfffc00, 0, FMT_D1, AM30, {SIMM8, DN0}},
|
|---|
| 1049 | { "mulqu", 0xfb140000, 0xfffc0000, 0, FMT_D2, AM30, {SIMM16, DN0}},
|
|---|
| 1050 | { "mulqu", 0xfd140000, 0xfffc0000, 0, FMT_D4, AM30, {IMM32, DN0}},
|
|---|
| 1051 | { "sat16", 0xf640, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
|
|---|
| 1052 | { "sat16", 0xf9ab00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 1053 |
|
|---|
| 1054 | { "sat24", 0xf650, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
|
|---|
| 1055 | { "sat24", 0xfbaf0000, 0xffff00ff, 0, FMT_D7, AM33, {RM2, RN0}},
|
|---|
| 1056 |
|
|---|
| 1057 | { "bsch", 0xfbff0000, 0xffff000f, 0, FMT_D7, AM33, {RM2, RN0, RD2}},
|
|---|
| 1058 | { "bsch", 0xf670, 0xfff0, 0, FMT_D0, AM30, {DM1, DN0}},
|
|---|
| 1059 | { "bsch", 0xf9fb00, 0xffff00, 0, FMT_D6, AM33, {RM2, RN0}},
|
|---|
| 1060 |
|
|---|
| 1061 | /* Extension. We need some instruction to trigger "emulated syscalls"
|
|---|
| 1062 | for our simulator. */
|
|---|
| 1063 | { "syscall", 0xf0e0, 0xfff0, 0, FMT_D0, AM33, {IMM4}},
|
|---|
| 1064 | { "syscall", 0xf0c0, 0xffff, 0, FMT_D0, 0, {UNUSED}},
|
|---|
| 1065 |
|
|---|
| 1066 | /* Extension. When talking to the simulator, gdb requires some instruction
|
|---|
| 1067 | that will trigger a "breakpoint" (really just an instruction that isn't
|
|---|
| 1068 | otherwise used by the tools. This instruction must be the same size
|
|---|
| 1069 | as the smallest instruction on the target machine. In the case of the
|
|---|
| 1070 | mn10x00 the "break" instruction must be one byte. 0xff is available on
|
|---|
| 1071 | both mn10x00 architectures. */
|
|---|
| 1072 | { "break", 0xff, 0xff, 0, FMT_S0, 0, {UNUSED}},
|
|---|
| 1073 |
|
|---|
| 1074 | { "add_add", 0xf7000000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1075 | { "add_add", 0xf7100000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1076 | { "add_add", 0xf7040000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1077 | { "add_add", 0xf7140000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1078 | { "add_sub", 0xf7200000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1079 | { "add_sub", 0xf7300000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1080 | { "add_sub", 0xf7240000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1081 | { "add_sub", 0xf7340000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1082 | { "add_cmp", 0xf7400000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1083 | { "add_cmp", 0xf7500000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1084 | { "add_cmp", 0xf7440000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1085 | { "add_cmp", 0xf7540000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1086 | { "add_mov", 0xf7600000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1087 | { "add_mov", 0xf7700000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1088 | { "add_mov", 0xf7640000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1089 | { "add_mov", 0xf7740000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1090 | { "add_asr", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1091 | { "add_asr", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1092 | { "add_asr", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1093 | { "add_asr", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1094 | { "add_lsr", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1095 | { "add_lsr", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1096 | { "add_lsr", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1097 | { "add_lsr", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1098 | { "add_asl", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1099 | { "add_asl", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1100 | { "add_asl", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1101 | { "add_asl", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1102 | { "cmp_add", 0xf7010000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1103 | { "cmp_add", 0xf7110000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1104 | { "cmp_add", 0xf7050000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1105 | { "cmp_add", 0xf7150000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1106 | { "cmp_sub", 0xf7210000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1107 | { "cmp_sub", 0xf7310000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1108 | { "cmp_sub", 0xf7250000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1109 | { "cmp_sub", 0xf7350000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1110 | { "cmp_mov", 0xf7610000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1111 | { "cmp_mov", 0xf7710000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1112 | { "cmp_mov", 0xf7650000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1113 | { "cmp_mov", 0xf7750000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1114 | { "cmp_asr", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1115 | { "cmp_asr", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1116 | { "cmp_asr", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1117 | { "cmp_asr", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1118 | { "cmp_lsr", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1119 | { "cmp_lsr", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1120 | { "cmp_lsr", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1121 | { "cmp_lsr", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1122 | { "cmp_asl", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1123 | { "cmp_asl", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1124 | { "cmp_asl", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1125 | { "cmp_asl", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1126 | { "sub_add", 0xf7020000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1127 | { "sub_add", 0xf7120000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1128 | { "sub_add", 0xf7060000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1129 | { "sub_add", 0xf7160000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1130 | { "sub_sub", 0xf7220000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1131 | { "sub_sub", 0xf7320000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1132 | { "sub_sub", 0xf7260000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1133 | { "sub_sub", 0xf7360000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1134 | { "sub_cmp", 0xf7420000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1135 | { "sub_cmp", 0xf7520000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1136 | { "sub_cmp", 0xf7460000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1137 | { "sub_cmp", 0xf7560000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1138 | { "sub_mov", 0xf7620000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1139 | { "sub_mov", 0xf7720000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1140 | { "sub_mov", 0xf7660000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1141 | { "sub_mov", 0xf7760000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1142 | { "sub_asr", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1143 | { "sub_asr", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1144 | { "sub_asr", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1145 | { "sub_asr", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1146 | { "sub_lsr", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1147 | { "sub_lsr", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1148 | { "sub_lsr", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1149 | { "sub_lsr", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1150 | { "sub_asl", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1151 | { "sub_asl", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1152 | { "sub_asl", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1153 | { "sub_asl", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1154 | { "mov_add", 0xf7030000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1155 | { "mov_add", 0xf7130000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1156 | { "mov_add", 0xf7070000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1157 | { "mov_add", 0xf7170000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1158 | { "mov_sub", 0xf7230000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1159 | { "mov_sub", 0xf7330000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1160 | { "mov_sub", 0xf7270000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1161 | { "mov_sub", 0xf7370000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1162 | { "mov_cmp", 0xf7430000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1163 | { "mov_cmp", 0xf7530000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1164 | { "mov_cmp", 0xf7470000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1165 | { "mov_cmp", 0xf7570000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1166 | { "mov_mov", 0xf7630000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1167 | { "mov_mov", 0xf7730000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1168 | { "mov_mov", 0xf7670000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1169 | { "mov_mov", 0xf7770000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, SIMM4_2, RN0}},
|
|---|
| 1170 | { "mov_asr", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1171 | { "mov_asr", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1172 | { "mov_asr", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1173 | { "mov_asr", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1174 | { "mov_lsr", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1175 | { "mov_lsr", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1176 | { "mov_lsr", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1177 | { "mov_lsr", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1178 | { "mov_asl", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1179 | { "mov_asl", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1180 | { "mov_asl", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, RM2, RN0}},
|
|---|
| 1181 | { "mov_asl", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_6, RN4, IMM4_2, RN0}},
|
|---|
| 1182 | { "and_add", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1183 | { "and_add", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1184 | { "and_sub", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1185 | { "and_sub", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1186 | { "and_cmp", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1187 | { "and_cmp", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1188 | { "and_mov", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1189 | { "and_mov", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1190 | { "and_asr", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1191 | { "and_asr", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1192 | { "and_lsr", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1193 | { "and_lsr", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1194 | { "and_asl", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1195 | { "and_asl", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1196 | { "dmach_add", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1197 | { "dmach_add", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1198 | { "dmach_sub", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1199 | { "dmach_sub", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1200 | { "dmach_cmp", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1201 | { "dmach_cmp", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1202 | { "dmach_mov", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1203 | { "dmach_mov", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1204 | { "dmach_asr", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1205 | { "dmach_asr", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1206 | { "dmach_lsr", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1207 | { "dmach_lsr", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1208 | { "dmach_asl", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1209 | { "dmach_asl", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1210 | { "xor_add", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1211 | { "xor_add", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1212 | { "xor_sub", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1213 | { "xor_sub", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1214 | { "xor_cmp", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1215 | { "xor_cmp", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1216 | { "xor_mov", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1217 | { "xor_mov", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1218 | { "xor_asr", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1219 | { "xor_asr", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1220 | { "xor_lsr", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1221 | { "xor_lsr", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1222 | { "xor_asl", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1223 | { "xor_asl", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1224 | { "swhw_add", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1225 | { "swhw_add", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1226 | { "swhw_sub", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1227 | { "swhw_sub", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1228 | { "swhw_cmp", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1229 | { "swhw_cmp", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1230 | { "swhw_mov", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1231 | { "swhw_mov", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1232 | { "swhw_asr", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1233 | { "swhw_asr", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1234 | { "swhw_lsr", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1235 | { "swhw_lsr", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1236 | { "swhw_asl", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1237 | { "swhw_asl", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1238 | { "or_add", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1239 | { "or_add", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1240 | { "or_sub", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1241 | { "or_sub", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1242 | { "or_cmp", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1243 | { "or_cmp", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1244 | { "or_mov", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1245 | { "or_mov", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1246 | { "or_asr", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1247 | { "or_asr", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1248 | { "or_lsr", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1249 | { "or_lsr", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1250 | { "or_asl", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1251 | { "or_asl", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1252 | { "sat16_add", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1253 | { "sat16_add", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1254 | { "sat16_sub", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1255 | { "sat16_sub", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1256 | { "sat16_cmp", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1257 | { "sat16_cmp", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1258 | { "sat16_mov", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1259 | { "sat16_mov", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, SIMM4_2, RN0}},
|
|---|
| 1260 | { "sat16_asr", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1261 | { "sat16_asr", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1262 | { "sat16_lsr", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1263 | { "sat16_lsr", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1264 | { "sat16_asl", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, RM2, RN0}},
|
|---|
| 1265 | { "sat16_asl", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM6, RN4, IMM4_2, RN0}},
|
|---|
| 1266 | /* Ugh. Synthetic instructions. */
|
|---|
| 1267 | { "add_and", 0xf7080000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1268 | { "add_and", 0xf7180000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1269 | { "add_dmach", 0xf7090000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1270 | { "add_dmach", 0xf7190000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1271 | { "add_or", 0xf70c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1272 | { "add_or", 0xf71c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1273 | { "add_sat16", 0xf70d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1274 | { "add_sat16", 0xf71d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1275 | { "add_swhw", 0xf70b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1276 | { "add_swhw", 0xf71b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1277 | { "add_xor", 0xf70a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1278 | { "add_xor", 0xf71a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1279 | { "asl_add", 0xf7c00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1280 | { "asl_add", 0xf7d00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1281 | { "asl_add", 0xf7c40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1282 | { "asl_add", 0xf7d40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1283 | { "asl_and", 0xf7c80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1284 | { "asl_and", 0xf7d80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1285 | { "asl_cmp", 0xf7c10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1286 | { "asl_cmp", 0xf7d10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }},
|
|---|
| 1287 | { "asl_cmp", 0xf7c50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1288 | { "asl_cmp", 0xf7d50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1289 | { "asl_dmach", 0xf7c90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1290 | { "asl_dmach", 0xf7d90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1291 | { "asl_mov", 0xf7c30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1292 | { "asl_mov", 0xf7d30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1293 | { "asl_mov", 0xf7c70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1294 | { "asl_mov", 0xf7d70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1295 | { "asl_or", 0xf7cc0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1296 | { "asl_or", 0xf7dc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1297 | { "asl_sat16", 0xf7cd0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1298 | { "asl_sat16", 0xf7dd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1299 | { "asl_sub", 0xf7c20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1300 | { "asl_sub", 0xf7d20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1301 | { "asl_sub", 0xf7c60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1302 | { "asl_sub", 0xf7d60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1303 | { "asl_swhw", 0xf7cb0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1304 | { "asl_swhw", 0xf7db0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1305 | { "asl_xor", 0xf7ca0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1306 | { "asl_xor", 0xf7da0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1307 | { "asr_add", 0xf7800000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1308 | { "asr_add", 0xf7900000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1309 | { "asr_add", 0xf7840000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1310 | { "asr_add", 0xf7940000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1311 | { "asr_and", 0xf7880000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1312 | { "asr_and", 0xf7980000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1313 | { "asr_cmp", 0xf7810000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1314 | { "asr_cmp", 0xf7910000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }},
|
|---|
| 1315 | { "asr_cmp", 0xf7850000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1316 | { "asr_cmp", 0xf7950000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1317 | { "asr_dmach", 0xf7890000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1318 | { "asr_dmach", 0xf7990000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1319 | { "asr_mov", 0xf7830000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1320 | { "asr_mov", 0xf7930000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1321 | { "asr_mov", 0xf7870000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1322 | { "asr_mov", 0xf7970000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1323 | { "asr_or", 0xf78c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1324 | { "asr_or", 0xf79c0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1325 | { "asr_sat16", 0xf78d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1326 | { "asr_sat16", 0xf79d0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1327 | { "asr_sub", 0xf7820000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1328 | { "asr_sub", 0xf7920000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1329 | { "asr_sub", 0xf7860000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1330 | { "asr_sub", 0xf7960000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1331 | { "asr_swhw", 0xf78b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1332 | { "asr_swhw", 0xf79b0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1333 | { "asr_xor", 0xf78a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1334 | { "asr_xor", 0xf79a0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1335 | { "cmp_and", 0xf7480000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1336 | { "cmp_and", 0xf7580000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1337 | { "cmp_dmach", 0xf7490000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1338 | { "cmp_dmach", 0xf7590000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1339 | { "cmp_or", 0xf74c0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1340 | { "cmp_or", 0xf75c0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1341 | { "cmp_sat16", 0xf74d0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1342 | { "cmp_sat16", 0xf75d0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1343 | { "cmp_swhw", 0xf74b0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1344 | { "cmp_swhw", 0xf75b0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1345 | { "cmp_xor", 0xf74a0000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1346 | { "cmp_xor", 0xf75a0000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1347 | { "lsr_add", 0xf7a00000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1348 | { "lsr_add", 0xf7b00000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1349 | { "lsr_add", 0xf7a40000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1350 | { "lsr_add", 0xf7b40000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1351 | { "lsr_and", 0xf7a80000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1352 | { "lsr_and", 0xf7b80000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1353 | { "lsr_cmp", 0xf7a10000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1354 | { "lsr_cmp", 0xf7b10000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4, }},
|
|---|
| 1355 | { "lsr_cmp", 0xf7a50000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1356 | { "lsr_cmp", 0xf7b50000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1357 | { "lsr_dmach", 0xf7a90000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1358 | { "lsr_dmach", 0xf7b90000, 0xffff0000, 0x0, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1359 | { "lsr_mov", 0xf7a30000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1360 | { "lsr_mov", 0xf7b30000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1361 | { "lsr_mov", 0xf7a70000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1362 | { "lsr_mov", 0xf7b70000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1363 | { "lsr_or", 0xf7ac0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1364 | { "lsr_or", 0xf7bc0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1365 | { "lsr_sat16", 0xf7ad0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1366 | { "lsr_sat16", 0xf7bd0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1367 | { "lsr_sub", 0xf7a20000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1368 | { "lsr_sub", 0xf7b20000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1369 | { "lsr_sub", 0xf7a60000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, SIMM4_6, RN4}},
|
|---|
| 1370 | { "lsr_sub", 0xf7b60000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, SIMM4_6, RN4}},
|
|---|
| 1371 | { "lsr_swhw", 0xf7ab0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1372 | { "lsr_swhw", 0xf7bb0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1373 | { "lsr_xor", 0xf7aa0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1374 | { "lsr_xor", 0xf7ba0000, 0xffff0000, 0xa, FMT_D10, AM33, {IMM4_2, RN0, RM6, RN4}},
|
|---|
| 1375 | { "mov_and", 0xf7680000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1376 | { "mov_and", 0xf7780000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1377 | { "mov_dmach", 0xf7690000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1378 | { "mov_dmach", 0xf7790000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1379 | { "mov_or", 0xf76c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1380 | { "mov_or", 0xf77c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1381 | { "mov_sat16", 0xf76d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1382 | { "mov_sat16", 0xf77d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1383 | { "mov_swhw", 0xf76b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1384 | { "mov_swhw", 0xf77b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1385 | { "mov_xor", 0xf76a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1386 | { "mov_xor", 0xf77a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1387 | { "sub_and", 0xf7280000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1388 | { "sub_and", 0xf7380000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1389 | { "sub_dmach", 0xf7290000, 0xffff0000, 0x0, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1390 | { "sub_dmach", 0xf7390000, 0xffff0000, 0x0, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1391 | { "sub_or", 0xf72c0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1392 | { "sub_or", 0xf73c0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1393 | { "sub_sat16", 0xf72d0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1394 | { "sub_sat16", 0xf73d0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1395 | { "sub_swhw", 0xf72b0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1396 | { "sub_swhw", 0xf73b0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1397 | { "sub_xor", 0xf72a0000, 0xffff0000, 0xa, FMT_D10, AM33, {RM2, RN0, RM6, RN4}},
|
|---|
| 1398 | { "sub_xor", 0xf73a0000, 0xffff0000, 0xa, FMT_D10, AM33, {SIMM4_2, RN0, RM6, RN4}},
|
|---|
| 1399 | { "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1400 | { "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1401 | { "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1402 | { "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1403 | { "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1404 | { "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1405 | { "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1406 | { "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1407 | { "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1408 | { "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1409 | { "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1410 | { "llt_mov", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1411 | { "lgt_mov", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1412 | { "lge_mov", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1413 | { "lle_mov", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1414 | { "lcs_mov", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1415 | { "lhi_mov", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1416 | { "lcc_mov", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1417 | { "lls_mov", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1418 | { "leq_mov", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1419 | { "lne_mov", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1420 | { "lra_mov", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
|
|---|
| 1421 |
|
|---|
| 1422 | { 0, 0, 0, 0, 0, 0, {0}},
|
|---|
| 1423 |
|
|---|
| 1424 | } ;
|
|---|
| 1425 |
|
|---|
| 1426 | const int mn10300_num_opcodes =
|
|---|
| 1427 | sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
|
|---|
| 1428 |
|
|---|
| 1429 | |
|---|
| 1430 |
|
|---|
