source: trunk/binutils/opcodes/iq2000-dis.c@ 2630

Last change on this file since 2630 was 607, checked in by bird, 22 years ago

Initial revision
  • Property cvs2svn:cvs-rev set to 1.1
  • Property svn:eol-style set to native
  • Property svn:executable set to *
File size: 18.3 KB
Line 
1/* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
3
4THIS FILE IS MACHINE GENERATED WITH CGEN.
5- the resultant file is machine generated, cgen-dis.in isn't
6
7Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
8
9This file is part of the GNU Binutils and GDB, the GNU debugger.
10
11This program is free software; you can redistribute it and/or modify
12it under the terms of the GNU General Public License as published by
13the Free Software Foundation; either version 2, or (at your option)
14any later version.
15
16This program is distributed in the hope that it will be useful,
17but WITHOUT ANY WARRANTY; without even the implied warranty of
18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19GNU General Public License for more details.
20
21You should have received a copy of the GNU General Public License
22along with this program; if not, write to the Free Software Foundation, Inc.,
2359 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24
25/* ??? Eventually more and more of this stuff can go to cpu-independent files.
26 Keep that in mind. */
27
28#include "sysdep.h"
29#include <stdio.h>
30#include "ansidecl.h"
31#include "dis-asm.h"
32#include "bfd.h"
33#include "symcat.h"
34#include "iq2000-desc.h"
35#include "iq2000-opc.h"
36#include "opintl.h"
37
38/* Default text to print if an instruction isn't recognized. */
39#define UNKNOWN_INSN_MSG _("*unknown*")
40
41static void print_normal
42 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int));
43static void print_address
44 PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
45static void print_keyword
46 PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
47static void print_insn_normal
48 PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
49 bfd_vma, int));
50static int print_insn
51 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned));
52static int default_print_insn
53 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *));
54static int read_insn
55 PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int,
56 CGEN_EXTRACT_INFO *, unsigned long *));
57
58
59/* -- disassembler routines inserted here */
60
61
62void iq2000_cgen_print_operand
63 PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *,
64 void const *, bfd_vma, int));
65
66/* Main entry point for printing operands.
67 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
68 of dis-asm.h on cgen.h.
69
70 This function is basically just a big switch statement. Earlier versions
71 used tables to look up the function to use, but
72 - if the table contains both assembler and disassembler functions then
73 the disassembler contains much of the assembler and vice-versa,
74 - there's a lot of inlining possibilities as things grow,
75 - using a switch statement avoids the function call overhead.
76
77 This function could be moved into `print_insn_normal', but keeping it
78 separate makes clear the interface between `print_insn_normal' and each of
79 the handlers. */
80
81void
82iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
83 CGEN_CPU_DESC cd;
84 int opindex;
85 PTR xinfo;
86 CGEN_FIELDS *fields;
87 void const *attrs ATTRIBUTE_UNUSED;
88 bfd_vma pc;
89 int length;
90{
91 disassemble_info *info = (disassemble_info *) xinfo;
92
93 switch (opindex)
94 {
95 case IQ2000_OPERAND_BASE :
96 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
97 break;
98 case IQ2000_OPERAND_BASEOFF :
99 print_address (cd, info, fields->f_imm, 0, pc, length);
100 break;
101 case IQ2000_OPERAND_BITNUM :
102 print_normal (cd, info, fields->f_rt, 0, pc, length);
103 break;
104 case IQ2000_OPERAND_BYTECOUNT :
105 print_normal (cd, info, fields->f_bytecount, 0, pc, length);
106 break;
107 case IQ2000_OPERAND_CAM_Y :
108 print_normal (cd, info, fields->f_cam_y, 0, pc, length);
109 break;
110 case IQ2000_OPERAND_CAM_Z :
111 print_normal (cd, info, fields->f_cam_z, 0, pc, length);
112 break;
113 case IQ2000_OPERAND_CM_3FUNC :
114 print_normal (cd, info, fields->f_cm_3func, 0, pc, length);
115 break;
116 case IQ2000_OPERAND_CM_3Z :
117 print_normal (cd, info, fields->f_cm_3z, 0, pc, length);
118 break;
119 case IQ2000_OPERAND_CM_4FUNC :
120 print_normal (cd, info, fields->f_cm_4func, 0, pc, length);
121 break;
122 case IQ2000_OPERAND_CM_4Z :
123 print_normal (cd, info, fields->f_cm_4z, 0, pc, length);
124 break;
125 case IQ2000_OPERAND_COUNT :
126 print_normal (cd, info, fields->f_count, 0, pc, length);
127 break;
128 case IQ2000_OPERAND_EXECODE :
129 print_normal (cd, info, fields->f_excode, 0, pc, length);
130 break;
131 case IQ2000_OPERAND_HI16 :
132 print_normal (cd, info, fields->f_imm, 0, pc, length);
133 break;
134 case IQ2000_OPERAND_IMM :
135 print_normal (cd, info, fields->f_imm, 0, pc, length);
136 break;
137 case IQ2000_OPERAND_INDEX :
138 print_normal (cd, info, fields->f_index, 0, pc, length);
139 break;
140 case IQ2000_OPERAND_JMPTARG :
141 print_address (cd, info, fields->f_jtarg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
142 break;
143 case IQ2000_OPERAND_JMPTARGQ10 :
144 print_address (cd, info, fields->f_jtargq10, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
145 break;
146 case IQ2000_OPERAND_LO16 :
147 print_normal (cd, info, fields->f_imm, 0, pc, length);
148 break;
149 case IQ2000_OPERAND_MASK :
150 print_normal (cd, info, fields->f_mask, 0, pc, length);
151 break;
152 case IQ2000_OPERAND_MASKL :
153 print_normal (cd, info, fields->f_maskl, 0, pc, length);
154 break;
155 case IQ2000_OPERAND_MASKQ10 :
156 print_normal (cd, info, fields->f_maskq10, 0, pc, length);
157 break;
158 case IQ2000_OPERAND_MASKR :
159 print_normal (cd, info, fields->f_rs, 0, pc, length);
160 break;
161 case IQ2000_OPERAND_MLO16 :
162 print_normal (cd, info, fields->f_imm, 0, pc, length);
163 break;
164 case IQ2000_OPERAND_OFFSET :
165 print_address (cd, info, fields->f_offset, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
166 break;
167 case IQ2000_OPERAND_RD :
168 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd, 0);
169 break;
170 case IQ2000_OPERAND_RD_RS :
171 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
172 break;
173 case IQ2000_OPERAND_RD_RT :
174 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rt, 0|(1<<CGEN_OPERAND_VIRTUAL));
175 break;
176 case IQ2000_OPERAND_RS :
177 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0);
178 break;
179 case IQ2000_OPERAND_RT :
180 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0);
181 break;
182 case IQ2000_OPERAND_RT_RS :
183 print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<<CGEN_OPERAND_VIRTUAL));
184 break;
185 case IQ2000_OPERAND_SHAMT :
186 print_normal (cd, info, fields->f_shamt, 0, pc, length);
187 break;
188
189 default :
190 /* xgettext:c-format */
191 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
192 opindex);
193 abort ();
194 }
195}
196
197cgen_print_fn * const iq2000_cgen_print_handlers[] =
198{
199 print_insn_normal,
200};
201
202
203void
204iq2000_cgen_init_dis (cd)
205 CGEN_CPU_DESC cd;
206{
207 iq2000_cgen_init_opcode_table (cd);
208 iq2000_cgen_init_ibld_table (cd);
209 cd->print_handlers = & iq2000_cgen_print_handlers[0];
210 cd->print_operand = iq2000_cgen_print_operand;
211}
212
213
214
215/* Default print handler. */
216
217static void
218print_normal (cd, dis_info, value, attrs, pc, length)
219 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
220 PTR dis_info;
221 long value;
222 unsigned int attrs;
223 bfd_vma pc ATTRIBUTE_UNUSED;
224 int length ATTRIBUTE_UNUSED;
225{
226 disassemble_info *info = (disassemble_info *) dis_info;
227
228#ifdef CGEN_PRINT_NORMAL
229 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
230#endif
231
232 /* Print the operand as directed by the attributes. */
233 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
234 ; /* nothing to do */
235 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
236 (*info->fprintf_func) (info->stream, "%ld", value);
237 else
238 (*info->fprintf_func) (info->stream, "0x%lx", value);
239}
240
241/* Default address handler. */
242
243static void
244print_address (cd, dis_info, value, attrs, pc, length)
245 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
246 PTR dis_info;
247 bfd_vma value;
248 unsigned int attrs;
249 bfd_vma pc ATTRIBUTE_UNUSED;
250 int length ATTRIBUTE_UNUSED;
251{
252 disassemble_info *info = (disassemble_info *) dis_info;
253
254#ifdef CGEN_PRINT_ADDRESS
255 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
256#endif
257
258 /* Print the operand as directed by the attributes. */
259 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
260 ; /* nothing to do */
261 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
262 (*info->print_address_func) (value, info);
263 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
264 (*info->print_address_func) (value, info);
265 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
266 (*info->fprintf_func) (info->stream, "%ld", (long) value);
267 else
268 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
269}
270
271/* Keyword print handler. */
272
273static void
274print_keyword (cd, dis_info, keyword_table, value, attrs)
275 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
276 PTR dis_info;
277 CGEN_KEYWORD *keyword_table;
278 long value;
279 unsigned int attrs ATTRIBUTE_UNUSED;
280{
281 disassemble_info *info = (disassemble_info *) dis_info;
282 const CGEN_KEYWORD_ENTRY *ke;
283
284 ke = cgen_keyword_lookup_value (keyword_table, value);
285 if (ke != NULL)
286 (*info->fprintf_func) (info->stream, "%s", ke->name);
287 else
288 (*info->fprintf_func) (info->stream, "???");
289}
290
291
292/* Default insn printer.
293
294 DIS_INFO is defined as `PTR' so the disassembler needn't know anything
295 about disassemble_info. */
296
297static void
298print_insn_normal (cd, dis_info, insn, fields, pc, length)
299 CGEN_CPU_DESC cd;
300 PTR dis_info;
301 const CGEN_INSN *insn;
302 CGEN_FIELDS *fields;
303 bfd_vma pc;
304 int length;
305{
306 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
307 disassemble_info *info = (disassemble_info *) dis_info;
308 const CGEN_SYNTAX_CHAR_TYPE *syn;
309
310 CGEN_INIT_PRINT (cd);
311
312 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
313 {
314 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
315 {
316 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
317 continue;
318 }
319 if (CGEN_SYNTAX_CHAR_P (*syn))
320 {
321 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
322 continue;
323 }
324
325 /* We have an operand. */
326 iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
327 fields, CGEN_INSN_ATTRS (insn), pc, length);
328 }
329}
330
331
332/* Subroutine of print_insn. Reads an insn into the given buffers and updates
333 the extract info.
334 Returns 0 if all is well, non-zero otherwise. */
335
336static int
337read_insn (cd, pc, info, buf, buflen, ex_info, insn_value)
338 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
339 bfd_vma pc;
340 disassemble_info *info;
341 char *buf;
342 int buflen;
343 CGEN_EXTRACT_INFO *ex_info;
344 unsigned long *insn_value;
345{
346 int status = (*info->read_memory_func) (pc, buf, buflen, info);
347 if (status != 0)
348 {
349 (*info->memory_error_func) (status, pc, info);
350 return -1;
351 }
352
353 ex_info->dis_info = info;
354 ex_info->valid = (1 << buflen) - 1;
355 ex_info->insn_bytes = buf;
356
357 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
358 return 0;
359}
360
361/* Utility to print an insn.
362 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
363 The result is the size of the insn in bytes or zero for an unknown insn
364 or -1 if an error occurs fetching data (memory_error_func will have
365 been called). */
366
367static int
368print_insn (cd, pc, info, buf, buflen)
369 CGEN_CPU_DESC cd;
370 bfd_vma pc;
371 disassemble_info *info;
372 char *buf;
373 unsigned int buflen;
374{
375 CGEN_INSN_INT insn_value;
376 const CGEN_INSN_LIST *insn_list;
377 CGEN_EXTRACT_INFO ex_info;
378 int basesize;
379
380 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
381 basesize = cd->base_insn_bitsize < buflen * 8 ?
382 cd->base_insn_bitsize : buflen * 8;
383 insn_value = cgen_get_insn_value (cd, buf, basesize);
384
385
386 /* Fill in ex_info fields like read_insn would. Don't actually call
387 read_insn, since the incoming buffer is already read (and possibly
388 modified a la m32r). */
389 ex_info.valid = (1 << buflen) - 1;
390 ex_info.dis_info = info;
391 ex_info.insn_bytes = buf;
392
393 /* The instructions are stored in hash lists.
394 Pick the first one and keep trying until we find the right one. */
395
396 insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value);
397 while (insn_list != NULL)
398 {
399 const CGEN_INSN *insn = insn_list->insn;
400 CGEN_FIELDS fields;
401 int length;
402 unsigned long insn_value_cropped;
403
404#ifdef CGEN_VALIDATE_INSN_SUPPORTED
405 /* Not needed as insn shouldn't be in hash lists if not supported. */
406 /* Supported by this cpu? */
407 if (! iq2000_cgen_insn_supported (cd, insn))
408 {
409 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
410 continue;
411 }
412#endif
413
414 /* Basic bit mask must be correct. */
415 /* ??? May wish to allow target to defer this check until the extract
416 handler. */
417
418 /* Base size may exceed this instruction's size. Extract the
419 relevant part from the buffer. */
420 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
421 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
422 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
423 info->endian == BFD_ENDIAN_BIG);
424 else
425 insn_value_cropped = insn_value;
426
427 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
428 == CGEN_INSN_BASE_VALUE (insn))
429 {
430 /* Printing is handled in two passes. The first pass parses the
431 machine insn and extracts the fields. The second pass prints
432 them. */
433
434 /* Make sure the entire insn is loaded into insn_value, if it
435 can fit. */
436 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
437 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
438 {
439 unsigned long full_insn_value;
440 int rc = read_insn (cd, pc, info, buf,
441 CGEN_INSN_BITSIZE (insn) / 8,
442 & ex_info, & full_insn_value);
443 if (rc != 0)
444 return rc;
445 length = CGEN_EXTRACT_FN (cd, insn)
446 (cd, insn, &ex_info, full_insn_value, &fields, pc);
447 }
448 else
449 length = CGEN_EXTRACT_FN (cd, insn)
450 (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
451
452 /* length < 0 -> error */
453 if (length < 0)
454 return length;
455 if (length > 0)
456 {
457 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
458 /* length is in bits, result is in bytes */
459 return length / 8;
460 }
461 }
462
463 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
464 }
465
466 return 0;
467}
468
469/* Default value for CGEN_PRINT_INSN.
470 The result is the size of the insn in bytes or zero for an unknown insn
471 or -1 if an error occured fetching bytes. */
472
473#ifndef CGEN_PRINT_INSN
474#define CGEN_PRINT_INSN default_print_insn
475#endif
476
477static int
478default_print_insn (cd, pc, info)
479 CGEN_CPU_DESC cd;
480 bfd_vma pc;
481 disassemble_info *info;
482{
483 char buf[CGEN_MAX_INSN_SIZE];
484 int buflen;
485 int status;
486
487 /* Attempt to read the base part of the insn. */
488 buflen = cd->base_insn_bitsize / 8;
489 status = (*info->read_memory_func) (pc, buf, buflen, info);
490
491 /* Try again with the minimum part, if min < base. */
492 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
493 {
494 buflen = cd->min_insn_bitsize / 8;
495 status = (*info->read_memory_func) (pc, buf, buflen, info);
496 }
497
498 if (status != 0)
499 {
500 (*info->memory_error_func) (status, pc, info);
501 return -1;
502 }
503
504 return print_insn (cd, pc, info, buf, buflen);
505}
506
507/* Main entry point.
508 Print one instruction from PC on INFO->STREAM.
509 Return the size of the instruction (in bytes). */
510
511typedef struct cpu_desc_list {
512 struct cpu_desc_list *next;
513 int isa;
514 int mach;
515 int endian;
516 CGEN_CPU_DESC cd;
517} cpu_desc_list;
518
519int
520print_insn_iq2000 (pc, info)
521 bfd_vma pc;
522 disassemble_info *info;
523{
524 static cpu_desc_list *cd_list = 0;
525 cpu_desc_list *cl = 0;
526 static CGEN_CPU_DESC cd = 0;
527 static int prev_isa;
528 static int prev_mach;
529 static int prev_endian;
530 int length;
531 int isa,mach;
532 int endian = (info->endian == BFD_ENDIAN_BIG
533 ? CGEN_ENDIAN_BIG
534 : CGEN_ENDIAN_LITTLE);
535 enum bfd_architecture arch;
536
537 /* ??? gdb will set mach but leave the architecture as "unknown" */
538#ifndef CGEN_BFD_ARCH
539#define CGEN_BFD_ARCH bfd_arch_iq2000
540#endif
541 arch = info->arch;
542 if (arch == bfd_arch_unknown)
543 arch = CGEN_BFD_ARCH;
544
545 /* There's no standard way to compute the machine or isa number
546 so we leave it to the target. */
547#ifdef CGEN_COMPUTE_MACH
548 mach = CGEN_COMPUTE_MACH (info);
549#else
550 mach = info->mach;
551#endif
552
553#ifdef CGEN_COMPUTE_ISA
554 isa = CGEN_COMPUTE_ISA (info);
555#else
556 isa = info->insn_sets;
557#endif
558
559 /* If we've switched cpu's, try to find a handle we've used before */
560 if (cd
561 && (isa != prev_isa
562 || mach != prev_mach
563 || endian != prev_endian))
564 {
565 cd = 0;
566 for (cl = cd_list; cl; cl = cl->next)
567 {
568 if (cl->isa == isa &&
569 cl->mach == mach &&
570 cl->endian == endian)
571 {
572 cd = cl->cd;
573 break;
574 }
575 }
576 }
577
578 /* If we haven't initialized yet, initialize the opcode table. */
579 if (! cd)
580 {
581 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
582 const char *mach_name;
583
584 if (!arch_type)
585 abort ();
586 mach_name = arch_type->printable_name;
587
588 prev_isa = isa;
589 prev_mach = mach;
590 prev_endian = endian;
591 cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
592 CGEN_CPU_OPEN_BFDMACH, mach_name,
593 CGEN_CPU_OPEN_ENDIAN, prev_endian,
594 CGEN_CPU_OPEN_END);
595 if (!cd)
596 abort ();
597
598 /* save this away for future reference */
599 cl = xmalloc (sizeof (struct cpu_desc_list));
600 cl->cd = cd;
601 cl->isa = isa;
602 cl->mach = mach;
603 cl->endian = endian;
604 cl->next = cd_list;
605 cd_list = cl;
606
607 iq2000_cgen_init_dis (cd);
608 }
609
610 /* We try to have as much common code as possible.
611 But at this point some targets need to take over. */
612 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
613 but if not possible try to move this hook elsewhere rather than
614 have two hooks. */
615 length = CGEN_PRINT_INSN (cd, pc, info);
616 if (length > 0)
617 return length;
618 if (length < 0)
619 return -1;
620
621 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
622 return cd->default_insn_bitsize / 8;
623}
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